2 * Support for OMAP DES and Triple DES HW acceleration.
4 * Copyright (c) 2013 Texas Instruments Incorporated
5 * Author: Joel Fernandes <joelf@ti.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
13 #define pr_fmt(fmt) "%s: " fmt, __func__
16 #define prn(num) printk(#num "=%d\n", num)
17 #define prx(num) printk(#num "=%x\n", num)
19 #define prn(num) do { } while (0)
20 #define prx(num) do { } while (0)
23 #include <linux/err.h>
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/errno.h>
27 #include <linux/kernel.h>
28 #include <linux/platform_device.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/of_device.h>
35 #include <linux/of_address.h>
37 #include <linux/crypto.h>
38 #include <linux/interrupt.h>
39 #include <crypto/scatterwalk.h>
40 #include <crypto/des.h>
41 #include <crypto/algapi.h>
42 #include <crypto/engine.h>
44 #include "omap-crypto.h"
46 #define DST_MAXBURST 2
48 #define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2)
50 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
52 #define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
55 #define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
57 #define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
58 #define DES_REG_CTRL_CBC BIT(4)
59 #define DES_REG_CTRL_TDES BIT(3)
60 #define DES_REG_CTRL_DIRECTION BIT(2)
61 #define DES_REG_CTRL_INPUT_READY BIT(1)
62 #define DES_REG_CTRL_OUTPUT_READY BIT(0)
64 #define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
66 #define DES_REG_REV(dd) ((dd)->pdata->rev_ofs)
68 #define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
70 #define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04))
72 #define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
73 #define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
74 #define DES_REG_IRQ_DATA_IN BIT(1)
75 #define DES_REG_IRQ_DATA_OUT BIT(2)
77 #define FLAGS_MODE_MASK 0x000f
78 #define FLAGS_ENCRYPT BIT(0)
79 #define FLAGS_CBC BIT(1)
80 #define FLAGS_INIT BIT(4)
81 #define FLAGS_BUSY BIT(6)
83 #define DEFAULT_AUTOSUSPEND_DELAY 1000
85 #define FLAGS_IN_DATA_ST_SHIFT 8
86 #define FLAGS_OUT_DATA_ST_SHIFT 10
89 struct omap_des_dev *dd;
92 u32 key[(3 * DES_KEY_SIZE) / sizeof(u32)];
96 struct omap_des_reqctx {
100 #define OMAP_DES_QUEUE_LENGTH 1
101 #define OMAP_DES_CACHE_SIZE 0
103 struct omap_des_algs_info {
104 struct crypto_alg *algs_list;
106 unsigned int registered;
109 struct omap_des_pdata {
110 struct omap_des_algs_info *algs_info;
111 unsigned int algs_info_size;
113 void (*trigger)(struct omap_des_dev *dd, int length);
134 struct omap_des_dev {
135 struct list_head list;
136 unsigned long phys_base;
137 void __iomem *io_base;
138 struct omap_des_ctx *ctx;
143 struct tasklet_struct done_task;
145 struct ablkcipher_request *req;
146 struct crypto_engine *engine;
148 * total is used by PIO mode for book keeping so introduce
149 * variable total_save as need it to calc page_order
154 struct scatterlist *in_sg;
155 struct scatterlist *out_sg;
157 /* Buffers for copying for unaligned cases */
158 struct scatterlist in_sgl;
159 struct scatterlist out_sgl;
160 struct scatterlist *orig_out;
162 struct scatter_walk in_walk;
163 struct scatter_walk out_walk;
164 struct dma_chan *dma_lch_in;
165 struct dma_chan *dma_lch_out;
169 const struct omap_des_pdata *pdata;
172 /* keep registered devices data here */
173 static LIST_HEAD(dev_list);
174 static DEFINE_SPINLOCK(list_lock);
177 #define omap_des_read(dd, offset) \
180 _read_ret = __raw_readl(dd->io_base + offset); \
181 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \
182 offset, _read_ret); \
186 static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
188 return __raw_readl(dd->io_base + offset);
193 #define omap_des_write(dd, offset, value) \
195 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
197 __raw_writel(value, dd->io_base + offset); \
200 static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
203 __raw_writel(value, dd->io_base + offset);
207 static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
212 val = omap_des_read(dd, offset);
215 omap_des_write(dd, offset, val);
218 static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
219 u32 *value, int count)
221 for (; count--; value++, offset += 4)
222 omap_des_write(dd, offset, *value);
225 static int omap_des_hw_init(struct omap_des_dev *dd)
230 * clocks are enabled when request starts and disabled when finished.
231 * It may be long delays between requests.
232 * Device might go to off mode to save power.
234 err = pm_runtime_get_sync(dd->dev);
236 pm_runtime_put_noidle(dd->dev);
237 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
241 if (!(dd->flags & FLAGS_INIT)) {
242 dd->flags |= FLAGS_INIT;
249 static int omap_des_write_ctrl(struct omap_des_dev *dd)
253 u32 val = 0, mask = 0;
255 err = omap_des_hw_init(dd);
259 key32 = dd->ctx->keylen / sizeof(u32);
261 /* it seems a key should always be set even if it has not changed */
262 for (i = 0; i < key32; i++) {
263 omap_des_write(dd, DES_REG_KEY(dd, i),
264 __le32_to_cpu(dd->ctx->key[i]));
267 if ((dd->flags & FLAGS_CBC) && dd->req->info)
268 omap_des_write_n(dd, DES_REG_IV(dd, 0), dd->req->info, 2);
270 if (dd->flags & FLAGS_CBC)
271 val |= DES_REG_CTRL_CBC;
272 if (dd->flags & FLAGS_ENCRYPT)
273 val |= DES_REG_CTRL_DIRECTION;
275 val |= DES_REG_CTRL_TDES;
277 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
279 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
284 static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
288 omap_des_write(dd, DES_REG_LENGTH_N(0), length);
290 val = dd->pdata->dma_start;
292 if (dd->dma_lch_out != NULL)
293 val |= dd->pdata->dma_enable_out;
294 if (dd->dma_lch_in != NULL)
295 val |= dd->pdata->dma_enable_in;
297 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
298 dd->pdata->dma_start;
300 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
303 static void omap_des_dma_stop(struct omap_des_dev *dd)
307 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
308 dd->pdata->dma_start;
310 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
313 static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
315 struct omap_des_dev *dd = NULL, *tmp;
317 spin_lock_bh(&list_lock);
319 list_for_each_entry(tmp, &dev_list, list) {
320 /* FIXME: take fist available des core */
326 /* already found before */
329 spin_unlock_bh(&list_lock);
334 static void omap_des_dma_out_callback(void *data)
336 struct omap_des_dev *dd = data;
338 /* dma_lch_out - completed */
339 tasklet_schedule(&dd->done_task);
342 static int omap_des_dma_init(struct omap_des_dev *dd)
346 dd->dma_lch_out = NULL;
347 dd->dma_lch_in = NULL;
349 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
350 if (IS_ERR(dd->dma_lch_in)) {
351 dev_err(dd->dev, "Unable to request in DMA channel\n");
352 return PTR_ERR(dd->dma_lch_in);
355 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
356 if (IS_ERR(dd->dma_lch_out)) {
357 dev_err(dd->dev, "Unable to request out DMA channel\n");
358 err = PTR_ERR(dd->dma_lch_out);
365 dma_release_channel(dd->dma_lch_in);
370 static void omap_des_dma_cleanup(struct omap_des_dev *dd)
375 dma_release_channel(dd->dma_lch_out);
376 dma_release_channel(dd->dma_lch_in);
379 static int omap_des_crypt_dma(struct crypto_tfm *tfm,
380 struct scatterlist *in_sg, struct scatterlist *out_sg,
381 int in_sg_len, int out_sg_len)
383 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
384 struct omap_des_dev *dd = ctx->dd;
385 struct dma_async_tx_descriptor *tx_in, *tx_out;
386 struct dma_slave_config cfg;
390 scatterwalk_start(&dd->in_walk, dd->in_sg);
391 scatterwalk_start(&dd->out_walk, dd->out_sg);
393 /* Enable DATAIN interrupt and let it take
395 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
399 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
401 memset(&cfg, 0, sizeof(cfg));
403 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
404 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
405 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
406 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
407 cfg.src_maxburst = DST_MAXBURST;
408 cfg.dst_maxburst = DST_MAXBURST;
411 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
413 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
418 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
420 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
422 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
426 /* No callback necessary */
427 tx_in->callback_param = dd;
430 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
432 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
437 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
439 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
441 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
445 tx_out->callback = omap_des_dma_out_callback;
446 tx_out->callback_param = dd;
448 dmaengine_submit(tx_in);
449 dmaengine_submit(tx_out);
451 dma_async_issue_pending(dd->dma_lch_in);
452 dma_async_issue_pending(dd->dma_lch_out);
455 dd->pdata->trigger(dd, dd->total);
460 static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
462 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
463 crypto_ablkcipher_reqtfm(dd->req));
466 pr_debug("total: %d\n", dd->total);
469 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
472 dev_err(dd->dev, "dma_map_sg() error\n");
476 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
479 dev_err(dd->dev, "dma_map_sg() error\n");
484 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
486 if (err && !dd->pio_only) {
487 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
488 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
495 static void omap_des_finish_req(struct omap_des_dev *dd, int err)
497 struct ablkcipher_request *req = dd->req;
499 pr_debug("err: %d\n", err);
501 crypto_finalize_cipher_request(dd->engine, req, err);
503 pm_runtime_mark_last_busy(dd->dev);
504 pm_runtime_put_autosuspend(dd->dev);
507 static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
509 pr_debug("total: %d\n", dd->total);
511 omap_des_dma_stop(dd);
513 dmaengine_terminate_all(dd->dma_lch_in);
514 dmaengine_terminate_all(dd->dma_lch_out);
519 static int omap_des_handle_queue(struct omap_des_dev *dd,
520 struct ablkcipher_request *req)
523 return crypto_transfer_cipher_request_to_engine(dd->engine, req);
528 static int omap_des_prepare_req(struct crypto_engine *engine,
529 struct ablkcipher_request *req)
531 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
532 crypto_ablkcipher_reqtfm(req));
533 struct omap_des_dev *dd = omap_des_find_dev(ctx);
534 struct omap_des_reqctx *rctx;
541 /* assign new request to device */
543 dd->total = req->nbytes;
544 dd->total_save = req->nbytes;
545 dd->in_sg = req->src;
546 dd->out_sg = req->dst;
547 dd->orig_out = req->dst;
549 flags = OMAP_CRYPTO_COPY_DATA;
550 if (req->src == req->dst)
551 flags |= OMAP_CRYPTO_FORCE_COPY;
553 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, DES_BLOCK_SIZE,
555 FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
559 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, DES_BLOCK_SIZE,
561 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
565 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
566 if (dd->in_sg_len < 0)
567 return dd->in_sg_len;
569 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
570 if (dd->out_sg_len < 0)
571 return dd->out_sg_len;
573 rctx = ablkcipher_request_ctx(req);
574 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
575 rctx->mode &= FLAGS_MODE_MASK;
576 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
581 return omap_des_write_ctrl(dd);
584 static int omap_des_crypt_req(struct crypto_engine *engine,
585 struct ablkcipher_request *req)
587 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
588 crypto_ablkcipher_reqtfm(req));
589 struct omap_des_dev *dd = omap_des_find_dev(ctx);
594 return omap_des_crypt_dma_start(dd);
597 static void omap_des_done_task(unsigned long data)
599 struct omap_des_dev *dd = (struct omap_des_dev *)data;
601 pr_debug("enter done_task\n");
604 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
606 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
607 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
609 omap_des_crypt_dma_stop(dd);
612 omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save,
613 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
615 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
616 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
618 omap_des_finish_req(dd, 0);
623 static int omap_des_crypt(struct ablkcipher_request *req, unsigned long mode)
625 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
626 crypto_ablkcipher_reqtfm(req));
627 struct omap_des_reqctx *rctx = ablkcipher_request_ctx(req);
628 struct omap_des_dev *dd;
630 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
631 !!(mode & FLAGS_ENCRYPT),
632 !!(mode & FLAGS_CBC));
634 if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) {
635 pr_err("request size is not exact amount of DES blocks\n");
639 dd = omap_des_find_dev(ctx);
645 return omap_des_handle_queue(dd, req);
648 /* ********************** ALG API ************************************ */
650 static int omap_des_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
653 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(cipher);
654 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
656 if (keylen != DES_KEY_SIZE && keylen != (3*DES_KEY_SIZE))
659 pr_debug("enter, keylen: %d\n", keylen);
661 /* Do we need to test against weak key? */
662 if (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY) {
663 u32 tmp[DES_EXPKEY_WORDS];
664 int ret = des_ekey(tmp, key);
667 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
672 memcpy(ctx->key, key, keylen);
673 ctx->keylen = keylen;
678 static int omap_des_ecb_encrypt(struct ablkcipher_request *req)
680 return omap_des_crypt(req, FLAGS_ENCRYPT);
683 static int omap_des_ecb_decrypt(struct ablkcipher_request *req)
685 return omap_des_crypt(req, 0);
688 static int omap_des_cbc_encrypt(struct ablkcipher_request *req)
690 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
693 static int omap_des_cbc_decrypt(struct ablkcipher_request *req)
695 return omap_des_crypt(req, FLAGS_CBC);
698 static int omap_des_cra_init(struct crypto_tfm *tfm)
702 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_des_reqctx);
707 static void omap_des_cra_exit(struct crypto_tfm *tfm)
712 /* ********************** ALGS ************************************ */
714 static struct crypto_alg algs_ecb_cbc[] = {
716 .cra_name = "ecb(des)",
717 .cra_driver_name = "ecb-des-omap",
719 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
720 CRYPTO_ALG_KERN_DRIVER_ONLY |
722 .cra_blocksize = DES_BLOCK_SIZE,
723 .cra_ctxsize = sizeof(struct omap_des_ctx),
725 .cra_type = &crypto_ablkcipher_type,
726 .cra_module = THIS_MODULE,
727 .cra_init = omap_des_cra_init,
728 .cra_exit = omap_des_cra_exit,
729 .cra_u.ablkcipher = {
730 .min_keysize = DES_KEY_SIZE,
731 .max_keysize = DES_KEY_SIZE,
732 .setkey = omap_des_setkey,
733 .encrypt = omap_des_ecb_encrypt,
734 .decrypt = omap_des_ecb_decrypt,
738 .cra_name = "cbc(des)",
739 .cra_driver_name = "cbc-des-omap",
741 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
742 CRYPTO_ALG_KERN_DRIVER_ONLY |
744 .cra_blocksize = DES_BLOCK_SIZE,
745 .cra_ctxsize = sizeof(struct omap_des_ctx),
747 .cra_type = &crypto_ablkcipher_type,
748 .cra_module = THIS_MODULE,
749 .cra_init = omap_des_cra_init,
750 .cra_exit = omap_des_cra_exit,
751 .cra_u.ablkcipher = {
752 .min_keysize = DES_KEY_SIZE,
753 .max_keysize = DES_KEY_SIZE,
754 .ivsize = DES_BLOCK_SIZE,
755 .setkey = omap_des_setkey,
756 .encrypt = omap_des_cbc_encrypt,
757 .decrypt = omap_des_cbc_decrypt,
761 .cra_name = "ecb(des3_ede)",
762 .cra_driver_name = "ecb-des3-omap",
764 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
765 CRYPTO_ALG_KERN_DRIVER_ONLY |
767 .cra_blocksize = DES_BLOCK_SIZE,
768 .cra_ctxsize = sizeof(struct omap_des_ctx),
770 .cra_type = &crypto_ablkcipher_type,
771 .cra_module = THIS_MODULE,
772 .cra_init = omap_des_cra_init,
773 .cra_exit = omap_des_cra_exit,
774 .cra_u.ablkcipher = {
775 .min_keysize = 3*DES_KEY_SIZE,
776 .max_keysize = 3*DES_KEY_SIZE,
777 .setkey = omap_des_setkey,
778 .encrypt = omap_des_ecb_encrypt,
779 .decrypt = omap_des_ecb_decrypt,
783 .cra_name = "cbc(des3_ede)",
784 .cra_driver_name = "cbc-des3-omap",
786 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
787 CRYPTO_ALG_KERN_DRIVER_ONLY |
789 .cra_blocksize = DES_BLOCK_SIZE,
790 .cra_ctxsize = sizeof(struct omap_des_ctx),
792 .cra_type = &crypto_ablkcipher_type,
793 .cra_module = THIS_MODULE,
794 .cra_init = omap_des_cra_init,
795 .cra_exit = omap_des_cra_exit,
796 .cra_u.ablkcipher = {
797 .min_keysize = 3*DES_KEY_SIZE,
798 .max_keysize = 3*DES_KEY_SIZE,
799 .ivsize = DES_BLOCK_SIZE,
800 .setkey = omap_des_setkey,
801 .encrypt = omap_des_cbc_encrypt,
802 .decrypt = omap_des_cbc_decrypt,
807 static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
809 .algs_list = algs_ecb_cbc,
810 .size = ARRAY_SIZE(algs_ecb_cbc),
815 static const struct omap_des_pdata omap_des_pdata_omap4 = {
816 .algs_info = omap_des_algs_info_ecb_cbc,
817 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
818 .trigger = omap_des_dma_trigger_omap4,
825 .irq_status_ofs = 0x3c,
826 .irq_enable_ofs = 0x40,
827 .dma_enable_in = BIT(5),
828 .dma_enable_out = BIT(6),
829 .major_mask = 0x0700,
831 .minor_mask = 0x003f,
835 static irqreturn_t omap_des_irq(int irq, void *dev_id)
837 struct omap_des_dev *dd = dev_id;
841 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
842 if (status & DES_REG_IRQ_DATA_IN) {
843 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
847 BUG_ON(_calc_walked(in) > dd->in_sg->length);
849 src = sg_virt(dd->in_sg) + _calc_walked(in);
851 for (i = 0; i < DES_BLOCK_WORDS; i++) {
852 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
854 scatterwalk_advance(&dd->in_walk, 4);
855 if (dd->in_sg->length == _calc_walked(in)) {
856 dd->in_sg = sg_next(dd->in_sg);
858 scatterwalk_start(&dd->in_walk,
860 src = sg_virt(dd->in_sg) +
868 /* Clear IRQ status */
869 status &= ~DES_REG_IRQ_DATA_IN;
870 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
872 /* Enable DATA_OUT interrupt */
873 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
875 } else if (status & DES_REG_IRQ_DATA_OUT) {
876 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
880 BUG_ON(_calc_walked(out) > dd->out_sg->length);
882 dst = sg_virt(dd->out_sg) + _calc_walked(out);
884 for (i = 0; i < DES_BLOCK_WORDS; i++) {
885 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
886 scatterwalk_advance(&dd->out_walk, 4);
887 if (dd->out_sg->length == _calc_walked(out)) {
888 dd->out_sg = sg_next(dd->out_sg);
890 scatterwalk_start(&dd->out_walk,
892 dst = sg_virt(dd->out_sg) +
900 BUG_ON(dd->total < DES_BLOCK_SIZE);
902 dd->total -= DES_BLOCK_SIZE;
904 /* Clear IRQ status */
905 status &= ~DES_REG_IRQ_DATA_OUT;
906 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
909 /* All bytes read! */
910 tasklet_schedule(&dd->done_task);
912 /* Enable DATA_IN interrupt for next block */
913 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
919 static const struct of_device_id omap_des_of_match[] = {
921 .compatible = "ti,omap4-des",
922 .data = &omap_des_pdata_omap4,
926 MODULE_DEVICE_TABLE(of, omap_des_of_match);
928 static int omap_des_get_of(struct omap_des_dev *dd,
929 struct platform_device *pdev)
932 dd->pdata = of_device_get_match_data(&pdev->dev);
934 dev_err(&pdev->dev, "no compatible OF match\n");
941 static int omap_des_get_of(struct omap_des_dev *dd,
948 static int omap_des_get_pdev(struct omap_des_dev *dd,
949 struct platform_device *pdev)
951 /* non-DT devices get pdata from pdev */
952 dd->pdata = pdev->dev.platform_data;
957 static int omap_des_probe(struct platform_device *pdev)
959 struct device *dev = &pdev->dev;
960 struct omap_des_dev *dd;
961 struct crypto_alg *algp;
962 struct resource *res;
963 int err = -ENOMEM, i, j, irq = -1;
966 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
968 dev_err(dev, "unable to alloc data struct.\n");
972 platform_set_drvdata(pdev, dd);
974 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
976 dev_err(dev, "no MEM resource info\n");
980 err = (dev->of_node) ? omap_des_get_of(dd, pdev) :
981 omap_des_get_pdev(dd, pdev);
985 dd->io_base = devm_ioremap_resource(dev, res);
986 if (IS_ERR(dd->io_base)) {
987 err = PTR_ERR(dd->io_base);
990 dd->phys_base = res->start;
992 pm_runtime_use_autosuspend(dev);
993 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
995 pm_runtime_enable(dev);
996 err = pm_runtime_get_sync(dev);
998 pm_runtime_put_noidle(dev);
999 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
1003 omap_des_dma_stop(dd);
1005 reg = omap_des_read(dd, DES_REG_REV(dd));
1007 pm_runtime_put_sync(dev);
1009 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
1010 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1011 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1013 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd);
1015 err = omap_des_dma_init(dd);
1016 if (err == -EPROBE_DEFER) {
1018 } else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
1021 irq = platform_get_irq(pdev, 0);
1023 dev_err(dev, "can't get IRQ resource: %d\n", irq);
1028 err = devm_request_irq(dev, irq, omap_des_irq, 0,
1031 dev_err(dev, "Unable to grab omap-des IRQ\n");
1037 INIT_LIST_HEAD(&dd->list);
1038 spin_lock(&list_lock);
1039 list_add_tail(&dd->list, &dev_list);
1040 spin_unlock(&list_lock);
1042 /* Initialize des crypto engine */
1043 dd->engine = crypto_engine_alloc_init(dev, 1);
1049 dd->engine->prepare_cipher_request = omap_des_prepare_req;
1050 dd->engine->cipher_one_request = omap_des_crypt_req;
1051 err = crypto_engine_start(dd->engine);
1055 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1056 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1057 algp = &dd->pdata->algs_info[i].algs_list[j];
1059 pr_debug("reg alg: %s\n", algp->cra_name);
1060 INIT_LIST_HEAD(&algp->cra_list);
1062 err = crypto_register_alg(algp);
1066 dd->pdata->algs_info[i].registered++;
1073 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1074 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1075 crypto_unregister_alg(
1076 &dd->pdata->algs_info[i].algs_list[j]);
1080 crypto_engine_exit(dd->engine);
1082 omap_des_dma_cleanup(dd);
1084 tasklet_kill(&dd->done_task);
1086 pm_runtime_disable(dev);
1090 dev_err(dev, "initialization failed.\n");
1094 static int omap_des_remove(struct platform_device *pdev)
1096 struct omap_des_dev *dd = platform_get_drvdata(pdev);
1102 spin_lock(&list_lock);
1103 list_del(&dd->list);
1104 spin_unlock(&list_lock);
1106 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1107 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1108 crypto_unregister_alg(
1109 &dd->pdata->algs_info[i].algs_list[j]);
1111 tasklet_kill(&dd->done_task);
1112 omap_des_dma_cleanup(dd);
1113 pm_runtime_disable(dd->dev);
1119 #ifdef CONFIG_PM_SLEEP
1120 static int omap_des_suspend(struct device *dev)
1122 pm_runtime_put_sync(dev);
1126 static int omap_des_resume(struct device *dev)
1130 err = pm_runtime_get_sync(dev);
1132 pm_runtime_put_noidle(dev);
1133 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err);
1140 static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume);
1142 static struct platform_driver omap_des_driver = {
1143 .probe = omap_des_probe,
1144 .remove = omap_des_remove,
1147 .pm = &omap_des_pm_ops,
1148 .of_match_table = of_match_ptr(omap_des_of_match),
1152 module_platform_driver(omap_des_driver);
1154 MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
1155 MODULE_LICENSE("GPL v2");
1156 MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");