1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for OMAP DES and Triple DES HW acceleration.
5 * Copyright (c) 2013 Texas Instruments Incorporated
6 * Author: Joel Fernandes <joelf@ti.com>
9 #define pr_fmt(fmt) "%s: " fmt, __func__
12 #define prn(num) printk(#num "=%d\n", num)
13 #define prx(num) printk(#num "=%x\n", num)
15 #define prn(num) do { } while (0)
16 #define prx(num) do { } while (0)
19 #include <linux/err.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/kernel.h>
24 #include <linux/platform_device.h>
25 #include <linux/scatterlist.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/dmaengine.h>
28 #include <linux/pm_runtime.h>
30 #include <linux/of_device.h>
31 #include <linux/of_address.h>
33 #include <linux/crypto.h>
34 #include <linux/interrupt.h>
35 #include <crypto/scatterwalk.h>
36 #include <crypto/internal/des.h>
37 #include <crypto/algapi.h>
38 #include <crypto/engine.h>
40 #include "omap-crypto.h"
42 #define DST_MAXBURST 2
44 #define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2)
46 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
48 #define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
51 #define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
53 #define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
54 #define DES_REG_CTRL_CBC BIT(4)
55 #define DES_REG_CTRL_TDES BIT(3)
56 #define DES_REG_CTRL_DIRECTION BIT(2)
57 #define DES_REG_CTRL_INPUT_READY BIT(1)
58 #define DES_REG_CTRL_OUTPUT_READY BIT(0)
60 #define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
62 #define DES_REG_REV(dd) ((dd)->pdata->rev_ofs)
64 #define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
66 #define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04))
68 #define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
69 #define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
70 #define DES_REG_IRQ_DATA_IN BIT(1)
71 #define DES_REG_IRQ_DATA_OUT BIT(2)
73 #define FLAGS_MODE_MASK 0x000f
74 #define FLAGS_ENCRYPT BIT(0)
75 #define FLAGS_CBC BIT(1)
76 #define FLAGS_INIT BIT(4)
77 #define FLAGS_BUSY BIT(6)
79 #define DEFAULT_AUTOSUSPEND_DELAY 1000
81 #define FLAGS_IN_DATA_ST_SHIFT 8
82 #define FLAGS_OUT_DATA_ST_SHIFT 10
85 struct crypto_engine_ctx enginectx;
86 struct omap_des_dev *dd;
89 u32 key[(3 * DES_KEY_SIZE) / sizeof(u32)];
93 struct omap_des_reqctx {
97 #define OMAP_DES_QUEUE_LENGTH 1
98 #define OMAP_DES_CACHE_SIZE 0
100 struct omap_des_algs_info {
101 struct crypto_alg *algs_list;
103 unsigned int registered;
106 struct omap_des_pdata {
107 struct omap_des_algs_info *algs_info;
108 unsigned int algs_info_size;
110 void (*trigger)(struct omap_des_dev *dd, int length);
131 struct omap_des_dev {
132 struct list_head list;
133 unsigned long phys_base;
134 void __iomem *io_base;
135 struct omap_des_ctx *ctx;
140 struct tasklet_struct done_task;
142 struct ablkcipher_request *req;
143 struct crypto_engine *engine;
145 * total is used by PIO mode for book keeping so introduce
146 * variable total_save as need it to calc page_order
151 struct scatterlist *in_sg;
152 struct scatterlist *out_sg;
154 /* Buffers for copying for unaligned cases */
155 struct scatterlist in_sgl;
156 struct scatterlist out_sgl;
157 struct scatterlist *orig_out;
159 struct scatter_walk in_walk;
160 struct scatter_walk out_walk;
161 struct dma_chan *dma_lch_in;
162 struct dma_chan *dma_lch_out;
166 const struct omap_des_pdata *pdata;
169 /* keep registered devices data here */
170 static LIST_HEAD(dev_list);
171 static DEFINE_SPINLOCK(list_lock);
174 #define omap_des_read(dd, offset) \
177 _read_ret = __raw_readl(dd->io_base + offset); \
178 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \
179 offset, _read_ret); \
183 static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
185 return __raw_readl(dd->io_base + offset);
190 #define omap_des_write(dd, offset, value) \
192 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
194 __raw_writel(value, dd->io_base + offset); \
197 static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
200 __raw_writel(value, dd->io_base + offset);
204 static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
209 val = omap_des_read(dd, offset);
212 omap_des_write(dd, offset, val);
215 static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
216 u32 *value, int count)
218 for (; count--; value++, offset += 4)
219 omap_des_write(dd, offset, *value);
222 static int omap_des_hw_init(struct omap_des_dev *dd)
227 * clocks are enabled when request starts and disabled when finished.
228 * It may be long delays between requests.
229 * Device might go to off mode to save power.
231 err = pm_runtime_get_sync(dd->dev);
233 pm_runtime_put_noidle(dd->dev);
234 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
238 if (!(dd->flags & FLAGS_INIT)) {
239 dd->flags |= FLAGS_INIT;
246 static int omap_des_write_ctrl(struct omap_des_dev *dd)
250 u32 val = 0, mask = 0;
252 err = omap_des_hw_init(dd);
256 key32 = dd->ctx->keylen / sizeof(u32);
258 /* it seems a key should always be set even if it has not changed */
259 for (i = 0; i < key32; i++) {
260 omap_des_write(dd, DES_REG_KEY(dd, i),
261 __le32_to_cpu(dd->ctx->key[i]));
264 if ((dd->flags & FLAGS_CBC) && dd->req->info)
265 omap_des_write_n(dd, DES_REG_IV(dd, 0), dd->req->info, 2);
267 if (dd->flags & FLAGS_CBC)
268 val |= DES_REG_CTRL_CBC;
269 if (dd->flags & FLAGS_ENCRYPT)
270 val |= DES_REG_CTRL_DIRECTION;
272 val |= DES_REG_CTRL_TDES;
274 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
276 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
281 static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
285 omap_des_write(dd, DES_REG_LENGTH_N(0), length);
287 val = dd->pdata->dma_start;
289 if (dd->dma_lch_out != NULL)
290 val |= dd->pdata->dma_enable_out;
291 if (dd->dma_lch_in != NULL)
292 val |= dd->pdata->dma_enable_in;
294 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
295 dd->pdata->dma_start;
297 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
300 static void omap_des_dma_stop(struct omap_des_dev *dd)
304 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
305 dd->pdata->dma_start;
307 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
310 static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
312 struct omap_des_dev *dd = NULL, *tmp;
314 spin_lock_bh(&list_lock);
316 list_for_each_entry(tmp, &dev_list, list) {
317 /* FIXME: take fist available des core */
323 /* already found before */
326 spin_unlock_bh(&list_lock);
331 static void omap_des_dma_out_callback(void *data)
333 struct omap_des_dev *dd = data;
335 /* dma_lch_out - completed */
336 tasklet_schedule(&dd->done_task);
339 static int omap_des_dma_init(struct omap_des_dev *dd)
343 dd->dma_lch_out = NULL;
344 dd->dma_lch_in = NULL;
346 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
347 if (IS_ERR(dd->dma_lch_in)) {
348 dev_err(dd->dev, "Unable to request in DMA channel\n");
349 return PTR_ERR(dd->dma_lch_in);
352 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
353 if (IS_ERR(dd->dma_lch_out)) {
354 dev_err(dd->dev, "Unable to request out DMA channel\n");
355 err = PTR_ERR(dd->dma_lch_out);
362 dma_release_channel(dd->dma_lch_in);
367 static void omap_des_dma_cleanup(struct omap_des_dev *dd)
372 dma_release_channel(dd->dma_lch_out);
373 dma_release_channel(dd->dma_lch_in);
376 static int omap_des_crypt_dma(struct crypto_tfm *tfm,
377 struct scatterlist *in_sg, struct scatterlist *out_sg,
378 int in_sg_len, int out_sg_len)
380 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
381 struct omap_des_dev *dd = ctx->dd;
382 struct dma_async_tx_descriptor *tx_in, *tx_out;
383 struct dma_slave_config cfg;
387 scatterwalk_start(&dd->in_walk, dd->in_sg);
388 scatterwalk_start(&dd->out_walk, dd->out_sg);
390 /* Enable DATAIN interrupt and let it take
392 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
396 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
398 memset(&cfg, 0, sizeof(cfg));
400 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
401 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
402 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
403 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
404 cfg.src_maxburst = DST_MAXBURST;
405 cfg.dst_maxburst = DST_MAXBURST;
408 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
410 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
415 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
417 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
419 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
423 /* No callback necessary */
424 tx_in->callback_param = dd;
427 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
429 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
434 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
436 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
438 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
442 tx_out->callback = omap_des_dma_out_callback;
443 tx_out->callback_param = dd;
445 dmaengine_submit(tx_in);
446 dmaengine_submit(tx_out);
448 dma_async_issue_pending(dd->dma_lch_in);
449 dma_async_issue_pending(dd->dma_lch_out);
452 dd->pdata->trigger(dd, dd->total);
457 static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
459 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
460 crypto_ablkcipher_reqtfm(dd->req));
463 pr_debug("total: %d\n", dd->total);
466 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
469 dev_err(dd->dev, "dma_map_sg() error\n");
473 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
476 dev_err(dd->dev, "dma_map_sg() error\n");
481 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
483 if (err && !dd->pio_only) {
484 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
485 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
492 static void omap_des_finish_req(struct omap_des_dev *dd, int err)
494 struct ablkcipher_request *req = dd->req;
496 pr_debug("err: %d\n", err);
498 crypto_finalize_ablkcipher_request(dd->engine, req, err);
500 pm_runtime_mark_last_busy(dd->dev);
501 pm_runtime_put_autosuspend(dd->dev);
504 static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
506 pr_debug("total: %d\n", dd->total);
508 omap_des_dma_stop(dd);
510 dmaengine_terminate_all(dd->dma_lch_in);
511 dmaengine_terminate_all(dd->dma_lch_out);
516 static int omap_des_handle_queue(struct omap_des_dev *dd,
517 struct ablkcipher_request *req)
520 return crypto_transfer_ablkcipher_request_to_engine(dd->engine, req);
525 static int omap_des_prepare_req(struct crypto_engine *engine,
528 struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base);
529 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
530 crypto_ablkcipher_reqtfm(req));
531 struct omap_des_dev *dd = omap_des_find_dev(ctx);
532 struct omap_des_reqctx *rctx;
539 /* assign new request to device */
541 dd->total = req->nbytes;
542 dd->total_save = req->nbytes;
543 dd->in_sg = req->src;
544 dd->out_sg = req->dst;
545 dd->orig_out = req->dst;
547 flags = OMAP_CRYPTO_COPY_DATA;
548 if (req->src == req->dst)
549 flags |= OMAP_CRYPTO_FORCE_COPY;
551 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, DES_BLOCK_SIZE,
553 FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
557 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, DES_BLOCK_SIZE,
559 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
563 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
564 if (dd->in_sg_len < 0)
565 return dd->in_sg_len;
567 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
568 if (dd->out_sg_len < 0)
569 return dd->out_sg_len;
571 rctx = ablkcipher_request_ctx(req);
572 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
573 rctx->mode &= FLAGS_MODE_MASK;
574 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
579 return omap_des_write_ctrl(dd);
582 static int omap_des_crypt_req(struct crypto_engine *engine,
585 struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base);
586 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
587 crypto_ablkcipher_reqtfm(req));
588 struct omap_des_dev *dd = omap_des_find_dev(ctx);
593 return omap_des_crypt_dma_start(dd);
596 static void omap_des_done_task(unsigned long data)
598 struct omap_des_dev *dd = (struct omap_des_dev *)data;
600 pr_debug("enter done_task\n");
603 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
605 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
606 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
608 omap_des_crypt_dma_stop(dd);
611 omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save,
612 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
614 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
615 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
617 omap_des_finish_req(dd, 0);
622 static int omap_des_crypt(struct ablkcipher_request *req, unsigned long mode)
624 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
625 crypto_ablkcipher_reqtfm(req));
626 struct omap_des_reqctx *rctx = ablkcipher_request_ctx(req);
627 struct omap_des_dev *dd;
629 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
630 !!(mode & FLAGS_ENCRYPT),
631 !!(mode & FLAGS_CBC));
633 if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) {
634 pr_err("request size is not exact amount of DES blocks\n");
638 dd = omap_des_find_dev(ctx);
644 return omap_des_handle_queue(dd, req);
647 /* ********************** ALG API ************************************ */
649 static int omap_des_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
652 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(cipher);
655 pr_debug("enter, keylen: %d\n", keylen);
657 err = verify_ablkcipher_des_key(cipher, key);
661 memcpy(ctx->key, key, keylen);
662 ctx->keylen = keylen;
667 static int omap_des3_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
670 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(cipher);
673 pr_debug("enter, keylen: %d\n", keylen);
675 err = verify_ablkcipher_des3_key(cipher, key);
679 memcpy(ctx->key, key, keylen);
680 ctx->keylen = keylen;
685 static int omap_des_ecb_encrypt(struct ablkcipher_request *req)
687 return omap_des_crypt(req, FLAGS_ENCRYPT);
690 static int omap_des_ecb_decrypt(struct ablkcipher_request *req)
692 return omap_des_crypt(req, 0);
695 static int omap_des_cbc_encrypt(struct ablkcipher_request *req)
697 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
700 static int omap_des_cbc_decrypt(struct ablkcipher_request *req)
702 return omap_des_crypt(req, FLAGS_CBC);
705 static int omap_des_prepare_req(struct crypto_engine *engine,
707 static int omap_des_crypt_req(struct crypto_engine *engine,
710 static int omap_des_cra_init(struct crypto_tfm *tfm)
712 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
716 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_des_reqctx);
718 ctx->enginectx.op.prepare_request = omap_des_prepare_req;
719 ctx->enginectx.op.unprepare_request = NULL;
720 ctx->enginectx.op.do_one_request = omap_des_crypt_req;
725 static void omap_des_cra_exit(struct crypto_tfm *tfm)
730 /* ********************** ALGS ************************************ */
732 static struct crypto_alg algs_ecb_cbc[] = {
734 .cra_name = "ecb(des)",
735 .cra_driver_name = "ecb-des-omap",
737 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
738 CRYPTO_ALG_KERN_DRIVER_ONLY |
740 .cra_blocksize = DES_BLOCK_SIZE,
741 .cra_ctxsize = sizeof(struct omap_des_ctx),
743 .cra_type = &crypto_ablkcipher_type,
744 .cra_module = THIS_MODULE,
745 .cra_init = omap_des_cra_init,
746 .cra_exit = omap_des_cra_exit,
747 .cra_u.ablkcipher = {
748 .min_keysize = DES_KEY_SIZE,
749 .max_keysize = DES_KEY_SIZE,
750 .setkey = omap_des_setkey,
751 .encrypt = omap_des_ecb_encrypt,
752 .decrypt = omap_des_ecb_decrypt,
756 .cra_name = "cbc(des)",
757 .cra_driver_name = "cbc-des-omap",
759 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
760 CRYPTO_ALG_KERN_DRIVER_ONLY |
762 .cra_blocksize = DES_BLOCK_SIZE,
763 .cra_ctxsize = sizeof(struct omap_des_ctx),
765 .cra_type = &crypto_ablkcipher_type,
766 .cra_module = THIS_MODULE,
767 .cra_init = omap_des_cra_init,
768 .cra_exit = omap_des_cra_exit,
769 .cra_u.ablkcipher = {
770 .min_keysize = DES_KEY_SIZE,
771 .max_keysize = DES_KEY_SIZE,
772 .ivsize = DES_BLOCK_SIZE,
773 .setkey = omap_des_setkey,
774 .encrypt = omap_des_cbc_encrypt,
775 .decrypt = omap_des_cbc_decrypt,
779 .cra_name = "ecb(des3_ede)",
780 .cra_driver_name = "ecb-des3-omap",
782 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
783 CRYPTO_ALG_KERN_DRIVER_ONLY |
785 .cra_blocksize = DES_BLOCK_SIZE,
786 .cra_ctxsize = sizeof(struct omap_des_ctx),
788 .cra_type = &crypto_ablkcipher_type,
789 .cra_module = THIS_MODULE,
790 .cra_init = omap_des_cra_init,
791 .cra_exit = omap_des_cra_exit,
792 .cra_u.ablkcipher = {
793 .min_keysize = 3*DES_KEY_SIZE,
794 .max_keysize = 3*DES_KEY_SIZE,
795 .setkey = omap_des3_setkey,
796 .encrypt = omap_des_ecb_encrypt,
797 .decrypt = omap_des_ecb_decrypt,
801 .cra_name = "cbc(des3_ede)",
802 .cra_driver_name = "cbc-des3-omap",
804 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
805 CRYPTO_ALG_KERN_DRIVER_ONLY |
807 .cra_blocksize = DES_BLOCK_SIZE,
808 .cra_ctxsize = sizeof(struct omap_des_ctx),
810 .cra_type = &crypto_ablkcipher_type,
811 .cra_module = THIS_MODULE,
812 .cra_init = omap_des_cra_init,
813 .cra_exit = omap_des_cra_exit,
814 .cra_u.ablkcipher = {
815 .min_keysize = 3*DES_KEY_SIZE,
816 .max_keysize = 3*DES_KEY_SIZE,
817 .ivsize = DES_BLOCK_SIZE,
818 .setkey = omap_des3_setkey,
819 .encrypt = omap_des_cbc_encrypt,
820 .decrypt = omap_des_cbc_decrypt,
825 static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
827 .algs_list = algs_ecb_cbc,
828 .size = ARRAY_SIZE(algs_ecb_cbc),
833 static const struct omap_des_pdata omap_des_pdata_omap4 = {
834 .algs_info = omap_des_algs_info_ecb_cbc,
835 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
836 .trigger = omap_des_dma_trigger_omap4,
843 .irq_status_ofs = 0x3c,
844 .irq_enable_ofs = 0x40,
845 .dma_enable_in = BIT(5),
846 .dma_enable_out = BIT(6),
847 .major_mask = 0x0700,
849 .minor_mask = 0x003f,
853 static irqreturn_t omap_des_irq(int irq, void *dev_id)
855 struct omap_des_dev *dd = dev_id;
859 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
860 if (status & DES_REG_IRQ_DATA_IN) {
861 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
865 BUG_ON(_calc_walked(in) > dd->in_sg->length);
867 src = sg_virt(dd->in_sg) + _calc_walked(in);
869 for (i = 0; i < DES_BLOCK_WORDS; i++) {
870 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
872 scatterwalk_advance(&dd->in_walk, 4);
873 if (dd->in_sg->length == _calc_walked(in)) {
874 dd->in_sg = sg_next(dd->in_sg);
876 scatterwalk_start(&dd->in_walk,
878 src = sg_virt(dd->in_sg) +
886 /* Clear IRQ status */
887 status &= ~DES_REG_IRQ_DATA_IN;
888 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
890 /* Enable DATA_OUT interrupt */
891 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
893 } else if (status & DES_REG_IRQ_DATA_OUT) {
894 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
898 BUG_ON(_calc_walked(out) > dd->out_sg->length);
900 dst = sg_virt(dd->out_sg) + _calc_walked(out);
902 for (i = 0; i < DES_BLOCK_WORDS; i++) {
903 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
904 scatterwalk_advance(&dd->out_walk, 4);
905 if (dd->out_sg->length == _calc_walked(out)) {
906 dd->out_sg = sg_next(dd->out_sg);
908 scatterwalk_start(&dd->out_walk,
910 dst = sg_virt(dd->out_sg) +
918 BUG_ON(dd->total < DES_BLOCK_SIZE);
920 dd->total -= DES_BLOCK_SIZE;
922 /* Clear IRQ status */
923 status &= ~DES_REG_IRQ_DATA_OUT;
924 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
927 /* All bytes read! */
928 tasklet_schedule(&dd->done_task);
930 /* Enable DATA_IN interrupt for next block */
931 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
937 static const struct of_device_id omap_des_of_match[] = {
939 .compatible = "ti,omap4-des",
940 .data = &omap_des_pdata_omap4,
944 MODULE_DEVICE_TABLE(of, omap_des_of_match);
946 static int omap_des_get_of(struct omap_des_dev *dd,
947 struct platform_device *pdev)
950 dd->pdata = of_device_get_match_data(&pdev->dev);
952 dev_err(&pdev->dev, "no compatible OF match\n");
959 static int omap_des_get_of(struct omap_des_dev *dd,
966 static int omap_des_get_pdev(struct omap_des_dev *dd,
967 struct platform_device *pdev)
969 /* non-DT devices get pdata from pdev */
970 dd->pdata = pdev->dev.platform_data;
975 static int omap_des_probe(struct platform_device *pdev)
977 struct device *dev = &pdev->dev;
978 struct omap_des_dev *dd;
979 struct crypto_alg *algp;
980 struct resource *res;
981 int err = -ENOMEM, i, j, irq = -1;
984 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
986 dev_err(dev, "unable to alloc data struct.\n");
990 platform_set_drvdata(pdev, dd);
992 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
994 dev_err(dev, "no MEM resource info\n");
998 err = (dev->of_node) ? omap_des_get_of(dd, pdev) :
999 omap_des_get_pdev(dd, pdev);
1003 dd->io_base = devm_ioremap_resource(dev, res);
1004 if (IS_ERR(dd->io_base)) {
1005 err = PTR_ERR(dd->io_base);
1008 dd->phys_base = res->start;
1010 pm_runtime_use_autosuspend(dev);
1011 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1013 pm_runtime_enable(dev);
1014 err = pm_runtime_get_sync(dev);
1016 pm_runtime_put_noidle(dev);
1017 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
1021 omap_des_dma_stop(dd);
1023 reg = omap_des_read(dd, DES_REG_REV(dd));
1025 pm_runtime_put_sync(dev);
1027 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
1028 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1029 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1031 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd);
1033 err = omap_des_dma_init(dd);
1034 if (err == -EPROBE_DEFER) {
1036 } else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
1039 irq = platform_get_irq(pdev, 0);
1045 err = devm_request_irq(dev, irq, omap_des_irq, 0,
1048 dev_err(dev, "Unable to grab omap-des IRQ\n");
1054 INIT_LIST_HEAD(&dd->list);
1055 spin_lock(&list_lock);
1056 list_add_tail(&dd->list, &dev_list);
1057 spin_unlock(&list_lock);
1059 /* Initialize des crypto engine */
1060 dd->engine = crypto_engine_alloc_init(dev, 1);
1066 err = crypto_engine_start(dd->engine);
1070 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1071 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1072 algp = &dd->pdata->algs_info[i].algs_list[j];
1074 pr_debug("reg alg: %s\n", algp->cra_name);
1076 err = crypto_register_alg(algp);
1080 dd->pdata->algs_info[i].registered++;
1087 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1088 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1089 crypto_unregister_alg(
1090 &dd->pdata->algs_info[i].algs_list[j]);
1094 crypto_engine_exit(dd->engine);
1096 omap_des_dma_cleanup(dd);
1098 tasklet_kill(&dd->done_task);
1100 pm_runtime_disable(dev);
1104 dev_err(dev, "initialization failed.\n");
1108 static int omap_des_remove(struct platform_device *pdev)
1110 struct omap_des_dev *dd = platform_get_drvdata(pdev);
1116 spin_lock(&list_lock);
1117 list_del(&dd->list);
1118 spin_unlock(&list_lock);
1120 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1121 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1122 crypto_unregister_alg(
1123 &dd->pdata->algs_info[i].algs_list[j]);
1125 tasklet_kill(&dd->done_task);
1126 omap_des_dma_cleanup(dd);
1127 pm_runtime_disable(dd->dev);
1133 #ifdef CONFIG_PM_SLEEP
1134 static int omap_des_suspend(struct device *dev)
1136 pm_runtime_put_sync(dev);
1140 static int omap_des_resume(struct device *dev)
1144 err = pm_runtime_get_sync(dev);
1146 pm_runtime_put_noidle(dev);
1147 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err);
1154 static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume);
1156 static struct platform_driver omap_des_driver = {
1157 .probe = omap_des_probe,
1158 .remove = omap_des_remove,
1161 .pm = &omap_des_pm_ops,
1162 .of_match_table = of_match_ptr(omap_des_of_match),
1166 module_platform_driver(omap_des_driver);
1168 MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
1169 MODULE_LICENSE("GPL v2");
1170 MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");