2 * Support for OMAP DES and Triple DES HW acceleration.
4 * Copyright (c) 2013 Texas Instruments Incorporated
5 * Author: Joel Fernandes <joelf@ti.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
13 #define pr_fmt(fmt) "%s: " fmt, __func__
16 #define prn(num) printk(#num "=%d\n", num)
17 #define prx(num) printk(#num "=%x\n", num)
19 #define prn(num) do { } while (0)
20 #define prx(num) do { } while (0)
23 #include <linux/err.h>
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/errno.h>
27 #include <linux/kernel.h>
28 #include <linux/platform_device.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/of_device.h>
35 #include <linux/of_address.h>
37 #include <linux/crypto.h>
38 #include <linux/interrupt.h>
39 #include <crypto/scatterwalk.h>
40 #include <crypto/des.h>
41 #include <crypto/algapi.h>
42 #include <crypto/engine.h>
44 #include "omap-crypto.h"
46 #define DST_MAXBURST 2
48 #define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2)
50 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
52 #define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
55 #define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
57 #define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
58 #define DES_REG_CTRL_CBC BIT(4)
59 #define DES_REG_CTRL_TDES BIT(3)
60 #define DES_REG_CTRL_DIRECTION BIT(2)
61 #define DES_REG_CTRL_INPUT_READY BIT(1)
62 #define DES_REG_CTRL_OUTPUT_READY BIT(0)
64 #define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
66 #define DES_REG_REV(dd) ((dd)->pdata->rev_ofs)
68 #define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
70 #define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04))
72 #define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
73 #define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
74 #define DES_REG_IRQ_DATA_IN BIT(1)
75 #define DES_REG_IRQ_DATA_OUT BIT(2)
77 #define FLAGS_MODE_MASK 0x000f
78 #define FLAGS_ENCRYPT BIT(0)
79 #define FLAGS_CBC BIT(1)
80 #define FLAGS_INIT BIT(4)
81 #define FLAGS_BUSY BIT(6)
83 #define DEFAULT_AUTOSUSPEND_DELAY 1000
85 #define FLAGS_IN_DATA_ST_SHIFT 8
86 #define FLAGS_OUT_DATA_ST_SHIFT 10
89 struct crypto_engine_ctx enginectx;
90 struct omap_des_dev *dd;
93 u32 key[(3 * DES_KEY_SIZE) / sizeof(u32)];
97 struct omap_des_reqctx {
101 #define OMAP_DES_QUEUE_LENGTH 1
102 #define OMAP_DES_CACHE_SIZE 0
104 struct omap_des_algs_info {
105 struct crypto_alg *algs_list;
107 unsigned int registered;
110 struct omap_des_pdata {
111 struct omap_des_algs_info *algs_info;
112 unsigned int algs_info_size;
114 void (*trigger)(struct omap_des_dev *dd, int length);
135 struct omap_des_dev {
136 struct list_head list;
137 unsigned long phys_base;
138 void __iomem *io_base;
139 struct omap_des_ctx *ctx;
144 struct tasklet_struct done_task;
146 struct ablkcipher_request *req;
147 struct crypto_engine *engine;
149 * total is used by PIO mode for book keeping so introduce
150 * variable total_save as need it to calc page_order
155 struct scatterlist *in_sg;
156 struct scatterlist *out_sg;
158 /* Buffers for copying for unaligned cases */
159 struct scatterlist in_sgl;
160 struct scatterlist out_sgl;
161 struct scatterlist *orig_out;
163 struct scatter_walk in_walk;
164 struct scatter_walk out_walk;
165 struct dma_chan *dma_lch_in;
166 struct dma_chan *dma_lch_out;
170 const struct omap_des_pdata *pdata;
173 /* keep registered devices data here */
174 static LIST_HEAD(dev_list);
175 static DEFINE_SPINLOCK(list_lock);
178 #define omap_des_read(dd, offset) \
181 _read_ret = __raw_readl(dd->io_base + offset); \
182 pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \
183 offset, _read_ret); \
187 static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
189 return __raw_readl(dd->io_base + offset);
194 #define omap_des_write(dd, offset, value) \
196 pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
198 __raw_writel(value, dd->io_base + offset); \
201 static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
204 __raw_writel(value, dd->io_base + offset);
208 static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
213 val = omap_des_read(dd, offset);
216 omap_des_write(dd, offset, val);
219 static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
220 u32 *value, int count)
222 for (; count--; value++, offset += 4)
223 omap_des_write(dd, offset, *value);
226 static int omap_des_hw_init(struct omap_des_dev *dd)
231 * clocks are enabled when request starts and disabled when finished.
232 * It may be long delays between requests.
233 * Device might go to off mode to save power.
235 err = pm_runtime_get_sync(dd->dev);
237 pm_runtime_put_noidle(dd->dev);
238 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
242 if (!(dd->flags & FLAGS_INIT)) {
243 dd->flags |= FLAGS_INIT;
250 static int omap_des_write_ctrl(struct omap_des_dev *dd)
254 u32 val = 0, mask = 0;
256 err = omap_des_hw_init(dd);
260 key32 = dd->ctx->keylen / sizeof(u32);
262 /* it seems a key should always be set even if it has not changed */
263 for (i = 0; i < key32; i++) {
264 omap_des_write(dd, DES_REG_KEY(dd, i),
265 __le32_to_cpu(dd->ctx->key[i]));
268 if ((dd->flags & FLAGS_CBC) && dd->req->info)
269 omap_des_write_n(dd, DES_REG_IV(dd, 0), dd->req->info, 2);
271 if (dd->flags & FLAGS_CBC)
272 val |= DES_REG_CTRL_CBC;
273 if (dd->flags & FLAGS_ENCRYPT)
274 val |= DES_REG_CTRL_DIRECTION;
276 val |= DES_REG_CTRL_TDES;
278 mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
280 omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
285 static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
289 omap_des_write(dd, DES_REG_LENGTH_N(0), length);
291 val = dd->pdata->dma_start;
293 if (dd->dma_lch_out != NULL)
294 val |= dd->pdata->dma_enable_out;
295 if (dd->dma_lch_in != NULL)
296 val |= dd->pdata->dma_enable_in;
298 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
299 dd->pdata->dma_start;
301 omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
304 static void omap_des_dma_stop(struct omap_des_dev *dd)
308 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
309 dd->pdata->dma_start;
311 omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
314 static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
316 struct omap_des_dev *dd = NULL, *tmp;
318 spin_lock_bh(&list_lock);
320 list_for_each_entry(tmp, &dev_list, list) {
321 /* FIXME: take fist available des core */
327 /* already found before */
330 spin_unlock_bh(&list_lock);
335 static void omap_des_dma_out_callback(void *data)
337 struct omap_des_dev *dd = data;
339 /* dma_lch_out - completed */
340 tasklet_schedule(&dd->done_task);
343 static int omap_des_dma_init(struct omap_des_dev *dd)
347 dd->dma_lch_out = NULL;
348 dd->dma_lch_in = NULL;
350 dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
351 if (IS_ERR(dd->dma_lch_in)) {
352 dev_err(dd->dev, "Unable to request in DMA channel\n");
353 return PTR_ERR(dd->dma_lch_in);
356 dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
357 if (IS_ERR(dd->dma_lch_out)) {
358 dev_err(dd->dev, "Unable to request out DMA channel\n");
359 err = PTR_ERR(dd->dma_lch_out);
366 dma_release_channel(dd->dma_lch_in);
371 static void omap_des_dma_cleanup(struct omap_des_dev *dd)
376 dma_release_channel(dd->dma_lch_out);
377 dma_release_channel(dd->dma_lch_in);
380 static int omap_des_crypt_dma(struct crypto_tfm *tfm,
381 struct scatterlist *in_sg, struct scatterlist *out_sg,
382 int in_sg_len, int out_sg_len)
384 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
385 struct omap_des_dev *dd = ctx->dd;
386 struct dma_async_tx_descriptor *tx_in, *tx_out;
387 struct dma_slave_config cfg;
391 scatterwalk_start(&dd->in_walk, dd->in_sg);
392 scatterwalk_start(&dd->out_walk, dd->out_sg);
394 /* Enable DATAIN interrupt and let it take
396 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
400 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
402 memset(&cfg, 0, sizeof(cfg));
404 cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
405 cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
406 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
407 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
408 cfg.src_maxburst = DST_MAXBURST;
409 cfg.dst_maxburst = DST_MAXBURST;
412 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
414 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
419 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
421 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
423 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
427 /* No callback necessary */
428 tx_in->callback_param = dd;
431 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
433 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
438 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
440 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
442 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
446 tx_out->callback = omap_des_dma_out_callback;
447 tx_out->callback_param = dd;
449 dmaengine_submit(tx_in);
450 dmaengine_submit(tx_out);
452 dma_async_issue_pending(dd->dma_lch_in);
453 dma_async_issue_pending(dd->dma_lch_out);
456 dd->pdata->trigger(dd, dd->total);
461 static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
463 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
464 crypto_ablkcipher_reqtfm(dd->req));
467 pr_debug("total: %d\n", dd->total);
470 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
473 dev_err(dd->dev, "dma_map_sg() error\n");
477 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
480 dev_err(dd->dev, "dma_map_sg() error\n");
485 err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
487 if (err && !dd->pio_only) {
488 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
489 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
496 static void omap_des_finish_req(struct omap_des_dev *dd, int err)
498 struct ablkcipher_request *req = dd->req;
500 pr_debug("err: %d\n", err);
502 crypto_finalize_ablkcipher_request(dd->engine, req, err);
504 pm_runtime_mark_last_busy(dd->dev);
505 pm_runtime_put_autosuspend(dd->dev);
508 static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
510 pr_debug("total: %d\n", dd->total);
512 omap_des_dma_stop(dd);
514 dmaengine_terminate_all(dd->dma_lch_in);
515 dmaengine_terminate_all(dd->dma_lch_out);
520 static int omap_des_handle_queue(struct omap_des_dev *dd,
521 struct ablkcipher_request *req)
524 return crypto_transfer_ablkcipher_request_to_engine(dd->engine, req);
529 static int omap_des_prepare_req(struct crypto_engine *engine,
532 struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base);
533 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
534 crypto_ablkcipher_reqtfm(req));
535 struct omap_des_dev *dd = omap_des_find_dev(ctx);
536 struct omap_des_reqctx *rctx;
543 /* assign new request to device */
545 dd->total = req->nbytes;
546 dd->total_save = req->nbytes;
547 dd->in_sg = req->src;
548 dd->out_sg = req->dst;
549 dd->orig_out = req->dst;
551 flags = OMAP_CRYPTO_COPY_DATA;
552 if (req->src == req->dst)
553 flags |= OMAP_CRYPTO_FORCE_COPY;
555 ret = omap_crypto_align_sg(&dd->in_sg, dd->total, DES_BLOCK_SIZE,
557 FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
561 ret = omap_crypto_align_sg(&dd->out_sg, dd->total, DES_BLOCK_SIZE,
563 FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
567 dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
568 if (dd->in_sg_len < 0)
569 return dd->in_sg_len;
571 dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
572 if (dd->out_sg_len < 0)
573 return dd->out_sg_len;
575 rctx = ablkcipher_request_ctx(req);
576 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
577 rctx->mode &= FLAGS_MODE_MASK;
578 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
583 return omap_des_write_ctrl(dd);
586 static int omap_des_crypt_req(struct crypto_engine *engine,
589 struct ablkcipher_request *req = container_of(areq, struct ablkcipher_request, base);
590 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
591 crypto_ablkcipher_reqtfm(req));
592 struct omap_des_dev *dd = omap_des_find_dev(ctx);
597 return omap_des_crypt_dma_start(dd);
600 static void omap_des_done_task(unsigned long data)
602 struct omap_des_dev *dd = (struct omap_des_dev *)data;
604 pr_debug("enter done_task\n");
607 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
609 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
610 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
612 omap_des_crypt_dma_stop(dd);
615 omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save,
616 FLAGS_IN_DATA_ST_SHIFT, dd->flags);
618 omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
619 FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
621 omap_des_finish_req(dd, 0);
626 static int omap_des_crypt(struct ablkcipher_request *req, unsigned long mode)
628 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(
629 crypto_ablkcipher_reqtfm(req));
630 struct omap_des_reqctx *rctx = ablkcipher_request_ctx(req);
631 struct omap_des_dev *dd;
633 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
634 !!(mode & FLAGS_ENCRYPT),
635 !!(mode & FLAGS_CBC));
637 if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) {
638 pr_err("request size is not exact amount of DES blocks\n");
642 dd = omap_des_find_dev(ctx);
648 return omap_des_handle_queue(dd, req);
651 /* ********************** ALG API ************************************ */
653 static int omap_des_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
656 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(cipher);
657 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
659 pr_debug("enter, keylen: %d\n", keylen);
661 /* Do we need to test against weak key? */
662 if (tfm->crt_flags & CRYPTO_TFM_REQ_FORBID_WEAK_KEYS) {
663 u32 tmp[DES_EXPKEY_WORDS];
664 int ret = des_ekey(tmp, key);
667 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
672 memcpy(ctx->key, key, keylen);
673 ctx->keylen = keylen;
678 static int omap_des3_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
681 struct omap_des_ctx *ctx = crypto_ablkcipher_ctx(cipher);
685 pr_debug("enter, keylen: %d\n", keylen);
687 flags = crypto_ablkcipher_get_flags(cipher);
688 err = __des3_verify_key(&flags, key);
690 crypto_ablkcipher_set_flags(cipher, flags);
694 memcpy(ctx->key, key, keylen);
695 ctx->keylen = keylen;
700 static int omap_des_ecb_encrypt(struct ablkcipher_request *req)
702 return omap_des_crypt(req, FLAGS_ENCRYPT);
705 static int omap_des_ecb_decrypt(struct ablkcipher_request *req)
707 return omap_des_crypt(req, 0);
710 static int omap_des_cbc_encrypt(struct ablkcipher_request *req)
712 return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
715 static int omap_des_cbc_decrypt(struct ablkcipher_request *req)
717 return omap_des_crypt(req, FLAGS_CBC);
720 static int omap_des_prepare_req(struct crypto_engine *engine,
722 static int omap_des_crypt_req(struct crypto_engine *engine,
725 static int omap_des_cra_init(struct crypto_tfm *tfm)
727 struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
731 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_des_reqctx);
733 ctx->enginectx.op.prepare_request = omap_des_prepare_req;
734 ctx->enginectx.op.unprepare_request = NULL;
735 ctx->enginectx.op.do_one_request = omap_des_crypt_req;
740 static void omap_des_cra_exit(struct crypto_tfm *tfm)
745 /* ********************** ALGS ************************************ */
747 static struct crypto_alg algs_ecb_cbc[] = {
749 .cra_name = "ecb(des)",
750 .cra_driver_name = "ecb-des-omap",
752 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
753 CRYPTO_ALG_KERN_DRIVER_ONLY |
755 .cra_blocksize = DES_BLOCK_SIZE,
756 .cra_ctxsize = sizeof(struct omap_des_ctx),
758 .cra_type = &crypto_ablkcipher_type,
759 .cra_module = THIS_MODULE,
760 .cra_init = omap_des_cra_init,
761 .cra_exit = omap_des_cra_exit,
762 .cra_u.ablkcipher = {
763 .min_keysize = DES_KEY_SIZE,
764 .max_keysize = DES_KEY_SIZE,
765 .setkey = omap_des_setkey,
766 .encrypt = omap_des_ecb_encrypt,
767 .decrypt = omap_des_ecb_decrypt,
771 .cra_name = "cbc(des)",
772 .cra_driver_name = "cbc-des-omap",
774 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
775 CRYPTO_ALG_KERN_DRIVER_ONLY |
777 .cra_blocksize = DES_BLOCK_SIZE,
778 .cra_ctxsize = sizeof(struct omap_des_ctx),
780 .cra_type = &crypto_ablkcipher_type,
781 .cra_module = THIS_MODULE,
782 .cra_init = omap_des_cra_init,
783 .cra_exit = omap_des_cra_exit,
784 .cra_u.ablkcipher = {
785 .min_keysize = DES_KEY_SIZE,
786 .max_keysize = DES_KEY_SIZE,
787 .ivsize = DES_BLOCK_SIZE,
788 .setkey = omap_des_setkey,
789 .encrypt = omap_des_cbc_encrypt,
790 .decrypt = omap_des_cbc_decrypt,
794 .cra_name = "ecb(des3_ede)",
795 .cra_driver_name = "ecb-des3-omap",
797 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
798 CRYPTO_ALG_KERN_DRIVER_ONLY |
800 .cra_blocksize = DES_BLOCK_SIZE,
801 .cra_ctxsize = sizeof(struct omap_des_ctx),
803 .cra_type = &crypto_ablkcipher_type,
804 .cra_module = THIS_MODULE,
805 .cra_init = omap_des_cra_init,
806 .cra_exit = omap_des_cra_exit,
807 .cra_u.ablkcipher = {
808 .min_keysize = 3*DES_KEY_SIZE,
809 .max_keysize = 3*DES_KEY_SIZE,
810 .setkey = omap_des3_setkey,
811 .encrypt = omap_des_ecb_encrypt,
812 .decrypt = omap_des_ecb_decrypt,
816 .cra_name = "cbc(des3_ede)",
817 .cra_driver_name = "cbc-des3-omap",
819 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
820 CRYPTO_ALG_KERN_DRIVER_ONLY |
822 .cra_blocksize = DES_BLOCK_SIZE,
823 .cra_ctxsize = sizeof(struct omap_des_ctx),
825 .cra_type = &crypto_ablkcipher_type,
826 .cra_module = THIS_MODULE,
827 .cra_init = omap_des_cra_init,
828 .cra_exit = omap_des_cra_exit,
829 .cra_u.ablkcipher = {
830 .min_keysize = 3*DES_KEY_SIZE,
831 .max_keysize = 3*DES_KEY_SIZE,
832 .ivsize = DES_BLOCK_SIZE,
833 .setkey = omap_des3_setkey,
834 .encrypt = omap_des_cbc_encrypt,
835 .decrypt = omap_des_cbc_decrypt,
840 static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
842 .algs_list = algs_ecb_cbc,
843 .size = ARRAY_SIZE(algs_ecb_cbc),
848 static const struct omap_des_pdata omap_des_pdata_omap4 = {
849 .algs_info = omap_des_algs_info_ecb_cbc,
850 .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
851 .trigger = omap_des_dma_trigger_omap4,
858 .irq_status_ofs = 0x3c,
859 .irq_enable_ofs = 0x40,
860 .dma_enable_in = BIT(5),
861 .dma_enable_out = BIT(6),
862 .major_mask = 0x0700,
864 .minor_mask = 0x003f,
868 static irqreturn_t omap_des_irq(int irq, void *dev_id)
870 struct omap_des_dev *dd = dev_id;
874 status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
875 if (status & DES_REG_IRQ_DATA_IN) {
876 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
880 BUG_ON(_calc_walked(in) > dd->in_sg->length);
882 src = sg_virt(dd->in_sg) + _calc_walked(in);
884 for (i = 0; i < DES_BLOCK_WORDS; i++) {
885 omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
887 scatterwalk_advance(&dd->in_walk, 4);
888 if (dd->in_sg->length == _calc_walked(in)) {
889 dd->in_sg = sg_next(dd->in_sg);
891 scatterwalk_start(&dd->in_walk,
893 src = sg_virt(dd->in_sg) +
901 /* Clear IRQ status */
902 status &= ~DES_REG_IRQ_DATA_IN;
903 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
905 /* Enable DATA_OUT interrupt */
906 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
908 } else if (status & DES_REG_IRQ_DATA_OUT) {
909 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
913 BUG_ON(_calc_walked(out) > dd->out_sg->length);
915 dst = sg_virt(dd->out_sg) + _calc_walked(out);
917 for (i = 0; i < DES_BLOCK_WORDS; i++) {
918 *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
919 scatterwalk_advance(&dd->out_walk, 4);
920 if (dd->out_sg->length == _calc_walked(out)) {
921 dd->out_sg = sg_next(dd->out_sg);
923 scatterwalk_start(&dd->out_walk,
925 dst = sg_virt(dd->out_sg) +
933 BUG_ON(dd->total < DES_BLOCK_SIZE);
935 dd->total -= DES_BLOCK_SIZE;
937 /* Clear IRQ status */
938 status &= ~DES_REG_IRQ_DATA_OUT;
939 omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
942 /* All bytes read! */
943 tasklet_schedule(&dd->done_task);
945 /* Enable DATA_IN interrupt for next block */
946 omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
952 static const struct of_device_id omap_des_of_match[] = {
954 .compatible = "ti,omap4-des",
955 .data = &omap_des_pdata_omap4,
959 MODULE_DEVICE_TABLE(of, omap_des_of_match);
961 static int omap_des_get_of(struct omap_des_dev *dd,
962 struct platform_device *pdev)
965 dd->pdata = of_device_get_match_data(&pdev->dev);
967 dev_err(&pdev->dev, "no compatible OF match\n");
974 static int omap_des_get_of(struct omap_des_dev *dd,
981 static int omap_des_get_pdev(struct omap_des_dev *dd,
982 struct platform_device *pdev)
984 /* non-DT devices get pdata from pdev */
985 dd->pdata = pdev->dev.platform_data;
990 static int omap_des_probe(struct platform_device *pdev)
992 struct device *dev = &pdev->dev;
993 struct omap_des_dev *dd;
994 struct crypto_alg *algp;
995 struct resource *res;
996 int err = -ENOMEM, i, j, irq = -1;
999 dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
1001 dev_err(dev, "unable to alloc data struct.\n");
1005 platform_set_drvdata(pdev, dd);
1007 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1009 dev_err(dev, "no MEM resource info\n");
1013 err = (dev->of_node) ? omap_des_get_of(dd, pdev) :
1014 omap_des_get_pdev(dd, pdev);
1018 dd->io_base = devm_ioremap_resource(dev, res);
1019 if (IS_ERR(dd->io_base)) {
1020 err = PTR_ERR(dd->io_base);
1023 dd->phys_base = res->start;
1025 pm_runtime_use_autosuspend(dev);
1026 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1028 pm_runtime_enable(dev);
1029 err = pm_runtime_get_sync(dev);
1031 pm_runtime_put_noidle(dev);
1032 dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
1036 omap_des_dma_stop(dd);
1038 reg = omap_des_read(dd, DES_REG_REV(dd));
1040 pm_runtime_put_sync(dev);
1042 dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
1043 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1044 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1046 tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd);
1048 err = omap_des_dma_init(dd);
1049 if (err == -EPROBE_DEFER) {
1051 } else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
1054 irq = platform_get_irq(pdev, 0);
1056 dev_err(dev, "can't get IRQ resource: %d\n", irq);
1061 err = devm_request_irq(dev, irq, omap_des_irq, 0,
1064 dev_err(dev, "Unable to grab omap-des IRQ\n");
1070 INIT_LIST_HEAD(&dd->list);
1071 spin_lock(&list_lock);
1072 list_add_tail(&dd->list, &dev_list);
1073 spin_unlock(&list_lock);
1075 /* Initialize des crypto engine */
1076 dd->engine = crypto_engine_alloc_init(dev, 1);
1082 err = crypto_engine_start(dd->engine);
1086 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1087 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1088 algp = &dd->pdata->algs_info[i].algs_list[j];
1090 pr_debug("reg alg: %s\n", algp->cra_name);
1092 err = crypto_register_alg(algp);
1096 dd->pdata->algs_info[i].registered++;
1103 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1104 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1105 crypto_unregister_alg(
1106 &dd->pdata->algs_info[i].algs_list[j]);
1110 crypto_engine_exit(dd->engine);
1112 omap_des_dma_cleanup(dd);
1114 tasklet_kill(&dd->done_task);
1116 pm_runtime_disable(dev);
1120 dev_err(dev, "initialization failed.\n");
1124 static int omap_des_remove(struct platform_device *pdev)
1126 struct omap_des_dev *dd = platform_get_drvdata(pdev);
1132 spin_lock(&list_lock);
1133 list_del(&dd->list);
1134 spin_unlock(&list_lock);
1136 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1137 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1138 crypto_unregister_alg(
1139 &dd->pdata->algs_info[i].algs_list[j]);
1141 tasklet_kill(&dd->done_task);
1142 omap_des_dma_cleanup(dd);
1143 pm_runtime_disable(dd->dev);
1149 #ifdef CONFIG_PM_SLEEP
1150 static int omap_des_suspend(struct device *dev)
1152 pm_runtime_put_sync(dev);
1156 static int omap_des_resume(struct device *dev)
1160 err = pm_runtime_get_sync(dev);
1162 pm_runtime_put_noidle(dev);
1163 dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err);
1170 static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume);
1172 static struct platform_driver omap_des_driver = {
1173 .probe = omap_des_probe,
1174 .remove = omap_des_remove,
1177 .pm = &omap_des_pm_ops,
1178 .of_match_table = of_match_ptr(omap_des_of_match),
1182 module_platform_driver(omap_des_driver);
1184 MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
1185 MODULE_LICENSE("GPL v2");
1186 MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");