drivers/crypto/omap-aes.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Cryptographic API.
   4  *
   5  * Support for OMAP AES HW acceleration.
   6  *
   7  * Copyright (c) 2010 Nokia Corporation
   8  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   9  * Copyright (c) 2011 Texas Instruments Incorporated
  10  */
  11
  12 #define pr_fmt(fmt) "%20s: " fmt, __func__
  13 #define prn(num) pr_debug(#num "=%d\n", num)
  14 #define prx(num) pr_debug(#num "=%x\n", num)
  15
  16 #include <linux/err.h>
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/errno.h>
  20 #include <linux/kernel.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/dmaengine.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/of_address.h>
  29 #include <linux/io.h>
  30 #include <linux/crypto.h>
  31 #include <linux/interrupt.h>
  32 #include <crypto/scatterwalk.h>
  33 #include <crypto/aes.h>
  34 #include <crypto/gcm.h>
  35 #include <crypto/engine.h>
  36 #include <crypto/internal/skcipher.h>
  37 #include <crypto/internal/aead.h>
  38
  39 #include "omap-crypto.h"
  40 #include "omap-aes.h"
  41
  42 /* keep registered devices data here */
  43 static LIST_HEAD(dev_list);
  44 static DEFINE_SPINLOCK(list_lock);
  45
  46 static int aes_fallback_sz = 200;
  47
  48 #ifdef DEBUG
  49 #define omap_aes_read(dd, offset)                               \
  50 ({                                                              \
  51         int _read_ret;                                          \
  52         _read_ret = __raw_readl(dd->io_base + offset);          \
  53         pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n",       \
  54                  offset, _read_ret);                            \
  55         _read_ret;                                              \
  56 })
  57 #else
  58 inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
  59 {
  60         return __raw_readl(dd->io_base + offset);
  61 }
  62 #endif
  63
  64 #ifdef DEBUG
  65 #define omap_aes_write(dd, offset, value)                               \
  66         do {                                                            \
  67                 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
  68                          offset, value);                                \
  69                 __raw_writel(value, dd->io_base + offset);              \
  70         } while (0)
  71 #else
  72 inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
  73                                   u32 value)
  74 {
  75         __raw_writel(value, dd->io_base + offset);
  76 }
  77 #endif
  78
  79 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
  80                                         u32 value, u32 mask)
  81 {
  82         u32 val;
  83
  84         val = omap_aes_read(dd, offset);
  85         val &= ~mask;
  86         val |= value;
  87         omap_aes_write(dd, offset, val);
  88 }
  89
  90 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
  91                                         u32 *value, int count)
  92 {
  93         for (; count--; value++, offset += 4)
  94                 omap_aes_write(dd, offset, *value);
  95 }
  96
  97 static int omap_aes_hw_init(struct omap_aes_dev *dd)
  98 {
  99         int err;
 100
 101         if (!(dd->flags & FLAGS_INIT)) {
 102                 dd->flags |= FLAGS_INIT;
 103                 dd->err = 0;
 104         }
 105
 106         err = pm_runtime_get_sync(dd->dev);
 107         if (err < 0) {
 108                 dev_err(dd->dev, "failed to get sync: %d\n", err);
 109                 return err;
 110         }
 111
 112         return 0;
 113 }
 114
 115 void omap_aes_clear_copy_flags(struct omap_aes_dev *dd)
 116 {
 117         dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT);
 118         dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT);
 119         dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT);
 120 }
 121
 122 int omap_aes_write_ctrl(struct omap_aes_dev *dd)
 123 {
 124         struct omap_aes_reqctx *rctx;
 125         unsigned int key32;
 126         int i, err;
 127         u32 val;
 128
 129         err = omap_aes_hw_init(dd);
 130         if (err)
 131                 return err;
 132
 133         key32 = dd->ctx->keylen / sizeof(u32);
 134
 135         /* RESET the key as previous HASH keys should not get affected*/
 136         if (dd->flags & FLAGS_GCM)
 137                 for (i = 0; i < 0x40; i = i + 4)
 138                         omap_aes_write(dd, i, 0x0);
 139
 140         for (i = 0; i < key32; i++) {
 141                 omap_aes_write(dd, AES_REG_KEY(dd, i),
 142                         __le32_to_cpu(dd->ctx->key[i]));
 143         }
 144
 145         if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->iv)
 146                 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (void *)dd->req->iv, 4);
 147
 148         if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) {
 149                 rctx = aead_request_ctx(dd->aead_req);
 150                 omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4);
 151         }
 152
 153         val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
 154         if (dd->flags & FLAGS_CBC)
 155                 val |= AES_REG_CTRL_CBC;
 156
 157         if (dd->flags & (FLAGS_CTR | FLAGS_GCM))
 158                 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
 159
 160         if (dd->flags & FLAGS_GCM)
 161                 val |= AES_REG_CTRL_GCM;
 162
 163         if (dd->flags & FLAGS_ENCRYPT)
 164                 val |= AES_REG_CTRL_DIRECTION;
 165
 166         omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK);
 167
 168         return 0;
 169 }
 170
 171 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
 172 {
 173         u32 mask, val;
 174
 175         val = dd->pdata->dma_start;
 176
 177         if (dd->dma_lch_out != NULL)
 178                 val |= dd->pdata->dma_enable_out;
 179         if (dd->dma_lch_in != NULL)
 180                 val |= dd->pdata->dma_enable_in;
 181
 182         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 183                dd->pdata->dma_start;
 184
 185         omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
 186
 187 }
 188
 189 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
 190 {
 191         omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
 192         omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
 193         if (dd->flags & FLAGS_GCM)
 194                 omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len);
 195
 196         omap_aes_dma_trigger_omap2(dd, length);
 197 }
 198
 199 static void omap_aes_dma_stop(struct omap_aes_dev *dd)
 200 {
 201         u32 mask;
 202
 203         mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
 204                dd->pdata->dma_start;
 205
 206         omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
 207 }
 208
 209 struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx)
 210 {
 211         struct omap_aes_dev *dd;
 212
 213         spin_lock_bh(&list_lock);
 214         dd = list_first_entry(&dev_list, struct omap_aes_dev, list);
 215         list_move_tail(&dd->list, &dev_list);
 216         rctx->dd = dd;
 217         spin_unlock_bh(&list_lock);
 218
 219         return dd;
 220 }
 221
 222 static void omap_aes_dma_out_callback(void *data)
 223 {
 224         struct omap_aes_dev *dd = data;
 225
 226         /* dma_lch_out - completed */
 227         tasklet_schedule(&dd->done_task);
 228 }
 229
 230 static int omap_aes_dma_init(struct omap_aes_dev *dd)
 231 {
 232         int err;
 233
 234         dd->dma_lch_out = NULL;
 235         dd->dma_lch_in = NULL;
 236
 237         dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
 238         if (IS_ERR(dd->dma_lch_in)) {
 239                 dev_err(dd->dev, "Unable to request in DMA channel\n");
 240                 return PTR_ERR(dd->dma_lch_in);
 241         }
 242
 243         dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
 244         if (IS_ERR(dd->dma_lch_out)) {
 245                 dev_err(dd->dev, "Unable to request out DMA channel\n");
 246                 err = PTR_ERR(dd->dma_lch_out);
 247                 goto err_dma_out;
 248         }
 249
 250         return 0;
 251
 252 err_dma_out:
 253         dma_release_channel(dd->dma_lch_in);
 254
 255         return err;
 256 }
 257
 258 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
 259 {
 260         if (dd->pio_only)
 261                 return;
 262
 263         dma_release_channel(dd->dma_lch_out);
 264         dma_release_channel(dd->dma_lch_in);
 265 }
 266
 267 static int omap_aes_crypt_dma(struct omap_aes_dev *dd,
 268                               struct scatterlist *in_sg,
 269                               struct scatterlist *out_sg,
 270                               int in_sg_len, int out_sg_len)
 271 {
 272         struct dma_async_tx_descriptor *tx_in, *tx_out;
 273         struct dma_slave_config cfg;
 274         int ret;
 275
 276         if (dd->pio_only) {
 277                 scatterwalk_start(&dd->in_walk, dd->in_sg);
 278                 scatterwalk_start(&dd->out_walk, dd->out_sg);
 279
 280                 /* Enable DATAIN interrupt and let it take
 281                    care of the rest */
 282                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
 283                 return 0;
 284         }
 285
 286         dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
 287
 288         memset(&cfg, 0, sizeof(cfg));
 289
 290         cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 291         cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
 292         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 293         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 294         cfg.src_maxburst = DST_MAXBURST;
 295         cfg.dst_maxburst = DST_MAXBURST;
 296
 297         /* IN */
 298         ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
 299         if (ret) {
 300                 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
 301                         ret);
 302                 return ret;
 303         }
 304
 305         tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
 306                                         DMA_MEM_TO_DEV,
 307                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 308         if (!tx_in) {
 309                 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
 310                 return -EINVAL;
 311         }
 312
 313         /* No callback necessary */
 314         tx_in->callback_param = dd;
 315
 316         /* OUT */
 317         ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
 318         if (ret) {
 319                 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
 320                         ret);
 321                 return ret;
 322         }
 323
 324         tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
 325                                         DMA_DEV_TO_MEM,
 326                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 327         if (!tx_out) {
 328                 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
 329                 return -EINVAL;
 330         }
 331
 332         if (dd->flags & FLAGS_GCM)
 333                 tx_out->callback = omap_aes_gcm_dma_out_callback;
 334         else
 335                 tx_out->callback = omap_aes_dma_out_callback;
 336         tx_out->callback_param = dd;
 337
 338         dmaengine_submit(tx_in);
 339         dmaengine_submit(tx_out);
 340
 341         dma_async_issue_pending(dd->dma_lch_in);
 342         dma_async_issue_pending(dd->dma_lch_out);
 343
 344         /* start DMA */
 345         dd->pdata->trigger(dd, dd->total);
 346
 347         return 0;
 348 }
 349
 350 int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
 351 {
 352         int err;
 353
 354         pr_debug("total: %d\n", dd->total);
 355
 356         if (!dd->pio_only) {
 357                 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
 358                                  DMA_TO_DEVICE);
 359                 if (!err) {
 360                         dev_err(dd->dev, "dma_map_sg() error\n");
 361                         return -EINVAL;
 362                 }
 363
 364                 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 365                                  DMA_FROM_DEVICE);
 366                 if (!err) {
 367                         dev_err(dd->dev, "dma_map_sg() error\n");
 368                         return -EINVAL;
 369                 }
 370         }
 371
 372         err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len,
 373                                  dd->out_sg_len);
 374         if (err && !dd->pio_only) {
 375                 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 376                 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 377                              DMA_FROM_DEVICE);
 378         }
 379
 380         return err;
 381 }
 382
 383 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
 384 {
 385         struct skcipher_request *req = dd->req;
 386
 387         pr_debug("err: %d\n", err);
 388
 389         crypto_finalize_skcipher_request(dd->engine, req, err);
 390
 391         pm_runtime_mark_last_busy(dd->dev);
 392         pm_runtime_put_autosuspend(dd->dev);
 393 }
 394
 395 int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
 396 {
 397         pr_debug("total: %d\n", dd->total);
 398
 399         omap_aes_dma_stop(dd);
 400
 401
 402         return 0;
 403 }
 404
 405 static int omap_aes_handle_queue(struct omap_aes_dev *dd,
 406                                  struct skcipher_request *req)
 407 {
 408         if (req)
 409                 return crypto_transfer_skcipher_request_to_engine(dd->engine, req);
 410
 411         return 0;
 412 }
 413
 414 static int omap_aes_prepare_req(struct crypto_engine *engine,
 415                                 void *areq)
 416 {
 417         struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
 418         struct omap_aes_ctx *ctx = crypto_skcipher_ctx(
 419                         crypto_skcipher_reqtfm(req));
 420         struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
 421         struct omap_aes_dev *dd = rctx->dd;
 422         int ret;
 423         u16 flags;
 424
 425         if (!dd)
 426                 return -ENODEV;
 427
 428         /* assign new request to device */
 429         dd->req = req;
 430         dd->total = req->cryptlen;
 431         dd->total_save = req->cryptlen;
 432         dd->in_sg = req->src;
 433         dd->out_sg = req->dst;
 434         dd->orig_out = req->dst;
 435
 436         flags = OMAP_CRYPTO_COPY_DATA;
 437         if (req->src == req->dst)
 438                 flags |= OMAP_CRYPTO_FORCE_COPY;
 439
 440         ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE,
 441                                    dd->in_sgl, flags,
 442                                    FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
 443         if (ret)
 444                 return ret;
 445
 446         ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE,
 447                                    &dd->out_sgl, 0,
 448                                    FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
 449         if (ret)
 450                 return ret;
 451
 452         dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
 453         if (dd->in_sg_len < 0)
 454                 return dd->in_sg_len;
 455
 456         dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
 457         if (dd->out_sg_len < 0)
 458                 return dd->out_sg_len;
 459
 460         rctx->mode &= FLAGS_MODE_MASK;
 461         dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
 462
 463         dd->ctx = ctx;
 464         rctx->dd = dd;
 465
 466         return omap_aes_write_ctrl(dd);
 467 }
 468
 469 static int omap_aes_crypt_req(struct crypto_engine *engine,
 470                               void *areq)
 471 {
 472         struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
 473         struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
 474         struct omap_aes_dev *dd = rctx->dd;
 475
 476         if (!dd)
 477                 return -ENODEV;
 478
 479         return omap_aes_crypt_dma_start(dd);
 480 }
 481
 482 static void omap_aes_done_task(unsigned long data)
 483 {
 484         struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
 485
 486         pr_debug("enter done_task\n");
 487
 488         if (!dd->pio_only) {
 489                 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
 490                                        DMA_FROM_DEVICE);
 491                 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
 492                 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
 493                              DMA_FROM_DEVICE);
 494                 omap_aes_crypt_dma_stop(dd);
 495         }
 496
 497         omap_crypto_cleanup(dd->in_sgl, NULL, 0, dd->total_save,
 498                             FLAGS_IN_DATA_ST_SHIFT, dd->flags);
 499
 500         omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
 501                             FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
 502
 503         omap_aes_finish_req(dd, 0);
 504
 505         pr_debug("exit\n");
 506 }
 507
 508 static int omap_aes_crypt(struct skcipher_request *req, unsigned long mode)
 509 {
 510         struct omap_aes_ctx *ctx = crypto_skcipher_ctx(
 511                         crypto_skcipher_reqtfm(req));
 512         struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
 513         struct omap_aes_dev *dd;
 514         int ret;
 515
 516         pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen,
 517                   !!(mode & FLAGS_ENCRYPT),
 518                   !!(mode & FLAGS_CBC));
 519
 520         if (req->cryptlen < aes_fallback_sz) {
 521                 SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
 522
 523                 skcipher_request_set_sync_tfm(subreq, ctx->fallback);
 524                 skcipher_request_set_callback(subreq, req->base.flags, NULL,
 525                                               NULL);
 526                 skcipher_request_set_crypt(subreq, req->src, req->dst,
 527                                            req->cryptlen, req->iv);
 528
 529                 if (mode & FLAGS_ENCRYPT)
 530                         ret = crypto_skcipher_encrypt(subreq);
 531                 else
 532                         ret = crypto_skcipher_decrypt(subreq);
 533
 534                 skcipher_request_zero(subreq);
 535                 return ret;
 536         }
 537         dd = omap_aes_find_dev(rctx);
 538         if (!dd)
 539                 return -ENODEV;
 540
 541         rctx->mode = mode;
 542
 543         return omap_aes_handle_queue(dd, req);
 544 }
 545
 546 /* ********************** ALG API ************************************ */
 547
 548 static int omap_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
 549                            unsigned int keylen)
 550 {
 551         struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
 552         int ret;
 553
 554         if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
 555                    keylen != AES_KEYSIZE_256)
 556                 return -EINVAL;
 557
 558         pr_debug("enter, keylen: %d\n", keylen);
 559
 560         memcpy(ctx->key, key, keylen);
 561         ctx->keylen = keylen;
 562
 563         crypto_sync_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK);
 564         crypto_sync_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags &
 565                                                  CRYPTO_TFM_REQ_MASK);
 566
 567         ret = crypto_sync_skcipher_setkey(ctx->fallback, key, keylen);
 568         if (!ret)
 569                 return 0;
 570
 571         return 0;
 572 }
 573
 574 static int omap_aes_ecb_encrypt(struct skcipher_request *req)
 575 {
 576         return omap_aes_crypt(req, FLAGS_ENCRYPT);
 577 }
 578
 579 static int omap_aes_ecb_decrypt(struct skcipher_request *req)
 580 {
 581         return omap_aes_crypt(req, 0);
 582 }
 583
 584 static int omap_aes_cbc_encrypt(struct skcipher_request *req)
 585 {
 586         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
 587 }
 588
 589 static int omap_aes_cbc_decrypt(struct skcipher_request *req)
 590 {
 591         return omap_aes_crypt(req, FLAGS_CBC);
 592 }
 593
 594 static int omap_aes_ctr_encrypt(struct skcipher_request *req)
 595 {
 596         return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
 597 }
 598
 599 static int omap_aes_ctr_decrypt(struct skcipher_request *req)
 600 {
 601         return omap_aes_crypt(req, FLAGS_CTR);
 602 }
 603
 604 static int omap_aes_prepare_req(struct crypto_engine *engine,
 605                                 void *req);
 606 static int omap_aes_crypt_req(struct crypto_engine *engine,
 607                               void *req);
 608
 609 static int omap_aes_init_tfm(struct crypto_skcipher *tfm)
 610 {
 611         const char *name = crypto_tfm_alg_name(&tfm->base);
 612         struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
 613         struct crypto_sync_skcipher *blk;
 614
 615         blk = crypto_alloc_sync_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
 616         if (IS_ERR(blk))
 617                 return PTR_ERR(blk);
 618
 619         ctx->fallback = blk;
 620
 621         crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_aes_reqctx));
 622
 623         ctx->enginectx.op.prepare_request = omap_aes_prepare_req;
 624         ctx->enginectx.op.unprepare_request = NULL;
 625         ctx->enginectx.op.do_one_request = omap_aes_crypt_req;
 626
 627         return 0;
 628 }
 629
 630 static int omap_aes_gcm_cra_init(struct crypto_aead *tfm)
 631 {
 632         struct omap_aes_dev *dd = NULL;
 633         struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm);
 634         int err;
 635
 636         /* Find AES device, currently picks the first device */
 637         spin_lock_bh(&list_lock);
 638         list_for_each_entry(dd, &dev_list, list) {
 639                 break;
 640         }
 641         spin_unlock_bh(&list_lock);
 642
 643         err = pm_runtime_get_sync(dd->dev);
 644         if (err < 0) {
 645                 dev_err(dd->dev, "%s: failed to get_sync(%d)\n",
 646                         __func__, err);
 647                 return err;
 648         }
 649
 650         tfm->reqsize = sizeof(struct omap_aes_reqctx);
 651         ctx->ctr = crypto_alloc_skcipher("ecb(aes)", 0, 0);
 652         if (IS_ERR(ctx->ctr)) {
 653                 pr_warn("could not load aes driver for encrypting IV\n");
 654                 return PTR_ERR(ctx->ctr);
 655         }
 656
 657         return 0;
 658 }
 659
 660 static void omap_aes_exit_tfm(struct crypto_skcipher *tfm)
 661 {
 662         struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
 663
 664         if (ctx->fallback)
 665                 crypto_free_sync_skcipher(ctx->fallback);
 666
 667         ctx->fallback = NULL;
 668 }
 669
 670 static void omap_aes_gcm_cra_exit(struct crypto_aead *tfm)
 671 {
 672         struct omap_aes_ctx *ctx = crypto_aead_ctx(tfm);
 673
 674         if (ctx->fallback)
 675                 crypto_free_sync_skcipher(ctx->fallback);
 676
 677         ctx->fallback = NULL;
 678
 679         if (ctx->ctr)
 680                 crypto_free_skcipher(ctx->ctr);
 681 }
 682
 683 /* ********************** ALGS ************************************ */
 684
 685 static struct skcipher_alg algs_ecb_cbc[] = {
 686 {
 687         .base.cra_name          = "ecb(aes)",
 688         .base.cra_driver_name   = "ecb-aes-omap",
 689         .base.cra_priority      = 300,
 690         .base.cra_flags         = CRYPTO_ALG_KERN_DRIVER_ONLY |
 691                                   CRYPTO_ALG_ASYNC |
 692                                   CRYPTO_ALG_NEED_FALLBACK,
 693         .base.cra_blocksize     = AES_BLOCK_SIZE,
 694         .base.cra_ctxsize       = sizeof(struct omap_aes_ctx),
 695         .base.cra_module        = THIS_MODULE,
 696
 697         .min_keysize            = AES_MIN_KEY_SIZE,
 698         .max_keysize            = AES_MAX_KEY_SIZE,
 699         .setkey                 = omap_aes_setkey,
 700         .encrypt                = omap_aes_ecb_encrypt,
 701         .decrypt                = omap_aes_ecb_decrypt,
 702         .init                   = omap_aes_init_tfm,
 703         .exit                   = omap_aes_exit_tfm,
 704 },
 705 {
 706         .base.cra_name          = "cbc(aes)",
 707         .base.cra_driver_name   = "cbc-aes-omap",
 708         .base.cra_priority      = 300,
 709         .base.cra_flags         = CRYPTO_ALG_KERN_DRIVER_ONLY |
 710                                   CRYPTO_ALG_ASYNC |
 711                                   CRYPTO_ALG_NEED_FALLBACK,
 712         .base.cra_blocksize     = AES_BLOCK_SIZE,
 713         .base.cra_ctxsize       = sizeof(struct omap_aes_ctx),
 714         .base.cra_module        = THIS_MODULE,
 715
 716         .min_keysize            = AES_MIN_KEY_SIZE,
 717         .max_keysize            = AES_MAX_KEY_SIZE,
 718         .ivsize                 = AES_BLOCK_SIZE,
 719         .setkey                 = omap_aes_setkey,
 720         .encrypt                = omap_aes_cbc_encrypt,
 721         .decrypt                = omap_aes_cbc_decrypt,
 722         .init                   = omap_aes_init_tfm,
 723         .exit                   = omap_aes_exit_tfm,
 724 }
 725 };
 726
 727 static struct skcipher_alg algs_ctr[] = {
 728 {
 729         .base.cra_name          = "ctr(aes)",
 730         .base.cra_driver_name   = "ctr-aes-omap",
 731         .base.cra_priority      = 300,
 732         .base.cra_flags         = CRYPTO_ALG_KERN_DRIVER_ONLY |
 733                                   CRYPTO_ALG_ASYNC |
 734                                   CRYPTO_ALG_NEED_FALLBACK,
 735         .base.cra_blocksize     = AES_BLOCK_SIZE,
 736         .base.cra_ctxsize       = sizeof(struct omap_aes_ctx),
 737         .base.cra_module        = THIS_MODULE,
 738
 739         .min_keysize            = AES_MIN_KEY_SIZE,
 740         .max_keysize            = AES_MAX_KEY_SIZE,
 741         .ivsize                 = AES_BLOCK_SIZE,
 742         .setkey                 = omap_aes_setkey,
 743         .encrypt                = omap_aes_ctr_encrypt,
 744         .decrypt                = omap_aes_ctr_decrypt,
 745         .init                   = omap_aes_init_tfm,
 746         .exit                   = omap_aes_exit_tfm,
 747 }
 748 };
 749
 750 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
 751         {
 752                 .algs_list      = algs_ecb_cbc,
 753                 .size           = ARRAY_SIZE(algs_ecb_cbc),
 754         },
 755 };
 756
 757 static struct aead_alg algs_aead_gcm[] = {
 758 {
 759         .base = {
 760                 .cra_name               = "gcm(aes)",
 761                 .cra_driver_name        = "gcm-aes-omap",
 762                 .cra_priority           = 300,
 763                 .cra_flags              = CRYPTO_ALG_ASYNC |
 764                                           CRYPTO_ALG_KERN_DRIVER_ONLY,
 765                 .cra_blocksize          = 1,
 766                 .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 767                 .cra_alignmask          = 0xf,
 768                 .cra_module             = THIS_MODULE,
 769         },
 770         .init           = omap_aes_gcm_cra_init,
 771         .exit           = omap_aes_gcm_cra_exit,
 772         .ivsize         = GCM_AES_IV_SIZE,
 773         .maxauthsize    = AES_BLOCK_SIZE,
 774         .setkey         = omap_aes_gcm_setkey,
 775         .encrypt        = omap_aes_gcm_encrypt,
 776         .decrypt        = omap_aes_gcm_decrypt,
 777 },
 778 {
 779         .base = {
 780                 .cra_name               = "rfc4106(gcm(aes))",
 781                 .cra_driver_name        = "rfc4106-gcm-aes-omap",
 782                 .cra_priority           = 300,
 783                 .cra_flags              = CRYPTO_ALG_ASYNC |
 784                                           CRYPTO_ALG_KERN_DRIVER_ONLY,
 785                 .cra_blocksize          = 1,
 786                 .cra_ctxsize            = sizeof(struct omap_aes_ctx),
 787                 .cra_alignmask          = 0xf,
 788                 .cra_module             = THIS_MODULE,
 789         },
 790         .init           = omap_aes_gcm_cra_init,
 791         .exit           = omap_aes_gcm_cra_exit,
 792         .maxauthsize    = AES_BLOCK_SIZE,
 793         .ivsize         = GCM_RFC4106_IV_SIZE,
 794         .setkey         = omap_aes_4106gcm_setkey,
 795         .encrypt        = omap_aes_4106gcm_encrypt,
 796         .decrypt        = omap_aes_4106gcm_decrypt,
 797 },
 798 };
 799
 800 static struct omap_aes_aead_algs omap_aes_aead_info = {
 801         .algs_list      =       algs_aead_gcm,
 802         .size           =       ARRAY_SIZE(algs_aead_gcm),
 803 };
 804
 805 static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
 806         .algs_info      = omap_aes_algs_info_ecb_cbc,
 807         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
 808         .trigger        = omap_aes_dma_trigger_omap2,
 809         .key_ofs        = 0x1c,
 810         .iv_ofs         = 0x20,
 811         .ctrl_ofs       = 0x30,
 812         .data_ofs       = 0x34,
 813         .rev_ofs        = 0x44,
 814         .mask_ofs       = 0x48,
 815         .dma_enable_in  = BIT(2),
 816         .dma_enable_out = BIT(3),
 817         .dma_start      = BIT(5),
 818         .major_mask     = 0xf0,
 819         .major_shift    = 4,
 820         .minor_mask     = 0x0f,
 821         .minor_shift    = 0,
 822 };
 823
 824 #ifdef CONFIG_OF
 825 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
 826         {
 827                 .algs_list      = algs_ecb_cbc,
 828                 .size           = ARRAY_SIZE(algs_ecb_cbc),
 829         },
 830         {
 831                 .algs_list      = algs_ctr,
 832                 .size           = ARRAY_SIZE(algs_ctr),
 833         },
 834 };
 835
 836 static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
 837         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
 838         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
 839         .trigger        = omap_aes_dma_trigger_omap2,
 840         .key_ofs        = 0x1c,
 841         .iv_ofs         = 0x20,
 842         .ctrl_ofs       = 0x30,
 843         .data_ofs       = 0x34,
 844         .rev_ofs        = 0x44,
 845         .mask_ofs       = 0x48,
 846         .dma_enable_in  = BIT(2),
 847         .dma_enable_out = BIT(3),
 848         .dma_start      = BIT(5),
 849         .major_mask     = 0xf0,
 850         .major_shift    = 4,
 851         .minor_mask     = 0x0f,
 852         .minor_shift    = 0,
 853 };
 854
 855 static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
 856         .algs_info      = omap_aes_algs_info_ecb_cbc_ctr,
 857         .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
 858         .aead_algs_info = &omap_aes_aead_info,
 859         .trigger        = omap_aes_dma_trigger_omap4,
 860         .key_ofs        = 0x3c,
 861         .iv_ofs         = 0x40,
 862         .ctrl_ofs       = 0x50,
 863         .data_ofs       = 0x60,
 864         .rev_ofs        = 0x80,
 865         .mask_ofs       = 0x84,
 866         .irq_status_ofs = 0x8c,
 867         .irq_enable_ofs = 0x90,
 868         .dma_enable_in  = BIT(5),
 869         .dma_enable_out = BIT(6),
 870         .major_mask     = 0x0700,
 871         .major_shift    = 8,
 872         .minor_mask     = 0x003f,
 873         .minor_shift    = 0,
 874 };
 875
 876 static irqreturn_t omap_aes_irq(int irq, void *dev_id)
 877 {
 878         struct omap_aes_dev *dd = dev_id;
 879         u32 status, i;
 880         u32 *src, *dst;
 881
 882         status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
 883         if (status & AES_REG_IRQ_DATA_IN) {
 884                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
 885
 886                 BUG_ON(!dd->in_sg);
 887
 888                 BUG_ON(_calc_walked(in) > dd->in_sg->length);
 889
 890                 src = sg_virt(dd->in_sg) + _calc_walked(in);
 891
 892                 for (i = 0; i < AES_BLOCK_WORDS; i++) {
 893                         omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
 894
 895                         scatterwalk_advance(&dd->in_walk, 4);
 896                         if (dd->in_sg->length == _calc_walked(in)) {
 897                                 dd->in_sg = sg_next(dd->in_sg);
 898                                 if (dd->in_sg) {
 899                                         scatterwalk_start(&dd->in_walk,
 900                                                           dd->in_sg);
 901                                         src = sg_virt(dd->in_sg) +
 902                                               _calc_walked(in);
 903                                 }
 904                         } else {
 905                                 src++;
 906                         }
 907                 }
 908
 909                 /* Clear IRQ status */
 910                 status &= ~AES_REG_IRQ_DATA_IN;
 911                 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
 912
 913                 /* Enable DATA_OUT interrupt */
 914                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
 915
 916         } else if (status & AES_REG_IRQ_DATA_OUT) {
 917                 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
 918
 919                 BUG_ON(!dd->out_sg);
 920
 921                 BUG_ON(_calc_walked(out) > dd->out_sg->length);
 922
 923                 dst = sg_virt(dd->out_sg) + _calc_walked(out);
 924
 925                 for (i = 0; i < AES_BLOCK_WORDS; i++) {
 926                         *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
 927                         scatterwalk_advance(&dd->out_walk, 4);
 928                         if (dd->out_sg->length == _calc_walked(out)) {
 929                                 dd->out_sg = sg_next(dd->out_sg);
 930                                 if (dd->out_sg) {
 931                                         scatterwalk_start(&dd->out_walk,
 932                                                           dd->out_sg);
 933                                         dst = sg_virt(dd->out_sg) +
 934                                               _calc_walked(out);
 935                                 }
 936                         } else {
 937                                 dst++;
 938                         }
 939                 }
 940
 941                 dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total);
 942
 943                 /* Clear IRQ status */
 944                 status &= ~AES_REG_IRQ_DATA_OUT;
 945                 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
 946
 947                 if (!dd->total)
 948                         /* All bytes read! */
 949                         tasklet_schedule(&dd->done_task);
 950                 else
 951                         /* Enable DATA_IN interrupt for next block */
 952                         omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
 953         }
 954
 955         return IRQ_HANDLED;
 956 }
 957
 958 static const struct of_device_id omap_aes_of_match[] = {
 959         {
 960                 .compatible     = "ti,omap2-aes",
 961                 .data           = &omap_aes_pdata_omap2,
 962         },
 963         {
 964                 .compatible     = "ti,omap3-aes",
 965                 .data           = &omap_aes_pdata_omap3,
 966         },
 967         {
 968                 .compatible     = "ti,omap4-aes",
 969                 .data           = &omap_aes_pdata_omap4,
 970         },
 971         {},
 972 };
 973 MODULE_DEVICE_TABLE(of, omap_aes_of_match);
 974
 975 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
 976                 struct device *dev, struct resource *res)
 977 {
 978         struct device_node *node = dev->of_node;
 979         int err = 0;
 980
 981         dd->pdata = of_device_get_match_data(dev);
 982         if (!dd->pdata) {
 983                 dev_err(dev, "no compatible OF match\n");
 984                 err = -EINVAL;
 985                 goto err;
 986         }
 987
 988         err = of_address_to_resource(node, 0, res);
 989         if (err < 0) {
 990                 dev_err(dev, "can't translate OF node address\n");
 991                 err = -EINVAL;
 992                 goto err;
 993         }
 994
 995 err:
 996         return err;
 997 }
 998 #else
 999 static const struct of_device_id omap_aes_of_match[] = {
1000         {},
1001 };
1002
1003 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1004                 struct device *dev, struct resource *res)
1005 {
1006         return -EINVAL;
1007 }
1008 #endif
1009
1010 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
1011                 struct platform_device *pdev, struct resource *res)
1012 {
1013         struct device *dev = &pdev->dev;
1014         struct resource *r;
1015         int err = 0;
1016
1017         /* Get the base address */
1018         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1019         if (!r) {
1020                 dev_err(dev, "no MEM resource info\n");
1021                 err = -ENODEV;
1022                 goto err;
1023         }
1024         memcpy(res, r, sizeof(*res));
1025
1026         /* Only OMAP2/3 can be non-DT */
1027         dd->pdata = &omap_aes_pdata_omap2;
1028
1029 err:
1030         return err;
1031 }
1032
1033 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
1034                              char *buf)
1035 {
1036         return sprintf(buf, "%d\n", aes_fallback_sz);
1037 }
1038
1039 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
1040                               const char *buf, size_t size)
1041 {
1042         ssize_t status;
1043         long value;
1044
1045         status = kstrtol(buf, 0, &value);
1046         if (status)
1047                 return status;
1048
1049         /* HW accelerator only works with buffers > 9 */
1050         if (value < 9) {
1051                 dev_err(dev, "minimum fallback size 9\n");
1052                 return -EINVAL;
1053         }
1054
1055         aes_fallback_sz = value;
1056
1057         return size;
1058 }
1059
1060 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
1061                               char *buf)
1062 {
1063         struct omap_aes_dev *dd = dev_get_drvdata(dev);
1064
1065         return sprintf(buf, "%d\n", dd->engine->queue.max_qlen);
1066 }
1067
1068 static ssize_t queue_len_store(struct device *dev,
1069                                struct device_attribute *attr, const char *buf,
1070                                size_t size)
1071 {
1072         struct omap_aes_dev *dd;
1073         ssize_t status;
1074         long value;
1075         unsigned long flags;
1076
1077         status = kstrtol(buf, 0, &value);
1078         if (status)
1079                 return status;
1080
1081         if (value < 1)
1082                 return -EINVAL;
1083
1084         /*
1085          * Changing the queue size in fly is safe, if size becomes smaller
1086          * than current size, it will just not accept new entries until
1087          * it has shrank enough.
1088          */
1089         spin_lock_bh(&list_lock);
1090         list_for_each_entry(dd, &dev_list, list) {
1091                 spin_lock_irqsave(&dd->lock, flags);
1092                 dd->engine->queue.max_qlen = value;
1093                 dd->aead_queue.base.max_qlen = value;
1094                 spin_unlock_irqrestore(&dd->lock, flags);
1095         }
1096         spin_unlock_bh(&list_lock);
1097
1098         return size;
1099 }
1100
1101 static DEVICE_ATTR_RW(queue_len);
1102 static DEVICE_ATTR_RW(fallback);
1103
1104 static struct attribute *omap_aes_attrs[] = {
1105         &dev_attr_queue_len.attr,
1106         &dev_attr_fallback.attr,
1107         NULL,
1108 };
1109
1110 static struct attribute_group omap_aes_attr_group = {
1111         .attrs = omap_aes_attrs,
1112 };
1113
1114 static int omap_aes_probe(struct platform_device *pdev)
1115 {
1116         struct device *dev = &pdev->dev;
1117         struct omap_aes_dev *dd;
1118         struct skcipher_alg *algp;
1119         struct aead_alg *aalg;
1120         struct resource res;
1121         int err = -ENOMEM, i, j, irq = -1;
1122         u32 reg;
1123
1124         dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
1125         if (dd == NULL) {
1126                 dev_err(dev, "unable to alloc data struct.\n");
1127                 goto err_data;
1128         }
1129         dd->dev = dev;
1130         platform_set_drvdata(pdev, dd);
1131
1132         aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH);
1133
1134         err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1135                                omap_aes_get_res_pdev(dd, pdev, &res);
1136         if (err)
1137                 goto err_res;
1138
1139         dd->io_base = devm_ioremap_resource(dev, &res);
1140         if (IS_ERR(dd->io_base)) {
1141                 err = PTR_ERR(dd->io_base);
1142                 goto err_res;
1143         }
1144         dd->phys_base = res.start;
1145
1146         pm_runtime_use_autosuspend(dev);
1147         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
1148
1149         pm_runtime_enable(dev);
1150         err = pm_runtime_get_sync(dev);
1151         if (err < 0) {
1152                 dev_err(dev, "%s: failed to get_sync(%d)\n",
1153                         __func__, err);
1154                 goto err_res;
1155         }
1156
1157         omap_aes_dma_stop(dd);
1158
1159         reg = omap_aes_read(dd, AES_REG_REV(dd));
1160
1161         pm_runtime_put_sync(dev);
1162
1163         dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1164                  (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1165                  (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1166
1167         tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1168
1169         err = omap_aes_dma_init(dd);
1170         if (err == -EPROBE_DEFER) {
1171                 goto err_irq;
1172         } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1173                 dd->pio_only = 1;
1174
1175                 irq = platform_get_irq(pdev, 0);
1176                 if (irq < 0) {
1177                         err = irq;
1178                         goto err_irq;
1179                 }
1180
1181                 err = devm_request_irq(dev, irq, omap_aes_irq, 0,
1182                                 dev_name(dev), dd);
1183                 if (err) {
1184                         dev_err(dev, "Unable to grab omap-aes IRQ\n");
1185                         goto err_irq;
1186                 }
1187         }
1188
1189         spin_lock_init(&dd->lock);
1190
1191         INIT_LIST_HEAD(&dd->list);
1192         spin_lock(&list_lock);
1193         list_add_tail(&dd->list, &dev_list);
1194         spin_unlock(&list_lock);
1195
1196         /* Initialize crypto engine */
1197         dd->engine = crypto_engine_alloc_init(dev, 1);
1198         if (!dd->engine) {
1199                 err = -ENOMEM;
1200                 goto err_engine;
1201         }
1202
1203         err = crypto_engine_start(dd->engine);
1204         if (err)
1205                 goto err_engine;
1206
1207         for (i = 0; i < dd->pdata->algs_info_size; i++) {
1208                 if (!dd->pdata->algs_info[i].registered) {
1209                         for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1210                                 algp = &dd->pdata->algs_info[i].algs_list[j];
1211
1212                                 pr_debug("reg alg: %s\n", algp->base.cra_name);
1213
1214                                 err = crypto_register_skcipher(algp);
1215                                 if (err)
1216                                         goto err_algs;
1217
1218                                 dd->pdata->algs_info[i].registered++;
1219                         }
1220                 }
1221         }
1222
1223         if (dd->pdata->aead_algs_info &&
1224             !dd->pdata->aead_algs_info->registered) {
1225                 for (i = 0; i < dd->pdata->aead_algs_info->size; i++) {
1226                         aalg = &dd->pdata->aead_algs_info->algs_list[i];
1227
1228                         pr_debug("reg alg: %s\n", aalg->base.cra_name);
1229
1230                         err = crypto_register_aead(aalg);
1231                         if (err)
1232                                 goto err_aead_algs;
1233
1234                         dd->pdata->aead_algs_info->registered++;
1235                 }
1236         }
1237
1238         err = sysfs_create_group(&dev->kobj, &omap_aes_attr_group);
1239         if (err) {
1240                 dev_err(dev, "could not create sysfs device attrs\n");
1241                 goto err_aead_algs;
1242         }
1243
1244         return 0;
1245 err_aead_algs:
1246         for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) {
1247                 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1248                 crypto_unregister_aead(aalg);
1249         }
1250 err_algs:
1251         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1252                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1253                         crypto_unregister_skcipher(
1254                                         &dd->pdata->algs_info[i].algs_list[j]);
1255
1256 err_engine:
1257         if (dd->engine)
1258                 crypto_engine_exit(dd->engine);
1259
1260         omap_aes_dma_cleanup(dd);
1261 err_irq:
1262         tasklet_kill(&dd->done_task);
1263         pm_runtime_disable(dev);
1264 err_res:
1265         dd = NULL;
1266 err_data:
1267         dev_err(dev, "initialization failed.\n");
1268         return err;
1269 }
1270
1271 static int omap_aes_remove(struct platform_device *pdev)
1272 {
1273         struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1274         struct aead_alg *aalg;
1275         int i, j;
1276
1277         if (!dd)
1278                 return -ENODEV;
1279
1280         spin_lock(&list_lock);
1281         list_del(&dd->list);
1282         spin_unlock(&list_lock);
1283
1284         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1285                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1286                         crypto_unregister_skcipher(
1287                                         &dd->pdata->algs_info[i].algs_list[j]);
1288
1289         for (i = dd->pdata->aead_algs_info->size - 1; i >= 0; i--) {
1290                 aalg = &dd->pdata->aead_algs_info->algs_list[i];
1291                 crypto_unregister_aead(aalg);
1292         }
1293
1294         crypto_engine_exit(dd->engine);
1295
1296         tasklet_kill(&dd->done_task);
1297         omap_aes_dma_cleanup(dd);
1298         pm_runtime_disable(dd->dev);
1299         dd = NULL;
1300
1301         return 0;
1302 }
1303
1304 #ifdef CONFIG_PM_SLEEP
1305 static int omap_aes_suspend(struct device *dev)
1306 {
1307         pm_runtime_put_sync(dev);
1308         return 0;
1309 }
1310
1311 static int omap_aes_resume(struct device *dev)
1312 {
1313         pm_runtime_get_sync(dev);
1314         return 0;
1315 }
1316 #endif
1317
1318 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
1319
1320 static struct platform_driver omap_aes_driver = {
1321         .probe  = omap_aes_probe,
1322         .remove = omap_aes_remove,
1323         .driver = {
1324                 .name   = "omap-aes",
1325                 .pm     = &omap_aes_pm_ops,
1326                 .of_match_table = omap_aes_of_match,
1327         },
1328 };
1329
1330 module_platform_driver(omap_aes_driver);
1331
1332 MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1333 MODULE_LICENSE("GPL v2");
1334 MODULE_AUTHOR("Dmitry Kasatkin");
1335