drivers/crypto/n2_core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* n2_core.c: Niagara2 Stream Processing Unit (SPU) crypto support.
   3  *
   4  * Copyright (C) 2010, 2011 David S. Miller <davem@davemloft.net>
   5  */
   6
   7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/cpumask.h>
  14 #include <linux/slab.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/crypto.h>
  17 #include <crypto/md5.h>
  18 #include <crypto/sha.h>
  19 #include <crypto/aes.h>
  20 #include <crypto/internal/des.h>
  21 #include <linux/mutex.h>
  22 #include <linux/delay.h>
  23 #include <linux/sched.h>
  24
  25 #include <crypto/internal/hash.h>
  26 #include <crypto/internal/skcipher.h>
  27 #include <crypto/scatterwalk.h>
  28 #include <crypto/algapi.h>
  29
  30 #include <asm/hypervisor.h>
  31 #include <asm/mdesc.h>
  32
  33 #include "n2_core.h"
  34
  35 #define DRV_MODULE_NAME         "n2_crypto"
  36 #define DRV_MODULE_VERSION      "0.2"
  37 #define DRV_MODULE_RELDATE      "July 28, 2011"
  38
  39 static const char version[] =
  40         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  41
  42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  43 MODULE_DESCRIPTION("Niagara2 Crypto driver");
  44 MODULE_LICENSE("GPL");
  45 MODULE_VERSION(DRV_MODULE_VERSION);
  46
  47 #define N2_CRA_PRIORITY         200
  48
  49 static DEFINE_MUTEX(spu_lock);
  50
  51 struct spu_queue {
  52         cpumask_t               sharing;
  53         unsigned long           qhandle;
  54
  55         spinlock_t              lock;
  56         u8                      q_type;
  57         void                    *q;
  58         unsigned long           head;
  59         unsigned long           tail;
  60         struct list_head        jobs;
  61
  62         unsigned long           devino;
  63
  64         char                    irq_name[32];
  65         unsigned int            irq;
  66
  67         struct list_head        list;
  68 };
  69
  70 struct spu_qreg {
  71         struct spu_queue        *queue;
  72         unsigned long           type;
  73 };
  74
  75 static struct spu_queue **cpu_to_cwq;
  76 static struct spu_queue **cpu_to_mau;
  77
  78 static unsigned long spu_next_offset(struct spu_queue *q, unsigned long off)
  79 {
  80         if (q->q_type == HV_NCS_QTYPE_MAU) {
  81                 off += MAU_ENTRY_SIZE;
  82                 if (off == (MAU_ENTRY_SIZE * MAU_NUM_ENTRIES))
  83                         off = 0;
  84         } else {
  85                 off += CWQ_ENTRY_SIZE;
  86                 if (off == (CWQ_ENTRY_SIZE * CWQ_NUM_ENTRIES))
  87                         off = 0;
  88         }
  89         return off;
  90 }
  91
  92 struct n2_request_common {
  93         struct list_head        entry;
  94         unsigned int            offset;
  95 };
  96 #define OFFSET_NOT_RUNNING      (~(unsigned int)0)
  97
  98 /* An async job request records the final tail value it used in
  99  * n2_request_common->offset, test to see if that offset is in
 100  * the range old_head, new_head, inclusive.
 101  */
 102 static inline bool job_finished(struct spu_queue *q, unsigned int offset,
 103                                 unsigned long old_head, unsigned long new_head)
 104 {
 105         if (old_head <= new_head) {
 106                 if (offset > old_head && offset <= new_head)
 107                         return true;
 108         } else {
 109                 if (offset > old_head || offset <= new_head)
 110                         return true;
 111         }
 112         return false;
 113 }
 114
 115 /* When the HEAD marker is unequal to the actual HEAD, we get
 116  * a virtual device INO interrupt.  We should process the
 117  * completed CWQ entries and adjust the HEAD marker to clear
 118  * the IRQ.
 119  */
 120 static irqreturn_t cwq_intr(int irq, void *dev_id)
 121 {
 122         unsigned long off, new_head, hv_ret;
 123         struct spu_queue *q = dev_id;
 124
 125         pr_err("CPU[%d]: Got CWQ interrupt for qhdl[%lx]\n",
 126                smp_processor_id(), q->qhandle);
 127
 128         spin_lock(&q->lock);
 129
 130         hv_ret = sun4v_ncs_gethead(q->qhandle, &new_head);
 131
 132         pr_err("CPU[%d]: CWQ gethead[%lx] hv_ret[%lu]\n",
 133                smp_processor_id(), new_head, hv_ret);
 134
 135         for (off = q->head; off != new_head; off = spu_next_offset(q, off)) {
 136                 /* XXX ... XXX */
 137         }
 138
 139         hv_ret = sun4v_ncs_sethead_marker(q->qhandle, new_head);
 140         if (hv_ret == HV_EOK)
 141                 q->head = new_head;
 142
 143         spin_unlock(&q->lock);
 144
 145         return IRQ_HANDLED;
 146 }
 147
 148 static irqreturn_t mau_intr(int irq, void *dev_id)
 149 {
 150         struct spu_queue *q = dev_id;
 151         unsigned long head, hv_ret;
 152
 153         spin_lock(&q->lock);
 154
 155         pr_err("CPU[%d]: Got MAU interrupt for qhdl[%lx]\n",
 156                smp_processor_id(), q->qhandle);
 157
 158         hv_ret = sun4v_ncs_gethead(q->qhandle, &head);
 159
 160         pr_err("CPU[%d]: MAU gethead[%lx] hv_ret[%lu]\n",
 161                smp_processor_id(), head, hv_ret);
 162
 163         sun4v_ncs_sethead_marker(q->qhandle, head);
 164
 165         spin_unlock(&q->lock);
 166
 167         return IRQ_HANDLED;
 168 }
 169
 170 static void *spu_queue_next(struct spu_queue *q, void *cur)
 171 {
 172         return q->q + spu_next_offset(q, cur - q->q);
 173 }
 174
 175 static int spu_queue_num_free(struct spu_queue *q)
 176 {
 177         unsigned long head = q->head;
 178         unsigned long tail = q->tail;
 179         unsigned long end = (CWQ_ENTRY_SIZE * CWQ_NUM_ENTRIES);
 180         unsigned long diff;
 181
 182         if (head > tail)
 183                 diff = head - tail;
 184         else
 185                 diff = (end - tail) + head;
 186
 187         return (diff / CWQ_ENTRY_SIZE) - 1;
 188 }
 189
 190 static void *spu_queue_alloc(struct spu_queue *q, int num_entries)
 191 {
 192         int avail = spu_queue_num_free(q);
 193
 194         if (avail >= num_entries)
 195                 return q->q + q->tail;
 196
 197         return NULL;
 198 }
 199
 200 static unsigned long spu_queue_submit(struct spu_queue *q, void *last)
 201 {
 202         unsigned long hv_ret, new_tail;
 203
 204         new_tail = spu_next_offset(q, last - q->q);
 205
 206         hv_ret = sun4v_ncs_settail(q->qhandle, new_tail);
 207         if (hv_ret == HV_EOK)
 208                 q->tail = new_tail;
 209         return hv_ret;
 210 }
 211
 212 static u64 control_word_base(unsigned int len, unsigned int hmac_key_len,
 213                              int enc_type, int auth_type,
 214                              unsigned int hash_len,
 215                              bool sfas, bool sob, bool eob, bool encrypt,
 216                              int opcode)
 217 {
 218         u64 word = (len - 1) & CONTROL_LEN;
 219
 220         word |= ((u64) opcode << CONTROL_OPCODE_SHIFT);
 221         word |= ((u64) enc_type << CONTROL_ENC_TYPE_SHIFT);
 222         word |= ((u64) auth_type << CONTROL_AUTH_TYPE_SHIFT);
 223         if (sfas)
 224                 word |= CONTROL_STORE_FINAL_AUTH_STATE;
 225         if (sob)
 226                 word |= CONTROL_START_OF_BLOCK;
 227         if (eob)
 228                 word |= CONTROL_END_OF_BLOCK;
 229         if (encrypt)
 230                 word |= CONTROL_ENCRYPT;
 231         if (hmac_key_len)
 232                 word |= ((u64) (hmac_key_len - 1)) << CONTROL_HMAC_KEY_LEN_SHIFT;
 233         if (hash_len)
 234                 word |= ((u64) (hash_len - 1)) << CONTROL_HASH_LEN_SHIFT;
 235
 236         return word;
 237 }
 238
 239 #if 0
 240 static inline bool n2_should_run_async(struct spu_queue *qp, int this_len)
 241 {
 242         if (this_len >= 64 ||
 243             qp->head != qp->tail)
 244                 return true;
 245         return false;
 246 }
 247 #endif
 248
 249 struct n2_ahash_alg {
 250         struct list_head        entry;
 251         const u8                *hash_zero;
 252         const u32               *hash_init;
 253         u8                      hw_op_hashsz;
 254         u8                      digest_size;
 255         u8                      auth_type;
 256         u8                      hmac_type;
 257         struct ahash_alg        alg;
 258 };
 259
 260 static inline struct n2_ahash_alg *n2_ahash_alg(struct crypto_tfm *tfm)
 261 {
 262         struct crypto_alg *alg = tfm->__crt_alg;
 263         struct ahash_alg *ahash_alg;
 264
 265         ahash_alg = container_of(alg, struct ahash_alg, halg.base);
 266
 267         return container_of(ahash_alg, struct n2_ahash_alg, alg);
 268 }
 269
 270 struct n2_hmac_alg {
 271         const char              *child_alg;
 272         struct n2_ahash_alg     derived;
 273 };
 274
 275 static inline struct n2_hmac_alg *n2_hmac_alg(struct crypto_tfm *tfm)
 276 {
 277         struct crypto_alg *alg = tfm->__crt_alg;
 278         struct ahash_alg *ahash_alg;
 279
 280         ahash_alg = container_of(alg, struct ahash_alg, halg.base);
 281
 282         return container_of(ahash_alg, struct n2_hmac_alg, derived.alg);
 283 }
 284
 285 struct n2_hash_ctx {
 286         struct crypto_ahash             *fallback_tfm;
 287 };
 288
 289 #define N2_HASH_KEY_MAX                 32 /* HW limit for all HMAC requests */
 290
 291 struct n2_hmac_ctx {
 292         struct n2_hash_ctx              base;
 293
 294         struct crypto_shash             *child_shash;
 295
 296         int                             hash_key_len;
 297         unsigned char                   hash_key[N2_HASH_KEY_MAX];
 298 };
 299
 300 struct n2_hash_req_ctx {
 301         union {
 302                 struct md5_state        md5;
 303                 struct sha1_state       sha1;
 304                 struct sha256_state     sha256;
 305         } u;
 306
 307         struct ahash_request            fallback_req;
 308 };
 309
 310 static int n2_hash_async_init(struct ahash_request *req)
 311 {
 312         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 313         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 314         struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 315
 316         ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 317         rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 318
 319         return crypto_ahash_init(&rctx->fallback_req);
 320 }
 321
 322 static int n2_hash_async_update(struct ahash_request *req)
 323 {
 324         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 325         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 326         struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 327
 328         ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 329         rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 330         rctx->fallback_req.nbytes = req->nbytes;
 331         rctx->fallback_req.src = req->src;
 332
 333         return crypto_ahash_update(&rctx->fallback_req);
 334 }
 335
 336 static int n2_hash_async_final(struct ahash_request *req)
 337 {
 338         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 339         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 340         struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 341
 342         ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 343         rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 344         rctx->fallback_req.result = req->result;
 345
 346         return crypto_ahash_final(&rctx->fallback_req);
 347 }
 348
 349 static int n2_hash_async_finup(struct ahash_request *req)
 350 {
 351         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 352         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 353         struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 354
 355         ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 356         rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 357         rctx->fallback_req.nbytes = req->nbytes;
 358         rctx->fallback_req.src = req->src;
 359         rctx->fallback_req.result = req->result;
 360
 361         return crypto_ahash_finup(&rctx->fallback_req);
 362 }
 363
 364 static int n2_hash_async_noimport(struct ahash_request *req, const void *in)
 365 {
 366         return -ENOSYS;
 367 }
 368
 369 static int n2_hash_async_noexport(struct ahash_request *req, void *out)
 370 {
 371         return -ENOSYS;
 372 }
 373
 374 static int n2_hash_cra_init(struct crypto_tfm *tfm)
 375 {
 376         const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
 377         struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
 378         struct n2_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 379         struct crypto_ahash *fallback_tfm;
 380         int err;
 381
 382         fallback_tfm = crypto_alloc_ahash(fallback_driver_name, 0,
 383                                           CRYPTO_ALG_NEED_FALLBACK);
 384         if (IS_ERR(fallback_tfm)) {
 385                 pr_warn("Fallback driver '%s' could not be loaded!\n",
 386                         fallback_driver_name);
 387                 err = PTR_ERR(fallback_tfm);
 388                 goto out;
 389         }
 390
 391         crypto_ahash_set_reqsize(ahash, (sizeof(struct n2_hash_req_ctx) +
 392                                          crypto_ahash_reqsize(fallback_tfm)));
 393
 394         ctx->fallback_tfm = fallback_tfm;
 395         return 0;
 396
 397 out:
 398         return err;
 399 }
 400
 401 static void n2_hash_cra_exit(struct crypto_tfm *tfm)
 402 {
 403         struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
 404         struct n2_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 405
 406         crypto_free_ahash(ctx->fallback_tfm);
 407 }
 408
 409 static int n2_hmac_cra_init(struct crypto_tfm *tfm)
 410 {
 411         const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
 412         struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
 413         struct n2_hmac_ctx *ctx = crypto_ahash_ctx(ahash);
 414         struct n2_hmac_alg *n2alg = n2_hmac_alg(tfm);
 415         struct crypto_ahash *fallback_tfm;
 416         struct crypto_shash *child_shash;
 417         int err;
 418
 419         fallback_tfm = crypto_alloc_ahash(fallback_driver_name, 0,
 420                                           CRYPTO_ALG_NEED_FALLBACK);
 421         if (IS_ERR(fallback_tfm)) {
 422                 pr_warn("Fallback driver '%s' could not be loaded!\n",
 423                         fallback_driver_name);
 424                 err = PTR_ERR(fallback_tfm);
 425                 goto out;
 426         }
 427
 428         child_shash = crypto_alloc_shash(n2alg->child_alg, 0, 0);
 429         if (IS_ERR(child_shash)) {
 430                 pr_warn("Child shash '%s' could not be loaded!\n",
 431                         n2alg->child_alg);
 432                 err = PTR_ERR(child_shash);
 433                 goto out_free_fallback;
 434         }
 435
 436         crypto_ahash_set_reqsize(ahash, (sizeof(struct n2_hash_req_ctx) +
 437                                          crypto_ahash_reqsize(fallback_tfm)));
 438
 439         ctx->child_shash = child_shash;
 440         ctx->base.fallback_tfm = fallback_tfm;
 441         return 0;
 442
 443 out_free_fallback:
 444         crypto_free_ahash(fallback_tfm);
 445
 446 out:
 447         return err;
 448 }
 449
 450 static void n2_hmac_cra_exit(struct crypto_tfm *tfm)
 451 {
 452         struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
 453         struct n2_hmac_ctx *ctx = crypto_ahash_ctx(ahash);
 454
 455         crypto_free_ahash(ctx->base.fallback_tfm);
 456         crypto_free_shash(ctx->child_shash);
 457 }
 458
 459 static int n2_hmac_async_setkey(struct crypto_ahash *tfm, const u8 *key,
 460                                 unsigned int keylen)
 461 {
 462         struct n2_hmac_ctx *ctx = crypto_ahash_ctx(tfm);
 463         struct crypto_shash *child_shash = ctx->child_shash;
 464         struct crypto_ahash *fallback_tfm;
 465         int err, bs, ds;
 466
 467         fallback_tfm = ctx->base.fallback_tfm;
 468         err = crypto_ahash_setkey(fallback_tfm, key, keylen);
 469         if (err)
 470                 return err;
 471
 472         bs = crypto_shash_blocksize(child_shash);
 473         ds = crypto_shash_digestsize(child_shash);
 474         BUG_ON(ds > N2_HASH_KEY_MAX);
 475         if (keylen > bs) {
 476                 err = crypto_shash_tfm_digest(child_shash, key, keylen,
 477                                               ctx->hash_key);
 478                 if (err)
 479                         return err;
 480                 keylen = ds;
 481         } else if (keylen <= N2_HASH_KEY_MAX)
 482                 memcpy(ctx->hash_key, key, keylen);
 483
 484         ctx->hash_key_len = keylen;
 485
 486         return err;
 487 }
 488
 489 static unsigned long wait_for_tail(struct spu_queue *qp)
 490 {
 491         unsigned long head, hv_ret;
 492
 493         do {
 494                 hv_ret = sun4v_ncs_gethead(qp->qhandle, &head);
 495                 if (hv_ret != HV_EOK) {
 496                         pr_err("Hypervisor error on gethead\n");
 497                         break;
 498                 }
 499                 if (head == qp->tail) {
 500                         qp->head = head;
 501                         break;
 502                 }
 503         } while (1);
 504         return hv_ret;
 505 }
 506
 507 static unsigned long submit_and_wait_for_tail(struct spu_queue *qp,
 508                                               struct cwq_initial_entry *ent)
 509 {
 510         unsigned long hv_ret = spu_queue_submit(qp, ent);
 511
 512         if (hv_ret == HV_EOK)
 513                 hv_ret = wait_for_tail(qp);
 514
 515         return hv_ret;
 516 }
 517
 518 static int n2_do_async_digest(struct ahash_request *req,
 519                               unsigned int auth_type, unsigned int digest_size,
 520                               unsigned int result_size, void *hash_loc,
 521                               unsigned long auth_key, unsigned int auth_key_len)
 522 {
 523         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 524         struct cwq_initial_entry *ent;
 525         struct crypto_hash_walk walk;
 526         struct spu_queue *qp;
 527         unsigned long flags;
 528         int err = -ENODEV;
 529         int nbytes, cpu;
 530
 531         /* The total effective length of the operation may not
 532          * exceed 2^16.
 533          */
 534         if (unlikely(req->nbytes > (1 << 16))) {
 535                 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 536                 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 537
 538                 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 539                 rctx->fallback_req.base.flags =
 540                         req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 541                 rctx->fallback_req.nbytes = req->nbytes;
 542                 rctx->fallback_req.src = req->src;
 543                 rctx->fallback_req.result = req->result;
 544
 545                 return crypto_ahash_digest(&rctx->fallback_req);
 546         }
 547
 548         nbytes = crypto_hash_walk_first(req, &walk);
 549
 550         cpu = get_cpu();
 551         qp = cpu_to_cwq[cpu];
 552         if (!qp)
 553                 goto out;
 554
 555         spin_lock_irqsave(&qp->lock, flags);
 556
 557         /* XXX can do better, improve this later by doing a by-hand scatterlist
 558          * XXX walk, etc.
 559          */
 560         ent = qp->q + qp->tail;
 561
 562         ent->control = control_word_base(nbytes, auth_key_len, 0,
 563                                          auth_type, digest_size,
 564                                          false, true, false, false,
 565                                          OPCODE_INPLACE_BIT |
 566                                          OPCODE_AUTH_MAC);
 567         ent->src_addr = __pa(walk.data);
 568         ent->auth_key_addr = auth_key;
 569         ent->auth_iv_addr = __pa(hash_loc);
 570         ent->final_auth_state_addr = 0UL;
 571         ent->enc_key_addr = 0UL;
 572         ent->enc_iv_addr = 0UL;
 573         ent->dest_addr = __pa(hash_loc);
 574
 575         nbytes = crypto_hash_walk_done(&walk, 0);
 576         while (nbytes > 0) {
 577                 ent = spu_queue_next(qp, ent);
 578
 579                 ent->control = (nbytes - 1);
 580                 ent->src_addr = __pa(walk.data);
 581                 ent->auth_key_addr = 0UL;
 582                 ent->auth_iv_addr = 0UL;
 583                 ent->final_auth_state_addr = 0UL;
 584                 ent->enc_key_addr = 0UL;
 585                 ent->enc_iv_addr = 0UL;
 586                 ent->dest_addr = 0UL;
 587
 588                 nbytes = crypto_hash_walk_done(&walk, 0);
 589         }
 590         ent->control |= CONTROL_END_OF_BLOCK;
 591
 592         if (submit_and_wait_for_tail(qp, ent) != HV_EOK)
 593                 err = -EINVAL;
 594         else
 595                 err = 0;
 596
 597         spin_unlock_irqrestore(&qp->lock, flags);
 598
 599         if (!err)
 600                 memcpy(req->result, hash_loc, result_size);
 601 out:
 602         put_cpu();
 603
 604         return err;
 605 }
 606
 607 static int n2_hash_async_digest(struct ahash_request *req)
 608 {
 609         struct n2_ahash_alg *n2alg = n2_ahash_alg(req->base.tfm);
 610         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 611         int ds;
 612
 613         ds = n2alg->digest_size;
 614         if (unlikely(req->nbytes == 0)) {
 615                 memcpy(req->result, n2alg->hash_zero, ds);
 616                 return 0;
 617         }
 618         memcpy(&rctx->u, n2alg->hash_init, n2alg->hw_op_hashsz);
 619
 620         return n2_do_async_digest(req, n2alg->auth_type,
 621                                   n2alg->hw_op_hashsz, ds,
 622                                   &rctx->u, 0UL, 0);
 623 }
 624
 625 static int n2_hmac_async_digest(struct ahash_request *req)
 626 {
 627         struct n2_hmac_alg *n2alg = n2_hmac_alg(req->base.tfm);
 628         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 629         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 630         struct n2_hmac_ctx *ctx = crypto_ahash_ctx(tfm);
 631         int ds;
 632
 633         ds = n2alg->derived.digest_size;
 634         if (unlikely(req->nbytes == 0) ||
 635             unlikely(ctx->hash_key_len > N2_HASH_KEY_MAX)) {
 636                 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 637                 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 638
 639                 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 640                 rctx->fallback_req.base.flags =
 641                         req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 642                 rctx->fallback_req.nbytes = req->nbytes;
 643                 rctx->fallback_req.src = req->src;
 644                 rctx->fallback_req.result = req->result;
 645
 646                 return crypto_ahash_digest(&rctx->fallback_req);
 647         }
 648         memcpy(&rctx->u, n2alg->derived.hash_init,
 649                n2alg->derived.hw_op_hashsz);
 650
 651         return n2_do_async_digest(req, n2alg->derived.hmac_type,
 652                                   n2alg->derived.hw_op_hashsz, ds,
 653                                   &rctx->u,
 654                                   __pa(&ctx->hash_key),
 655                                   ctx->hash_key_len);
 656 }
 657
 658 struct n2_skcipher_context {
 659         int                     key_len;
 660         int                     enc_type;
 661         union {
 662                 u8              aes[AES_MAX_KEY_SIZE];
 663                 u8              des[DES_KEY_SIZE];
 664                 u8              des3[3 * DES_KEY_SIZE];
 665                 u8              arc4[258]; /* S-box, X, Y */
 666         } key;
 667 };
 668
 669 #define N2_CHUNK_ARR_LEN        16
 670
 671 struct n2_crypto_chunk {
 672         struct list_head        entry;
 673         unsigned long           iv_paddr : 44;
 674         unsigned long           arr_len : 20;
 675         unsigned long           dest_paddr;
 676         unsigned long           dest_final;
 677         struct {
 678                 unsigned long   src_paddr : 44;
 679                 unsigned long   src_len : 20;
 680         } arr[N2_CHUNK_ARR_LEN];
 681 };
 682
 683 struct n2_request_context {
 684         struct skcipher_walk    walk;
 685         struct list_head        chunk_list;
 686         struct n2_crypto_chunk  chunk;
 687         u8                      temp_iv[16];
 688 };
 689
 690 /* The SPU allows some level of flexibility for partial cipher blocks
 691  * being specified in a descriptor.
 692  *
 693  * It merely requires that every descriptor's length field is at least
 694  * as large as the cipher block size.  This means that a cipher block
 695  * can span at most 2 descriptors.  However, this does not allow a
 696  * partial block to span into the final descriptor as that would
 697  * violate the rule (since every descriptor's length must be at lest
 698  * the block size).  So, for example, assuming an 8 byte block size:
 699  *
 700  *      0xe --> 0xa --> 0x8
 701  *
 702  * is a valid length sequence, whereas:
 703  *
 704  *      0xe --> 0xb --> 0x7
 705  *
 706  * is not a valid sequence.
 707  */
 708
 709 struct n2_skcipher_alg {
 710         struct list_head        entry;
 711         u8                      enc_type;
 712         struct skcipher_alg     skcipher;
 713 };
 714
 715 static inline struct n2_skcipher_alg *n2_skcipher_alg(struct crypto_skcipher *tfm)
 716 {
 717         struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
 718
 719         return container_of(alg, struct n2_skcipher_alg, skcipher);
 720 }
 721
 722 struct n2_skcipher_request_context {
 723         struct skcipher_walk    walk;
 724 };
 725
 726 static int n2_aes_setkey(struct crypto_skcipher *skcipher, const u8 *key,
 727                          unsigned int keylen)
 728 {
 729         struct crypto_tfm *tfm = crypto_skcipher_tfm(skcipher);
 730         struct n2_skcipher_context *ctx = crypto_tfm_ctx(tfm);
 731         struct n2_skcipher_alg *n2alg = n2_skcipher_alg(skcipher);
 732
 733         ctx->enc_type = (n2alg->enc_type & ENC_TYPE_CHAINING_MASK);
 734
 735         switch (keylen) {
 736         case AES_KEYSIZE_128:
 737                 ctx->enc_type |= ENC_TYPE_ALG_AES128;
 738                 break;
 739         case AES_KEYSIZE_192:
 740                 ctx->enc_type |= ENC_TYPE_ALG_AES192;
 741                 break;
 742         case AES_KEYSIZE_256:
 743                 ctx->enc_type |= ENC_TYPE_ALG_AES256;
 744                 break;
 745         default:
 746                 return -EINVAL;
 747         }
 748
 749         ctx->key_len = keylen;
 750         memcpy(ctx->key.aes, key, keylen);
 751         return 0;
 752 }
 753
 754 static int n2_des_setkey(struct crypto_skcipher *skcipher, const u8 *key,
 755                          unsigned int keylen)
 756 {
 757         struct crypto_tfm *tfm = crypto_skcipher_tfm(skcipher);
 758         struct n2_skcipher_context *ctx = crypto_tfm_ctx(tfm);
 759         struct n2_skcipher_alg *n2alg = n2_skcipher_alg(skcipher);
 760         int err;
 761
 762         err = verify_skcipher_des_key(skcipher, key);
 763         if (err)
 764                 return err;
 765
 766         ctx->enc_type = n2alg->enc_type;
 767
 768         ctx->key_len = keylen;
 769         memcpy(ctx->key.des, key, keylen);
 770         return 0;
 771 }
 772
 773 static int n2_3des_setkey(struct crypto_skcipher *skcipher, const u8 *key,
 774                           unsigned int keylen)
 775 {
 776         struct crypto_tfm *tfm = crypto_skcipher_tfm(skcipher);
 777         struct n2_skcipher_context *ctx = crypto_tfm_ctx(tfm);
 778         struct n2_skcipher_alg *n2alg = n2_skcipher_alg(skcipher);
 779         int err;
 780
 781         err = verify_skcipher_des3_key(skcipher, key);
 782         if (err)
 783                 return err;
 784
 785         ctx->enc_type = n2alg->enc_type;
 786
 787         ctx->key_len = keylen;
 788         memcpy(ctx->key.des3, key, keylen);
 789         return 0;
 790 }
 791
 792 static int n2_arc4_setkey(struct crypto_skcipher *skcipher, const u8 *key,
 793                           unsigned int keylen)
 794 {
 795         struct crypto_tfm *tfm = crypto_skcipher_tfm(skcipher);
 796         struct n2_skcipher_context *ctx = crypto_tfm_ctx(tfm);
 797         struct n2_skcipher_alg *n2alg = n2_skcipher_alg(skcipher);
 798         u8 *s = ctx->key.arc4;
 799         u8 *x = s + 256;
 800         u8 *y = x + 1;
 801         int i, j, k;
 802
 803         ctx->enc_type = n2alg->enc_type;
 804
 805         j = k = 0;
 806         *x = 0;
 807         *y = 0;
 808         for (i = 0; i < 256; i++)
 809                 s[i] = i;
 810         for (i = 0; i < 256; i++) {
 811                 u8 a = s[i];
 812                 j = (j + key[k] + a) & 0xff;
 813                 s[i] = s[j];
 814                 s[j] = a;
 815                 if (++k >= keylen)
 816                         k = 0;
 817         }
 818
 819         return 0;
 820 }
 821
 822 static inline int skcipher_descriptor_len(int nbytes, unsigned int block_size)
 823 {
 824         int this_len = nbytes;
 825
 826         this_len -= (nbytes & (block_size - 1));
 827         return this_len > (1 << 16) ? (1 << 16) : this_len;
 828 }
 829
 830 static int __n2_crypt_chunk(struct crypto_skcipher *skcipher,
 831                             struct n2_crypto_chunk *cp,
 832                             struct spu_queue *qp, bool encrypt)
 833 {
 834         struct n2_skcipher_context *ctx = crypto_skcipher_ctx(skcipher);
 835         struct cwq_initial_entry *ent;
 836         bool in_place;
 837         int i;
 838
 839         ent = spu_queue_alloc(qp, cp->arr_len);
 840         if (!ent) {
 841                 pr_info("queue_alloc() of %d fails\n",
 842                         cp->arr_len);
 843                 return -EBUSY;
 844         }
 845
 846         in_place = (cp->dest_paddr == cp->arr[0].src_paddr);
 847
 848         ent->control = control_word_base(cp->arr[0].src_len,
 849                                          0, ctx->enc_type, 0, 0,
 850                                          false, true, false, encrypt,
 851                                          OPCODE_ENCRYPT |
 852                                          (in_place ? OPCODE_INPLACE_BIT : 0));
 853         ent->src_addr = cp->arr[0].src_paddr;
 854         ent->auth_key_addr = 0UL;
 855         ent->auth_iv_addr = 0UL;
 856         ent->final_auth_state_addr = 0UL;
 857         ent->enc_key_addr = __pa(&ctx->key);
 858         ent->enc_iv_addr = cp->iv_paddr;
 859         ent->dest_addr = (in_place ? 0UL : cp->dest_paddr);
 860
 861         for (i = 1; i < cp->arr_len; i++) {
 862                 ent = spu_queue_next(qp, ent);
 863
 864                 ent->control = cp->arr[i].src_len - 1;
 865                 ent->src_addr = cp->arr[i].src_paddr;
 866                 ent->auth_key_addr = 0UL;
 867                 ent->auth_iv_addr = 0UL;
 868                 ent->final_auth_state_addr = 0UL;
 869                 ent->enc_key_addr = 0UL;
 870                 ent->enc_iv_addr = 0UL;
 871                 ent->dest_addr = 0UL;
 872         }
 873         ent->control |= CONTROL_END_OF_BLOCK;
 874
 875         return (spu_queue_submit(qp, ent) != HV_EOK) ? -EINVAL : 0;
 876 }
 877
 878 static int n2_compute_chunks(struct skcipher_request *req)
 879 {
 880         struct n2_request_context *rctx = skcipher_request_ctx(req);
 881         struct skcipher_walk *walk = &rctx->walk;
 882         struct n2_crypto_chunk *chunk;
 883         unsigned long dest_prev;
 884         unsigned int tot_len;
 885         bool prev_in_place;
 886         int err, nbytes;
 887
 888         err = skcipher_walk_async(walk, req);
 889         if (err)
 890                 return err;
 891
 892         INIT_LIST_HEAD(&rctx->chunk_list);
 893
 894         chunk = &rctx->chunk;
 895         INIT_LIST_HEAD(&chunk->entry);
 896
 897         chunk->iv_paddr = 0UL;
 898         chunk->arr_len = 0;
 899         chunk->dest_paddr = 0UL;
 900
 901         prev_in_place = false;
 902         dest_prev = ~0UL;
 903         tot_len = 0;
 904
 905         while ((nbytes = walk->nbytes) != 0) {
 906                 unsigned long dest_paddr, src_paddr;
 907                 bool in_place;
 908                 int this_len;
 909
 910                 src_paddr = (page_to_phys(walk->src.phys.page) +
 911                              walk->src.phys.offset);
 912                 dest_paddr = (page_to_phys(walk->dst.phys.page) +
 913                               walk->dst.phys.offset);
 914                 in_place = (src_paddr == dest_paddr);
 915                 this_len = skcipher_descriptor_len(nbytes, walk->blocksize);
 916
 917                 if (chunk->arr_len != 0) {
 918                         if (in_place != prev_in_place ||
 919                             (!prev_in_place &&
 920                              dest_paddr != dest_prev) ||
 921                             chunk->arr_len == N2_CHUNK_ARR_LEN ||
 922                             tot_len + this_len > (1 << 16)) {
 923                                 chunk->dest_final = dest_prev;
 924                                 list_add_tail(&chunk->entry,
 925                                               &rctx->chunk_list);
 926                                 chunk = kzalloc(sizeof(*chunk), GFP_ATOMIC);
 927                                 if (!chunk) {
 928                                         err = -ENOMEM;
 929                                         break;
 930                                 }
 931                                 INIT_LIST_HEAD(&chunk->entry);
 932                         }
 933                 }
 934                 if (chunk->arr_len == 0) {
 935                         chunk->dest_paddr = dest_paddr;
 936                         tot_len = 0;
 937                 }
 938                 chunk->arr[chunk->arr_len].src_paddr = src_paddr;
 939                 chunk->arr[chunk->arr_len].src_len = this_len;
 940                 chunk->arr_len++;
 941
 942                 dest_prev = dest_paddr + this_len;
 943                 prev_in_place = in_place;
 944                 tot_len += this_len;
 945
 946                 err = skcipher_walk_done(walk, nbytes - this_len);
 947                 if (err)
 948                         break;
 949         }
 950         if (!err && chunk->arr_len != 0) {
 951                 chunk->dest_final = dest_prev;
 952                 list_add_tail(&chunk->entry, &rctx->chunk_list);
 953         }
 954
 955         return err;
 956 }
 957
 958 static void n2_chunk_complete(struct skcipher_request *req, void *final_iv)
 959 {
 960         struct n2_request_context *rctx = skcipher_request_ctx(req);
 961         struct n2_crypto_chunk *c, *tmp;
 962
 963         if (final_iv)
 964                 memcpy(rctx->walk.iv, final_iv, rctx->walk.blocksize);
 965
 966         list_for_each_entry_safe(c, tmp, &rctx->chunk_list, entry) {
 967                 list_del(&c->entry);
 968                 if (unlikely(c != &rctx->chunk))
 969                         kfree(c);
 970         }
 971
 972 }
 973
 974 static int n2_do_ecb(struct skcipher_request *req, bool encrypt)
 975 {
 976         struct n2_request_context *rctx = skcipher_request_ctx(req);
 977         struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
 978         int err = n2_compute_chunks(req);
 979         struct n2_crypto_chunk *c, *tmp;
 980         unsigned long flags, hv_ret;
 981         struct spu_queue *qp;
 982
 983         if (err)
 984                 return err;
 985
 986         qp = cpu_to_cwq[get_cpu()];
 987         err = -ENODEV;
 988         if (!qp)
 989                 goto out;
 990
 991         spin_lock_irqsave(&qp->lock, flags);
 992
 993         list_for_each_entry_safe(c, tmp, &rctx->chunk_list, entry) {
 994                 err = __n2_crypt_chunk(tfm, c, qp, encrypt);
 995                 if (err)
 996                         break;
 997                 list_del(&c->entry);
 998                 if (unlikely(c != &rctx->chunk))
 999                         kfree(c);
1000         }
1001         if (!err) {
1002                 hv_ret = wait_for_tail(qp);
1003                 if (hv_ret != HV_EOK)
1004                         err = -EINVAL;
1005         }
1006
1007         spin_unlock_irqrestore(&qp->lock, flags);
1008
1009 out:
1010         put_cpu();
1011
1012         n2_chunk_complete(req, NULL);
1013         return err;
1014 }
1015
1016 static int n2_encrypt_ecb(struct skcipher_request *req)
1017 {
1018         return n2_do_ecb(req, true);
1019 }
1020
1021 static int n2_decrypt_ecb(struct skcipher_request *req)
1022 {
1023         return n2_do_ecb(req, false);
1024 }
1025
1026 static int n2_do_chaining(struct skcipher_request *req, bool encrypt)
1027 {
1028         struct n2_request_context *rctx = skcipher_request_ctx(req);
1029         struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
1030         unsigned long flags, hv_ret, iv_paddr;
1031         int err = n2_compute_chunks(req);
1032         struct n2_crypto_chunk *c, *tmp;
1033         struct spu_queue *qp;
1034         void *final_iv_addr;
1035
1036         final_iv_addr = NULL;
1037
1038         if (err)
1039                 return err;
1040
1041         qp = cpu_to_cwq[get_cpu()];
1042         err = -ENODEV;
1043         if (!qp)
1044                 goto out;
1045
1046         spin_lock_irqsave(&qp->lock, flags);
1047
1048         if (encrypt) {
1049                 iv_paddr = __pa(rctx->walk.iv);
1050                 list_for_each_entry_safe(c, tmp, &rctx->chunk_list,
1051                                          entry) {
1052                         c->iv_paddr = iv_paddr;
1053                         err = __n2_crypt_chunk(tfm, c, qp, true);
1054                         if (err)
1055                                 break;
1056                         iv_paddr = c->dest_final - rctx->walk.blocksize;
1057                         list_del(&c->entry);
1058                         if (unlikely(c != &rctx->chunk))
1059                                 kfree(c);
1060                 }
1061                 final_iv_addr = __va(iv_paddr);
1062         } else {
1063                 list_for_each_entry_safe_reverse(c, tmp, &rctx->chunk_list,
1064                                                  entry) {
1065                         if (c == &rctx->chunk) {
1066                                 iv_paddr = __pa(rctx->walk.iv);
1067                         } else {
1068                                 iv_paddr = (tmp->arr[tmp->arr_len-1].src_paddr +
1069                                             tmp->arr[tmp->arr_len-1].src_len -
1070                                             rctx->walk.blocksize);
1071                         }
1072                         if (!final_iv_addr) {
1073                                 unsigned long pa;
1074
1075                                 pa = (c->arr[c->arr_len-1].src_paddr +
1076                                       c->arr[c->arr_len-1].src_len -
1077                                       rctx->walk.blocksize);
1078                                 final_iv_addr = rctx->temp_iv;
1079                                 memcpy(rctx->temp_iv, __va(pa),
1080                                        rctx->walk.blocksize);
1081                         }
1082                         c->iv_paddr = iv_paddr;
1083                         err = __n2_crypt_chunk(tfm, c, qp, false);
1084                         if (err)
1085                                 break;
1086                         list_del(&c->entry);
1087                         if (unlikely(c != &rctx->chunk))
1088                                 kfree(c);
1089                 }
1090         }
1091         if (!err) {
1092                 hv_ret = wait_for_tail(qp);
1093                 if (hv_ret != HV_EOK)
1094                         err = -EINVAL;
1095         }
1096
1097         spin_unlock_irqrestore(&qp->lock, flags);
1098
1099 out:
1100         put_cpu();
1101
1102         n2_chunk_complete(req, err ? NULL : final_iv_addr);
1103         return err;
1104 }
1105
1106 static int n2_encrypt_chaining(struct skcipher_request *req)
1107 {
1108         return n2_do_chaining(req, true);
1109 }
1110
1111 static int n2_decrypt_chaining(struct skcipher_request *req)
1112 {
1113         return n2_do_chaining(req, false);
1114 }
1115
1116 struct n2_skcipher_tmpl {
1117         const char              *name;
1118         const char              *drv_name;
1119         u8                      block_size;
1120         u8                      enc_type;
1121         struct skcipher_alg     skcipher;
1122 };
1123
1124 static const struct n2_skcipher_tmpl skcipher_tmpls[] = {
1125         /* ARC4: only ECB is supported (chaining bits ignored) */
1126         {       .name           = "ecb(arc4)",
1127                 .drv_name       = "ecb-arc4",
1128                 .block_size     = 1,
1129                 .enc_type       = (ENC_TYPE_ALG_RC4_STREAM |
1130                                    ENC_TYPE_CHAINING_ECB),
1131                 .skcipher       = {
1132                         .min_keysize    = 1,
1133                         .max_keysize    = 256,
1134                         .setkey         = n2_arc4_setkey,
1135                         .encrypt        = n2_encrypt_ecb,
1136                         .decrypt        = n2_decrypt_ecb,
1137                 },
1138         },
1139
1140         /* DES: ECB CBC and CFB are supported */
1141         {       .name           = "ecb(des)",
1142                 .drv_name       = "ecb-des",
1143                 .block_size     = DES_BLOCK_SIZE,
1144                 .enc_type       = (ENC_TYPE_ALG_DES |
1145                                    ENC_TYPE_CHAINING_ECB),
1146                 .skcipher       = {
1147                         .min_keysize    = DES_KEY_SIZE,
1148                         .max_keysize    = DES_KEY_SIZE,
1149                         .setkey         = n2_des_setkey,
1150                         .encrypt        = n2_encrypt_ecb,
1151                         .decrypt        = n2_decrypt_ecb,
1152                 },
1153         },
1154         {       .name           = "cbc(des)",
1155                 .drv_name       = "cbc-des",
1156                 .block_size     = DES_BLOCK_SIZE,
1157                 .enc_type       = (ENC_TYPE_ALG_DES |
1158                                    ENC_TYPE_CHAINING_CBC),
1159                 .skcipher       = {
1160                         .ivsize         = DES_BLOCK_SIZE,
1161                         .min_keysize    = DES_KEY_SIZE,
1162                         .max_keysize    = DES_KEY_SIZE,
1163                         .setkey         = n2_des_setkey,
1164                         .encrypt        = n2_encrypt_chaining,
1165                         .decrypt        = n2_decrypt_chaining,
1166                 },
1167         },
1168         {       .name           = "cfb(des)",
1169                 .drv_name       = "cfb-des",
1170                 .block_size     = DES_BLOCK_SIZE,
1171                 .enc_type       = (ENC_TYPE_ALG_DES |
1172                                    ENC_TYPE_CHAINING_CFB),
1173                 .skcipher       = {
1174                         .min_keysize    = DES_KEY_SIZE,
1175                         .max_keysize    = DES_KEY_SIZE,
1176                         .setkey         = n2_des_setkey,
1177                         .encrypt        = n2_encrypt_chaining,
1178                         .decrypt        = n2_decrypt_chaining,
1179                 },
1180         },
1181
1182         /* 3DES: ECB CBC and CFB are supported */
1183         {       .name           = "ecb(des3_ede)",
1184                 .drv_name       = "ecb-3des",
1185                 .block_size     = DES_BLOCK_SIZE,
1186                 .enc_type       = (ENC_TYPE_ALG_3DES |
1187                                    ENC_TYPE_CHAINING_ECB),
1188                 .skcipher       = {
1189                         .min_keysize    = 3 * DES_KEY_SIZE,
1190                         .max_keysize    = 3 * DES_KEY_SIZE,
1191                         .setkey         = n2_3des_setkey,
1192                         .encrypt        = n2_encrypt_ecb,
1193                         .decrypt        = n2_decrypt_ecb,
1194                 },
1195         },
1196         {       .name           = "cbc(des3_ede)",
1197                 .drv_name       = "cbc-3des",
1198                 .block_size     = DES_BLOCK_SIZE,
1199                 .enc_type       = (ENC_TYPE_ALG_3DES |
1200                                    ENC_TYPE_CHAINING_CBC),
1201                 .skcipher       = {
1202                         .ivsize         = DES_BLOCK_SIZE,
1203                         .min_keysize    = 3 * DES_KEY_SIZE,
1204                         .max_keysize    = 3 * DES_KEY_SIZE,
1205                         .setkey         = n2_3des_setkey,
1206                         .encrypt        = n2_encrypt_chaining,
1207                         .decrypt        = n2_decrypt_chaining,
1208                 },
1209         },
1210         {       .name           = "cfb(des3_ede)",
1211                 .drv_name       = "cfb-3des",
1212                 .block_size     = DES_BLOCK_SIZE,
1213                 .enc_type       = (ENC_TYPE_ALG_3DES |
1214                                    ENC_TYPE_CHAINING_CFB),
1215                 .skcipher       = {
1216                         .min_keysize    = 3 * DES_KEY_SIZE,
1217                         .max_keysize    = 3 * DES_KEY_SIZE,
1218                         .setkey         = n2_3des_setkey,
1219                         .encrypt        = n2_encrypt_chaining,
1220                         .decrypt        = n2_decrypt_chaining,
1221                 },
1222         },
1223         /* AES: ECB CBC and CTR are supported */
1224         {       .name           = "ecb(aes)",
1225                 .drv_name       = "ecb-aes",
1226                 .block_size     = AES_BLOCK_SIZE,
1227                 .enc_type       = (ENC_TYPE_ALG_AES128 |
1228                                    ENC_TYPE_CHAINING_ECB),
1229                 .skcipher       = {
1230                         .min_keysize    = AES_MIN_KEY_SIZE,
1231                         .max_keysize    = AES_MAX_KEY_SIZE,
1232                         .setkey         = n2_aes_setkey,
1233                         .encrypt        = n2_encrypt_ecb,
1234                         .decrypt        = n2_decrypt_ecb,
1235                 },
1236         },
1237         {       .name           = "cbc(aes)",
1238                 .drv_name       = "cbc-aes",
1239                 .block_size     = AES_BLOCK_SIZE,
1240                 .enc_type       = (ENC_TYPE_ALG_AES128 |
1241                                    ENC_TYPE_CHAINING_CBC),
1242                 .skcipher       = {
1243                         .ivsize         = AES_BLOCK_SIZE,
1244                         .min_keysize    = AES_MIN_KEY_SIZE,
1245                         .max_keysize    = AES_MAX_KEY_SIZE,
1246                         .setkey         = n2_aes_setkey,
1247                         .encrypt        = n2_encrypt_chaining,
1248                         .decrypt        = n2_decrypt_chaining,
1249                 },
1250         },
1251         {       .name           = "ctr(aes)",
1252                 .drv_name       = "ctr-aes",
1253                 .block_size     = AES_BLOCK_SIZE,
1254                 .enc_type       = (ENC_TYPE_ALG_AES128 |
1255                                    ENC_TYPE_CHAINING_COUNTER),
1256                 .skcipher       = {
1257                         .ivsize         = AES_BLOCK_SIZE,
1258                         .min_keysize    = AES_MIN_KEY_SIZE,
1259                         .max_keysize    = AES_MAX_KEY_SIZE,
1260                         .setkey         = n2_aes_setkey,
1261                         .encrypt        = n2_encrypt_chaining,
1262                         .decrypt        = n2_encrypt_chaining,
1263                 },
1264         },
1265
1266 };
1267 #define NUM_CIPHER_TMPLS ARRAY_SIZE(skcipher_tmpls)
1268
1269 static LIST_HEAD(skcipher_algs);
1270
1271 struct n2_hash_tmpl {
1272         const char      *name;
1273         const u8        *hash_zero;
1274         const u32       *hash_init;
1275         u8              hw_op_hashsz;
1276         u8              digest_size;
1277         u8              block_size;
1278         u8              auth_type;
1279         u8              hmac_type;
1280 };
1281
1282 static const u32 n2_md5_init[MD5_HASH_WORDS] = {
1283         cpu_to_le32(MD5_H0),
1284         cpu_to_le32(MD5_H1),
1285         cpu_to_le32(MD5_H2),
1286         cpu_to_le32(MD5_H3),
1287 };
1288 static const u32 n2_sha1_init[SHA1_DIGEST_SIZE / 4] = {
1289         SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4,
1290 };
1291 static const u32 n2_sha256_init[SHA256_DIGEST_SIZE / 4] = {
1292         SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3,
1293         SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7,
1294 };
1295 static const u32 n2_sha224_init[SHA256_DIGEST_SIZE / 4] = {
1296         SHA224_H0, SHA224_H1, SHA224_H2, SHA224_H3,
1297         SHA224_H4, SHA224_H5, SHA224_H6, SHA224_H7,
1298 };
1299
1300 static const struct n2_hash_tmpl hash_tmpls[] = {
1301         { .name         = "md5",
1302           .hash_zero    = md5_zero_message_hash,
1303           .hash_init    = n2_md5_init,
1304           .auth_type    = AUTH_TYPE_MD5,
1305           .hmac_type    = AUTH_TYPE_HMAC_MD5,
1306           .hw_op_hashsz = MD5_DIGEST_SIZE,
1307           .digest_size  = MD5_DIGEST_SIZE,
1308           .block_size   = MD5_HMAC_BLOCK_SIZE },
1309         { .name         = "sha1",
1310           .hash_zero    = sha1_zero_message_hash,
1311           .hash_init    = n2_sha1_init,
1312           .auth_type    = AUTH_TYPE_SHA1,
1313           .hmac_type    = AUTH_TYPE_HMAC_SHA1,
1314           .hw_op_hashsz = SHA1_DIGEST_SIZE,
1315           .digest_size  = SHA1_DIGEST_SIZE,
1316           .block_size   = SHA1_BLOCK_SIZE },
1317         { .name         = "sha256",
1318           .hash_zero    = sha256_zero_message_hash,
1319           .hash_init    = n2_sha256_init,
1320           .auth_type    = AUTH_TYPE_SHA256,
1321           .hmac_type    = AUTH_TYPE_HMAC_SHA256,
1322           .hw_op_hashsz = SHA256_DIGEST_SIZE,
1323           .digest_size  = SHA256_DIGEST_SIZE,
1324           .block_size   = SHA256_BLOCK_SIZE },
1325         { .name         = "sha224",
1326           .hash_zero    = sha224_zero_message_hash,
1327           .hash_init    = n2_sha224_init,
1328           .auth_type    = AUTH_TYPE_SHA256,
1329           .hmac_type    = AUTH_TYPE_RESERVED,
1330           .hw_op_hashsz = SHA256_DIGEST_SIZE,
1331           .digest_size  = SHA224_DIGEST_SIZE,
1332           .block_size   = SHA224_BLOCK_SIZE },
1333 };
1334 #define NUM_HASH_TMPLS ARRAY_SIZE(hash_tmpls)
1335
1336 static LIST_HEAD(ahash_algs);
1337 static LIST_HEAD(hmac_algs);
1338
1339 static int algs_registered;
1340
1341 static void __n2_unregister_algs(void)
1342 {
1343         struct n2_skcipher_alg *skcipher, *skcipher_tmp;
1344         struct n2_ahash_alg *alg, *alg_tmp;
1345         struct n2_hmac_alg *hmac, *hmac_tmp;
1346
1347         list_for_each_entry_safe(skcipher, skcipher_tmp, &skcipher_algs, entry) {
1348                 crypto_unregister_skcipher(&skcipher->skcipher);
1349                 list_del(&skcipher->entry);
1350                 kfree(skcipher);
1351         }
1352         list_for_each_entry_safe(hmac, hmac_tmp, &hmac_algs, derived.entry) {
1353                 crypto_unregister_ahash(&hmac->derived.alg);
1354                 list_del(&hmac->derived.entry);
1355                 kfree(hmac);
1356         }
1357         list_for_each_entry_safe(alg, alg_tmp, &ahash_algs, entry) {
1358                 crypto_unregister_ahash(&alg->alg);
1359                 list_del(&alg->entry);
1360                 kfree(alg);
1361         }
1362 }
1363
1364 static int n2_skcipher_init_tfm(struct crypto_skcipher *tfm)
1365 {
1366         crypto_skcipher_set_reqsize(tfm, sizeof(struct n2_request_context));
1367         return 0;
1368 }
1369
1370 static int __n2_register_one_skcipher(const struct n2_skcipher_tmpl *tmpl)
1371 {
1372         struct n2_skcipher_alg *p = kzalloc(sizeof(*p), GFP_KERNEL);
1373         struct skcipher_alg *alg;
1374         int err;
1375
1376         if (!p)
1377                 return -ENOMEM;
1378
1379         alg = &p->skcipher;
1380         *alg = tmpl->skcipher;
1381
1382         snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);
1383         snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-n2", tmpl->drv_name);
1384         alg->base.cra_priority = N2_CRA_PRIORITY;
1385         alg->base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC;
1386         alg->base.cra_blocksize = tmpl->block_size;
1387         p->enc_type = tmpl->enc_type;
1388         alg->base.cra_ctxsize = sizeof(struct n2_skcipher_context);
1389         alg->base.cra_module = THIS_MODULE;
1390         alg->init = n2_skcipher_init_tfm;
1391
1392         list_add(&p->entry, &skcipher_algs);
1393         err = crypto_register_skcipher(alg);
1394         if (err) {
1395                 pr_err("%s alg registration failed\n", alg->base.cra_name);
1396                 list_del(&p->entry);
1397                 kfree(p);
1398         } else {
1399                 pr_info("%s alg registered\n", alg->base.cra_name);
1400         }
1401         return err;
1402 }
1403
1404 static int __n2_register_one_hmac(struct n2_ahash_alg *n2ahash)
1405 {
1406         struct n2_hmac_alg *p = kzalloc(sizeof(*p), GFP_KERNEL);
1407         struct ahash_alg *ahash;
1408         struct crypto_alg *base;
1409         int err;
1410
1411         if (!p)
1412                 return -ENOMEM;
1413
1414         p->child_alg = n2ahash->alg.halg.base.cra_name;
1415         memcpy(&p->derived, n2ahash, sizeof(struct n2_ahash_alg));
1416         INIT_LIST_HEAD(&p->derived.entry);
1417
1418         ahash = &p->derived.alg;
1419         ahash->digest = n2_hmac_async_digest;
1420         ahash->setkey = n2_hmac_async_setkey;
1421
1422         base = &ahash->halg.base;
1423         snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "hmac(%s)", p->child_alg);
1424         snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "hmac-%s-n2", p->child_alg);
1425
1426         base->cra_ctxsize = sizeof(struct n2_hmac_ctx);
1427         base->cra_init = n2_hmac_cra_init;
1428         base->cra_exit = n2_hmac_cra_exit;
1429
1430         list_add(&p->derived.entry, &hmac_algs);
1431         err = crypto_register_ahash(ahash);
1432         if (err) {
1433                 pr_err("%s alg registration failed\n", base->cra_name);
1434                 list_del(&p->derived.entry);
1435                 kfree(p);
1436         } else {
1437                 pr_info("%s alg registered\n", base->cra_name);
1438         }
1439         return err;
1440 }
1441
1442 static int __n2_register_one_ahash(const struct n2_hash_tmpl *tmpl)
1443 {
1444         struct n2_ahash_alg *p = kzalloc(sizeof(*p), GFP_KERNEL);
1445         struct hash_alg_common *halg;
1446         struct crypto_alg *base;
1447         struct ahash_alg *ahash;
1448         int err;
1449
1450         if (!p)
1451                 return -ENOMEM;
1452
1453         p->hash_zero = tmpl->hash_zero;
1454         p->hash_init = tmpl->hash_init;
1455         p->auth_type = tmpl->auth_type;
1456         p->hmac_type = tmpl->hmac_type;
1457         p->hw_op_hashsz = tmpl->hw_op_hashsz;
1458         p->digest_size = tmpl->digest_size;
1459
1460         ahash = &p->alg;
1461         ahash->init = n2_hash_async_init;
1462         ahash->update = n2_hash_async_update;
1463         ahash->final = n2_hash_async_final;
1464         ahash->finup = n2_hash_async_finup;
1465         ahash->digest = n2_hash_async_digest;
1466         ahash->export = n2_hash_async_noexport;
1467         ahash->import = n2_hash_async_noimport;
1468
1469         halg = &ahash->halg;
1470         halg->digestsize = tmpl->digest_size;
1471
1472         base = &halg->base;
1473         snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);
1474         snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-n2", tmpl->name);
1475         base->cra_priority = N2_CRA_PRIORITY;
1476         base->cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1477                           CRYPTO_ALG_NEED_FALLBACK;
1478         base->cra_blocksize = tmpl->block_size;
1479         base->cra_ctxsize = sizeof(struct n2_hash_ctx);
1480         base->cra_module = THIS_MODULE;
1481         base->cra_init = n2_hash_cra_init;
1482         base->cra_exit = n2_hash_cra_exit;
1483
1484         list_add(&p->entry, &ahash_algs);
1485         err = crypto_register_ahash(ahash);
1486         if (err) {
1487                 pr_err("%s alg registration failed\n", base->cra_name);
1488                 list_del(&p->entry);
1489                 kfree(p);
1490         } else {
1491                 pr_info("%s alg registered\n", base->cra_name);
1492         }
1493         if (!err && p->hmac_type != AUTH_TYPE_RESERVED)
1494                 err = __n2_register_one_hmac(p);
1495         return err;
1496 }
1497
1498 static int n2_register_algs(void)
1499 {
1500         int i, err = 0;
1501
1502         mutex_lock(&spu_lock);
1503         if (algs_registered++)
1504                 goto out;
1505
1506         for (i = 0; i < NUM_HASH_TMPLS; i++) {
1507                 err = __n2_register_one_ahash(&hash_tmpls[i]);
1508                 if (err) {
1509                         __n2_unregister_algs();
1510                         goto out;
1511                 }
1512         }
1513         for (i = 0; i < NUM_CIPHER_TMPLS; i++) {
1514                 err = __n2_register_one_skcipher(&skcipher_tmpls[i]);
1515                 if (err) {
1516                         __n2_unregister_algs();
1517                         goto out;
1518                 }
1519         }
1520
1521 out:
1522         mutex_unlock(&spu_lock);
1523         return err;
1524 }
1525
1526 static void n2_unregister_algs(void)
1527 {
1528         mutex_lock(&spu_lock);
1529         if (!--algs_registered)
1530                 __n2_unregister_algs();
1531         mutex_unlock(&spu_lock);
1532 }
1533
1534 /* To map CWQ queues to interrupt sources, the hypervisor API provides
1535  * a devino.  This isn't very useful to us because all of the
1536  * interrupts listed in the device_node have been translated to
1537  * Linux virtual IRQ cookie numbers.
1538  *
1539  * So we have to back-translate, going through the 'intr' and 'ino'
1540  * property tables of the n2cp MDESC node, matching it with the OF
1541  * 'interrupts' property entries, in order to to figure out which
1542  * devino goes to which already-translated IRQ.
1543  */
1544 static int find_devino_index(struct platform_device *dev, struct spu_mdesc_info *ip,
1545                              unsigned long dev_ino)
1546 {
1547         const unsigned int *dev_intrs;
1548         unsigned int intr;
1549         int i;
1550
1551         for (i = 0; i < ip->num_intrs; i++) {
1552                 if (ip->ino_table[i].ino == dev_ino)
1553                         break;
1554         }
1555         if (i == ip->num_intrs)
1556                 return -ENODEV;
1557
1558         intr = ip->ino_table[i].intr;
1559
1560         dev_intrs = of_get_property(dev->dev.of_node, "interrupts", NULL);
1561         if (!dev_intrs)
1562                 return -ENODEV;
1563
1564         for (i = 0; i < dev->archdata.num_irqs; i++) {
1565                 if (dev_intrs[i] == intr)
1566                         return i;
1567         }
1568
1569         return -ENODEV;
1570 }
1571
1572 static int spu_map_ino(struct platform_device *dev, struct spu_mdesc_info *ip,
1573                        const char *irq_name, struct spu_queue *p,
1574                        irq_handler_t handler)
1575 {
1576         unsigned long herr;
1577         int index;
1578
1579         herr = sun4v_ncs_qhandle_to_devino(p->qhandle, &p->devino);
1580         if (herr)
1581                 return -EINVAL;
1582
1583         index = find_devino_index(dev, ip, p->devino);
1584         if (index < 0)
1585                 return index;
1586
1587         p->irq = dev->archdata.irqs[index];
1588
1589         sprintf(p->irq_name, "%s-%d", irq_name, index);
1590
1591         return request_irq(p->irq, handler, 0, p->irq_name, p);
1592 }
1593
1594 static struct kmem_cache *queue_cache[2];
1595
1596 static void *new_queue(unsigned long q_type)
1597 {
1598         return kmem_cache_zalloc(queue_cache[q_type - 1], GFP_KERNEL);
1599 }
1600
1601 static void free_queue(void *p, unsigned long q_type)
1602 {
1603         kmem_cache_free(queue_cache[q_type - 1], p);
1604 }
1605
1606 static int queue_cache_init(void)
1607 {
1608         if (!queue_cache[HV_NCS_QTYPE_MAU - 1])
1609                 queue_cache[HV_NCS_QTYPE_MAU - 1] =
1610                         kmem_cache_create("mau_queue",
1611                                           (MAU_NUM_ENTRIES *
1612                                            MAU_ENTRY_SIZE),
1613                                           MAU_ENTRY_SIZE, 0, NULL);
1614         if (!queue_cache[HV_NCS_QTYPE_MAU - 1])
1615                 return -ENOMEM;
1616
1617         if (!queue_cache[HV_NCS_QTYPE_CWQ - 1])
1618                 queue_cache[HV_NCS_QTYPE_CWQ - 1] =
1619                         kmem_cache_create("cwq_queue",
1620                                           (CWQ_NUM_ENTRIES *
1621                                            CWQ_ENTRY_SIZE),
1622                                           CWQ_ENTRY_SIZE, 0, NULL);
1623         if (!queue_cache[HV_NCS_QTYPE_CWQ - 1]) {
1624                 kmem_cache_destroy(queue_cache[HV_NCS_QTYPE_MAU - 1]);
1625                 queue_cache[HV_NCS_QTYPE_MAU - 1] = NULL;
1626                 return -ENOMEM;
1627         }
1628         return 0;
1629 }
1630
1631 static void queue_cache_destroy(void)
1632 {
1633         kmem_cache_destroy(queue_cache[HV_NCS_QTYPE_MAU - 1]);
1634         kmem_cache_destroy(queue_cache[HV_NCS_QTYPE_CWQ - 1]);
1635         queue_cache[HV_NCS_QTYPE_MAU - 1] = NULL;
1636         queue_cache[HV_NCS_QTYPE_CWQ - 1] = NULL;
1637 }
1638
1639 static long spu_queue_register_workfn(void *arg)
1640 {
1641         struct spu_qreg *qr = arg;
1642         struct spu_queue *p = qr->queue;
1643         unsigned long q_type = qr->type;
1644         unsigned long hv_ret;
1645
1646         hv_ret = sun4v_ncs_qconf(q_type, __pa(p->q),
1647                                  CWQ_NUM_ENTRIES, &p->qhandle);
1648         if (!hv_ret)
1649                 sun4v_ncs_sethead_marker(p->qhandle, 0);
1650
1651         return hv_ret ? -EINVAL : 0;
1652 }
1653
1654 static int spu_queue_register(struct spu_queue *p, unsigned long q_type)
1655 {
1656         int cpu = cpumask_any_and(&p->sharing, cpu_online_mask);
1657         struct spu_qreg qr = { .queue = p, .type = q_type };
1658
1659         return work_on_cpu_safe(cpu, spu_queue_register_workfn, &qr);
1660 }
1661
1662 static int spu_queue_setup(struct spu_queue *p)
1663 {
1664         int err;
1665
1666         p->q = new_queue(p->q_type);
1667         if (!p->q)
1668                 return -ENOMEM;
1669
1670         err = spu_queue_register(p, p->q_type);
1671         if (err) {
1672                 free_queue(p->q, p->q_type);
1673                 p->q = NULL;
1674         }
1675
1676         return err;
1677 }
1678
1679 static void spu_queue_destroy(struct spu_queue *p)
1680 {
1681         unsigned long hv_ret;
1682
1683         if (!p->q)
1684                 return;
1685
1686         hv_ret = sun4v_ncs_qconf(p->q_type, p->qhandle, 0, &p->qhandle);
1687
1688         if (!hv_ret)
1689                 free_queue(p->q, p->q_type);
1690 }
1691
1692 static void spu_list_destroy(struct list_head *list)
1693 {
1694         struct spu_queue *p, *n;
1695
1696         list_for_each_entry_safe(p, n, list, list) {
1697                 int i;
1698
1699                 for (i = 0; i < NR_CPUS; i++) {
1700                         if (cpu_to_cwq[i] == p)
1701                                 cpu_to_cwq[i] = NULL;
1702                 }
1703
1704                 if (p->irq) {
1705                         free_irq(p->irq, p);
1706                         p->irq = 0;
1707                 }
1708                 spu_queue_destroy(p);
1709                 list_del(&p->list);
1710                 kfree(p);
1711         }
1712 }
1713
1714 /* Walk the backward arcs of a CWQ 'exec-unit' node,
1715  * gathering cpu membership information.
1716  */
1717 static int spu_mdesc_walk_arcs(struct mdesc_handle *mdesc,
1718                                struct platform_device *dev,
1719                                u64 node, struct spu_queue *p,
1720                                struct spu_queue **table)
1721 {
1722         u64 arc;
1723
1724         mdesc_for_each_arc(arc, mdesc, node, MDESC_ARC_TYPE_BACK) {
1725                 u64 tgt = mdesc_arc_target(mdesc, arc);
1726                 const char *name = mdesc_node_name(mdesc, tgt);
1727                 const u64 *id;
1728
1729                 if (strcmp(name, "cpu"))
1730                         continue;
1731                 id = mdesc_get_property(mdesc, tgt, "id", NULL);
1732                 if (table[*id] != NULL) {
1733                         dev_err(&dev->dev, "%pOF: SPU cpu slot already set.\n",
1734                                 dev->dev.of_node);
1735                         return -EINVAL;
1736                 }
1737                 cpumask_set_cpu(*id, &p->sharing);
1738                 table[*id] = p;
1739         }
1740         return 0;
1741 }
1742
1743 /* Process an 'exec-unit' MDESC node of type 'cwq'.  */
1744 static int handle_exec_unit(struct spu_mdesc_info *ip, struct list_head *list,
1745                             struct platform_device *dev, struct mdesc_handle *mdesc,
1746                             u64 node, const char *iname, unsigned long q_type,
1747                             irq_handler_t handler, struct spu_queue **table)
1748 {
1749         struct spu_queue *p;
1750         int err;
1751
1752         p = kzalloc(sizeof(struct spu_queue), GFP_KERNEL);
1753         if (!p) {
1754                 dev_err(&dev->dev, "%pOF: Could not allocate SPU queue.\n",
1755                         dev->dev.of_node);
1756                 return -ENOMEM;
1757         }
1758
1759         cpumask_clear(&p->sharing);
1760         spin_lock_init(&p->lock);
1761         p->q_type = q_type;
1762         INIT_LIST_HEAD(&p->jobs);
1763         list_add(&p->list, list);
1764
1765         err = spu_mdesc_walk_arcs(mdesc, dev, node, p, table);
1766         if (err)
1767                 return err;
1768
1769         err = spu_queue_setup(p);
1770         if (err)
1771                 return err;
1772
1773         return spu_map_ino(dev, ip, iname, p, handler);
1774 }
1775
1776 static int spu_mdesc_scan(struct mdesc_handle *mdesc, struct platform_device *dev,
1777                           struct spu_mdesc_info *ip, struct list_head *list,
1778                           const char *exec_name, unsigned long q_type,
1779                           irq_handler_t handler, struct spu_queue **table)
1780 {
1781         int err = 0;
1782         u64 node;
1783
1784         mdesc_for_each_node_by_name(mdesc, node, "exec-unit") {
1785                 const char *type;
1786
1787                 type = mdesc_get_property(mdesc, node, "type", NULL);
1788                 if (!type || strcmp(type, exec_name))
1789                         continue;
1790
1791                 err = handle_exec_unit(ip, list, dev, mdesc, node,
1792                                        exec_name, q_type, handler, table);
1793                 if (err) {
1794                         spu_list_destroy(list);
1795                         break;
1796                 }
1797         }
1798
1799         return err;
1800 }
1801
1802 static int get_irq_props(struct mdesc_handle *mdesc, u64 node,
1803                          struct spu_mdesc_info *ip)
1804 {
1805         const u64 *ino;
1806         int ino_len;
1807         int i;
1808
1809         ino = mdesc_get_property(mdesc, node, "ino", &ino_len);
1810         if (!ino) {
1811                 printk("NO 'ino'\n");
1812                 return -ENODEV;
1813         }
1814
1815         ip->num_intrs = ino_len / sizeof(u64);
1816         ip->ino_table = kzalloc((sizeof(struct ino_blob) *
1817                                  ip->num_intrs),
1818                                 GFP_KERNEL);
1819         if (!ip->ino_table)
1820                 return -ENOMEM;
1821
1822         for (i = 0; i < ip->num_intrs; i++) {
1823                 struct ino_blob *b = &ip->ino_table[i];
1824                 b->intr = i + 1;
1825                 b->ino = ino[i];
1826         }
1827
1828         return 0;
1829 }
1830
1831 static int grab_mdesc_irq_props(struct mdesc_handle *mdesc,
1832                                 struct platform_device *dev,
1833                                 struct spu_mdesc_info *ip,
1834                                 const char *node_name)
1835 {
1836         const unsigned int *reg;
1837         u64 node;
1838
1839         reg = of_get_property(dev->dev.of_node, "reg", NULL);
1840         if (!reg)
1841                 return -ENODEV;
1842
1843         mdesc_for_each_node_by_name(mdesc, node, "virtual-device") {
1844                 const char *name;
1845                 const u64 *chdl;
1846
1847                 name = mdesc_get_property(mdesc, node, "name", NULL);
1848                 if (!name || strcmp(name, node_name))
1849                         continue;
1850                 chdl = mdesc_get_property(mdesc, node, "cfg-handle", NULL);
1851                 if (!chdl || (*chdl != *reg))
1852                         continue;
1853                 ip->cfg_handle = *chdl;
1854                 return get_irq_props(mdesc, node, ip);
1855         }
1856
1857         return -ENODEV;
1858 }
1859
1860 static unsigned long n2_spu_hvapi_major;
1861 static unsigned long n2_spu_hvapi_minor;
1862
1863 static int n2_spu_hvapi_register(void)
1864 {
1865         int err;
1866
1867         n2_spu_hvapi_major = 2;
1868         n2_spu_hvapi_minor = 0;
1869
1870         err = sun4v_hvapi_register(HV_GRP_NCS,
1871                                    n2_spu_hvapi_major,
1872                                    &n2_spu_hvapi_minor);
1873
1874         if (!err)
1875                 pr_info("Registered NCS HVAPI version %lu.%lu\n",
1876                         n2_spu_hvapi_major,
1877                         n2_spu_hvapi_minor);
1878
1879         return err;
1880 }
1881
1882 static void n2_spu_hvapi_unregister(void)
1883 {
1884         sun4v_hvapi_unregister(HV_GRP_NCS);
1885 }
1886
1887 static int global_ref;
1888
1889 static int grab_global_resources(void)
1890 {
1891         int err = 0;
1892
1893         mutex_lock(&spu_lock);
1894
1895         if (global_ref++)
1896                 goto out;
1897
1898         err = n2_spu_hvapi_register();
1899         if (err)
1900                 goto out;
1901
1902         err = queue_cache_init();
1903         if (err)
1904                 goto out_hvapi_release;
1905
1906         err = -ENOMEM;
1907         cpu_to_cwq = kcalloc(NR_CPUS, sizeof(struct spu_queue *),
1908                              GFP_KERNEL);
1909         if (!cpu_to_cwq)
1910                 goto out_queue_cache_destroy;
1911
1912         cpu_to_mau = kcalloc(NR_CPUS, sizeof(struct spu_queue *),
1913                              GFP_KERNEL);
1914         if (!cpu_to_mau)
1915                 goto out_free_cwq_table;
1916
1917         err = 0;
1918
1919 out:
1920         if (err)
1921                 global_ref--;
1922         mutex_unlock(&spu_lock);
1923         return err;
1924
1925 out_free_cwq_table:
1926         kfree(cpu_to_cwq);
1927         cpu_to_cwq = NULL;
1928
1929 out_queue_cache_destroy:
1930         queue_cache_destroy();
1931
1932 out_hvapi_release:
1933         n2_spu_hvapi_unregister();
1934         goto out;
1935 }
1936
1937 static void release_global_resources(void)
1938 {
1939         mutex_lock(&spu_lock);
1940         if (!--global_ref) {
1941                 kfree(cpu_to_cwq);
1942                 cpu_to_cwq = NULL;
1943
1944                 kfree(cpu_to_mau);
1945                 cpu_to_mau = NULL;
1946
1947                 queue_cache_destroy();
1948                 n2_spu_hvapi_unregister();
1949         }
1950         mutex_unlock(&spu_lock);
1951 }
1952
1953 static struct n2_crypto *alloc_n2cp(void)
1954 {
1955         struct n2_crypto *np = kzalloc(sizeof(struct n2_crypto), GFP_KERNEL);
1956
1957         if (np)
1958                 INIT_LIST_HEAD(&np->cwq_list);
1959
1960         return np;
1961 }
1962
1963 static void free_n2cp(struct n2_crypto *np)
1964 {
1965         kfree(np->cwq_info.ino_table);
1966         np->cwq_info.ino_table = NULL;
1967
1968         kfree(np);
1969 }
1970
1971 static void n2_spu_driver_version(void)
1972 {
1973         static int n2_spu_version_printed;
1974
1975         if (n2_spu_version_printed++ == 0)
1976                 pr_info("%s", version);
1977 }
1978
1979 static int n2_crypto_probe(struct platform_device *dev)
1980 {
1981         struct mdesc_handle *mdesc;
1982         struct n2_crypto *np;
1983         int err;
1984
1985         n2_spu_driver_version();
1986
1987         pr_info("Found N2CP at %pOF\n", dev->dev.of_node);
1988
1989         np = alloc_n2cp();
1990         if (!np) {
1991                 dev_err(&dev->dev, "%pOF: Unable to allocate n2cp.\n",
1992                         dev->dev.of_node);
1993                 return -ENOMEM;
1994         }
1995
1996         err = grab_global_resources();
1997         if (err) {
1998                 dev_err(&dev->dev, "%pOF: Unable to grab global resources.\n",
1999                         dev->dev.of_node);
2000                 goto out_free_n2cp;
2001         }
2002
2003         mdesc = mdesc_grab();
2004
2005         if (!mdesc) {
2006                 dev_err(&dev->dev, "%pOF: Unable to grab MDESC.\n",
2007                         dev->dev.of_node);
2008                 err = -ENODEV;
2009                 goto out_free_global;
2010         }
2011         err = grab_mdesc_irq_props(mdesc, dev, &np->cwq_info, "n2cp");
2012         if (err) {
2013                 dev_err(&dev->dev, "%pOF: Unable to grab IRQ props.\n",
2014                         dev->dev.of_node);
2015                 mdesc_release(mdesc);
2016                 goto out_free_global;
2017         }
2018
2019         err = spu_mdesc_scan(mdesc, dev, &np->cwq_info, &np->cwq_list,
2020                              "cwq", HV_NCS_QTYPE_CWQ, cwq_intr,
2021                              cpu_to_cwq);
2022         mdesc_release(mdesc);
2023
2024         if (err) {
2025                 dev_err(&dev->dev, "%pOF: CWQ MDESC scan failed.\n",
2026                         dev->dev.of_node);
2027                 goto out_free_global;
2028         }
2029
2030         err = n2_register_algs();
2031         if (err) {
2032                 dev_err(&dev->dev, "%pOF: Unable to register algorithms.\n",
2033                         dev->dev.of_node);
2034                 goto out_free_spu_list;
2035         }
2036
2037         dev_set_drvdata(&dev->dev, np);
2038
2039         return 0;
2040
2041 out_free_spu_list:
2042         spu_list_destroy(&np->cwq_list);
2043
2044 out_free_global:
2045         release_global_resources();
2046
2047 out_free_n2cp:
2048         free_n2cp(np);
2049
2050         return err;
2051 }
2052
2053 static int n2_crypto_remove(struct platform_device *dev)
2054 {
2055         struct n2_crypto *np = dev_get_drvdata(&dev->dev);
2056
2057         n2_unregister_algs();
2058
2059         spu_list_destroy(&np->cwq_list);
2060
2061         release_global_resources();
2062
2063         free_n2cp(np);
2064
2065         return 0;
2066 }
2067
2068 static struct n2_mau *alloc_ncp(void)
2069 {
2070         struct n2_mau *mp = kzalloc(sizeof(struct n2_mau), GFP_KERNEL);
2071
2072         if (mp)
2073                 INIT_LIST_HEAD(&mp->mau_list);
2074
2075         return mp;
2076 }
2077
2078 static void free_ncp(struct n2_mau *mp)
2079 {
2080         kfree(mp->mau_info.ino_table);
2081         mp->mau_info.ino_table = NULL;
2082
2083         kfree(mp);
2084 }
2085
2086 static int n2_mau_probe(struct platform_device *dev)
2087 {
2088         struct mdesc_handle *mdesc;
2089         struct n2_mau *mp;
2090         int err;
2091
2092         n2_spu_driver_version();
2093
2094         pr_info("Found NCP at %pOF\n", dev->dev.of_node);
2095
2096         mp = alloc_ncp();
2097         if (!mp) {
2098                 dev_err(&dev->dev, "%pOF: Unable to allocate ncp.\n",
2099                         dev->dev.of_node);
2100                 return -ENOMEM;
2101         }
2102
2103         err = grab_global_resources();
2104         if (err) {
2105                 dev_err(&dev->dev, "%pOF: Unable to grab global resources.\n",
2106                         dev->dev.of_node);
2107                 goto out_free_ncp;
2108         }
2109
2110         mdesc = mdesc_grab();
2111
2112         if (!mdesc) {
2113                 dev_err(&dev->dev, "%pOF: Unable to grab MDESC.\n",
2114                         dev->dev.of_node);
2115                 err = -ENODEV;
2116                 goto out_free_global;
2117         }
2118
2119         err = grab_mdesc_irq_props(mdesc, dev, &mp->mau_info, "ncp");
2120         if (err) {
2121                 dev_err(&dev->dev, "%pOF: Unable to grab IRQ props.\n",
2122                         dev->dev.of_node);
2123                 mdesc_release(mdesc);
2124                 goto out_free_global;
2125         }
2126
2127         err = spu_mdesc_scan(mdesc, dev, &mp->mau_info, &mp->mau_list,
2128                              "mau", HV_NCS_QTYPE_MAU, mau_intr,
2129                              cpu_to_mau);
2130         mdesc_release(mdesc);
2131
2132         if (err) {
2133                 dev_err(&dev->dev, "%pOF: MAU MDESC scan failed.\n",
2134                         dev->dev.of_node);
2135                 goto out_free_global;
2136         }
2137
2138         dev_set_drvdata(&dev->dev, mp);
2139
2140         return 0;
2141
2142 out_free_global:
2143         release_global_resources();
2144
2145 out_free_ncp:
2146         free_ncp(mp);
2147
2148         return err;
2149 }
2150
2151 static int n2_mau_remove(struct platform_device *dev)
2152 {
2153         struct n2_mau *mp = dev_get_drvdata(&dev->dev);
2154
2155         spu_list_destroy(&mp->mau_list);
2156
2157         release_global_resources();
2158
2159         free_ncp(mp);
2160
2161         return 0;
2162 }
2163
2164 static const struct of_device_id n2_crypto_match[] = {
2165         {
2166                 .name = "n2cp",
2167                 .compatible = "SUNW,n2-cwq",
2168         },
2169         {
2170                 .name = "n2cp",
2171                 .compatible = "SUNW,vf-cwq",
2172         },
2173         {
2174                 .name = "n2cp",
2175                 .compatible = "SUNW,kt-cwq",
2176         },
2177         {},
2178 };
2179
2180 MODULE_DEVICE_TABLE(of, n2_crypto_match);
2181
2182 static struct platform_driver n2_crypto_driver = {
2183         .driver = {
2184                 .name           =       "n2cp",
2185                 .of_match_table =       n2_crypto_match,
2186         },
2187         .probe          =       n2_crypto_probe,
2188         .remove         =       n2_crypto_remove,
2189 };
2190
2191 static const struct of_device_id n2_mau_match[] = {
2192         {
2193                 .name = "ncp",
2194                 .compatible = "SUNW,n2-mau",
2195         },
2196         {
2197                 .name = "ncp",
2198                 .compatible = "SUNW,vf-mau",
2199         },
2200         {
2201                 .name = "ncp",
2202                 .compatible = "SUNW,kt-mau",
2203         },
2204         {},
2205 };
2206
2207 MODULE_DEVICE_TABLE(of, n2_mau_match);
2208
2209 static struct platform_driver n2_mau_driver = {
2210         .driver = {
2211                 .name           =       "ncp",
2212                 .of_match_table =       n2_mau_match,
2213         },
2214         .probe          =       n2_mau_probe,
2215         .remove         =       n2_mau_remove,
2216 };
2217
2218 static struct platform_driver * const drivers[] = {
2219         &n2_crypto_driver,
2220         &n2_mau_driver,
2221 };
2222
2223 static int __init n2_init(void)
2224 {
2225         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2226 }
2227
2228 static void __exit n2_exit(void)
2229 {
2230         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2231 }
2232
2233 module_init(n2_init);
2234 module_exit(n2_exit);