1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hash algorithms supported by the CESA: MD5, SHA1 and SHA256.
5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
6 * Author: Arnaud Ebalard <arno@natisbad.org>
8 * This work is based on an initial version written by
9 * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
12 #include <crypto/hmac.h>
13 #include <crypto/md5.h>
14 #include <crypto/sha.h>
18 struct mv_cesa_ahash_dma_iter {
19 struct mv_cesa_dma_iter base;
20 struct mv_cesa_sg_dma_iter src;
24 mv_cesa_ahash_req_iter_init(struct mv_cesa_ahash_dma_iter *iter,
25 struct ahash_request *req)
27 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
28 unsigned int len = req->nbytes + creq->cache_ptr;
31 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
33 mv_cesa_req_dma_iter_init(&iter->base, len);
34 mv_cesa_sg_dma_iter_init(&iter->src, req->src, DMA_TO_DEVICE);
35 iter->src.op_offset = creq->cache_ptr;
39 mv_cesa_ahash_req_iter_next_op(struct mv_cesa_ahash_dma_iter *iter)
41 iter->src.op_offset = 0;
43 return mv_cesa_req_dma_iter_next_op(&iter->base);
47 mv_cesa_ahash_dma_alloc_cache(struct mv_cesa_ahash_dma_req *req, gfp_t flags)
49 req->cache = dma_pool_alloc(cesa_dev->dma->cache_pool, flags,
58 mv_cesa_ahash_dma_free_cache(struct mv_cesa_ahash_dma_req *req)
63 dma_pool_free(cesa_dev->dma->cache_pool, req->cache,
67 static int mv_cesa_ahash_dma_alloc_padding(struct mv_cesa_ahash_dma_req *req,
73 req->padding = dma_pool_alloc(cesa_dev->dma->padding_pool, flags,
81 static void mv_cesa_ahash_dma_free_padding(struct mv_cesa_ahash_dma_req *req)
86 dma_pool_free(cesa_dev->dma->padding_pool, req->padding,
91 static inline void mv_cesa_ahash_dma_last_cleanup(struct ahash_request *req)
93 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
95 mv_cesa_ahash_dma_free_padding(&creq->req.dma);
98 static inline void mv_cesa_ahash_dma_cleanup(struct ahash_request *req)
100 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
102 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
103 mv_cesa_ahash_dma_free_cache(&creq->req.dma);
104 mv_cesa_dma_cleanup(&creq->base);
107 static inline void mv_cesa_ahash_cleanup(struct ahash_request *req)
109 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
111 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
112 mv_cesa_ahash_dma_cleanup(req);
115 static void mv_cesa_ahash_last_cleanup(struct ahash_request *req)
117 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
119 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
120 mv_cesa_ahash_dma_last_cleanup(req);
123 static int mv_cesa_ahash_pad_len(struct mv_cesa_ahash_req *creq)
125 unsigned int index, padlen;
127 index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
128 padlen = (index < 56) ? (56 - index) : (64 + 56 - index);
133 static int mv_cesa_ahash_pad_req(struct mv_cesa_ahash_req *creq, u8 *buf)
138 /* Pad out to 56 mod 64 */
139 padlen = mv_cesa_ahash_pad_len(creq);
140 memset(buf + 1, 0, padlen - 1);
143 __le64 bits = cpu_to_le64(creq->len << 3);
145 memcpy(buf + padlen, &bits, sizeof(bits));
147 __be64 bits = cpu_to_be64(creq->len << 3);
149 memcpy(buf + padlen, &bits, sizeof(bits));
155 static void mv_cesa_ahash_std_step(struct ahash_request *req)
157 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
158 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
159 struct mv_cesa_engine *engine = creq->base.engine;
160 struct mv_cesa_op_ctx *op;
161 unsigned int new_cache_ptr = 0;
164 unsigned int digsize;
167 mv_cesa_adjust_op(engine, &creq->op_tmpl);
168 memcpy_toio(engine->sram, &creq->op_tmpl, sizeof(creq->op_tmpl));
171 digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
172 for (i = 0; i < digsize / 4; i++)
173 writel_relaxed(creq->state[i],
174 engine->regs + CESA_IVDIG(i));
178 memcpy_toio(engine->sram + CESA_SA_DATA_SRAM_OFFSET,
179 creq->cache, creq->cache_ptr);
181 len = min_t(size_t, req->nbytes + creq->cache_ptr - sreq->offset,
182 CESA_SA_SRAM_PAYLOAD_SIZE);
184 if (!creq->last_req) {
185 new_cache_ptr = len & CESA_HASH_BLOCK_SIZE_MSK;
186 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
189 if (len - creq->cache_ptr)
190 sreq->offset += sg_pcopy_to_buffer(req->src, creq->src_nents,
192 CESA_SA_DATA_SRAM_OFFSET +
194 len - creq->cache_ptr,
199 frag_mode = mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK;
201 if (creq->last_req && sreq->offset == req->nbytes &&
202 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
203 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
204 frag_mode = CESA_SA_DESC_CFG_NOT_FRAG;
205 else if (frag_mode == CESA_SA_DESC_CFG_MID_FRAG)
206 frag_mode = CESA_SA_DESC_CFG_LAST_FRAG;
209 if (frag_mode == CESA_SA_DESC_CFG_NOT_FRAG ||
210 frag_mode == CESA_SA_DESC_CFG_LAST_FRAG) {
212 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
213 mv_cesa_set_mac_op_total_len(op, creq->len);
215 int trailerlen = mv_cesa_ahash_pad_len(creq) + 8;
217 if (len + trailerlen > CESA_SA_SRAM_PAYLOAD_SIZE) {
218 len &= CESA_HASH_BLOCK_SIZE_MSK;
219 new_cache_ptr = 64 - trailerlen;
220 memcpy_fromio(creq->cache,
222 CESA_SA_DATA_SRAM_OFFSET + len,
225 len += mv_cesa_ahash_pad_req(creq,
227 CESA_SA_DATA_SRAM_OFFSET);
230 if (frag_mode == CESA_SA_DESC_CFG_LAST_FRAG)
231 frag_mode = CESA_SA_DESC_CFG_MID_FRAG;
233 frag_mode = CESA_SA_DESC_CFG_FIRST_FRAG;
237 mv_cesa_set_mac_op_frag_len(op, len);
238 mv_cesa_update_op_cfg(op, frag_mode, CESA_SA_DESC_CFG_FRAG_MSK);
240 /* FIXME: only update enc_len field */
241 memcpy_toio(engine->sram, op, sizeof(*op));
243 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
244 mv_cesa_update_op_cfg(op, CESA_SA_DESC_CFG_MID_FRAG,
245 CESA_SA_DESC_CFG_FRAG_MSK);
247 creq->cache_ptr = new_cache_ptr;
249 mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE);
250 writel_relaxed(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG);
251 WARN_ON(readl(engine->regs + CESA_SA_CMD) &
252 CESA_SA_CMD_EN_CESA_SA_ACCL0);
253 writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
256 static int mv_cesa_ahash_std_process(struct ahash_request *req, u32 status)
258 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
259 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
261 if (sreq->offset < (req->nbytes - creq->cache_ptr))
267 static inline void mv_cesa_ahash_dma_prepare(struct ahash_request *req)
269 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
270 struct mv_cesa_req *basereq = &creq->base;
272 mv_cesa_dma_prepare(basereq, basereq->engine);
275 static void mv_cesa_ahash_std_prepare(struct ahash_request *req)
277 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
278 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
283 static void mv_cesa_ahash_dma_step(struct ahash_request *req)
285 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
286 struct mv_cesa_req *base = &creq->base;
288 /* We must explicitly set the digest state. */
289 if (base->chain.first->flags & CESA_TDMA_SET_STATE) {
290 struct mv_cesa_engine *engine = base->engine;
293 /* Set the hash state in the IVDIG regs. */
294 for (i = 0; i < ARRAY_SIZE(creq->state); i++)
295 writel_relaxed(creq->state[i], engine->regs +
299 mv_cesa_dma_step(base);
302 static void mv_cesa_ahash_step(struct crypto_async_request *req)
304 struct ahash_request *ahashreq = ahash_request_cast(req);
305 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
307 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
308 mv_cesa_ahash_dma_step(ahashreq);
310 mv_cesa_ahash_std_step(ahashreq);
313 static int mv_cesa_ahash_process(struct crypto_async_request *req, u32 status)
315 struct ahash_request *ahashreq = ahash_request_cast(req);
316 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
318 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
319 return mv_cesa_dma_process(&creq->base, status);
321 return mv_cesa_ahash_std_process(ahashreq, status);
324 static void mv_cesa_ahash_complete(struct crypto_async_request *req)
326 struct ahash_request *ahashreq = ahash_request_cast(req);
327 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
328 struct mv_cesa_engine *engine = creq->base.engine;
329 unsigned int digsize;
332 digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));
334 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ &&
335 (creq->base.chain.last->flags & CESA_TDMA_TYPE_MSK) ==
340 * Result is already in the correct endianness when the SA is
343 data = creq->base.chain.last->op->ctx.hash.hash;
344 for (i = 0; i < digsize / 4; i++)
345 creq->state[i] = cpu_to_le32(data[i]);
347 memcpy(ahashreq->result, data, digsize);
349 for (i = 0; i < digsize / 4; i++)
350 creq->state[i] = readl_relaxed(engine->regs +
352 if (creq->last_req) {
354 * Hardware's MD5 digest is in little endian format, but
355 * SHA in big endian format
358 __le32 *result = (void *)ahashreq->result;
360 for (i = 0; i < digsize / 4; i++)
361 result[i] = cpu_to_le32(creq->state[i]);
363 __be32 *result = (void *)ahashreq->result;
365 for (i = 0; i < digsize / 4; i++)
366 result[i] = cpu_to_be32(creq->state[i]);
371 atomic_sub(ahashreq->nbytes, &engine->load);
374 static void mv_cesa_ahash_prepare(struct crypto_async_request *req,
375 struct mv_cesa_engine *engine)
377 struct ahash_request *ahashreq = ahash_request_cast(req);
378 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
380 creq->base.engine = engine;
382 if (mv_cesa_req_get_type(&creq->base) == CESA_DMA_REQ)
383 mv_cesa_ahash_dma_prepare(ahashreq);
385 mv_cesa_ahash_std_prepare(ahashreq);
388 static void mv_cesa_ahash_req_cleanup(struct crypto_async_request *req)
390 struct ahash_request *ahashreq = ahash_request_cast(req);
391 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
394 mv_cesa_ahash_last_cleanup(ahashreq);
396 mv_cesa_ahash_cleanup(ahashreq);
399 sg_pcopy_to_buffer(ahashreq->src, creq->src_nents,
402 ahashreq->nbytes - creq->cache_ptr);
405 static const struct mv_cesa_req_ops mv_cesa_ahash_req_ops = {
406 .step = mv_cesa_ahash_step,
407 .process = mv_cesa_ahash_process,
408 .cleanup = mv_cesa_ahash_req_cleanup,
409 .complete = mv_cesa_ahash_complete,
412 static void mv_cesa_ahash_init(struct ahash_request *req,
413 struct mv_cesa_op_ctx *tmpl, bool algo_le)
415 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
417 memset(creq, 0, sizeof(*creq));
418 mv_cesa_update_op_cfg(tmpl,
419 CESA_SA_DESC_CFG_OP_MAC_ONLY |
420 CESA_SA_DESC_CFG_FIRST_FRAG,
421 CESA_SA_DESC_CFG_OP_MSK |
422 CESA_SA_DESC_CFG_FRAG_MSK);
423 mv_cesa_set_mac_op_total_len(tmpl, 0);
424 mv_cesa_set_mac_op_frag_len(tmpl, 0);
425 creq->op_tmpl = *tmpl;
427 creq->algo_le = algo_le;
430 static inline int mv_cesa_ahash_cra_init(struct crypto_tfm *tfm)
432 struct mv_cesa_hash_ctx *ctx = crypto_tfm_ctx(tfm);
434 ctx->base.ops = &mv_cesa_ahash_req_ops;
436 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
437 sizeof(struct mv_cesa_ahash_req));
441 static bool mv_cesa_ahash_cache_req(struct ahash_request *req)
443 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
446 if (creq->cache_ptr + req->nbytes < CESA_MAX_HASH_BLOCK_SIZE &&
453 sg_pcopy_to_buffer(req->src, creq->src_nents,
454 creq->cache + creq->cache_ptr,
457 creq->cache_ptr += req->nbytes;
463 static struct mv_cesa_op_ctx *
464 mv_cesa_dma_add_frag(struct mv_cesa_tdma_chain *chain,
465 struct mv_cesa_op_ctx *tmpl, unsigned int frag_len,
468 struct mv_cesa_op_ctx *op;
471 op = mv_cesa_dma_add_op(chain, tmpl, false, flags);
475 /* Set the operation block fragment length. */
476 mv_cesa_set_mac_op_frag_len(op, frag_len);
478 /* Append dummy desc to launch operation */
479 ret = mv_cesa_dma_add_dummy_launch(chain, flags);
483 if (mv_cesa_mac_op_is_first_frag(tmpl))
484 mv_cesa_update_op_cfg(tmpl,
485 CESA_SA_DESC_CFG_MID_FRAG,
486 CESA_SA_DESC_CFG_FRAG_MSK);
492 mv_cesa_ahash_dma_add_cache(struct mv_cesa_tdma_chain *chain,
493 struct mv_cesa_ahash_req *creq,
496 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
499 if (!creq->cache_ptr)
502 ret = mv_cesa_ahash_dma_alloc_cache(ahashdreq, flags);
506 memcpy(ahashdreq->cache, creq->cache, creq->cache_ptr);
508 return mv_cesa_dma_add_data_transfer(chain,
509 CESA_SA_DATA_SRAM_OFFSET,
510 ahashdreq->cache_dma,
512 CESA_TDMA_DST_IN_SRAM,
516 static struct mv_cesa_op_ctx *
517 mv_cesa_ahash_dma_last_req(struct mv_cesa_tdma_chain *chain,
518 struct mv_cesa_ahash_dma_iter *dma_iter,
519 struct mv_cesa_ahash_req *creq,
520 unsigned int frag_len, gfp_t flags)
522 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
523 unsigned int len, trailerlen, padoff = 0;
524 struct mv_cesa_op_ctx *op;
528 * If the transfer is smaller than our maximum length, and we have
529 * some data outstanding, we can ask the engine to finish the hash.
531 if (creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX && frag_len) {
532 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len,
537 mv_cesa_set_mac_op_total_len(op, creq->len);
538 mv_cesa_update_op_cfg(op, mv_cesa_mac_op_is_first_frag(op) ?
539 CESA_SA_DESC_CFG_NOT_FRAG :
540 CESA_SA_DESC_CFG_LAST_FRAG,
541 CESA_SA_DESC_CFG_FRAG_MSK);
543 ret = mv_cesa_dma_add_result_op(chain,
544 CESA_SA_CFG_SRAM_OFFSET,
545 CESA_SA_DATA_SRAM_OFFSET,
546 CESA_TDMA_SRC_IN_SRAM, flags);
548 return ERR_PTR(-ENOMEM);
553 * The request is longer than the engine can handle, or we have
554 * no data outstanding. Manually generate the padding, adding it
555 * as a "mid" fragment.
557 ret = mv_cesa_ahash_dma_alloc_padding(ahashdreq, flags);
561 trailerlen = mv_cesa_ahash_pad_req(creq, ahashdreq->padding);
563 len = min(CESA_SA_SRAM_PAYLOAD_SIZE - frag_len, trailerlen);
565 ret = mv_cesa_dma_add_data_transfer(chain,
566 CESA_SA_DATA_SRAM_OFFSET +
568 ahashdreq->padding_dma,
569 len, CESA_TDMA_DST_IN_SRAM,
574 op = mv_cesa_dma_add_frag(chain, &creq->op_tmpl, frag_len + len,
579 if (len == trailerlen)
585 ret = mv_cesa_dma_add_data_transfer(chain,
586 CESA_SA_DATA_SRAM_OFFSET,
587 ahashdreq->padding_dma +
590 CESA_TDMA_DST_IN_SRAM,
595 return mv_cesa_dma_add_frag(chain, &creq->op_tmpl, trailerlen - padoff,
599 static int mv_cesa_ahash_dma_req_init(struct ahash_request *req)
601 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
602 gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
603 GFP_KERNEL : GFP_ATOMIC;
604 struct mv_cesa_req *basereq = &creq->base;
605 struct mv_cesa_ahash_dma_iter iter;
606 struct mv_cesa_op_ctx *op = NULL;
607 unsigned int frag_len;
608 bool set_state = false;
612 basereq->chain.first = NULL;
613 basereq->chain.last = NULL;
615 if (!mv_cesa_mac_op_is_first_frag(&creq->op_tmpl))
618 if (creq->src_nents) {
619 ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents,
627 mv_cesa_tdma_desc_iter_init(&basereq->chain);
628 mv_cesa_ahash_req_iter_init(&iter, req);
631 * Add the cache (left-over data from a previous block) first.
632 * This will never overflow the SRAM size.
634 ret = mv_cesa_ahash_dma_add_cache(&basereq->chain, creq, flags);
640 * Add all the new data, inserting an operation block and
641 * launch command between each full SRAM block-worth of
642 * data. We intentionally do not add the final op block.
645 ret = mv_cesa_dma_add_op_transfers(&basereq->chain,
651 frag_len = iter.base.op_len;
653 if (!mv_cesa_ahash_req_iter_next_op(&iter))
656 op = mv_cesa_dma_add_frag(&basereq->chain,
665 /* Account for the data that was in the cache. */
666 frag_len = iter.base.op_len;
670 * At this point, frag_len indicates whether we have any data
671 * outstanding which needs an operation. Queue up the final
672 * operation, which depends whether this is the final request.
675 op = mv_cesa_ahash_dma_last_req(&basereq->chain, &iter, creq,
678 op = mv_cesa_dma_add_frag(&basereq->chain, &creq->op_tmpl,
687 * If results are copied via DMA, this means that this
688 * request can be directly processed by the engine,
689 * without partial updates. So we can chain it at the
690 * DMA level with other requests.
692 type = basereq->chain.last->flags & CESA_TDMA_TYPE_MSK;
694 if (op && type != CESA_TDMA_RESULT) {
695 /* Add dummy desc to wait for crypto operation end */
696 ret = mv_cesa_dma_add_dummy_end(&basereq->chain, flags);
702 creq->cache_ptr = req->nbytes + creq->cache_ptr -
707 basereq->chain.last->flags |= CESA_TDMA_END_OF_REQ;
709 if (type != CESA_TDMA_RESULT)
710 basereq->chain.last->flags |= CESA_TDMA_BREAK_CHAIN;
714 * Put the CESA_TDMA_SET_STATE flag on the first tdma desc to
715 * let the step logic know that the IVDIG registers should be
716 * explicitly set before launching a TDMA chain.
718 basereq->chain.first->flags |= CESA_TDMA_SET_STATE;
724 mv_cesa_dma_cleanup(basereq);
725 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
728 mv_cesa_ahash_last_cleanup(req);
733 static int mv_cesa_ahash_req_init(struct ahash_request *req, bool *cached)
735 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
737 creq->src_nents = sg_nents_for_len(req->src, req->nbytes);
738 if (creq->src_nents < 0) {
739 dev_err(cesa_dev->dev, "Invalid number of src SG");
740 return creq->src_nents;
743 *cached = mv_cesa_ahash_cache_req(req);
748 if (cesa_dev->caps->has_tdma)
749 return mv_cesa_ahash_dma_req_init(req);
754 static int mv_cesa_ahash_queue_req(struct ahash_request *req)
756 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
757 struct mv_cesa_engine *engine;
761 ret = mv_cesa_ahash_req_init(req, &cached);
768 engine = mv_cesa_select_engine(req->nbytes);
769 mv_cesa_ahash_prepare(&req->base, engine);
771 ret = mv_cesa_queue_req(&req->base, &creq->base);
773 if (mv_cesa_req_needs_cleanup(&req->base, ret))
774 mv_cesa_ahash_cleanup(req);
779 static int mv_cesa_ahash_update(struct ahash_request *req)
781 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
783 creq->len += req->nbytes;
785 return mv_cesa_ahash_queue_req(req);
788 static int mv_cesa_ahash_final(struct ahash_request *req)
790 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
791 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
793 mv_cesa_set_mac_op_total_len(tmpl, creq->len);
794 creq->last_req = true;
797 return mv_cesa_ahash_queue_req(req);
800 static int mv_cesa_ahash_finup(struct ahash_request *req)
802 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
803 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
805 creq->len += req->nbytes;
806 mv_cesa_set_mac_op_total_len(tmpl, creq->len);
807 creq->last_req = true;
809 return mv_cesa_ahash_queue_req(req);
812 static int mv_cesa_ahash_export(struct ahash_request *req, void *hash,
813 u64 *len, void *cache)
815 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
816 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
817 unsigned int digsize = crypto_ahash_digestsize(ahash);
818 unsigned int blocksize;
820 blocksize = crypto_ahash_blocksize(ahash);
823 memcpy(hash, creq->state, digsize);
824 memset(cache, 0, blocksize);
825 memcpy(cache, creq->cache, creq->cache_ptr);
830 static int mv_cesa_ahash_import(struct ahash_request *req, const void *hash,
831 u64 len, const void *cache)
833 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
834 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
835 unsigned int digsize = crypto_ahash_digestsize(ahash);
836 unsigned int blocksize;
837 unsigned int cache_ptr;
840 ret = crypto_ahash_init(req);
844 blocksize = crypto_ahash_blocksize(ahash);
845 if (len >= blocksize)
846 mv_cesa_update_op_cfg(&creq->op_tmpl,
847 CESA_SA_DESC_CFG_MID_FRAG,
848 CESA_SA_DESC_CFG_FRAG_MSK);
851 memcpy(creq->state, hash, digsize);
854 cache_ptr = do_div(len, blocksize);
858 memcpy(creq->cache, cache, cache_ptr);
859 creq->cache_ptr = cache_ptr;
864 static int mv_cesa_md5_init(struct ahash_request *req)
866 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
867 struct mv_cesa_op_ctx tmpl = { };
869 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_MD5);
871 mv_cesa_ahash_init(req, &tmpl, true);
873 creq->state[0] = MD5_H0;
874 creq->state[1] = MD5_H1;
875 creq->state[2] = MD5_H2;
876 creq->state[3] = MD5_H3;
881 static int mv_cesa_md5_export(struct ahash_request *req, void *out)
883 struct md5_state *out_state = out;
885 return mv_cesa_ahash_export(req, out_state->hash,
886 &out_state->byte_count, out_state->block);
889 static int mv_cesa_md5_import(struct ahash_request *req, const void *in)
891 const struct md5_state *in_state = in;
893 return mv_cesa_ahash_import(req, in_state->hash, in_state->byte_count,
897 static int mv_cesa_md5_digest(struct ahash_request *req)
901 ret = mv_cesa_md5_init(req);
905 return mv_cesa_ahash_finup(req);
908 struct ahash_alg mv_md5_alg = {
909 .init = mv_cesa_md5_init,
910 .update = mv_cesa_ahash_update,
911 .final = mv_cesa_ahash_final,
912 .finup = mv_cesa_ahash_finup,
913 .digest = mv_cesa_md5_digest,
914 .export = mv_cesa_md5_export,
915 .import = mv_cesa_md5_import,
917 .digestsize = MD5_DIGEST_SIZE,
918 .statesize = sizeof(struct md5_state),
921 .cra_driver_name = "mv-md5",
923 .cra_flags = CRYPTO_ALG_ASYNC |
924 CRYPTO_ALG_ALLOCATES_MEMORY |
925 CRYPTO_ALG_KERN_DRIVER_ONLY,
926 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
927 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
928 .cra_init = mv_cesa_ahash_cra_init,
929 .cra_module = THIS_MODULE,
934 static int mv_cesa_sha1_init(struct ahash_request *req)
936 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
937 struct mv_cesa_op_ctx tmpl = { };
939 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA1);
941 mv_cesa_ahash_init(req, &tmpl, false);
943 creq->state[0] = SHA1_H0;
944 creq->state[1] = SHA1_H1;
945 creq->state[2] = SHA1_H2;
946 creq->state[3] = SHA1_H3;
947 creq->state[4] = SHA1_H4;
952 static int mv_cesa_sha1_export(struct ahash_request *req, void *out)
954 struct sha1_state *out_state = out;
956 return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
960 static int mv_cesa_sha1_import(struct ahash_request *req, const void *in)
962 const struct sha1_state *in_state = in;
964 return mv_cesa_ahash_import(req, in_state->state, in_state->count,
968 static int mv_cesa_sha1_digest(struct ahash_request *req)
972 ret = mv_cesa_sha1_init(req);
976 return mv_cesa_ahash_finup(req);
979 struct ahash_alg mv_sha1_alg = {
980 .init = mv_cesa_sha1_init,
981 .update = mv_cesa_ahash_update,
982 .final = mv_cesa_ahash_final,
983 .finup = mv_cesa_ahash_finup,
984 .digest = mv_cesa_sha1_digest,
985 .export = mv_cesa_sha1_export,
986 .import = mv_cesa_sha1_import,
988 .digestsize = SHA1_DIGEST_SIZE,
989 .statesize = sizeof(struct sha1_state),
992 .cra_driver_name = "mv-sha1",
994 .cra_flags = CRYPTO_ALG_ASYNC |
995 CRYPTO_ALG_ALLOCATES_MEMORY |
996 CRYPTO_ALG_KERN_DRIVER_ONLY,
997 .cra_blocksize = SHA1_BLOCK_SIZE,
998 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
999 .cra_init = mv_cesa_ahash_cra_init,
1000 .cra_module = THIS_MODULE,
1005 static int mv_cesa_sha256_init(struct ahash_request *req)
1007 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
1008 struct mv_cesa_op_ctx tmpl = { };
1010 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA256);
1012 mv_cesa_ahash_init(req, &tmpl, false);
1014 creq->state[0] = SHA256_H0;
1015 creq->state[1] = SHA256_H1;
1016 creq->state[2] = SHA256_H2;
1017 creq->state[3] = SHA256_H3;
1018 creq->state[4] = SHA256_H4;
1019 creq->state[5] = SHA256_H5;
1020 creq->state[6] = SHA256_H6;
1021 creq->state[7] = SHA256_H7;
1026 static int mv_cesa_sha256_digest(struct ahash_request *req)
1030 ret = mv_cesa_sha256_init(req);
1034 return mv_cesa_ahash_finup(req);
1037 static int mv_cesa_sha256_export(struct ahash_request *req, void *out)
1039 struct sha256_state *out_state = out;
1041 return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
1045 static int mv_cesa_sha256_import(struct ahash_request *req, const void *in)
1047 const struct sha256_state *in_state = in;
1049 return mv_cesa_ahash_import(req, in_state->state, in_state->count,
1053 struct ahash_alg mv_sha256_alg = {
1054 .init = mv_cesa_sha256_init,
1055 .update = mv_cesa_ahash_update,
1056 .final = mv_cesa_ahash_final,
1057 .finup = mv_cesa_ahash_finup,
1058 .digest = mv_cesa_sha256_digest,
1059 .export = mv_cesa_sha256_export,
1060 .import = mv_cesa_sha256_import,
1062 .digestsize = SHA256_DIGEST_SIZE,
1063 .statesize = sizeof(struct sha256_state),
1065 .cra_name = "sha256",
1066 .cra_driver_name = "mv-sha256",
1067 .cra_priority = 300,
1068 .cra_flags = CRYPTO_ALG_ASYNC |
1069 CRYPTO_ALG_ALLOCATES_MEMORY |
1070 CRYPTO_ALG_KERN_DRIVER_ONLY,
1071 .cra_blocksize = SHA256_BLOCK_SIZE,
1072 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
1073 .cra_init = mv_cesa_ahash_cra_init,
1074 .cra_module = THIS_MODULE,
1079 struct mv_cesa_ahash_result {
1080 struct completion completion;
1084 static void mv_cesa_hmac_ahash_complete(struct crypto_async_request *req,
1087 struct mv_cesa_ahash_result *result = req->data;
1089 if (error == -EINPROGRESS)
1092 result->error = error;
1093 complete(&result->completion);
1096 static int mv_cesa_ahmac_iv_state_init(struct ahash_request *req, u8 *pad,
1097 void *state, unsigned int blocksize)
1099 struct mv_cesa_ahash_result result;
1100 struct scatterlist sg;
1103 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1104 mv_cesa_hmac_ahash_complete, &result);
1105 sg_init_one(&sg, pad, blocksize);
1106 ahash_request_set_crypt(req, &sg, pad, blocksize);
1107 init_completion(&result.completion);
1109 ret = crypto_ahash_init(req);
1113 ret = crypto_ahash_update(req);
1114 if (ret && ret != -EINPROGRESS)
1117 wait_for_completion_interruptible(&result.completion);
1119 return result.error;
1121 ret = crypto_ahash_export(req, state);
1128 static int mv_cesa_ahmac_pad_init(struct ahash_request *req,
1129 const u8 *key, unsigned int keylen,
1131 unsigned int blocksize)
1133 struct mv_cesa_ahash_result result;
1134 struct scatterlist sg;
1138 if (keylen <= blocksize) {
1139 memcpy(ipad, key, keylen);
1141 u8 *keydup = kmemdup(key, keylen, GFP_KERNEL);
1146 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1147 mv_cesa_hmac_ahash_complete,
1149 sg_init_one(&sg, keydup, keylen);
1150 ahash_request_set_crypt(req, &sg, ipad, keylen);
1151 init_completion(&result.completion);
1153 ret = crypto_ahash_digest(req);
1154 if (ret == -EINPROGRESS) {
1155 wait_for_completion_interruptible(&result.completion);
1159 /* Set the memory region to 0 to avoid any leak. */
1160 kfree_sensitive(keydup);
1165 keylen = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
1168 memset(ipad + keylen, 0, blocksize - keylen);
1169 memcpy(opad, ipad, blocksize);
1171 for (i = 0; i < blocksize; i++) {
1172 ipad[i] ^= HMAC_IPAD_VALUE;
1173 opad[i] ^= HMAC_OPAD_VALUE;
1179 static int mv_cesa_ahmac_setkey(const char *hash_alg_name,
1180 const u8 *key, unsigned int keylen,
1181 void *istate, void *ostate)
1183 struct ahash_request *req;
1184 struct crypto_ahash *tfm;
1185 unsigned int blocksize;
1190 tfm = crypto_alloc_ahash(hash_alg_name, 0, 0);
1192 return PTR_ERR(tfm);
1194 req = ahash_request_alloc(tfm, GFP_KERNEL);
1200 crypto_ahash_clear_flags(tfm, ~0);
1202 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1204 ipad = kcalloc(2, blocksize, GFP_KERNEL);
1210 opad = ipad + blocksize;
1212 ret = mv_cesa_ahmac_pad_init(req, key, keylen, ipad, opad, blocksize);
1216 ret = mv_cesa_ahmac_iv_state_init(req, ipad, istate, blocksize);
1220 ret = mv_cesa_ahmac_iv_state_init(req, opad, ostate, blocksize);
1225 ahash_request_free(req);
1227 crypto_free_ahash(tfm);
1232 static int mv_cesa_ahmac_cra_init(struct crypto_tfm *tfm)
1234 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(tfm);
1236 ctx->base.ops = &mv_cesa_ahash_req_ops;
1238 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1239 sizeof(struct mv_cesa_ahash_req));
1243 static int mv_cesa_ahmac_md5_init(struct ahash_request *req)
1245 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1246 struct mv_cesa_op_ctx tmpl = { };
1248 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_MD5);
1249 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1251 mv_cesa_ahash_init(req, &tmpl, true);
1256 static int mv_cesa_ahmac_md5_setkey(struct crypto_ahash *tfm, const u8 *key,
1257 unsigned int keylen)
1259 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1260 struct md5_state istate, ostate;
1263 ret = mv_cesa_ahmac_setkey("mv-md5", key, keylen, &istate, &ostate);
1267 for (i = 0; i < ARRAY_SIZE(istate.hash); i++)
1268 ctx->iv[i] = be32_to_cpu(istate.hash[i]);
1270 for (i = 0; i < ARRAY_SIZE(ostate.hash); i++)
1271 ctx->iv[i + 8] = be32_to_cpu(ostate.hash[i]);
1276 static int mv_cesa_ahmac_md5_digest(struct ahash_request *req)
1280 ret = mv_cesa_ahmac_md5_init(req);
1284 return mv_cesa_ahash_finup(req);
1287 struct ahash_alg mv_ahmac_md5_alg = {
1288 .init = mv_cesa_ahmac_md5_init,
1289 .update = mv_cesa_ahash_update,
1290 .final = mv_cesa_ahash_final,
1291 .finup = mv_cesa_ahash_finup,
1292 .digest = mv_cesa_ahmac_md5_digest,
1293 .setkey = mv_cesa_ahmac_md5_setkey,
1294 .export = mv_cesa_md5_export,
1295 .import = mv_cesa_md5_import,
1297 .digestsize = MD5_DIGEST_SIZE,
1298 .statesize = sizeof(struct md5_state),
1300 .cra_name = "hmac(md5)",
1301 .cra_driver_name = "mv-hmac-md5",
1302 .cra_priority = 300,
1303 .cra_flags = CRYPTO_ALG_ASYNC |
1304 CRYPTO_ALG_ALLOCATES_MEMORY |
1305 CRYPTO_ALG_KERN_DRIVER_ONLY,
1306 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
1307 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1308 .cra_init = mv_cesa_ahmac_cra_init,
1309 .cra_module = THIS_MODULE,
1314 static int mv_cesa_ahmac_sha1_init(struct ahash_request *req)
1316 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1317 struct mv_cesa_op_ctx tmpl = { };
1319 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA1);
1320 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1322 mv_cesa_ahash_init(req, &tmpl, false);
1327 static int mv_cesa_ahmac_sha1_setkey(struct crypto_ahash *tfm, const u8 *key,
1328 unsigned int keylen)
1330 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1331 struct sha1_state istate, ostate;
1334 ret = mv_cesa_ahmac_setkey("mv-sha1", key, keylen, &istate, &ostate);
1338 for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1339 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1341 for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1342 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1347 static int mv_cesa_ahmac_sha1_digest(struct ahash_request *req)
1351 ret = mv_cesa_ahmac_sha1_init(req);
1355 return mv_cesa_ahash_finup(req);
1358 struct ahash_alg mv_ahmac_sha1_alg = {
1359 .init = mv_cesa_ahmac_sha1_init,
1360 .update = mv_cesa_ahash_update,
1361 .final = mv_cesa_ahash_final,
1362 .finup = mv_cesa_ahash_finup,
1363 .digest = mv_cesa_ahmac_sha1_digest,
1364 .setkey = mv_cesa_ahmac_sha1_setkey,
1365 .export = mv_cesa_sha1_export,
1366 .import = mv_cesa_sha1_import,
1368 .digestsize = SHA1_DIGEST_SIZE,
1369 .statesize = sizeof(struct sha1_state),
1371 .cra_name = "hmac(sha1)",
1372 .cra_driver_name = "mv-hmac-sha1",
1373 .cra_priority = 300,
1374 .cra_flags = CRYPTO_ALG_ASYNC |
1375 CRYPTO_ALG_ALLOCATES_MEMORY |
1376 CRYPTO_ALG_KERN_DRIVER_ONLY,
1377 .cra_blocksize = SHA1_BLOCK_SIZE,
1378 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1379 .cra_init = mv_cesa_ahmac_cra_init,
1380 .cra_module = THIS_MODULE,
1385 static int mv_cesa_ahmac_sha256_setkey(struct crypto_ahash *tfm, const u8 *key,
1386 unsigned int keylen)
1388 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1389 struct sha256_state istate, ostate;
1392 ret = mv_cesa_ahmac_setkey("mv-sha256", key, keylen, &istate, &ostate);
1396 for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1397 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1399 for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1400 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1405 static int mv_cesa_ahmac_sha256_init(struct ahash_request *req)
1407 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1408 struct mv_cesa_op_ctx tmpl = { };
1410 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA256);
1411 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1413 mv_cesa_ahash_init(req, &tmpl, false);
1418 static int mv_cesa_ahmac_sha256_digest(struct ahash_request *req)
1422 ret = mv_cesa_ahmac_sha256_init(req);
1426 return mv_cesa_ahash_finup(req);
1429 struct ahash_alg mv_ahmac_sha256_alg = {
1430 .init = mv_cesa_ahmac_sha256_init,
1431 .update = mv_cesa_ahash_update,
1432 .final = mv_cesa_ahash_final,
1433 .finup = mv_cesa_ahash_finup,
1434 .digest = mv_cesa_ahmac_sha256_digest,
1435 .setkey = mv_cesa_ahmac_sha256_setkey,
1436 .export = mv_cesa_sha256_export,
1437 .import = mv_cesa_sha256_import,
1439 .digestsize = SHA256_DIGEST_SIZE,
1440 .statesize = sizeof(struct sha256_state),
1442 .cra_name = "hmac(sha256)",
1443 .cra_driver_name = "mv-hmac-sha256",
1444 .cra_priority = 300,
1445 .cra_flags = CRYPTO_ALG_ASYNC |
1446 CRYPTO_ALG_ALLOCATES_MEMORY |
1447 CRYPTO_ALG_KERN_DRIVER_ONLY,
1448 .cra_blocksize = SHA256_BLOCK_SIZE,
1449 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1450 .cra_init = mv_cesa_ahmac_cra_init,
1451 .cra_module = THIS_MODULE,