drivers/crypto/ixp4xx_crypto.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Intel IXP4xx NPE-C crypto driver
   4  *
   5  * Copyright (C) 2008 Christian Hohnstaedt <chohnstaedt@innominate.com>
   6  */
   7
   8 #include <linux/platform_device.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/dmapool.h>
  11 #include <linux/crypto.h>
  12 #include <linux/kernel.h>
  13 #include <linux/rtnetlink.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/gfp.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19
  20 #include <crypto/ctr.h>
  21 #include <crypto/internal/des.h>
  22 #include <crypto/aes.h>
  23 #include <crypto/hmac.h>
  24 #include <crypto/sha1.h>
  25 #include <crypto/algapi.h>
  26 #include <crypto/internal/aead.h>
  27 #include <crypto/internal/skcipher.h>
  28 #include <crypto/authenc.h>
  29 #include <crypto/scatterwalk.h>
  30
  31 #include <linux/soc/ixp4xx/npe.h>
  32 #include <linux/soc/ixp4xx/qmgr.h>
  33
  34 #define MAX_KEYLEN 32
  35
  36 /* hash: cfgword + 2 * digestlen; crypt: keylen + cfgword */
  37 #define NPE_CTX_LEN 80
  38 #define AES_BLOCK128 16
  39
  40 #define NPE_OP_HASH_VERIFY   0x01
  41 #define NPE_OP_CCM_ENABLE    0x04
  42 #define NPE_OP_CRYPT_ENABLE  0x08
  43 #define NPE_OP_HASH_ENABLE   0x10
  44 #define NPE_OP_NOT_IN_PLACE  0x20
  45 #define NPE_OP_HMAC_DISABLE  0x40
  46 #define NPE_OP_CRYPT_ENCRYPT 0x80
  47
  48 #define NPE_OP_CCM_GEN_MIC   0xcc
  49 #define NPE_OP_HASH_GEN_ICV  0x50
  50 #define NPE_OP_ENC_GEN_KEY   0xc9
  51
  52 #define MOD_ECB     0x0000
  53 #define MOD_CTR     0x1000
  54 #define MOD_CBC_ENC 0x2000
  55 #define MOD_CBC_DEC 0x3000
  56 #define MOD_CCM_ENC 0x4000
  57 #define MOD_CCM_DEC 0x5000
  58
  59 #define KEYLEN_128  4
  60 #define KEYLEN_192  6
  61 #define KEYLEN_256  8
  62
  63 #define CIPH_DECR   0x0000
  64 #define CIPH_ENCR   0x0400
  65
  66 #define MOD_DES     0x0000
  67 #define MOD_TDEA2   0x0100
  68 #define MOD_3DES   0x0200
  69 #define MOD_AES     0x0800
  70 #define MOD_AES128  (0x0800 | KEYLEN_128)
  71 #define MOD_AES192  (0x0900 | KEYLEN_192)
  72 #define MOD_AES256  (0x0a00 | KEYLEN_256)
  73
  74 #define MAX_IVLEN   16
  75 #define NPE_QLEN    16
  76 /* Space for registering when the first
  77  * NPE_QLEN crypt_ctl are busy */
  78 #define NPE_QLEN_TOTAL 64
  79
  80 #define CTL_FLAG_UNUSED         0x0000
  81 #define CTL_FLAG_USED           0x1000
  82 #define CTL_FLAG_PERFORM_ABLK   0x0001
  83 #define CTL_FLAG_GEN_ICV        0x0002
  84 #define CTL_FLAG_GEN_REVAES     0x0004
  85 #define CTL_FLAG_PERFORM_AEAD   0x0008
  86 #define CTL_FLAG_MASK           0x000f
  87
  88 #define HMAC_PAD_BLOCKLEN SHA1_BLOCK_SIZE
  89
  90 #define MD5_DIGEST_SIZE   16
  91
  92 struct buffer_desc {
  93         u32 phys_next;
  94 #ifdef __ARMEB__
  95         u16 buf_len;
  96         u16 pkt_len;
  97 #else
  98         u16 pkt_len;
  99         u16 buf_len;
 100 #endif
 101         dma_addr_t phys_addr;
 102         u32 __reserved[4];
 103         struct buffer_desc *next;
 104         enum dma_data_direction dir;
 105 };
 106
 107 struct crypt_ctl {
 108 #ifdef __ARMEB__
 109         u8 mode;                /* NPE_OP_*  operation mode */
 110         u8 init_len;
 111         u16 reserved;
 112 #else
 113         u16 reserved;
 114         u8 init_len;
 115         u8 mode;                /* NPE_OP_*  operation mode */
 116 #endif
 117         u8 iv[MAX_IVLEN];       /* IV for CBC mode or CTR IV for CTR mode */
 118         dma_addr_t icv_rev_aes; /* icv or rev aes */
 119         dma_addr_t src_buf;
 120         dma_addr_t dst_buf;
 121 #ifdef __ARMEB__
 122         u16 auth_offs;          /* Authentication start offset */
 123         u16 auth_len;           /* Authentication data length */
 124         u16 crypt_offs;         /* Cryption start offset */
 125         u16 crypt_len;          /* Cryption data length */
 126 #else
 127         u16 auth_len;           /* Authentication data length */
 128         u16 auth_offs;          /* Authentication start offset */
 129         u16 crypt_len;          /* Cryption data length */
 130         u16 crypt_offs;         /* Cryption start offset */
 131 #endif
 132         u32 aadAddr;            /* Additional Auth Data Addr for CCM mode */
 133         u32 crypto_ctx;         /* NPE Crypto Param structure address */
 134
 135         /* Used by Host: 4*4 bytes*/
 136         unsigned int ctl_flags;
 137         union {
 138                 struct skcipher_request *ablk_req;
 139                 struct aead_request *aead_req;
 140                 struct crypto_tfm *tfm;
 141         } data;
 142         struct buffer_desc *regist_buf;
 143         u8 *regist_ptr;
 144 };
 145
 146 struct ablk_ctx {
 147         struct buffer_desc *src;
 148         struct buffer_desc *dst;
 149         u8 iv[MAX_IVLEN];
 150         bool encrypt;
 151         struct skcipher_request fallback_req;   // keep at the end
 152 };
 153
 154 struct aead_ctx {
 155         struct buffer_desc *src;
 156         struct buffer_desc *dst;
 157         struct scatterlist ivlist;
 158         /* used when the hmac is not on one sg entry */
 159         u8 *hmac_virt;
 160         int encrypt;
 161 };
 162
 163 struct ix_hash_algo {
 164         u32 cfgword;
 165         unsigned char *icv;
 166 };
 167
 168 struct ix_sa_dir {
 169         unsigned char *npe_ctx;
 170         dma_addr_t npe_ctx_phys;
 171         int npe_ctx_idx;
 172         u8 npe_mode;
 173 };
 174
 175 struct ixp_ctx {
 176         struct ix_sa_dir encrypt;
 177         struct ix_sa_dir decrypt;
 178         int authkey_len;
 179         u8 authkey[MAX_KEYLEN];
 180         int enckey_len;
 181         u8 enckey[MAX_KEYLEN];
 182         u8 salt[MAX_IVLEN];
 183         u8 nonce[CTR_RFC3686_NONCE_SIZE];
 184         unsigned int salted;
 185         atomic_t configuring;
 186         struct completion completion;
 187         struct crypto_skcipher *fallback_tfm;
 188 };
 189
 190 struct ixp_alg {
 191         struct skcipher_alg crypto;
 192         const struct ix_hash_algo *hash;
 193         u32 cfg_enc;
 194         u32 cfg_dec;
 195
 196         int registered;
 197 };
 198
 199 struct ixp_aead_alg {
 200         struct aead_alg crypto;
 201         const struct ix_hash_algo *hash;
 202         u32 cfg_enc;
 203         u32 cfg_dec;
 204
 205         int registered;
 206 };
 207
 208 static const struct ix_hash_algo hash_alg_md5 = {
 209         .cfgword        = 0xAA010004,
 210         .icv            = "\x01\x23\x45\x67\x89\xAB\xCD\xEF"
 211                           "\xFE\xDC\xBA\x98\x76\x54\x32\x10",
 212 };
 213
 214 static const struct ix_hash_algo hash_alg_sha1 = {
 215         .cfgword        = 0x00000005,
 216         .icv            = "\x67\x45\x23\x01\xEF\xCD\xAB\x89\x98\xBA"
 217                           "\xDC\xFE\x10\x32\x54\x76\xC3\xD2\xE1\xF0",
 218 };
 219
 220 static struct npe *npe_c;
 221
 222 static unsigned int send_qid;
 223 static unsigned int recv_qid;
 224 static struct dma_pool *buffer_pool;
 225 static struct dma_pool *ctx_pool;
 226
 227 static struct crypt_ctl *crypt_virt;
 228 static dma_addr_t crypt_phys;
 229
 230 static int support_aes = 1;
 231
 232 static struct platform_device *pdev;
 233
 234 static inline dma_addr_t crypt_virt2phys(struct crypt_ctl *virt)
 235 {
 236         return crypt_phys + (virt - crypt_virt) * sizeof(struct crypt_ctl);
 237 }
 238
 239 static inline struct crypt_ctl *crypt_phys2virt(dma_addr_t phys)
 240 {
 241         return crypt_virt + (phys - crypt_phys) / sizeof(struct crypt_ctl);
 242 }
 243
 244 static inline u32 cipher_cfg_enc(struct crypto_tfm *tfm)
 245 {
 246         return container_of(tfm->__crt_alg, struct ixp_alg, crypto.base)->cfg_enc;
 247 }
 248
 249 static inline u32 cipher_cfg_dec(struct crypto_tfm *tfm)
 250 {
 251         return container_of(tfm->__crt_alg, struct ixp_alg, crypto.base)->cfg_dec;
 252 }
 253
 254 static inline const struct ix_hash_algo *ix_hash(struct crypto_tfm *tfm)
 255 {
 256         return container_of(tfm->__crt_alg, struct ixp_alg, crypto.base)->hash;
 257 }
 258
 259 static int setup_crypt_desc(void)
 260 {
 261         struct device *dev = &pdev->dev;
 262
 263         BUILD_BUG_ON(sizeof(struct crypt_ctl) != 64);
 264         crypt_virt = dma_alloc_coherent(dev,
 265                                         NPE_QLEN * sizeof(struct crypt_ctl),
 266                                         &crypt_phys, GFP_ATOMIC);
 267         if (!crypt_virt)
 268                 return -ENOMEM;
 269         return 0;
 270 }
 271
 272 static DEFINE_SPINLOCK(desc_lock);
 273 static struct crypt_ctl *get_crypt_desc(void)
 274 {
 275         int i;
 276         static int idx;
 277         unsigned long flags;
 278
 279         spin_lock_irqsave(&desc_lock, flags);
 280
 281         if (unlikely(!crypt_virt))
 282                 setup_crypt_desc();
 283         if (unlikely(!crypt_virt)) {
 284                 spin_unlock_irqrestore(&desc_lock, flags);
 285                 return NULL;
 286         }
 287         i = idx;
 288         if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
 289                 if (++idx >= NPE_QLEN)
 290                         idx = 0;
 291                 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
 292                 spin_unlock_irqrestore(&desc_lock, flags);
 293                 return crypt_virt + i;
 294         } else {
 295                 spin_unlock_irqrestore(&desc_lock, flags);
 296                 return NULL;
 297         }
 298 }
 299
 300 static DEFINE_SPINLOCK(emerg_lock);
 301 static struct crypt_ctl *get_crypt_desc_emerg(void)
 302 {
 303         int i;
 304         static int idx = NPE_QLEN;
 305         struct crypt_ctl *desc;
 306         unsigned long flags;
 307
 308         desc = get_crypt_desc();
 309         if (desc)
 310                 return desc;
 311         if (unlikely(!crypt_virt))
 312                 return NULL;
 313
 314         spin_lock_irqsave(&emerg_lock, flags);
 315         i = idx;
 316         if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
 317                 if (++idx >= NPE_QLEN_TOTAL)
 318                         idx = NPE_QLEN;
 319                 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
 320                 spin_unlock_irqrestore(&emerg_lock, flags);
 321                 return crypt_virt + i;
 322         } else {
 323                 spin_unlock_irqrestore(&emerg_lock, flags);
 324                 return NULL;
 325         }
 326 }
 327
 328 static void free_buf_chain(struct device *dev, struct buffer_desc *buf,
 329                            dma_addr_t phys)
 330 {
 331         while (buf) {
 332                 struct buffer_desc *buf1;
 333                 u32 phys1;
 334
 335                 buf1 = buf->next;
 336                 phys1 = buf->phys_next;
 337                 dma_unmap_single(dev, buf->phys_addr, buf->buf_len, buf->dir);
 338                 dma_pool_free(buffer_pool, buf, phys);
 339                 buf = buf1;
 340                 phys = phys1;
 341         }
 342 }
 343
 344 static struct tasklet_struct crypto_done_tasklet;
 345
 346 static void finish_scattered_hmac(struct crypt_ctl *crypt)
 347 {
 348         struct aead_request *req = crypt->data.aead_req;
 349         struct aead_ctx *req_ctx = aead_request_ctx(req);
 350         struct crypto_aead *tfm = crypto_aead_reqtfm(req);
 351         int authsize = crypto_aead_authsize(tfm);
 352         int decryptlen = req->assoclen + req->cryptlen - authsize;
 353
 354         if (req_ctx->encrypt) {
 355                 scatterwalk_map_and_copy(req_ctx->hmac_virt, req->dst,
 356                                          decryptlen, authsize, 1);
 357         }
 358         dma_pool_free(buffer_pool, req_ctx->hmac_virt, crypt->icv_rev_aes);
 359 }
 360
 361 static void one_packet(dma_addr_t phys)
 362 {
 363         struct device *dev = &pdev->dev;
 364         struct crypt_ctl *crypt;
 365         struct ixp_ctx *ctx;
 366         int failed;
 367
 368         failed = phys & 0x1 ? -EBADMSG : 0;
 369         phys &= ~0x3;
 370         crypt = crypt_phys2virt(phys);
 371
 372         switch (crypt->ctl_flags & CTL_FLAG_MASK) {
 373         case CTL_FLAG_PERFORM_AEAD: {
 374                 struct aead_request *req = crypt->data.aead_req;
 375                 struct aead_ctx *req_ctx = aead_request_ctx(req);
 376
 377                 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
 378                 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
 379                 if (req_ctx->hmac_virt)
 380                         finish_scattered_hmac(crypt);
 381
 382                 req->base.complete(&req->base, failed);
 383                 break;
 384         }
 385         case CTL_FLAG_PERFORM_ABLK: {
 386                 struct skcipher_request *req = crypt->data.ablk_req;
 387                 struct ablk_ctx *req_ctx = skcipher_request_ctx(req);
 388                 struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
 389                 unsigned int ivsize = crypto_skcipher_ivsize(tfm);
 390                 unsigned int offset;
 391
 392                 if (ivsize > 0) {
 393                         offset = req->cryptlen - ivsize;
 394                         if (req_ctx->encrypt) {
 395                                 scatterwalk_map_and_copy(req->iv, req->dst,
 396                                                          offset, ivsize, 0);
 397                         } else {
 398                                 memcpy(req->iv, req_ctx->iv, ivsize);
 399                                 memzero_explicit(req_ctx->iv, ivsize);
 400                         }
 401                 }
 402
 403                 if (req_ctx->dst)
 404                         free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
 405
 406                 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
 407                 req->base.complete(&req->base, failed);
 408                 break;
 409         }
 410         case CTL_FLAG_GEN_ICV:
 411                 ctx = crypto_tfm_ctx(crypt->data.tfm);
 412                 dma_pool_free(ctx_pool, crypt->regist_ptr,
 413                               crypt->regist_buf->phys_addr);
 414                 dma_pool_free(buffer_pool, crypt->regist_buf, crypt->src_buf);
 415                 if (atomic_dec_and_test(&ctx->configuring))
 416                         complete(&ctx->completion);
 417                 break;
 418         case CTL_FLAG_GEN_REVAES:
 419                 ctx = crypto_tfm_ctx(crypt->data.tfm);
 420                 *(u32 *)ctx->decrypt.npe_ctx &= cpu_to_be32(~CIPH_ENCR);
 421                 if (atomic_dec_and_test(&ctx->configuring))
 422                         complete(&ctx->completion);
 423                 break;
 424         default:
 425                 BUG();
 426         }
 427         crypt->ctl_flags = CTL_FLAG_UNUSED;
 428 }
 429
 430 static void irqhandler(void *_unused)
 431 {
 432         tasklet_schedule(&crypto_done_tasklet);
 433 }
 434
 435 static void crypto_done_action(unsigned long arg)
 436 {
 437         int i;
 438
 439         for (i = 0; i < 4; i++) {
 440                 dma_addr_t phys = qmgr_get_entry(recv_qid);
 441                 if (!phys)
 442                         return;
 443                 one_packet(phys);
 444         }
 445         tasklet_schedule(&crypto_done_tasklet);
 446 }
 447
 448 static int init_ixp_crypto(struct device *dev)
 449 {
 450         struct device_node *np = dev->of_node;
 451         u32 msg[2] = { 0, 0 };
 452         int ret = -ENODEV;
 453         u32 npe_id;
 454
 455         dev_info(dev, "probing...\n");
 456
 457         /* Locate the NPE and queue manager to use from device tree */
 458         if (IS_ENABLED(CONFIG_OF) && np) {
 459                 struct of_phandle_args queue_spec;
 460                 struct of_phandle_args npe_spec;
 461
 462                 ret = of_parse_phandle_with_fixed_args(np, "intel,npe-handle",
 463                                                        1, 0, &npe_spec);
 464                 if (ret) {
 465                         dev_err(dev, "no NPE engine specified\n");
 466                         return -ENODEV;
 467                 }
 468                 npe_id = npe_spec.args[0];
 469
 470                 ret = of_parse_phandle_with_fixed_args(np, "queue-rx", 1, 0,
 471                                                        &queue_spec);
 472                 if (ret) {
 473                         dev_err(dev, "no rx queue phandle\n");
 474                         return -ENODEV;
 475                 }
 476                 recv_qid = queue_spec.args[0];
 477
 478                 ret = of_parse_phandle_with_fixed_args(np, "queue-txready", 1, 0,
 479                                                        &queue_spec);
 480                 if (ret) {
 481                         dev_err(dev, "no txready queue phandle\n");
 482                         return -ENODEV;
 483                 }
 484                 send_qid = queue_spec.args[0];
 485         } else {
 486                 /*
 487                  * Hardcoded engine when using platform data, this goes away
 488                  * when we switch to using DT only.
 489                  */
 490                 npe_id = 2;
 491                 send_qid = 29;
 492                 recv_qid = 30;
 493         }
 494
 495         npe_c = npe_request(npe_id);
 496         if (!npe_c)
 497                 return ret;
 498
 499         if (!npe_running(npe_c)) {
 500                 ret = npe_load_firmware(npe_c, npe_name(npe_c), dev);
 501                 if (ret)
 502                         goto npe_release;
 503                 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
 504                         goto npe_error;
 505         } else {
 506                 if (npe_send_message(npe_c, msg, "STATUS_MSG"))
 507                         goto npe_error;
 508
 509                 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
 510                         goto npe_error;
 511         }
 512
 513         switch ((msg[1] >> 16) & 0xff) {
 514         case 3:
 515                 dev_warn(dev, "Firmware of %s lacks AES support\n", npe_name(npe_c));
 516                 support_aes = 0;
 517                 break;
 518         case 4:
 519         case 5:
 520                 support_aes = 1;
 521                 break;
 522         default:
 523                 dev_err(dev, "Firmware of %s lacks crypto support\n", npe_name(npe_c));
 524                 ret = -ENODEV;
 525                 goto npe_release;
 526         }
 527         /* buffer_pool will also be used to sometimes store the hmac,
 528          * so assure it is large enough
 529          */
 530         BUILD_BUG_ON(SHA1_DIGEST_SIZE > sizeof(struct buffer_desc));
 531         buffer_pool = dma_pool_create("buffer", dev, sizeof(struct buffer_desc),
 532                                       32, 0);
 533         ret = -ENOMEM;
 534         if (!buffer_pool)
 535                 goto err;
 536
 537         ctx_pool = dma_pool_create("context", dev, NPE_CTX_LEN, 16, 0);
 538         if (!ctx_pool)
 539                 goto err;
 540
 541         ret = qmgr_request_queue(send_qid, NPE_QLEN_TOTAL, 0, 0,
 542                                  "ixp_crypto:out", NULL);
 543         if (ret)
 544                 goto err;
 545         ret = qmgr_request_queue(recv_qid, NPE_QLEN, 0, 0,
 546                                  "ixp_crypto:in", NULL);
 547         if (ret) {
 548                 qmgr_release_queue(send_qid);
 549                 goto err;
 550         }
 551         qmgr_set_irq(recv_qid, QUEUE_IRQ_SRC_NOT_EMPTY, irqhandler, NULL);
 552         tasklet_init(&crypto_done_tasklet, crypto_done_action, 0);
 553
 554         qmgr_enable_irq(recv_qid);
 555         return 0;
 556
 557 npe_error:
 558         dev_err(dev, "%s not responding\n", npe_name(npe_c));
 559         ret = -EIO;
 560 err:
 561         dma_pool_destroy(ctx_pool);
 562         dma_pool_destroy(buffer_pool);
 563 npe_release:
 564         npe_release(npe_c);
 565         return ret;
 566 }
 567
 568 static void release_ixp_crypto(struct device *dev)
 569 {
 570         qmgr_disable_irq(recv_qid);
 571         tasklet_kill(&crypto_done_tasklet);
 572
 573         qmgr_release_queue(send_qid);
 574         qmgr_release_queue(recv_qid);
 575
 576         dma_pool_destroy(ctx_pool);
 577         dma_pool_destroy(buffer_pool);
 578
 579         npe_release(npe_c);
 580
 581         if (crypt_virt)
 582                 dma_free_coherent(dev, NPE_QLEN * sizeof(struct crypt_ctl),
 583                                   crypt_virt, crypt_phys);
 584 }
 585
 586 static void reset_sa_dir(struct ix_sa_dir *dir)
 587 {
 588         memset(dir->npe_ctx, 0, NPE_CTX_LEN);
 589         dir->npe_ctx_idx = 0;
 590         dir->npe_mode = 0;
 591 }
 592
 593 static int init_sa_dir(struct ix_sa_dir *dir)
 594 {
 595         dir->npe_ctx = dma_pool_alloc(ctx_pool, GFP_KERNEL, &dir->npe_ctx_phys);
 596         if (!dir->npe_ctx)
 597                 return -ENOMEM;
 598
 599         reset_sa_dir(dir);
 600         return 0;
 601 }
 602
 603 static void free_sa_dir(struct ix_sa_dir *dir)
 604 {
 605         memset(dir->npe_ctx, 0, NPE_CTX_LEN);
 606         dma_pool_free(ctx_pool, dir->npe_ctx, dir->npe_ctx_phys);
 607 }
 608
 609 static int init_tfm(struct crypto_tfm *tfm)
 610 {
 611         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 612         int ret;
 613
 614         atomic_set(&ctx->configuring, 0);
 615         ret = init_sa_dir(&ctx->encrypt);
 616         if (ret)
 617                 return ret;
 618         ret = init_sa_dir(&ctx->decrypt);
 619         if (ret)
 620                 free_sa_dir(&ctx->encrypt);
 621
 622         return ret;
 623 }
 624
 625 static int init_tfm_ablk(struct crypto_skcipher *tfm)
 626 {
 627         struct crypto_tfm *ctfm = crypto_skcipher_tfm(tfm);
 628         struct ixp_ctx *ctx = crypto_tfm_ctx(ctfm);
 629         const char *name = crypto_tfm_alg_name(ctfm);
 630
 631         ctx->fallback_tfm = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
 632         if (IS_ERR(ctx->fallback_tfm)) {
 633                 pr_err("ERROR: Cannot allocate fallback for %s %ld\n",
 634                         name, PTR_ERR(ctx->fallback_tfm));
 635                 return PTR_ERR(ctx->fallback_tfm);
 636         }
 637
 638         pr_info("Fallback for %s is %s\n",
 639                  crypto_tfm_alg_driver_name(&tfm->base),
 640                  crypto_tfm_alg_driver_name(crypto_skcipher_tfm(ctx->fallback_tfm))
 641                  );
 642
 643         crypto_skcipher_set_reqsize(tfm, sizeof(struct ablk_ctx) + crypto_skcipher_reqsize(ctx->fallback_tfm));
 644         return init_tfm(crypto_skcipher_tfm(tfm));
 645 }
 646
 647 static int init_tfm_aead(struct crypto_aead *tfm)
 648 {
 649         crypto_aead_set_reqsize(tfm, sizeof(struct aead_ctx));
 650         return init_tfm(crypto_aead_tfm(tfm));
 651 }
 652
 653 static void exit_tfm(struct crypto_tfm *tfm)
 654 {
 655         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 656
 657         free_sa_dir(&ctx->encrypt);
 658         free_sa_dir(&ctx->decrypt);
 659 }
 660
 661 static void exit_tfm_ablk(struct crypto_skcipher *tfm)
 662 {
 663         struct crypto_tfm *ctfm = crypto_skcipher_tfm(tfm);
 664         struct ixp_ctx *ctx = crypto_tfm_ctx(ctfm);
 665
 666         crypto_free_skcipher(ctx->fallback_tfm);
 667         exit_tfm(crypto_skcipher_tfm(tfm));
 668 }
 669
 670 static void exit_tfm_aead(struct crypto_aead *tfm)
 671 {
 672         exit_tfm(crypto_aead_tfm(tfm));
 673 }
 674
 675 static int register_chain_var(struct crypto_tfm *tfm, u8 xpad, u32 target,
 676                               int init_len, u32 ctx_addr, const u8 *key,
 677                               int key_len)
 678 {
 679         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 680         struct crypt_ctl *crypt;
 681         struct buffer_desc *buf;
 682         int i;
 683         u8 *pad;
 684         dma_addr_t pad_phys, buf_phys;
 685
 686         BUILD_BUG_ON(NPE_CTX_LEN < HMAC_PAD_BLOCKLEN);
 687         pad = dma_pool_alloc(ctx_pool, GFP_KERNEL, &pad_phys);
 688         if (!pad)
 689                 return -ENOMEM;
 690         buf = dma_pool_alloc(buffer_pool, GFP_KERNEL, &buf_phys);
 691         if (!buf) {
 692                 dma_pool_free(ctx_pool, pad, pad_phys);
 693                 return -ENOMEM;
 694         }
 695         crypt = get_crypt_desc_emerg();
 696         if (!crypt) {
 697                 dma_pool_free(ctx_pool, pad, pad_phys);
 698                 dma_pool_free(buffer_pool, buf, buf_phys);
 699                 return -EAGAIN;
 700         }
 701
 702         memcpy(pad, key, key_len);
 703         memset(pad + key_len, 0, HMAC_PAD_BLOCKLEN - key_len);
 704         for (i = 0; i < HMAC_PAD_BLOCKLEN; i++)
 705                 pad[i] ^= xpad;
 706
 707         crypt->data.tfm = tfm;
 708         crypt->regist_ptr = pad;
 709         crypt->regist_buf = buf;
 710
 711         crypt->auth_offs = 0;
 712         crypt->auth_len = HMAC_PAD_BLOCKLEN;
 713         crypt->crypto_ctx = ctx_addr;
 714         crypt->src_buf = buf_phys;
 715         crypt->icv_rev_aes = target;
 716         crypt->mode = NPE_OP_HASH_GEN_ICV;
 717         crypt->init_len = init_len;
 718         crypt->ctl_flags |= CTL_FLAG_GEN_ICV;
 719
 720         buf->next = 0;
 721         buf->buf_len = HMAC_PAD_BLOCKLEN;
 722         buf->pkt_len = 0;
 723         buf->phys_addr = pad_phys;
 724
 725         atomic_inc(&ctx->configuring);
 726         qmgr_put_entry(send_qid, crypt_virt2phys(crypt));
 727         BUG_ON(qmgr_stat_overflow(send_qid));
 728         return 0;
 729 }
 730
 731 static int setup_auth(struct crypto_tfm *tfm, int encrypt, unsigned int authsize,
 732                       const u8 *key, int key_len, unsigned int digest_len)
 733 {
 734         u32 itarget, otarget, npe_ctx_addr;
 735         unsigned char *cinfo;
 736         int init_len, ret = 0;
 737         u32 cfgword;
 738         struct ix_sa_dir *dir;
 739         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 740         const struct ix_hash_algo *algo;
 741
 742         dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
 743         cinfo = dir->npe_ctx + dir->npe_ctx_idx;
 744         algo = ix_hash(tfm);
 745
 746         /* write cfg word to cryptinfo */
 747         cfgword = algo->cfgword | (authsize << 6); /* (authsize/4) << 8 */
 748 #ifndef __ARMEB__
 749         cfgword ^= 0xAA000000; /* change the "byte swap" flags */
 750 #endif
 751         *(u32 *)cinfo = cpu_to_be32(cfgword);
 752         cinfo += sizeof(cfgword);
 753
 754         /* write ICV to cryptinfo */
 755         memcpy(cinfo, algo->icv, digest_len);
 756         cinfo += digest_len;
 757
 758         itarget = dir->npe_ctx_phys + dir->npe_ctx_idx
 759                                 + sizeof(algo->cfgword);
 760         otarget = itarget + digest_len;
 761         init_len = cinfo - (dir->npe_ctx + dir->npe_ctx_idx);
 762         npe_ctx_addr = dir->npe_ctx_phys + dir->npe_ctx_idx;
 763
 764         dir->npe_ctx_idx += init_len;
 765         dir->npe_mode |= NPE_OP_HASH_ENABLE;
 766
 767         if (!encrypt)
 768                 dir->npe_mode |= NPE_OP_HASH_VERIFY;
 769
 770         ret = register_chain_var(tfm, HMAC_OPAD_VALUE, otarget,
 771                                  init_len, npe_ctx_addr, key, key_len);
 772         if (ret)
 773                 return ret;
 774         return register_chain_var(tfm, HMAC_IPAD_VALUE, itarget,
 775                                   init_len, npe_ctx_addr, key, key_len);
 776 }
 777
 778 static int gen_rev_aes_key(struct crypto_tfm *tfm)
 779 {
 780         struct crypt_ctl *crypt;
 781         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 782         struct ix_sa_dir *dir = &ctx->decrypt;
 783
 784         crypt = get_crypt_desc_emerg();
 785         if (!crypt)
 786                 return -EAGAIN;
 787
 788         *(u32 *)dir->npe_ctx |= cpu_to_be32(CIPH_ENCR);
 789
 790         crypt->data.tfm = tfm;
 791         crypt->crypt_offs = 0;
 792         crypt->crypt_len = AES_BLOCK128;
 793         crypt->src_buf = 0;
 794         crypt->crypto_ctx = dir->npe_ctx_phys;
 795         crypt->icv_rev_aes = dir->npe_ctx_phys + sizeof(u32);
 796         crypt->mode = NPE_OP_ENC_GEN_KEY;
 797         crypt->init_len = dir->npe_ctx_idx;
 798         crypt->ctl_flags |= CTL_FLAG_GEN_REVAES;
 799
 800         atomic_inc(&ctx->configuring);
 801         qmgr_put_entry(send_qid, crypt_virt2phys(crypt));
 802         BUG_ON(qmgr_stat_overflow(send_qid));
 803         return 0;
 804 }
 805
 806 static int setup_cipher(struct crypto_tfm *tfm, int encrypt, const u8 *key,
 807                         int key_len)
 808 {
 809         u8 *cinfo;
 810         u32 cipher_cfg;
 811         u32 keylen_cfg = 0;
 812         struct ix_sa_dir *dir;
 813         struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
 814         int err;
 815
 816         dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
 817         cinfo = dir->npe_ctx;
 818
 819         if (encrypt) {
 820                 cipher_cfg = cipher_cfg_enc(tfm);
 821                 dir->npe_mode |= NPE_OP_CRYPT_ENCRYPT;
 822         } else {
 823                 cipher_cfg = cipher_cfg_dec(tfm);
 824         }
 825         if (cipher_cfg & MOD_AES) {
 826                 switch (key_len) {
 827                 case 16:
 828                         keylen_cfg = MOD_AES128;
 829                         break;
 830                 case 24:
 831                         keylen_cfg = MOD_AES192;
 832                         break;
 833                 case 32:
 834                         keylen_cfg = MOD_AES256;
 835                         break;
 836                 default:
 837                         return -EINVAL;
 838                 }
 839                 cipher_cfg |= keylen_cfg;
 840         } else {
 841                 err = crypto_des_verify_key(tfm, key);
 842                 if (err)
 843                         return err;
 844         }
 845         /* write cfg word to cryptinfo */
 846         *(u32 *)cinfo = cpu_to_be32(cipher_cfg);
 847         cinfo += sizeof(cipher_cfg);
 848
 849         /* write cipher key to cryptinfo */
 850         memcpy(cinfo, key, key_len);
 851         /* NPE wants keylen set to DES3_EDE_KEY_SIZE even for single DES */
 852         if (key_len < DES3_EDE_KEY_SIZE && !(cipher_cfg & MOD_AES)) {
 853                 memset(cinfo + key_len, 0, DES3_EDE_KEY_SIZE - key_len);
 854                 key_len = DES3_EDE_KEY_SIZE;
 855         }
 856         dir->npe_ctx_idx = sizeof(cipher_cfg) + key_len;
 857         dir->npe_mode |= NPE_OP_CRYPT_ENABLE;
 858         if ((cipher_cfg & MOD_AES) && !encrypt)
 859                 return gen_rev_aes_key(tfm);
 860
 861         return 0;
 862 }
 863
 864 static struct buffer_desc *chainup_buffers(struct device *dev,
 865                 struct scatterlist *sg, unsigned int nbytes,
 866                 struct buffer_desc *buf, gfp_t flags,
 867                 enum dma_data_direction dir)
 868 {
 869         for (; nbytes > 0; sg = sg_next(sg)) {
 870                 unsigned int len = min(nbytes, sg->length);
 871                 struct buffer_desc *next_buf;
 872                 dma_addr_t next_buf_phys;
 873                 void *ptr;
 874
 875                 nbytes -= len;
 876                 ptr = sg_virt(sg);
 877                 next_buf = dma_pool_alloc(buffer_pool, flags, &next_buf_phys);
 878                 if (!next_buf) {
 879                         buf = NULL;
 880                         break;
 881                 }
 882                 sg_dma_address(sg) = dma_map_single(dev, ptr, len, dir);
 883                 buf->next = next_buf;
 884                 buf->phys_next = next_buf_phys;
 885                 buf = next_buf;
 886
 887                 buf->phys_addr = sg_dma_address(sg);
 888                 buf->buf_len = len;
 889                 buf->dir = dir;
 890         }
 891         buf->next = NULL;
 892         buf->phys_next = 0;
 893         return buf;
 894 }
 895
 896 static int ablk_setkey(struct crypto_skcipher *tfm, const u8 *key,
 897                        unsigned int key_len)
 898 {
 899         struct ixp_ctx *ctx = crypto_skcipher_ctx(tfm);
 900         int ret;
 901
 902         init_completion(&ctx->completion);
 903         atomic_inc(&ctx->configuring);
 904
 905         reset_sa_dir(&ctx->encrypt);
 906         reset_sa_dir(&ctx->decrypt);
 907
 908         ctx->encrypt.npe_mode = NPE_OP_HMAC_DISABLE;
 909         ctx->decrypt.npe_mode = NPE_OP_HMAC_DISABLE;
 910
 911         ret = setup_cipher(&tfm->base, 0, key, key_len);
 912         if (ret)
 913                 goto out;
 914         ret = setup_cipher(&tfm->base, 1, key, key_len);
 915 out:
 916         if (!atomic_dec_and_test(&ctx->configuring))
 917                 wait_for_completion(&ctx->completion);
 918         if (ret)
 919                 return ret;
 920         crypto_skcipher_clear_flags(ctx->fallback_tfm, CRYPTO_TFM_REQ_MASK);
 921         crypto_skcipher_set_flags(ctx->fallback_tfm, tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK);
 922
 923         return crypto_skcipher_setkey(ctx->fallback_tfm, key, key_len);
 924 }
 925
 926 static int ablk_des3_setkey(struct crypto_skcipher *tfm, const u8 *key,
 927                             unsigned int key_len)
 928 {
 929         return verify_skcipher_des3_key(tfm, key) ?:
 930                ablk_setkey(tfm, key, key_len);
 931 }
 932
 933 static int ablk_rfc3686_setkey(struct crypto_skcipher *tfm, const u8 *key,
 934                                unsigned int key_len)
 935 {
 936         struct ixp_ctx *ctx = crypto_skcipher_ctx(tfm);
 937
 938         /* the nonce is stored in bytes at end of key */
 939         if (key_len < CTR_RFC3686_NONCE_SIZE)
 940                 return -EINVAL;
 941
 942         memcpy(ctx->nonce, key + (key_len - CTR_RFC3686_NONCE_SIZE),
 943                CTR_RFC3686_NONCE_SIZE);
 944
 945         key_len -= CTR_RFC3686_NONCE_SIZE;
 946         return ablk_setkey(tfm, key, key_len);
 947 }
 948
 949 static int ixp4xx_cipher_fallback(struct skcipher_request *areq, int encrypt)
 950 {
 951         struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
 952         struct ixp_ctx *op = crypto_skcipher_ctx(tfm);
 953         struct ablk_ctx *rctx = skcipher_request_ctx(areq);
 954         int err;
 955
 956         skcipher_request_set_tfm(&rctx->fallback_req, op->fallback_tfm);
 957         skcipher_request_set_callback(&rctx->fallback_req, areq->base.flags,
 958                                       areq->base.complete, areq->base.data);
 959         skcipher_request_set_crypt(&rctx->fallback_req, areq->src, areq->dst,
 960                                    areq->cryptlen, areq->iv);
 961         if (encrypt)
 962                 err = crypto_skcipher_encrypt(&rctx->fallback_req);
 963         else
 964                 err = crypto_skcipher_decrypt(&rctx->fallback_req);
 965         return err;
 966 }
 967
 968 static int ablk_perform(struct skcipher_request *req, int encrypt)
 969 {
 970         struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
 971         struct ixp_ctx *ctx = crypto_skcipher_ctx(tfm);
 972         unsigned int ivsize = crypto_skcipher_ivsize(tfm);
 973         struct ix_sa_dir *dir;
 974         struct crypt_ctl *crypt;
 975         unsigned int nbytes = req->cryptlen;
 976         enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
 977         struct ablk_ctx *req_ctx = skcipher_request_ctx(req);
 978         struct buffer_desc src_hook;
 979         struct device *dev = &pdev->dev;
 980         unsigned int offset;
 981         gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
 982                                 GFP_KERNEL : GFP_ATOMIC;
 983
 984         if (sg_nents(req->src) > 1 || sg_nents(req->dst) > 1)
 985                 return ixp4xx_cipher_fallback(req, encrypt);
 986
 987         if (qmgr_stat_full(send_qid))
 988                 return -EAGAIN;
 989         if (atomic_read(&ctx->configuring))
 990                 return -EAGAIN;
 991
 992         dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
 993         req_ctx->encrypt = encrypt;
 994
 995         crypt = get_crypt_desc();
 996         if (!crypt)
 997                 return -ENOMEM;
 998
 999         crypt->data.ablk_req = req;
1000         crypt->crypto_ctx = dir->npe_ctx_phys;
1001         crypt->mode = dir->npe_mode;
1002         crypt->init_len = dir->npe_ctx_idx;
1003
1004         crypt->crypt_offs = 0;
1005         crypt->crypt_len = nbytes;
1006
1007         BUG_ON(ivsize && !req->iv);
1008         memcpy(crypt->iv, req->iv, ivsize);
1009         if (ivsize > 0 && !encrypt) {
1010                 offset = req->cryptlen - ivsize;
1011                 scatterwalk_map_and_copy(req_ctx->iv, req->src, offset, ivsize, 0);
1012         }
1013         if (req->src != req->dst) {
1014                 struct buffer_desc dst_hook;
1015
1016                 crypt->mode |= NPE_OP_NOT_IN_PLACE;
1017                 /* This was never tested by Intel
1018                  * for more than one dst buffer, I think. */
1019                 req_ctx->dst = NULL;
1020                 if (!chainup_buffers(dev, req->dst, nbytes, &dst_hook,
1021                                      flags, DMA_FROM_DEVICE))
1022                         goto free_buf_dest;
1023                 src_direction = DMA_TO_DEVICE;
1024                 req_ctx->dst = dst_hook.next;
1025                 crypt->dst_buf = dst_hook.phys_next;
1026         } else {
1027                 req_ctx->dst = NULL;
1028         }
1029         req_ctx->src = NULL;
1030         if (!chainup_buffers(dev, req->src, nbytes, &src_hook, flags,
1031                              src_direction))
1032                 goto free_buf_src;
1033
1034         req_ctx->src = src_hook.next;
1035         crypt->src_buf = src_hook.phys_next;
1036         crypt->ctl_flags |= CTL_FLAG_PERFORM_ABLK;
1037         qmgr_put_entry(send_qid, crypt_virt2phys(crypt));
1038         BUG_ON(qmgr_stat_overflow(send_qid));
1039         return -EINPROGRESS;
1040
1041 free_buf_src:
1042         free_buf_chain(dev, req_ctx->src, crypt->src_buf);
1043 free_buf_dest:
1044         if (req->src != req->dst)
1045                 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
1046
1047         crypt->ctl_flags = CTL_FLAG_UNUSED;
1048         return -ENOMEM;
1049 }
1050
1051 static int ablk_encrypt(struct skcipher_request *req)
1052 {
1053         return ablk_perform(req, 1);
1054 }
1055
1056 static int ablk_decrypt(struct skcipher_request *req)
1057 {
1058         return ablk_perform(req, 0);
1059 }
1060
1061 static int ablk_rfc3686_crypt(struct skcipher_request *req)
1062 {
1063         struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
1064         struct ixp_ctx *ctx = crypto_skcipher_ctx(tfm);
1065         u8 iv[CTR_RFC3686_BLOCK_SIZE];
1066         u8 *info = req->iv;
1067         int ret;
1068
1069         /* set up counter block */
1070         memcpy(iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
1071         memcpy(iv + CTR_RFC3686_NONCE_SIZE, info, CTR_RFC3686_IV_SIZE);
1072
1073         /* initialize counter portion of counter block */
1074         *(__be32 *)(iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
1075                 cpu_to_be32(1);
1076
1077         req->iv = iv;
1078         ret = ablk_perform(req, 1);
1079         req->iv = info;
1080         return ret;
1081 }
1082
1083 static int aead_perform(struct aead_request *req, int encrypt,
1084                         int cryptoffset, int eff_cryptlen, u8 *iv)
1085 {
1086         struct crypto_aead *tfm = crypto_aead_reqtfm(req);
1087         struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1088         unsigned int ivsize = crypto_aead_ivsize(tfm);
1089         unsigned int authsize = crypto_aead_authsize(tfm);
1090         struct ix_sa_dir *dir;
1091         struct crypt_ctl *crypt;
1092         unsigned int cryptlen;
1093         struct buffer_desc *buf, src_hook;
1094         struct aead_ctx *req_ctx = aead_request_ctx(req);
1095         struct device *dev = &pdev->dev;
1096         gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
1097                                 GFP_KERNEL : GFP_ATOMIC;
1098         enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
1099         unsigned int lastlen;
1100
1101         if (qmgr_stat_full(send_qid))
1102                 return -EAGAIN;
1103         if (atomic_read(&ctx->configuring))
1104                 return -EAGAIN;
1105
1106         if (encrypt) {
1107                 dir = &ctx->encrypt;
1108                 cryptlen = req->cryptlen;
1109         } else {
1110                 dir = &ctx->decrypt;
1111                 /* req->cryptlen includes the authsize when decrypting */
1112                 cryptlen = req->cryptlen - authsize;
1113                 eff_cryptlen -= authsize;
1114         }
1115         crypt = get_crypt_desc();
1116         if (!crypt)
1117                 return -ENOMEM;
1118
1119         crypt->data.aead_req = req;
1120         crypt->crypto_ctx = dir->npe_ctx_phys;
1121         crypt->mode = dir->npe_mode;
1122         crypt->init_len = dir->npe_ctx_idx;
1123
1124         crypt->crypt_offs = cryptoffset;
1125         crypt->crypt_len = eff_cryptlen;
1126
1127         crypt->auth_offs = 0;
1128         crypt->auth_len = req->assoclen + cryptlen;
1129         BUG_ON(ivsize && !req->iv);
1130         memcpy(crypt->iv, req->iv, ivsize);
1131
1132         buf = chainup_buffers(dev, req->src, crypt->auth_len,
1133                               &src_hook, flags, src_direction);
1134         req_ctx->src = src_hook.next;
1135         crypt->src_buf = src_hook.phys_next;
1136         if (!buf)
1137                 goto free_buf_src;
1138
1139         lastlen = buf->buf_len;
1140         if (lastlen >= authsize)
1141                 crypt->icv_rev_aes = buf->phys_addr +
1142                                      buf->buf_len - authsize;
1143
1144         req_ctx->dst = NULL;
1145
1146         if (req->src != req->dst) {
1147                 struct buffer_desc dst_hook;
1148
1149                 crypt->mode |= NPE_OP_NOT_IN_PLACE;
1150                 src_direction = DMA_TO_DEVICE;
1151
1152                 buf = chainup_buffers(dev, req->dst, crypt->auth_len,
1153                                       &dst_hook, flags, DMA_FROM_DEVICE);
1154                 req_ctx->dst = dst_hook.next;
1155                 crypt->dst_buf = dst_hook.phys_next;
1156
1157                 if (!buf)
1158                         goto free_buf_dst;
1159
1160                 if (encrypt) {
1161                         lastlen = buf->buf_len;
1162                         if (lastlen >= authsize)
1163                                 crypt->icv_rev_aes = buf->phys_addr +
1164                                                      buf->buf_len - authsize;
1165                 }
1166         }
1167
1168         if (unlikely(lastlen < authsize)) {
1169                 /* The 12 hmac bytes are scattered,
1170                  * we need to copy them into a safe buffer */
1171                 req_ctx->hmac_virt = dma_pool_alloc(buffer_pool, flags,
1172                                                     &crypt->icv_rev_aes);
1173                 if (unlikely(!req_ctx->hmac_virt))
1174                         goto free_buf_dst;
1175                 if (!encrypt) {
1176                         scatterwalk_map_and_copy(req_ctx->hmac_virt,
1177                                                  req->src, cryptlen, authsize, 0);
1178                 }
1179                 req_ctx->encrypt = encrypt;
1180         } else {
1181                 req_ctx->hmac_virt = NULL;
1182         }
1183
1184         crypt->ctl_flags |= CTL_FLAG_PERFORM_AEAD;
1185         qmgr_put_entry(send_qid, crypt_virt2phys(crypt));
1186         BUG_ON(qmgr_stat_overflow(send_qid));
1187         return -EINPROGRESS;
1188
1189 free_buf_dst:
1190         free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
1191 free_buf_src:
1192         free_buf_chain(dev, req_ctx->src, crypt->src_buf);
1193         crypt->ctl_flags = CTL_FLAG_UNUSED;
1194         return -ENOMEM;
1195 }
1196
1197 static int aead_setup(struct crypto_aead *tfm, unsigned int authsize)
1198 {
1199         struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1200         unsigned int digest_len = crypto_aead_maxauthsize(tfm);
1201         int ret;
1202
1203         if (!ctx->enckey_len && !ctx->authkey_len)
1204                 return 0;
1205         init_completion(&ctx->completion);
1206         atomic_inc(&ctx->configuring);
1207
1208         reset_sa_dir(&ctx->encrypt);
1209         reset_sa_dir(&ctx->decrypt);
1210
1211         ret = setup_cipher(&tfm->base, 0, ctx->enckey, ctx->enckey_len);
1212         if (ret)
1213                 goto out;
1214         ret = setup_cipher(&tfm->base, 1, ctx->enckey, ctx->enckey_len);
1215         if (ret)
1216                 goto out;
1217         ret = setup_auth(&tfm->base, 0, authsize, ctx->authkey,
1218                          ctx->authkey_len, digest_len);
1219         if (ret)
1220                 goto out;
1221         ret = setup_auth(&tfm->base, 1, authsize,  ctx->authkey,
1222                          ctx->authkey_len, digest_len);
1223 out:
1224         if (!atomic_dec_and_test(&ctx->configuring))
1225                 wait_for_completion(&ctx->completion);
1226         return ret;
1227 }
1228
1229 static int aead_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
1230 {
1231         int max = crypto_aead_maxauthsize(tfm) >> 2;
1232
1233         if ((authsize >> 2) < 1 || (authsize >> 2) > max || (authsize & 3))
1234                 return -EINVAL;
1235         return aead_setup(tfm, authsize);
1236 }
1237
1238 static int aead_setkey(struct crypto_aead *tfm, const u8 *key,
1239                        unsigned int keylen)
1240 {
1241         struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1242         struct crypto_authenc_keys keys;
1243
1244         if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
1245                 goto badkey;
1246
1247         if (keys.authkeylen > sizeof(ctx->authkey))
1248                 goto badkey;
1249
1250         if (keys.enckeylen > sizeof(ctx->enckey))
1251                 goto badkey;
1252
1253         memcpy(ctx->authkey, keys.authkey, keys.authkeylen);
1254         memcpy(ctx->enckey, keys.enckey, keys.enckeylen);
1255         ctx->authkey_len = keys.authkeylen;
1256         ctx->enckey_len = keys.enckeylen;
1257
1258         memzero_explicit(&keys, sizeof(keys));
1259         return aead_setup(tfm, crypto_aead_authsize(tfm));
1260 badkey:
1261         memzero_explicit(&keys, sizeof(keys));
1262         return -EINVAL;
1263 }
1264
1265 static int des3_aead_setkey(struct crypto_aead *tfm, const u8 *key,
1266                             unsigned int keylen)
1267 {
1268         struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1269         struct crypto_authenc_keys keys;
1270         int err;
1271
1272         err = crypto_authenc_extractkeys(&keys, key, keylen);
1273         if (unlikely(err))
1274                 goto badkey;
1275
1276         err = -EINVAL;
1277         if (keys.authkeylen > sizeof(ctx->authkey))
1278                 goto badkey;
1279
1280         err = verify_aead_des3_key(tfm, keys.enckey, keys.enckeylen);
1281         if (err)
1282                 goto badkey;
1283
1284         memcpy(ctx->authkey, keys.authkey, keys.authkeylen);
1285         memcpy(ctx->enckey, keys.enckey, keys.enckeylen);
1286         ctx->authkey_len = keys.authkeylen;
1287         ctx->enckey_len = keys.enckeylen;
1288
1289         memzero_explicit(&keys, sizeof(keys));
1290         return aead_setup(tfm, crypto_aead_authsize(tfm));
1291 badkey:
1292         memzero_explicit(&keys, sizeof(keys));
1293         return err;
1294 }
1295
1296 static int aead_encrypt(struct aead_request *req)
1297 {
1298         return aead_perform(req, 1, req->assoclen, req->cryptlen, req->iv);
1299 }
1300
1301 static int aead_decrypt(struct aead_request *req)
1302 {
1303         return aead_perform(req, 0, req->assoclen, req->cryptlen, req->iv);
1304 }
1305
1306 static struct ixp_alg ixp4xx_algos[] = {
1307 {
1308         .crypto = {
1309                 .base.cra_name          = "cbc(des)",
1310                 .base.cra_blocksize     = DES_BLOCK_SIZE,
1311
1312                 .min_keysize            = DES_KEY_SIZE,
1313                 .max_keysize            = DES_KEY_SIZE,
1314                 .ivsize                 = DES_BLOCK_SIZE,
1315         },
1316         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1317         .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1318
1319 }, {
1320         .crypto = {
1321                 .base.cra_name          = "ecb(des)",
1322                 .base.cra_blocksize     = DES_BLOCK_SIZE,
1323                 .min_keysize            = DES_KEY_SIZE,
1324                 .max_keysize            = DES_KEY_SIZE,
1325         },
1326         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_ECB | KEYLEN_192,
1327         .cfg_dec = CIPH_DECR | MOD_DES | MOD_ECB | KEYLEN_192,
1328 }, {
1329         .crypto = {
1330                 .base.cra_name          = "cbc(des3_ede)",
1331                 .base.cra_blocksize     = DES3_EDE_BLOCK_SIZE,
1332
1333                 .min_keysize            = DES3_EDE_KEY_SIZE,
1334                 .max_keysize            = DES3_EDE_KEY_SIZE,
1335                 .ivsize                 = DES3_EDE_BLOCK_SIZE,
1336                 .setkey                 = ablk_des3_setkey,
1337         },
1338         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1339         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1340 }, {
1341         .crypto = {
1342                 .base.cra_name          = "ecb(des3_ede)",
1343                 .base.cra_blocksize     = DES3_EDE_BLOCK_SIZE,
1344
1345                 .min_keysize            = DES3_EDE_KEY_SIZE,
1346                 .max_keysize            = DES3_EDE_KEY_SIZE,
1347                 .setkey                 = ablk_des3_setkey,
1348         },
1349         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_ECB | KEYLEN_192,
1350         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_ECB | KEYLEN_192,
1351 }, {
1352         .crypto = {
1353                 .base.cra_name          = "cbc(aes)",
1354                 .base.cra_blocksize     = AES_BLOCK_SIZE,
1355
1356                 .min_keysize            = AES_MIN_KEY_SIZE,
1357                 .max_keysize            = AES_MAX_KEY_SIZE,
1358                 .ivsize                 = AES_BLOCK_SIZE,
1359         },
1360         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1361         .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1362 }, {
1363         .crypto = {
1364                 .base.cra_name          = "ecb(aes)",
1365                 .base.cra_blocksize     = AES_BLOCK_SIZE,
1366
1367                 .min_keysize            = AES_MIN_KEY_SIZE,
1368                 .max_keysize            = AES_MAX_KEY_SIZE,
1369         },
1370         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_ECB,
1371         .cfg_dec = CIPH_DECR | MOD_AES | MOD_ECB,
1372 }, {
1373         .crypto = {
1374                 .base.cra_name          = "ctr(aes)",
1375                 .base.cra_blocksize     = 1,
1376
1377                 .min_keysize            = AES_MIN_KEY_SIZE,
1378                 .max_keysize            = AES_MAX_KEY_SIZE,
1379                 .ivsize                 = AES_BLOCK_SIZE,
1380         },
1381         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1382         .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1383 }, {
1384         .crypto = {
1385                 .base.cra_name          = "rfc3686(ctr(aes))",
1386                 .base.cra_blocksize     = 1,
1387
1388                 .min_keysize            = AES_MIN_KEY_SIZE,
1389                 .max_keysize            = AES_MAX_KEY_SIZE,
1390                 .ivsize                 = AES_BLOCK_SIZE,
1391                 .setkey                 = ablk_rfc3686_setkey,
1392                 .encrypt                = ablk_rfc3686_crypt,
1393                 .decrypt                = ablk_rfc3686_crypt,
1394         },
1395         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1396         .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1397 } };
1398
1399 static struct ixp_aead_alg ixp4xx_aeads[] = {
1400 {
1401         .crypto = {
1402                 .base = {
1403                         .cra_name       = "authenc(hmac(md5),cbc(des))",
1404                         .cra_blocksize  = DES_BLOCK_SIZE,
1405                 },
1406                 .ivsize         = DES_BLOCK_SIZE,
1407                 .maxauthsize    = MD5_DIGEST_SIZE,
1408         },
1409         .hash = &hash_alg_md5,
1410         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1411         .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1412 }, {
1413         .crypto = {
1414                 .base = {
1415                         .cra_name       = "authenc(hmac(md5),cbc(des3_ede))",
1416                         .cra_blocksize  = DES3_EDE_BLOCK_SIZE,
1417                 },
1418                 .ivsize         = DES3_EDE_BLOCK_SIZE,
1419                 .maxauthsize    = MD5_DIGEST_SIZE,
1420                 .setkey         = des3_aead_setkey,
1421         },
1422         .hash = &hash_alg_md5,
1423         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1424         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1425 }, {
1426         .crypto = {
1427                 .base = {
1428                         .cra_name       = "authenc(hmac(sha1),cbc(des))",
1429                         .cra_blocksize  = DES_BLOCK_SIZE,
1430                 },
1431                         .ivsize         = DES_BLOCK_SIZE,
1432                         .maxauthsize    = SHA1_DIGEST_SIZE,
1433         },
1434         .hash = &hash_alg_sha1,
1435         .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1436         .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1437 }, {
1438         .crypto = {
1439                 .base = {
1440                         .cra_name       = "authenc(hmac(sha1),cbc(des3_ede))",
1441                         .cra_blocksize  = DES3_EDE_BLOCK_SIZE,
1442                 },
1443                 .ivsize         = DES3_EDE_BLOCK_SIZE,
1444                 .maxauthsize    = SHA1_DIGEST_SIZE,
1445                 .setkey         = des3_aead_setkey,
1446         },
1447         .hash = &hash_alg_sha1,
1448         .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1449         .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1450 }, {
1451         .crypto = {
1452                 .base = {
1453                         .cra_name       = "authenc(hmac(md5),cbc(aes))",
1454                         .cra_blocksize  = AES_BLOCK_SIZE,
1455                 },
1456                 .ivsize         = AES_BLOCK_SIZE,
1457                 .maxauthsize    = MD5_DIGEST_SIZE,
1458         },
1459         .hash = &hash_alg_md5,
1460         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1461         .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1462 }, {
1463         .crypto = {
1464                 .base = {
1465                         .cra_name       = "authenc(hmac(sha1),cbc(aes))",
1466                         .cra_blocksize  = AES_BLOCK_SIZE,
1467                 },
1468                 .ivsize         = AES_BLOCK_SIZE,
1469                 .maxauthsize    = SHA1_DIGEST_SIZE,
1470         },
1471         .hash = &hash_alg_sha1,
1472         .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1473         .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1474 } };
1475
1476 #define IXP_POSTFIX "-ixp4xx"
1477
1478 static int ixp_crypto_probe(struct platform_device *_pdev)
1479 {
1480         struct device *dev = &_pdev->dev;
1481         int num = ARRAY_SIZE(ixp4xx_algos);
1482         int i, err;
1483
1484         pdev = _pdev;
1485
1486         err = init_ixp_crypto(dev);
1487         if (err)
1488                 return err;
1489
1490         for (i = 0; i < num; i++) {
1491                 struct skcipher_alg *cra = &ixp4xx_algos[i].crypto;
1492
1493                 if (snprintf(cra->base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
1494                              "%s"IXP_POSTFIX, cra->base.cra_name) >=
1495                              CRYPTO_MAX_ALG_NAME)
1496                         continue;
1497                 if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES))
1498                         continue;
1499
1500                 /* block ciphers */
1501                 cra->base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1502                                       CRYPTO_ALG_ASYNC |
1503                                       CRYPTO_ALG_ALLOCATES_MEMORY |
1504                                       CRYPTO_ALG_NEED_FALLBACK;
1505                 if (!cra->setkey)
1506                         cra->setkey = ablk_setkey;
1507                 if (!cra->encrypt)
1508                         cra->encrypt = ablk_encrypt;
1509                 if (!cra->decrypt)
1510                         cra->decrypt = ablk_decrypt;
1511                 cra->init = init_tfm_ablk;
1512                 cra->exit = exit_tfm_ablk;
1513
1514                 cra->base.cra_ctxsize = sizeof(struct ixp_ctx);
1515                 cra->base.cra_module = THIS_MODULE;
1516                 cra->base.cra_alignmask = 3;
1517                 cra->base.cra_priority = 300;
1518                 if (crypto_register_skcipher(cra))
1519                         dev_err(&pdev->dev, "Failed to register '%s'\n",
1520                                 cra->base.cra_name);
1521                 else
1522                         ixp4xx_algos[i].registered = 1;
1523         }
1524
1525         for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) {
1526                 struct aead_alg *cra = &ixp4xx_aeads[i].crypto;
1527
1528                 if (snprintf(cra->base.cra_driver_name, CRYPTO_MAX_ALG_NAME,
1529                              "%s"IXP_POSTFIX, cra->base.cra_name) >=
1530                     CRYPTO_MAX_ALG_NAME)
1531                         continue;
1532                 if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES))
1533                         continue;
1534
1535                 /* authenc */
1536                 cra->base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1537                                       CRYPTO_ALG_ASYNC |
1538                                       CRYPTO_ALG_ALLOCATES_MEMORY;
1539                 cra->setkey = cra->setkey ?: aead_setkey;
1540                 cra->setauthsize = aead_setauthsize;
1541                 cra->encrypt = aead_encrypt;
1542                 cra->decrypt = aead_decrypt;
1543                 cra->init = init_tfm_aead;
1544                 cra->exit = exit_tfm_aead;
1545
1546                 cra->base.cra_ctxsize = sizeof(struct ixp_ctx);
1547                 cra->base.cra_module = THIS_MODULE;
1548                 cra->base.cra_alignmask = 3;
1549                 cra->base.cra_priority = 300;
1550
1551                 if (crypto_register_aead(cra))
1552                         dev_err(&pdev->dev, "Failed to register '%s'\n",
1553                                 cra->base.cra_driver_name);
1554                 else
1555                         ixp4xx_aeads[i].registered = 1;
1556         }
1557         return 0;
1558 }
1559
1560 static int ixp_crypto_remove(struct platform_device *pdev)
1561 {
1562         int num = ARRAY_SIZE(ixp4xx_algos);
1563         int i;
1564
1565         for (i = 0; i < ARRAY_SIZE(ixp4xx_aeads); i++) {
1566                 if (ixp4xx_aeads[i].registered)
1567                         crypto_unregister_aead(&ixp4xx_aeads[i].crypto);
1568         }
1569
1570         for (i = 0; i < num; i++) {
1571                 if (ixp4xx_algos[i].registered)
1572                         crypto_unregister_skcipher(&ixp4xx_algos[i].crypto);
1573         }
1574         release_ixp_crypto(&pdev->dev);
1575
1576         return 0;
1577 }
1578 static const struct of_device_id ixp4xx_crypto_of_match[] = {
1579         {
1580                 .compatible = "intel,ixp4xx-crypto",
1581         },
1582         {},
1583 };
1584
1585 static struct platform_driver ixp_crypto_driver = {
1586         .probe = ixp_crypto_probe,
1587         .remove = ixp_crypto_remove,
1588         .driver = {
1589                 .name = "ixp4xx_crypto",
1590                 .of_match_table = ixp4xx_crypto_of_match,
1591         },
1592 };
1593 module_platform_driver(ixp_crypto_driver);
1594
1595 MODULE_LICENSE("GPL");
1596 MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");
1597 MODULE_DESCRIPTION("IXP4xx hardware crypto");
1598