1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 HiSilicon Limited. */
4 #include <linux/acpi.h>
6 #include <linux/bitmap.h>
7 #include <linux/dma-mapping.h>
10 #include <linux/irqreturn.h>
11 #include <linux/log2.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/seq_file.h>
14 #include <linux/slab.h>
15 #include <linux/uacce.h>
16 #include <linux/uaccess.h>
17 #include <uapi/misc/uacce/hisi_qm.h>
20 /* eq/aeq irq enable */
21 #define QM_VF_AEQ_INT_SOURCE 0x0
22 #define QM_VF_AEQ_INT_MASK 0x4
23 #define QM_VF_EQ_INT_SOURCE 0x8
24 #define QM_VF_EQ_INT_MASK 0xc
25 #define QM_IRQ_NUM_V1 1
26 #define QM_IRQ_NUM_PF_V2 4
27 #define QM_IRQ_NUM_VF_V2 2
28 #define QM_IRQ_NUM_VF_V3 3
30 #define QM_EQ_EVENT_IRQ_VECTOR 0
31 #define QM_AEQ_EVENT_IRQ_VECTOR 1
32 #define QM_CMD_EVENT_IRQ_VECTOR 2
33 #define QM_ABNORMAL_EVENT_IRQ_VECTOR 3
36 #define QM_MB_CMD_SQC 0x0
37 #define QM_MB_CMD_CQC 0x1
38 #define QM_MB_CMD_EQC 0x2
39 #define QM_MB_CMD_AEQC 0x3
40 #define QM_MB_CMD_SQC_BT 0x4
41 #define QM_MB_CMD_CQC_BT 0x5
42 #define QM_MB_CMD_SQC_VFT_V2 0x6
43 #define QM_MB_CMD_STOP_QP 0x8
44 #define QM_MB_CMD_SRC 0xc
45 #define QM_MB_CMD_DST 0xd
47 #define QM_MB_CMD_SEND_BASE 0x300
48 #define QM_MB_EVENT_SHIFT 8
49 #define QM_MB_BUSY_SHIFT 13
50 #define QM_MB_OP_SHIFT 14
51 #define QM_MB_CMD_DATA_ADDR_L 0x304
52 #define QM_MB_CMD_DATA_ADDR_H 0x308
53 #define QM_MB_PING_ALL_VFS 0xffff
54 #define QM_MB_CMD_DATA_SHIFT 32
55 #define QM_MB_CMD_DATA_MASK GENMASK(31, 0)
58 #define QM_SQ_HOP_NUM_SHIFT 0
59 #define QM_SQ_PAGE_SIZE_SHIFT 4
60 #define QM_SQ_BUF_SIZE_SHIFT 8
61 #define QM_SQ_SQE_SIZE_SHIFT 12
62 #define QM_SQ_PRIORITY_SHIFT 0
63 #define QM_SQ_ORDERS_SHIFT 4
64 #define QM_SQ_TYPE_SHIFT 8
65 #define QM_QC_PASID_ENABLE 0x1
66 #define QM_QC_PASID_ENABLE_SHIFT 7
68 #define QM_SQ_TYPE_MASK GENMASK(3, 0)
69 #define QM_SQ_TAIL_IDX(sqc) ((le16_to_cpu((sqc)->w11) >> 6) & 0x1)
72 #define QM_CQ_HOP_NUM_SHIFT 0
73 #define QM_CQ_PAGE_SIZE_SHIFT 4
74 #define QM_CQ_BUF_SIZE_SHIFT 8
75 #define QM_CQ_CQE_SIZE_SHIFT 12
76 #define QM_CQ_PHASE_SHIFT 0
77 #define QM_CQ_FLAG_SHIFT 1
79 #define QM_CQE_PHASE(cqe) (le16_to_cpu((cqe)->w7) & 0x1)
80 #define QM_QC_CQE_SIZE 4
81 #define QM_CQ_TAIL_IDX(cqc) ((le16_to_cpu((cqc)->w11) >> 6) & 0x1)
84 #define QM_EQE_AEQE_SIZE (2UL << 12)
85 #define QM_EQC_PHASE_SHIFT 16
87 #define QM_EQE_PHASE(eqe) ((le32_to_cpu((eqe)->dw0) >> 16) & 0x1)
88 #define QM_EQE_CQN_MASK GENMASK(15, 0)
90 #define QM_AEQE_PHASE(aeqe) ((le32_to_cpu((aeqe)->dw0) >> 16) & 0x1)
91 #define QM_AEQE_TYPE_SHIFT 17
93 #define QM_DOORBELL_CMD_SQ 0
94 #define QM_DOORBELL_CMD_CQ 1
95 #define QM_DOORBELL_CMD_EQ 2
96 #define QM_DOORBELL_CMD_AEQ 3
98 #define QM_DOORBELL_BASE_V1 0x340
99 #define QM_DB_CMD_SHIFT_V1 16
100 #define QM_DB_INDEX_SHIFT_V1 32
101 #define QM_DB_PRIORITY_SHIFT_V1 48
102 #define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
103 #define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
104 #define QM_QUE_ISO_CFG_V 0x0030
105 #define QM_PAGE_SIZE 0x0034
106 #define QM_QUE_ISO_EN 0x100154
107 #define QM_CAPBILITY 0x100158
108 #define QM_QP_NUN_MASK GENMASK(10, 0)
109 #define QM_QP_DB_INTERVAL 0x10000
110 #define QM_QP_MAX_NUM_SHIFT 11
111 #define QM_DB_CMD_SHIFT_V2 12
112 #define QM_DB_RAND_SHIFT_V2 16
113 #define QM_DB_INDEX_SHIFT_V2 32
114 #define QM_DB_PRIORITY_SHIFT_V2 48
116 #define QM_MEM_START_INIT 0x100040
117 #define QM_MEM_INIT_DONE 0x100044
118 #define QM_VFT_CFG_RDY 0x10006c
119 #define QM_VFT_CFG_OP_WR 0x100058
120 #define QM_VFT_CFG_TYPE 0x10005c
121 #define QM_SQC_VFT 0x0
122 #define QM_CQC_VFT 0x1
123 #define QM_VFT_CFG 0x100060
124 #define QM_VFT_CFG_OP_ENABLE 0x100054
126 #define QM_VFT_CFG_DATA_L 0x100064
127 #define QM_VFT_CFG_DATA_H 0x100068
128 #define QM_SQC_VFT_BUF_SIZE (7ULL << 8)
129 #define QM_SQC_VFT_SQC_SIZE (5ULL << 12)
130 #define QM_SQC_VFT_INDEX_NUMBER (1ULL << 16)
131 #define QM_SQC_VFT_START_SQN_SHIFT 28
132 #define QM_SQC_VFT_VALID (1ULL << 44)
133 #define QM_SQC_VFT_SQN_SHIFT 45
134 #define QM_CQC_VFT_BUF_SIZE (7ULL << 8)
135 #define QM_CQC_VFT_SQC_SIZE (5ULL << 12)
136 #define QM_CQC_VFT_INDEX_NUMBER (1ULL << 16)
137 #define QM_CQC_VFT_VALID (1ULL << 28)
139 #define QM_SQC_VFT_BASE_SHIFT_V2 28
140 #define QM_SQC_VFT_BASE_MASK_V2 GENMASK(15, 0)
141 #define QM_SQC_VFT_NUM_SHIFT_V2 45
142 #define QM_SQC_VFT_NUM_MASK_v2 GENMASK(9, 0)
144 #define QM_DFX_CNT_CLR_CE 0x100118
146 #define QM_ABNORMAL_INT_SOURCE 0x100000
147 #define QM_ABNORMAL_INT_SOURCE_CLR GENMASK(14, 0)
148 #define QM_ABNORMAL_INT_MASK 0x100004
149 #define QM_ABNORMAL_INT_MASK_VALUE 0x7fff
150 #define QM_ABNORMAL_INT_STATUS 0x100008
151 #define QM_ABNORMAL_INT_SET 0x10000c
152 #define QM_ABNORMAL_INF00 0x100010
153 #define QM_FIFO_OVERFLOW_TYPE 0xc0
154 #define QM_FIFO_OVERFLOW_TYPE_SHIFT 6
155 #define QM_FIFO_OVERFLOW_VF 0x3f
156 #define QM_ABNORMAL_INF01 0x100014
157 #define QM_DB_TIMEOUT_TYPE 0xc0
158 #define QM_DB_TIMEOUT_TYPE_SHIFT 6
159 #define QM_DB_TIMEOUT_VF 0x3f
160 #define QM_RAS_CE_ENABLE 0x1000ec
161 #define QM_RAS_FE_ENABLE 0x1000f0
162 #define QM_RAS_NFE_ENABLE 0x1000f4
163 #define QM_RAS_CE_THRESHOLD 0x1000f8
164 #define QM_RAS_CE_TIMES_PER_IRQ 1
165 #define QM_RAS_MSI_INT_SEL 0x1040f4
166 #define QM_OOO_SHUTDOWN_SEL 0x1040f8
168 #define QM_RESET_WAIT_TIMEOUT 400
169 #define QM_PEH_VENDOR_ID 0x1000d8
170 #define ACC_VENDOR_ID_VALUE 0x5a5a
171 #define QM_PEH_DFX_INFO0 0x1000fc
172 #define QM_PEH_DFX_INFO1 0x100100
173 #define QM_PEH_DFX_MASK (BIT(0) | BIT(2))
174 #define QM_PEH_MSI_FINISH_MASK GENMASK(19, 16)
175 #define ACC_PEH_SRIOV_CTRL_VF_MSE_SHIFT 3
176 #define ACC_PEH_MSI_DISABLE GENMASK(31, 0)
177 #define ACC_MASTER_GLOBAL_CTRL_SHUTDOWN 0x1
178 #define ACC_MASTER_TRANS_RETURN_RW 3
179 #define ACC_MASTER_TRANS_RETURN 0x300150
180 #define ACC_MASTER_GLOBAL_CTRL 0x300000
181 #define ACC_AM_CFG_PORT_WR_EN 0x30001c
182 #define QM_RAS_NFE_MBIT_DISABLE ~QM_ECC_MBIT
183 #define ACC_AM_ROB_ECC_INT_STS 0x300104
184 #define ACC_ROB_ECC_ERR_MULTPL BIT(1)
185 #define QM_MSI_CAP_ENABLE BIT(16)
187 /* interfunction communication */
188 #define QM_IFC_READY_STATUS 0x100128
189 #define QM_IFC_C_STS_M 0x10012C
190 #define QM_IFC_INT_SET_P 0x100130
191 #define QM_IFC_INT_CFG 0x100134
192 #define QM_IFC_INT_SOURCE_P 0x100138
193 #define QM_IFC_INT_SOURCE_V 0x0020
194 #define QM_IFC_INT_MASK 0x0024
195 #define QM_IFC_INT_STATUS 0x0028
196 #define QM_IFC_INT_SET_V 0x002C
197 #define QM_IFC_SEND_ALL_VFS GENMASK(6, 0)
198 #define QM_IFC_INT_SOURCE_CLR GENMASK(63, 0)
199 #define QM_IFC_INT_SOURCE_MASK BIT(0)
200 #define QM_IFC_INT_DISABLE BIT(0)
201 #define QM_IFC_INT_STATUS_MASK BIT(0)
202 #define QM_IFC_INT_SET_MASK BIT(0)
203 #define QM_WAIT_DST_ACK 10
204 #define QM_MAX_PF_WAIT_COUNT 10
205 #define QM_MAX_VF_WAIT_COUNT 40
206 #define QM_VF_RESET_WAIT_US 20000
207 #define QM_VF_RESET_WAIT_CNT 3000
208 #define QM_VF_RESET_WAIT_TIMEOUT_US \
209 (QM_VF_RESET_WAIT_US * QM_VF_RESET_WAIT_CNT)
211 #define QM_DFX_MB_CNT_VF 0x104010
212 #define QM_DFX_DB_CNT_VF 0x104020
213 #define QM_DFX_SQE_CNT_VF_SQN 0x104030
214 #define QM_DFX_CQE_CNT_VF_CQN 0x104040
215 #define QM_DFX_QN_SHIFT 16
216 #define CURRENT_FUN_MASK GENMASK(5, 0)
217 #define CURRENT_Q_MASK GENMASK(31, 16)
219 #define POLL_PERIOD 10
220 #define POLL_TIMEOUT 1000
221 #define WAIT_PERIOD_US_MAX 200
222 #define WAIT_PERIOD_US_MIN 100
223 #define MAX_WAIT_COUNTS 1000
224 #define QM_CACHE_WB_START 0x204
225 #define QM_CACHE_WB_DONE 0x208
229 #define QM_SQE_DATA_ALIGN_MASK GENMASK(6, 0)
230 #define QMC_ALIGN(sz) ALIGN(sz, 32)
232 #define QM_DBG_READ_LEN 256
233 #define QM_DBG_WRITE_LEN 1024
234 #define QM_DBG_TMP_BUF_LEN 22
235 #define QM_PCI_COMMAND_INVALID ~0
237 #define WAIT_PERIOD 20
238 #define REMOVE_WAIT_DELAY 10
239 #define QM_SQE_ADDR_MASK GENMASK(7, 0)
240 #define QM_EQ_DEPTH (1024 * 2)
242 #define QM_DRIVER_REMOVING 0
243 #define QM_RST_SCHED 1
244 #define QM_RESETTING 2
245 #define QM_QOS_PARAM_NUM 2
246 #define QM_QOS_VAL_NUM 1
247 #define QM_QOS_BDF_PARAM_NUM 4
248 #define QM_QOS_MAX_VAL 1000
249 #define QM_QOS_RATE 100
250 #define QM_QOS_EXPAND_RATE 1000
251 #define QM_SHAPER_CIR_B_MASK GENMASK(7, 0)
252 #define QM_SHAPER_CIR_U_MASK GENMASK(10, 8)
253 #define QM_SHAPER_CIR_S_MASK GENMASK(14, 11)
254 #define QM_SHAPER_FACTOR_CIR_U_SHIFT 8
255 #define QM_SHAPER_FACTOR_CIR_S_SHIFT 11
256 #define QM_SHAPER_FACTOR_CBS_B_SHIFT 15
257 #define QM_SHAPER_FACTOR_CBS_S_SHIFT 19
258 #define QM_SHAPER_CBS_B 1
259 #define QM_SHAPER_CBS_S 16
260 #define QM_SHAPER_VFT_OFFSET 6
261 #define WAIT_FOR_QOS_VF 100
262 #define QM_QOS_MIN_ERROR_RATE 5
263 #define QM_QOS_TYPICAL_NUM 8
264 #define QM_SHAPER_MIN_CBS_S 8
265 #define QM_QOS_TICK 0x300U
266 #define QM_QOS_DIVISOR_CLK 0x1f40U
267 #define QM_QOS_MAX_CIR_B 200
268 #define QM_QOS_MIN_CIR_B 100
269 #define QM_QOS_MAX_CIR_U 6
270 #define QM_QOS_MAX_CIR_S 11
271 #define QM_QOS_VAL_MAX_LEN 32
273 #define QM_AUTOSUSPEND_DELAY 3000
275 #define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \
276 (((hop_num) << QM_CQ_HOP_NUM_SHIFT) | \
277 ((pg_sz) << QM_CQ_PAGE_SIZE_SHIFT) | \
278 ((buf_sz) << QM_CQ_BUF_SIZE_SHIFT) | \
279 ((cqe_sz) << QM_CQ_CQE_SIZE_SHIFT))
281 #define QM_MK_CQC_DW3_V2(cqe_sz) \
282 ((QM_Q_DEPTH - 1) | ((cqe_sz) << QM_CQ_CQE_SIZE_SHIFT))
284 #define QM_MK_SQC_W13(priority, orders, alg_type) \
285 (((priority) << QM_SQ_PRIORITY_SHIFT) | \
286 ((orders) << QM_SQ_ORDERS_SHIFT) | \
287 (((alg_type) & QM_SQ_TYPE_MASK) << QM_SQ_TYPE_SHIFT))
289 #define QM_MK_SQC_DW3_V1(hop_num, pg_sz, buf_sz, sqe_sz) \
290 (((hop_num) << QM_SQ_HOP_NUM_SHIFT) | \
291 ((pg_sz) << QM_SQ_PAGE_SIZE_SHIFT) | \
292 ((buf_sz) << QM_SQ_BUF_SIZE_SHIFT) | \
293 ((u32)ilog2(sqe_sz) << QM_SQ_SQE_SIZE_SHIFT))
295 #define QM_MK_SQC_DW3_V2(sqe_sz) \
296 ((QM_Q_DEPTH - 1) | ((u32)ilog2(sqe_sz) << QM_SQ_SQE_SIZE_SHIFT))
298 #define INIT_QC_COMMON(qc, base, pasid) do { \
301 (qc)->base_l = cpu_to_le32(lower_32_bits(base)); \
302 (qc)->base_h = cpu_to_le32(upper_32_bits(base)); \
306 (qc)->pasid = cpu_to_le16(pasid); \
317 enum acc_err_result {
329 QM_PF_FLR_PREPARE = 0x01,
422 struct hisi_qm_resource {
425 struct list_head list;
428 struct hisi_qm_hw_ops {
429 int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number);
430 void (*qm_db)(struct hisi_qm *qm, u16 qn,
431 u8 cmd, u16 index, u8 priority);
432 u32 (*get_irq_num)(struct hisi_qm *qm);
433 int (*debug_init)(struct hisi_qm *qm);
434 void (*hw_error_init)(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe);
435 void (*hw_error_uninit)(struct hisi_qm *qm);
436 enum acc_err_result (*hw_error_handle)(struct hisi_qm *qm);
437 int (*stop_qp)(struct hisi_qp *qp);
438 int (*set_msi)(struct hisi_qm *qm, bool set);
439 int (*ping_all_vfs)(struct hisi_qm *qm, u64 cmd);
440 int (*ping_pf)(struct hisi_qm *qm, u64 cmd);
448 static struct qm_dfx_item qm_dfx_files[] = {
449 {"err_irq", offsetof(struct qm_dfx, err_irq_cnt)},
450 {"aeq_irq", offsetof(struct qm_dfx, aeq_irq_cnt)},
451 {"abnormal_irq", offsetof(struct qm_dfx, abnormal_irq_cnt)},
452 {"create_qp_err", offsetof(struct qm_dfx, create_qp_err_cnt)},
453 {"mb_err", offsetof(struct qm_dfx, mb_err_cnt)},
456 static const char * const qm_debug_file_name[] = {
457 [CURRENT_QM] = "current_qm",
458 [CURRENT_Q] = "current_q",
459 [CLEAR_ENABLE] = "clear_enable",
462 struct hisi_qm_hw_error {
467 static const struct hisi_qm_hw_error qm_hw_error[] = {
468 { .int_msk = BIT(0), .msg = "qm_axi_rresp" },
469 { .int_msk = BIT(1), .msg = "qm_axi_bresp" },
470 { .int_msk = BIT(2), .msg = "qm_ecc_mbit" },
471 { .int_msk = BIT(3), .msg = "qm_ecc_1bit" },
472 { .int_msk = BIT(4), .msg = "qm_acc_get_task_timeout" },
473 { .int_msk = BIT(5), .msg = "qm_acc_do_task_timeout" },
474 { .int_msk = BIT(6), .msg = "qm_acc_wb_not_ready_timeout" },
475 { .int_msk = BIT(7), .msg = "qm_sq_cq_vf_invalid" },
476 { .int_msk = BIT(8), .msg = "qm_cq_vf_invalid" },
477 { .int_msk = BIT(9), .msg = "qm_sq_vf_invalid" },
478 { .int_msk = BIT(10), .msg = "qm_db_timeout" },
479 { .int_msk = BIT(11), .msg = "qm_of_fifo_of" },
480 { .int_msk = BIT(12), .msg = "qm_db_random_invalid" },
481 { .int_msk = BIT(13), .msg = "qm_mailbox_timeout" },
482 { .int_msk = BIT(14), .msg = "qm_flr_timeout" },
486 static const char * const qm_db_timeout[] = {
487 "sq", "cq", "eq", "aeq",
490 static const char * const qm_fifo_overflow[] = {
494 static const char * const qm_s[] = {
495 "init", "start", "close", "stop",
498 static const char * const qp_s[] = {
499 "none", "init", "start", "stop", "close",
502 static const u32 typical_qos_val[QM_QOS_TYPICAL_NUM] = {100, 250, 500, 1000,
503 10000, 25000, 50000, 100000};
504 static const u32 typical_qos_cbs_s[QM_QOS_TYPICAL_NUM] = {9, 10, 11, 12, 16,
507 static bool qm_avail_state(struct hisi_qm *qm, enum qm_state new)
509 enum qm_state curr = atomic_read(&qm->status.flags);
514 if (new == QM_START || new == QM_CLOSE)
522 if (new == QM_CLOSE || new == QM_START)
529 dev_dbg(&qm->pdev->dev, "change qm state from %s to %s\n",
530 qm_s[curr], qm_s[new]);
533 dev_warn(&qm->pdev->dev, "Can not change qm state from %s to %s\n",
534 qm_s[curr], qm_s[new]);
539 static bool qm_qp_avail_state(struct hisi_qm *qm, struct hisi_qp *qp,
542 enum qm_state qm_curr = atomic_read(&qm->status.flags);
543 enum qp_state qp_curr = 0;
547 qp_curr = atomic_read(&qp->qp_status.flags);
551 if (qm_curr == QM_START || qm_curr == QM_INIT)
555 if ((qm_curr == QM_START && qp_curr == QP_INIT) ||
556 (qm_curr == QM_START && qp_curr == QP_STOP))
560 if ((qm_curr == QM_START && qp_curr == QP_START) ||
561 (qp_curr == QP_INIT))
565 if ((qm_curr == QM_START && qp_curr == QP_INIT) ||
566 (qm_curr == QM_START && qp_curr == QP_STOP) ||
567 (qm_curr == QM_STOP && qp_curr == QP_STOP) ||
568 (qm_curr == QM_STOP && qp_curr == QP_INIT))
575 dev_dbg(&qm->pdev->dev, "change qp state from %s to %s in QM %s\n",
576 qp_s[qp_curr], qp_s[new], qm_s[qm_curr]);
579 dev_warn(&qm->pdev->dev,
580 "Can not change qp state from %s to %s in QM %s\n",
581 qp_s[qp_curr], qp_s[new], qm_s[qm_curr]);
586 static void qm_mb_pre_init(struct qm_mailbox *mailbox, u8 cmd,
587 u64 base, u16 queue, bool op)
589 mailbox->w0 = cpu_to_le16((cmd) |
590 ((op) ? 0x1 << QM_MB_OP_SHIFT : 0) |
591 (0x1 << QM_MB_BUSY_SHIFT));
592 mailbox->queue_num = cpu_to_le16(queue);
593 mailbox->base_l = cpu_to_le32(lower_32_bits(base));
594 mailbox->base_h = cpu_to_le32(upper_32_bits(base));
598 /* return 0 mailbox ready, -ETIMEDOUT hardware timeout */
599 static int qm_wait_mb_ready(struct hisi_qm *qm)
603 return readl_relaxed_poll_timeout(qm->io_base + QM_MB_CMD_SEND_BASE,
604 val, !((val >> QM_MB_BUSY_SHIFT) &
605 0x1), POLL_PERIOD, POLL_TIMEOUT);
608 /* 128 bit should be written to hardware at one time to trigger a mailbox */
609 static void qm_mb_write(struct hisi_qm *qm, const void *src)
611 void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
612 unsigned long tmp0 = 0, tmp1 = 0;
614 if (!IS_ENABLED(CONFIG_ARM64)) {
615 memcpy_toio(fun_base, src, 16);
620 asm volatile("ldp %0, %1, %3\n"
625 "+Q" (*((char __iomem *)fun_base))
626 : "Q" (*((char *)src))
630 static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox)
632 if (unlikely(qm_wait_mb_ready(qm))) {
633 dev_err(&qm->pdev->dev, "QM mailbox is busy to start!\n");
637 qm_mb_write(qm, mailbox);
639 if (unlikely(qm_wait_mb_ready(qm))) {
640 dev_err(&qm->pdev->dev, "QM mailbox operation timeout!\n");
647 atomic64_inc(&qm->debug.dfx.mb_err_cnt);
651 static int qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
654 struct qm_mailbox mailbox;
657 dev_dbg(&qm->pdev->dev, "QM mailbox request to q%u: %u-%llx\n",
658 queue, cmd, (unsigned long long)dma_addr);
660 qm_mb_pre_init(&mailbox, cmd, dma_addr, queue, op);
662 mutex_lock(&qm->mailbox_lock);
663 ret = qm_mb_nolock(qm, &mailbox);
664 mutex_unlock(&qm->mailbox_lock);
669 static void qm_db_v1(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
673 doorbell = qn | ((u64)cmd << QM_DB_CMD_SHIFT_V1) |
674 ((u64)index << QM_DB_INDEX_SHIFT_V1) |
675 ((u64)priority << QM_DB_PRIORITY_SHIFT_V1);
677 writeq(doorbell, qm->io_base + QM_DOORBELL_BASE_V1);
680 static void qm_db_v2(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
682 void __iomem *io_base = qm->io_base;
686 if (cmd == QM_DOORBELL_CMD_SQ || cmd == QM_DOORBELL_CMD_CQ)
687 io_base = qm->db_io_base + (u64)qn * qm->db_interval +
688 QM_DOORBELL_SQ_CQ_BASE_V2;
690 io_base += QM_DOORBELL_EQ_AEQ_BASE_V2;
692 doorbell = qn | ((u64)cmd << QM_DB_CMD_SHIFT_V2) |
693 ((u64)randata << QM_DB_RAND_SHIFT_V2) |
694 ((u64)index << QM_DB_INDEX_SHIFT_V2) |
695 ((u64)priority << QM_DB_PRIORITY_SHIFT_V2);
697 writeq(doorbell, io_base);
700 static void qm_db(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
702 dev_dbg(&qm->pdev->dev, "QM doorbell request: qn=%u, cmd=%u, index=%u\n",
705 qm->ops->qm_db(qm, qn, cmd, index, priority);
708 static int qm_dev_mem_reset(struct hisi_qm *qm)
712 writel(0x1, qm->io_base + QM_MEM_START_INIT);
713 return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val,
714 val & BIT(0), POLL_PERIOD,
718 static u32 qm_get_irq_num_v1(struct hisi_qm *qm)
720 return QM_IRQ_NUM_V1;
723 static u32 qm_get_irq_num_v2(struct hisi_qm *qm)
725 if (qm->fun_type == QM_HW_PF)
726 return QM_IRQ_NUM_PF_V2;
728 return QM_IRQ_NUM_VF_V2;
731 static u32 qm_get_irq_num_v3(struct hisi_qm *qm)
733 if (qm->fun_type == QM_HW_PF)
734 return QM_IRQ_NUM_PF_V2;
736 return QM_IRQ_NUM_VF_V3;
739 static int qm_pm_get_sync(struct hisi_qm *qm)
741 struct device *dev = &qm->pdev->dev;
744 if (qm->fun_type == QM_HW_VF || qm->ver < QM_HW_V3)
747 ret = pm_runtime_resume_and_get(dev);
749 dev_err(dev, "failed to get_sync(%d).\n", ret);
756 static void qm_pm_put_sync(struct hisi_qm *qm)
758 struct device *dev = &qm->pdev->dev;
760 if (qm->fun_type == QM_HW_VF || qm->ver < QM_HW_V3)
763 pm_runtime_mark_last_busy(dev);
764 pm_runtime_put_autosuspend(dev);
767 static struct hisi_qp *qm_to_hisi_qp(struct hisi_qm *qm, struct qm_eqe *eqe)
769 u16 cqn = le32_to_cpu(eqe->dw0) & QM_EQE_CQN_MASK;
771 return &qm->qp_array[cqn];
774 static void qm_cq_head_update(struct hisi_qp *qp)
776 if (qp->qp_status.cq_head == QM_Q_DEPTH - 1) {
777 qp->qp_status.cqc_phase = !qp->qp_status.cqc_phase;
778 qp->qp_status.cq_head = 0;
780 qp->qp_status.cq_head++;
784 static void qm_poll_qp(struct hisi_qp *qp, struct hisi_qm *qm)
786 if (unlikely(atomic_read(&qp->qp_status.flags) == QP_STOP))
795 struct qm_cqe *cqe = qp->cqe + qp->qp_status.cq_head;
797 while (QM_CQE_PHASE(cqe) == qp->qp_status.cqc_phase) {
799 qp->req_cb(qp, qp->sqe + qm->sqe_size *
800 le16_to_cpu(cqe->sq_head));
801 qm_cq_head_update(qp);
802 cqe = qp->cqe + qp->qp_status.cq_head;
803 qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ,
804 qp->qp_status.cq_head, 0);
805 atomic_dec(&qp->qp_status.used);
809 qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ,
810 qp->qp_status.cq_head, 1);
814 static void qm_work_process(struct work_struct *work)
816 struct hisi_qm *qm = container_of(work, struct hisi_qm, work);
817 struct qm_eqe *eqe = qm->eqe + qm->status.eq_head;
821 while (QM_EQE_PHASE(eqe) == qm->status.eqc_phase) {
823 qp = qm_to_hisi_qp(qm, eqe);
826 if (qm->status.eq_head == QM_EQ_DEPTH - 1) {
827 qm->status.eqc_phase = !qm->status.eqc_phase;
829 qm->status.eq_head = 0;
832 qm->status.eq_head++;
835 if (eqe_num == QM_EQ_DEPTH / 2 - 1) {
837 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
841 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
844 static irqreturn_t do_qm_irq(int irq, void *data)
846 struct hisi_qm *qm = (struct hisi_qm *)data;
848 /* the workqueue created by device driver of QM */
850 queue_work(qm->wq, &qm->work);
852 schedule_work(&qm->work);
857 static irqreturn_t qm_irq(int irq, void *data)
859 struct hisi_qm *qm = data;
861 if (readl(qm->io_base + QM_VF_EQ_INT_SOURCE))
862 return do_qm_irq(irq, data);
864 atomic64_inc(&qm->debug.dfx.err_irq_cnt);
865 dev_err(&qm->pdev->dev, "invalid int source\n");
866 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
871 static irqreturn_t qm_mb_cmd_irq(int irq, void *data)
873 struct hisi_qm *qm = data;
876 val = readl(qm->io_base + QM_IFC_INT_STATUS);
877 val &= QM_IFC_INT_STATUS_MASK;
881 schedule_work(&qm->cmd_process);
886 static irqreturn_t qm_aeq_irq(int irq, void *data)
888 struct hisi_qm *qm = data;
889 struct qm_aeqe *aeqe = qm->aeqe + qm->status.aeq_head;
892 atomic64_inc(&qm->debug.dfx.aeq_irq_cnt);
893 if (!readl(qm->io_base + QM_VF_AEQ_INT_SOURCE))
896 while (QM_AEQE_PHASE(aeqe) == qm->status.aeqc_phase) {
897 type = le32_to_cpu(aeqe->dw0) >> QM_AEQE_TYPE_SHIFT;
898 if (type < ARRAY_SIZE(qm_fifo_overflow))
899 dev_err(&qm->pdev->dev, "%s overflow\n",
900 qm_fifo_overflow[type]);
902 dev_err(&qm->pdev->dev, "unknown error type %u\n",
905 if (qm->status.aeq_head == QM_Q_DEPTH - 1) {
906 qm->status.aeqc_phase = !qm->status.aeqc_phase;
908 qm->status.aeq_head = 0;
911 qm->status.aeq_head++;
914 qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0);
920 static void qm_irq_unregister(struct hisi_qm *qm)
922 struct pci_dev *pdev = qm->pdev;
924 free_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR), qm);
926 if (qm->ver > QM_HW_V1) {
927 free_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR), qm);
929 if (qm->fun_type == QM_HW_PF)
930 free_irq(pci_irq_vector(pdev,
931 QM_ABNORMAL_EVENT_IRQ_VECTOR), qm);
934 if (qm->ver > QM_HW_V2)
935 free_irq(pci_irq_vector(pdev, QM_CMD_EVENT_IRQ_VECTOR), qm);
938 static void qm_init_qp_status(struct hisi_qp *qp)
940 struct hisi_qp_status *qp_status = &qp->qp_status;
942 qp_status->sq_tail = 0;
943 qp_status->cq_head = 0;
944 qp_status->cqc_phase = true;
945 atomic_set(&qp_status->used, 0);
948 static void qm_init_prefetch(struct hisi_qm *qm)
950 struct device *dev = &qm->pdev->dev;
953 if (qm->ver < QM_HW_V3)
967 dev_err(dev, "system page size is not support: %lu, default set to 4KB",
971 writel(page_type, qm->io_base + QM_PAGE_SIZE);
976 * IR = X Mbps if ir = 1 means IR = 100 Mbps, if ir = 10000 means = 10Gbps
978 * IR_b * (2 ^ IR_u) * 8
979 * IR(Mbps) * 10 ^ -3 = -------------------------
982 static u32 acc_shaper_para_calc(u64 cir_b, u64 cir_u, u64 cir_s)
984 return ((cir_b * QM_QOS_DIVISOR_CLK) * (1 << cir_u)) /
985 (QM_QOS_TICK * (1 << cir_s));
988 static u32 acc_shaper_calc_cbs_s(u32 ir)
992 if (ir < typical_qos_val[0])
993 return QM_SHAPER_MIN_CBS_S;
995 for (i = 1; i < QM_QOS_TYPICAL_NUM; i++) {
996 if (ir >= typical_qos_val[i - 1] && ir < typical_qos_val[i])
997 return typical_qos_cbs_s[i - 1];
1000 return typical_qos_cbs_s[QM_QOS_TYPICAL_NUM - 1];
1003 static int qm_get_shaper_para(u32 ir, struct qm_shaper_factor *factor)
1005 u32 cir_b, cir_u, cir_s, ir_calc;
1008 factor->cbs_s = acc_shaper_calc_cbs_s(ir);
1010 for (cir_b = QM_QOS_MIN_CIR_B; cir_b <= QM_QOS_MAX_CIR_B; cir_b++) {
1011 for (cir_u = 0; cir_u <= QM_QOS_MAX_CIR_U; cir_u++) {
1012 for (cir_s = 0; cir_s <= QM_QOS_MAX_CIR_S; cir_s++) {
1013 /** the formula is changed to:
1014 * IR_b * (2 ^ IR_u) * DIVISOR_CLK
1015 * IR(Mbps) = -------------------------
1018 ir_calc = acc_shaper_para_calc(cir_b, cir_u,
1020 error_rate = QM_QOS_EXPAND_RATE * (u32)abs(ir_calc - ir) / ir;
1021 if (error_rate <= QM_QOS_MIN_ERROR_RATE) {
1022 factor->cir_b = cir_b;
1023 factor->cir_u = cir_u;
1024 factor->cir_s = cir_s;
1035 static void qm_vft_data_cfg(struct hisi_qm *qm, enum vft_type type, u32 base,
1036 u32 number, struct qm_shaper_factor *factor)
1043 if (qm->ver == QM_HW_V1) {
1044 tmp = QM_SQC_VFT_BUF_SIZE |
1045 QM_SQC_VFT_SQC_SIZE |
1046 QM_SQC_VFT_INDEX_NUMBER |
1048 (u64)base << QM_SQC_VFT_START_SQN_SHIFT;
1050 tmp = (u64)base << QM_SQC_VFT_START_SQN_SHIFT |
1052 (u64)(number - 1) << QM_SQC_VFT_SQN_SHIFT;
1056 if (qm->ver == QM_HW_V1) {
1057 tmp = QM_CQC_VFT_BUF_SIZE |
1058 QM_CQC_VFT_SQC_SIZE |
1059 QM_CQC_VFT_INDEX_NUMBER |
1062 tmp = QM_CQC_VFT_VALID;
1066 if (qm->ver >= QM_HW_V3) {
1067 tmp = factor->cir_b |
1068 (factor->cir_u << QM_SHAPER_FACTOR_CIR_U_SHIFT) |
1069 (factor->cir_s << QM_SHAPER_FACTOR_CIR_S_SHIFT) |
1070 (QM_SHAPER_CBS_B << QM_SHAPER_FACTOR_CBS_B_SHIFT) |
1071 (factor->cbs_s << QM_SHAPER_FACTOR_CBS_S_SHIFT);
1077 writel(lower_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_L);
1078 writel(upper_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_H);
1081 static int qm_set_vft_common(struct hisi_qm *qm, enum vft_type type,
1082 u32 fun_num, u32 base, u32 number)
1084 struct qm_shaper_factor *factor = &qm->factor[fun_num];
1088 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
1089 val & BIT(0), POLL_PERIOD,
1094 writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR);
1095 writel(type, qm->io_base + QM_VFT_CFG_TYPE);
1096 if (type == SHAPER_VFT)
1097 fun_num |= base << QM_SHAPER_VFT_OFFSET;
1099 writel(fun_num, qm->io_base + QM_VFT_CFG);
1101 qm_vft_data_cfg(qm, type, base, number, factor);
1103 writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
1104 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
1106 return readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
1107 val & BIT(0), POLL_PERIOD,
1111 static int qm_shaper_init_vft(struct hisi_qm *qm, u32 fun_num)
1115 qm->factor[fun_num].func_qos = QM_QOS_MAX_VAL;
1116 ret = qm_get_shaper_para(QM_QOS_MAX_VAL * QM_QOS_RATE, &qm->factor[fun_num]);
1118 dev_err(&qm->pdev->dev, "failed to calculate shaper parameter!\n");
1121 writel(qm->type_rate, qm->io_base + QM_SHAPER_CFG);
1122 for (i = ALG_TYPE_0; i <= ALG_TYPE_1; i++) {
1123 /* The base number of queue reuse for different alg type */
1124 ret = qm_set_vft_common(qm, SHAPER_VFT, fun_num, i, 1);
1132 /* The config should be conducted after qm_dev_mem_reset() */
1133 static int qm_set_sqc_cqc_vft(struct hisi_qm *qm, u32 fun_num, u32 base,
1138 for (i = SQC_VFT; i <= CQC_VFT; i++) {
1139 ret = qm_set_vft_common(qm, i, fun_num, base, number);
1144 /* init default shaper qos val */
1145 if (qm->ver >= QM_HW_V3) {
1146 ret = qm_shaper_init_vft(qm, fun_num);
1153 for (i = SQC_VFT; i <= CQC_VFT; i++) {
1154 ret = qm_set_vft_common(qm, i, fun_num, 0, 0);
1161 static int qm_get_vft_v2(struct hisi_qm *qm, u32 *base, u32 *number)
1166 ret = qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1);
1170 sqc_vft = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
1171 ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
1172 *base = QM_SQC_VFT_BASE_MASK_V2 & (sqc_vft >> QM_SQC_VFT_BASE_SHIFT_V2);
1173 *number = (QM_SQC_VFT_NUM_MASK_v2 &
1174 (sqc_vft >> QM_SQC_VFT_NUM_SHIFT_V2)) + 1;
1179 static int qm_get_vf_qp_num(struct hisi_qm *qm, u32 fun_num)
1181 u32 remain_q_num, vfq_num;
1182 u32 num_vfs = qm->vfs_num;
1184 vfq_num = (qm->ctrl_qp_num - qm->qp_num) / num_vfs;
1185 if (vfq_num >= qm->max_qp_num)
1186 return qm->max_qp_num;
1188 remain_q_num = (qm->ctrl_qp_num - qm->qp_num) % num_vfs;
1189 if (vfq_num + remain_q_num <= qm->max_qp_num)
1190 return fun_num == num_vfs ? vfq_num + remain_q_num : vfq_num;
1193 * if vfq_num + remain_q_num > max_qp_num, the last VFs,
1194 * each with one more queue.
1196 return fun_num + remain_q_num > num_vfs ? vfq_num + 1 : vfq_num;
1199 static struct hisi_qm *file_to_qm(struct debugfs_file *file)
1201 struct qm_debug *debug = file->debug;
1203 return container_of(debug, struct hisi_qm, debug);
1206 static u32 current_q_read(struct hisi_qm *qm)
1208 return readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) >> QM_DFX_QN_SHIFT;
1211 static int current_q_write(struct hisi_qm *qm, u32 val)
1215 if (val >= qm->debug.curr_qm_qp_num)
1218 tmp = val << QM_DFX_QN_SHIFT |
1219 (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_FUN_MASK);
1220 writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
1222 tmp = val << QM_DFX_QN_SHIFT |
1223 (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_FUN_MASK);
1224 writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
1229 static u32 clear_enable_read(struct hisi_qm *qm)
1231 return readl(qm->io_base + QM_DFX_CNT_CLR_CE);
1234 /* rd_clr_ctrl 1 enable read clear, otherwise 0 disable it */
1235 static int clear_enable_write(struct hisi_qm *qm, u32 rd_clr_ctrl)
1237 if (rd_clr_ctrl > 1)
1240 writel(rd_clr_ctrl, qm->io_base + QM_DFX_CNT_CLR_CE);
1245 static u32 current_qm_read(struct hisi_qm *qm)
1247 return readl(qm->io_base + QM_DFX_MB_CNT_VF);
1250 static int current_qm_write(struct hisi_qm *qm, u32 val)
1254 if (val > qm->vfs_num)
1257 /* According PF or VF Dev ID to calculation curr_qm_qp_num and store */
1259 qm->debug.curr_qm_qp_num = qm->qp_num;
1261 qm->debug.curr_qm_qp_num = qm_get_vf_qp_num(qm, val);
1263 writel(val, qm->io_base + QM_DFX_MB_CNT_VF);
1264 writel(val, qm->io_base + QM_DFX_DB_CNT_VF);
1267 (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK);
1268 writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
1271 (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK);
1272 writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
1277 static ssize_t qm_debug_read(struct file *filp, char __user *buf,
1278 size_t count, loff_t *pos)
1280 struct debugfs_file *file = filp->private_data;
1281 enum qm_debug_file index = file->index;
1282 struct hisi_qm *qm = file_to_qm(file);
1283 char tbuf[QM_DBG_TMP_BUF_LEN];
1287 ret = hisi_qm_get_dfx_access(qm);
1291 mutex_lock(&file->lock);
1294 val = current_qm_read(qm);
1297 val = current_q_read(qm);
1300 val = clear_enable_read(qm);
1305 mutex_unlock(&file->lock);
1307 hisi_qm_put_dfx_access(qm);
1308 ret = scnprintf(tbuf, QM_DBG_TMP_BUF_LEN, "%u\n", val);
1309 return simple_read_from_buffer(buf, count, pos, tbuf, ret);
1312 mutex_unlock(&file->lock);
1313 hisi_qm_put_dfx_access(qm);
1317 static ssize_t qm_debug_write(struct file *filp, const char __user *buf,
1318 size_t count, loff_t *pos)
1320 struct debugfs_file *file = filp->private_data;
1321 enum qm_debug_file index = file->index;
1322 struct hisi_qm *qm = file_to_qm(file);
1324 char tbuf[QM_DBG_TMP_BUF_LEN];
1330 if (count >= QM_DBG_TMP_BUF_LEN)
1333 len = simple_write_to_buffer(tbuf, QM_DBG_TMP_BUF_LEN - 1, pos, buf,
1339 if (kstrtoul(tbuf, 0, &val))
1342 ret = hisi_qm_get_dfx_access(qm);
1346 mutex_lock(&file->lock);
1349 ret = current_qm_write(qm, val);
1352 ret = current_q_write(qm, val);
1355 ret = clear_enable_write(qm, val);
1360 mutex_unlock(&file->lock);
1362 hisi_qm_put_dfx_access(qm);
1370 static const struct file_operations qm_debug_fops = {
1371 .owner = THIS_MODULE,
1372 .open = simple_open,
1373 .read = qm_debug_read,
1374 .write = qm_debug_write,
1377 #define CNT_CYC_REGS_NUM 10
1378 static const struct debugfs_reg32 qm_dfx_regs[] = {
1379 /* XXX_CNT are reading clear register */
1380 {"QM_ECC_1BIT_CNT ", 0x104000ull},
1381 {"QM_ECC_MBIT_CNT ", 0x104008ull},
1382 {"QM_DFX_MB_CNT ", 0x104018ull},
1383 {"QM_DFX_DB_CNT ", 0x104028ull},
1384 {"QM_DFX_SQE_CNT ", 0x104038ull},
1385 {"QM_DFX_CQE_CNT ", 0x104048ull},
1386 {"QM_DFX_SEND_SQE_TO_ACC_CNT ", 0x104050ull},
1387 {"QM_DFX_WB_SQE_FROM_ACC_CNT ", 0x104058ull},
1388 {"QM_DFX_ACC_FINISH_CNT ", 0x104060ull},
1389 {"QM_DFX_CQE_ERR_CNT ", 0x1040b4ull},
1390 {"QM_DFX_FUNS_ACTIVE_ST ", 0x200ull},
1391 {"QM_ECC_1BIT_INF ", 0x104004ull},
1392 {"QM_ECC_MBIT_INF ", 0x10400cull},
1393 {"QM_DFX_ACC_RDY_VLD0 ", 0x1040a0ull},
1394 {"QM_DFX_ACC_RDY_VLD1 ", 0x1040a4ull},
1395 {"QM_DFX_AXI_RDY_VLD ", 0x1040a8ull},
1396 {"QM_DFX_FF_ST0 ", 0x1040c8ull},
1397 {"QM_DFX_FF_ST1 ", 0x1040ccull},
1398 {"QM_DFX_FF_ST2 ", 0x1040d0ull},
1399 {"QM_DFX_FF_ST3 ", 0x1040d4ull},
1400 {"QM_DFX_FF_ST4 ", 0x1040d8ull},
1401 {"QM_DFX_FF_ST5 ", 0x1040dcull},
1402 {"QM_DFX_FF_ST6 ", 0x1040e0ull},
1403 {"QM_IN_IDLE_ST ", 0x1040e4ull},
1406 static const struct debugfs_reg32 qm_vf_dfx_regs[] = {
1407 {"QM_DFX_FUNS_ACTIVE_ST ", 0x200ull},
1411 * hisi_qm_regs_dump() - Dump registers's value.
1412 * @s: debugfs file handle.
1413 * @regset: accelerator registers information.
1415 * Dump accelerator registers.
1417 void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset)
1419 struct pci_dev *pdev = to_pci_dev(regset->dev);
1420 struct hisi_qm *qm = pci_get_drvdata(pdev);
1421 const struct debugfs_reg32 *regs = regset->regs;
1422 int regs_len = regset->nregs;
1426 ret = hisi_qm_get_dfx_access(qm);
1430 for (i = 0; i < regs_len; i++) {
1431 val = readl(regset->base + regs[i].offset);
1432 seq_printf(s, "%s= 0x%08x\n", regs[i].name, val);
1435 hisi_qm_put_dfx_access(qm);
1437 EXPORT_SYMBOL_GPL(hisi_qm_regs_dump);
1439 static int qm_regs_show(struct seq_file *s, void *unused)
1441 struct hisi_qm *qm = s->private;
1442 struct debugfs_regset32 regset;
1444 if (qm->fun_type == QM_HW_PF) {
1445 regset.regs = qm_dfx_regs;
1446 regset.nregs = ARRAY_SIZE(qm_dfx_regs);
1448 regset.regs = qm_vf_dfx_regs;
1449 regset.nregs = ARRAY_SIZE(qm_vf_dfx_regs);
1452 regset.base = qm->io_base;
1453 regset.dev = &qm->pdev->dev;
1455 hisi_qm_regs_dump(s, ®set);
1460 DEFINE_SHOW_ATTRIBUTE(qm_regs);
1462 static ssize_t qm_cmd_read(struct file *filp, char __user *buffer,
1463 size_t count, loff_t *pos)
1465 char buf[QM_DBG_READ_LEN];
1468 len = scnprintf(buf, QM_DBG_READ_LEN, "%s\n",
1469 "Please echo help to cmd to get help information");
1471 return simple_read_from_buffer(buffer, count, pos, buf, len);
1474 static void *qm_ctx_alloc(struct hisi_qm *qm, size_t ctx_size,
1475 dma_addr_t *dma_addr)
1477 struct device *dev = &qm->pdev->dev;
1480 ctx_addr = kzalloc(ctx_size, GFP_KERNEL);
1482 return ERR_PTR(-ENOMEM);
1484 *dma_addr = dma_map_single(dev, ctx_addr, ctx_size, DMA_FROM_DEVICE);
1485 if (dma_mapping_error(dev, *dma_addr)) {
1486 dev_err(dev, "DMA mapping error!\n");
1488 return ERR_PTR(-ENOMEM);
1494 static void qm_ctx_free(struct hisi_qm *qm, size_t ctx_size,
1495 const void *ctx_addr, dma_addr_t *dma_addr)
1497 struct device *dev = &qm->pdev->dev;
1499 dma_unmap_single(dev, *dma_addr, ctx_size, DMA_FROM_DEVICE);
1503 static int dump_show(struct hisi_qm *qm, void *info,
1504 unsigned int info_size, char *info_name)
1506 struct device *dev = &qm->pdev->dev;
1507 u8 *info_buf, *info_curr = info;
1509 #define BYTE_PER_DW 4
1511 info_buf = kzalloc(info_size, GFP_KERNEL);
1515 for (i = 0; i < info_size; i++, info_curr++) {
1516 if (i % BYTE_PER_DW == 0)
1517 info_buf[i + 3UL] = *info_curr;
1518 else if (i % BYTE_PER_DW == 1)
1519 info_buf[i + 1UL] = *info_curr;
1520 else if (i % BYTE_PER_DW == 2)
1521 info_buf[i - 1] = *info_curr;
1522 else if (i % BYTE_PER_DW == 3)
1523 info_buf[i - 3] = *info_curr;
1526 dev_info(dev, "%s DUMP\n", info_name);
1527 for (i = 0; i < info_size; i += BYTE_PER_DW) {
1528 pr_info("DW%u: %02X%02X %02X%02X\n", i / BYTE_PER_DW,
1529 info_buf[i], info_buf[i + 1UL],
1530 info_buf[i + 2UL], info_buf[i + 3UL]);
1538 static int qm_dump_sqc_raw(struct hisi_qm *qm, dma_addr_t dma_addr, u16 qp_id)
1540 return qm_mb(qm, QM_MB_CMD_SQC, dma_addr, qp_id, 1);
1543 static int qm_dump_cqc_raw(struct hisi_qm *qm, dma_addr_t dma_addr, u16 qp_id)
1545 return qm_mb(qm, QM_MB_CMD_CQC, dma_addr, qp_id, 1);
1548 static int qm_sqc_dump(struct hisi_qm *qm, const char *s)
1550 struct device *dev = &qm->pdev->dev;
1551 struct qm_sqc *sqc, *sqc_curr;
1559 ret = kstrtou32(s, 0, &qp_id);
1560 if (ret || qp_id >= qm->qp_num) {
1561 dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1);
1565 sqc = qm_ctx_alloc(qm, sizeof(*sqc), &sqc_dma);
1567 return PTR_ERR(sqc);
1569 ret = qm_dump_sqc_raw(qm, sqc_dma, qp_id);
1571 down_read(&qm->qps_lock);
1573 sqc_curr = qm->sqc + qp_id;
1575 ret = dump_show(qm, sqc_curr, sizeof(*sqc),
1578 dev_info(dev, "Show soft sqc failed!\n");
1580 up_read(&qm->qps_lock);
1585 ret = dump_show(qm, sqc, sizeof(*sqc), "SQC");
1587 dev_info(dev, "Show hw sqc failed!\n");
1590 qm_ctx_free(qm, sizeof(*sqc), sqc, &sqc_dma);
1594 static int qm_cqc_dump(struct hisi_qm *qm, const char *s)
1596 struct device *dev = &qm->pdev->dev;
1597 struct qm_cqc *cqc, *cqc_curr;
1605 ret = kstrtou32(s, 0, &qp_id);
1606 if (ret || qp_id >= qm->qp_num) {
1607 dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1);
1611 cqc = qm_ctx_alloc(qm, sizeof(*cqc), &cqc_dma);
1613 return PTR_ERR(cqc);
1615 ret = qm_dump_cqc_raw(qm, cqc_dma, qp_id);
1617 down_read(&qm->qps_lock);
1619 cqc_curr = qm->cqc + qp_id;
1621 ret = dump_show(qm, cqc_curr, sizeof(*cqc),
1624 dev_info(dev, "Show soft cqc failed!\n");
1626 up_read(&qm->qps_lock);
1631 ret = dump_show(qm, cqc, sizeof(*cqc), "CQC");
1633 dev_info(dev, "Show hw cqc failed!\n");
1636 qm_ctx_free(qm, sizeof(*cqc), cqc, &cqc_dma);
1640 static int qm_eqc_aeqc_dump(struct hisi_qm *qm, char *s, size_t size,
1641 int cmd, char *name)
1643 struct device *dev = &qm->pdev->dev;
1644 dma_addr_t xeqc_dma;
1648 if (strsep(&s, " ")) {
1649 dev_err(dev, "Please do not input extra characters!\n");
1653 xeqc = qm_ctx_alloc(qm, size, &xeqc_dma);
1655 return PTR_ERR(xeqc);
1657 ret = qm_mb(qm, cmd, xeqc_dma, 0, 1);
1661 ret = dump_show(qm, xeqc, size, name);
1663 dev_info(dev, "Show hw %s failed!\n", name);
1666 qm_ctx_free(qm, size, xeqc, &xeqc_dma);
1670 static int q_dump_param_parse(struct hisi_qm *qm, char *s,
1671 u32 *e_id, u32 *q_id)
1673 struct device *dev = &qm->pdev->dev;
1674 unsigned int qp_num = qm->qp_num;
1678 presult = strsep(&s, " ");
1680 dev_err(dev, "Please input qp number!\n");
1684 ret = kstrtou32(presult, 0, q_id);
1685 if (ret || *q_id >= qp_num) {
1686 dev_err(dev, "Please input qp num (0-%u)", qp_num - 1);
1690 presult = strsep(&s, " ");
1692 dev_err(dev, "Please input sqe number!\n");
1696 ret = kstrtou32(presult, 0, e_id);
1697 if (ret || *e_id >= QM_Q_DEPTH) {
1698 dev_err(dev, "Please input sqe num (0-%d)", QM_Q_DEPTH - 1);
1702 if (strsep(&s, " ")) {
1703 dev_err(dev, "Please do not input extra characters!\n");
1710 static int qm_sq_dump(struct hisi_qm *qm, char *s)
1712 struct device *dev = &qm->pdev->dev;
1713 void *sqe, *sqe_curr;
1718 ret = q_dump_param_parse(qm, s, &sqe_id, &qp_id);
1722 sqe = kzalloc(qm->sqe_size * QM_Q_DEPTH, GFP_KERNEL);
1726 qp = &qm->qp_array[qp_id];
1727 memcpy(sqe, qp->sqe, qm->sqe_size * QM_Q_DEPTH);
1728 sqe_curr = sqe + (u32)(sqe_id * qm->sqe_size);
1729 memset(sqe_curr + qm->debug.sqe_mask_offset, QM_SQE_ADDR_MASK,
1730 qm->debug.sqe_mask_len);
1732 ret = dump_show(qm, sqe_curr, qm->sqe_size, "SQE");
1734 dev_info(dev, "Show sqe failed!\n");
1741 static int qm_cq_dump(struct hisi_qm *qm, char *s)
1743 struct device *dev = &qm->pdev->dev;
1744 struct qm_cqe *cqe_curr;
1749 ret = q_dump_param_parse(qm, s, &cqe_id, &qp_id);
1753 qp = &qm->qp_array[qp_id];
1754 cqe_curr = qp->cqe + cqe_id;
1755 ret = dump_show(qm, cqe_curr, sizeof(struct qm_cqe), "CQE");
1757 dev_info(dev, "Show cqe failed!\n");
1762 static int qm_eq_aeq_dump(struct hisi_qm *qm, const char *s,
1763 size_t size, char *name)
1765 struct device *dev = &qm->pdev->dev;
1773 ret = kstrtou32(s, 0, &xeqe_id);
1777 if (!strcmp(name, "EQE") && xeqe_id >= QM_EQ_DEPTH) {
1778 dev_err(dev, "Please input eqe num (0-%d)", QM_EQ_DEPTH - 1);
1780 } else if (!strcmp(name, "AEQE") && xeqe_id >= QM_Q_DEPTH) {
1781 dev_err(dev, "Please input aeqe num (0-%d)", QM_Q_DEPTH - 1);
1785 down_read(&qm->qps_lock);
1787 if (qm->eqe && !strcmp(name, "EQE")) {
1788 xeqe = qm->eqe + xeqe_id;
1789 } else if (qm->aeqe && !strcmp(name, "AEQE")) {
1790 xeqe = qm->aeqe + xeqe_id;
1796 ret = dump_show(qm, xeqe, size, name);
1798 dev_info(dev, "Show %s failed!\n", name);
1801 up_read(&qm->qps_lock);
1805 static int qm_dbg_help(struct hisi_qm *qm, char *s)
1807 struct device *dev = &qm->pdev->dev;
1809 if (strsep(&s, " ")) {
1810 dev_err(dev, "Please do not input extra characters!\n");
1814 dev_info(dev, "available commands:\n");
1815 dev_info(dev, "sqc <num>\n");
1816 dev_info(dev, "cqc <num>\n");
1817 dev_info(dev, "eqc\n");
1818 dev_info(dev, "aeqc\n");
1819 dev_info(dev, "sq <num> <e>\n");
1820 dev_info(dev, "cq <num> <e>\n");
1821 dev_info(dev, "eq <e>\n");
1822 dev_info(dev, "aeq <e>\n");
1827 static int qm_cmd_write_dump(struct hisi_qm *qm, const char *cmd_buf)
1829 struct device *dev = &qm->pdev->dev;
1830 char *presult, *s, *s_tmp;
1833 s = kstrdup(cmd_buf, GFP_KERNEL);
1838 presult = strsep(&s, " ");
1841 goto err_buffer_free;
1844 if (!strcmp(presult, "sqc"))
1845 ret = qm_sqc_dump(qm, s);
1846 else if (!strcmp(presult, "cqc"))
1847 ret = qm_cqc_dump(qm, s);
1848 else if (!strcmp(presult, "eqc"))
1849 ret = qm_eqc_aeqc_dump(qm, s, sizeof(struct qm_eqc),
1850 QM_MB_CMD_EQC, "EQC");
1851 else if (!strcmp(presult, "aeqc"))
1852 ret = qm_eqc_aeqc_dump(qm, s, sizeof(struct qm_aeqc),
1853 QM_MB_CMD_AEQC, "AEQC");
1854 else if (!strcmp(presult, "sq"))
1855 ret = qm_sq_dump(qm, s);
1856 else if (!strcmp(presult, "cq"))
1857 ret = qm_cq_dump(qm, s);
1858 else if (!strcmp(presult, "eq"))
1859 ret = qm_eq_aeq_dump(qm, s, sizeof(struct qm_eqe), "EQE");
1860 else if (!strcmp(presult, "aeq"))
1861 ret = qm_eq_aeq_dump(qm, s, sizeof(struct qm_aeqe), "AEQE");
1862 else if (!strcmp(presult, "help"))
1863 ret = qm_dbg_help(qm, s);
1868 dev_info(dev, "Please echo help\n");
1876 static ssize_t qm_cmd_write(struct file *filp, const char __user *buffer,
1877 size_t count, loff_t *pos)
1879 struct hisi_qm *qm = filp->private_data;
1880 char *cmd_buf, *cmd_buf_tmp;
1886 ret = hisi_qm_get_dfx_access(qm);
1890 /* Judge if the instance is being reset. */
1891 if (unlikely(atomic_read(&qm->status.flags) == QM_STOP))
1894 if (count > QM_DBG_WRITE_LEN) {
1896 goto put_dfx_access;
1899 cmd_buf = memdup_user_nul(buffer, count);
1900 if (IS_ERR(cmd_buf)) {
1901 ret = PTR_ERR(cmd_buf);
1902 goto put_dfx_access;
1905 cmd_buf_tmp = strchr(cmd_buf, '\n');
1907 *cmd_buf_tmp = '\0';
1908 count = cmd_buf_tmp - cmd_buf + 1;
1911 ret = qm_cmd_write_dump(qm, cmd_buf);
1914 goto put_dfx_access;
1922 hisi_qm_put_dfx_access(qm);
1926 static const struct file_operations qm_cmd_fops = {
1927 .owner = THIS_MODULE,
1928 .open = simple_open,
1929 .read = qm_cmd_read,
1930 .write = qm_cmd_write,
1933 static void qm_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir,
1934 enum qm_debug_file index)
1936 struct debugfs_file *file = qm->debug.files + index;
1938 debugfs_create_file(qm_debug_file_name[index], 0600, dir, file,
1941 file->index = index;
1942 mutex_init(&file->lock);
1943 file->debug = &qm->debug;
1946 static void qm_hw_error_init_v1(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe)
1948 writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
1951 static void qm_hw_error_cfg(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe)
1953 qm->error_mask = ce | nfe | fe;
1954 /* clear QM hw residual error source */
1955 writel(QM_ABNORMAL_INT_SOURCE_CLR,
1956 qm->io_base + QM_ABNORMAL_INT_SOURCE);
1958 /* configure error type */
1959 writel(ce, qm->io_base + QM_RAS_CE_ENABLE);
1960 writel(QM_RAS_CE_TIMES_PER_IRQ, qm->io_base + QM_RAS_CE_THRESHOLD);
1961 writel(nfe, qm->io_base + QM_RAS_NFE_ENABLE);
1962 writel(fe, qm->io_base + QM_RAS_FE_ENABLE);
1965 static void qm_hw_error_init_v2(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe)
1967 u32 irq_enable = ce | nfe | fe;
1968 u32 irq_unmask = ~irq_enable;
1970 qm_hw_error_cfg(qm, ce, nfe, fe);
1972 irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
1973 writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);
1976 static void qm_hw_error_uninit_v2(struct hisi_qm *qm)
1978 writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
1981 static void qm_hw_error_init_v3(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe)
1983 u32 irq_enable = ce | nfe | fe;
1984 u32 irq_unmask = ~irq_enable;
1986 qm_hw_error_cfg(qm, ce, nfe, fe);
1988 /* enable close master ooo when hardware error happened */
1989 writel(nfe & (~QM_DB_RANDOM_INVALID), qm->io_base + QM_OOO_SHUTDOWN_SEL);
1991 irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
1992 writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);
1995 static void qm_hw_error_uninit_v3(struct hisi_qm *qm)
1997 writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
1999 /* disable close master ooo when hardware error happened */
2000 writel(0x0, qm->io_base + QM_OOO_SHUTDOWN_SEL);
2003 static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status)
2005 const struct hisi_qm_hw_error *err;
2006 struct device *dev = &qm->pdev->dev;
2007 u32 reg_val, type, vf_num;
2010 for (i = 0; i < ARRAY_SIZE(qm_hw_error); i++) {
2011 err = &qm_hw_error[i];
2012 if (!(err->int_msk & error_status))
2015 dev_err(dev, "%s [error status=0x%x] found\n",
2016 err->msg, err->int_msk);
2018 if (err->int_msk & QM_DB_TIMEOUT) {
2019 reg_val = readl(qm->io_base + QM_ABNORMAL_INF01);
2020 type = (reg_val & QM_DB_TIMEOUT_TYPE) >>
2021 QM_DB_TIMEOUT_TYPE_SHIFT;
2022 vf_num = reg_val & QM_DB_TIMEOUT_VF;
2023 dev_err(dev, "qm %s doorbell timeout in function %u\n",
2024 qm_db_timeout[type], vf_num);
2025 } else if (err->int_msk & QM_OF_FIFO_OF) {
2026 reg_val = readl(qm->io_base + QM_ABNORMAL_INF00);
2027 type = (reg_val & QM_FIFO_OVERFLOW_TYPE) >>
2028 QM_FIFO_OVERFLOW_TYPE_SHIFT;
2029 vf_num = reg_val & QM_FIFO_OVERFLOW_VF;
2031 if (type < ARRAY_SIZE(qm_fifo_overflow))
2032 dev_err(dev, "qm %s fifo overflow in function %u\n",
2033 qm_fifo_overflow[type], vf_num);
2035 dev_err(dev, "unknown error type\n");
2040 static enum acc_err_result qm_hw_error_handle_v2(struct hisi_qm *qm)
2042 u32 error_status, tmp, val;
2045 tmp = readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
2046 error_status = qm->error_mask & tmp;
2049 if (error_status & QM_ECC_MBIT)
2050 qm->err_status.is_qm_ecc_mbit = true;
2052 qm_log_hw_error(qm, error_status);
2053 val = error_status | QM_DB_RANDOM_INVALID | QM_BASE_CE;
2054 /* ce error does not need to be reset */
2055 if (val == (QM_DB_RANDOM_INVALID | QM_BASE_CE)) {
2056 writel(error_status, qm->io_base +
2057 QM_ABNORMAL_INT_SOURCE);
2058 writel(qm->err_info.nfe,
2059 qm->io_base + QM_RAS_NFE_ENABLE);
2060 return ACC_ERR_RECOVERED;
2063 return ACC_ERR_NEED_RESET;
2066 return ACC_ERR_RECOVERED;
2069 static u32 qm_get_hw_error_status(struct hisi_qm *qm)
2071 return readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
2074 static u32 qm_get_dev_err_status(struct hisi_qm *qm)
2076 return qm->err_ini->get_dev_hw_err_status(qm);
2079 /* Check if the error causes the master ooo block */
2080 static int qm_check_dev_error(struct hisi_qm *qm)
2084 if (qm->fun_type == QM_HW_VF)
2087 val = qm_get_hw_error_status(qm);
2088 dev_val = qm_get_dev_err_status(qm);
2090 if (qm->ver < QM_HW_V3)
2091 return (val & QM_ECC_MBIT) ||
2092 (dev_val & qm->err_info.ecc_2bits_mask);
2094 return (val & readl(qm->io_base + QM_OOO_SHUTDOWN_SEL)) ||
2095 (dev_val & (~qm->err_info.dev_ce_mask));
2098 static int qm_get_mb_cmd(struct hisi_qm *qm, u64 *msg, u16 fun_num)
2100 struct qm_mailbox mailbox;
2103 qm_mb_pre_init(&mailbox, QM_MB_CMD_DST, 0, fun_num, 0);
2104 mutex_lock(&qm->mailbox_lock);
2105 ret = qm_mb_nolock(qm, &mailbox);
2109 *msg = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
2110 ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
2113 mutex_unlock(&qm->mailbox_lock);
2117 static void qm_clear_cmd_interrupt(struct hisi_qm *qm, u64 vf_mask)
2121 if (qm->fun_type == QM_HW_PF)
2122 writeq(vf_mask, qm->io_base + QM_IFC_INT_SOURCE_P);
2124 val = readl(qm->io_base + QM_IFC_INT_SOURCE_V);
2125 val |= QM_IFC_INT_SOURCE_MASK;
2126 writel(val, qm->io_base + QM_IFC_INT_SOURCE_V);
2129 static void qm_handle_vf_msg(struct hisi_qm *qm, u32 vf_id)
2131 struct device *dev = &qm->pdev->dev;
2136 ret = qm_get_mb_cmd(qm, &msg, vf_id);
2138 dev_err(dev, "failed to get msg from VF(%u)!\n", vf_id);
2142 cmd = msg & QM_MB_CMD_DATA_MASK;
2144 case QM_VF_PREPARE_FAIL:
2145 dev_err(dev, "failed to stop VF(%u)!\n", vf_id);
2147 case QM_VF_START_FAIL:
2148 dev_err(dev, "failed to start VF(%u)!\n", vf_id);
2150 case QM_VF_PREPARE_DONE:
2151 case QM_VF_START_DONE:
2154 dev_err(dev, "unsupported cmd %u sent by VF(%u)!\n", cmd, vf_id);
2159 static int qm_wait_vf_prepare_finish(struct hisi_qm *qm)
2161 struct device *dev = &qm->pdev->dev;
2162 u32 vfs_num = qm->vfs_num;
2168 if (!qm->vfs_num || qm->ver < QM_HW_V3)
2172 val = readq(qm->io_base + QM_IFC_INT_SOURCE_P);
2173 /* All VFs send command to PF, break */
2174 if ((val & GENMASK(vfs_num, 1)) == GENMASK(vfs_num, 1))
2177 if (++cnt > QM_MAX_PF_WAIT_COUNT) {
2182 msleep(QM_WAIT_DST_ACK);
2185 /* PF check VFs msg */
2186 for (i = 1; i <= vfs_num; i++) {
2188 qm_handle_vf_msg(qm, i);
2190 dev_err(dev, "VF(%u) not ping PF!\n", i);
2193 /* PF clear interrupt to ack VFs */
2194 qm_clear_cmd_interrupt(qm, val);
2199 static void qm_trigger_vf_interrupt(struct hisi_qm *qm, u32 fun_num)
2203 val = readl(qm->io_base + QM_IFC_INT_CFG);
2204 val &= ~QM_IFC_SEND_ALL_VFS;
2206 writel(val, qm->io_base + QM_IFC_INT_CFG);
2208 val = readl(qm->io_base + QM_IFC_INT_SET_P);
2209 val |= QM_IFC_INT_SET_MASK;
2210 writel(val, qm->io_base + QM_IFC_INT_SET_P);
2213 static void qm_trigger_pf_interrupt(struct hisi_qm *qm)
2217 val = readl(qm->io_base + QM_IFC_INT_SET_V);
2218 val |= QM_IFC_INT_SET_MASK;
2219 writel(val, qm->io_base + QM_IFC_INT_SET_V);
2222 static int qm_ping_single_vf(struct hisi_qm *qm, u64 cmd, u32 fun_num)
2224 struct device *dev = &qm->pdev->dev;
2225 struct qm_mailbox mailbox;
2230 qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, fun_num, 0);
2231 mutex_lock(&qm->mailbox_lock);
2232 ret = qm_mb_nolock(qm, &mailbox);
2234 dev_err(dev, "failed to send command to vf(%u)!\n", fun_num);
2238 qm_trigger_vf_interrupt(qm, fun_num);
2240 msleep(QM_WAIT_DST_ACK);
2241 val = readq(qm->io_base + QM_IFC_READY_STATUS);
2242 /* if VF respond, PF notifies VF successfully. */
2243 if (!(val & BIT(fun_num)))
2246 if (++cnt > QM_MAX_PF_WAIT_COUNT) {
2247 dev_err(dev, "failed to get response from VF(%u)!\n", fun_num);
2254 mutex_unlock(&qm->mailbox_lock);
2258 static int qm_ping_all_vfs(struct hisi_qm *qm, u64 cmd)
2260 struct device *dev = &qm->pdev->dev;
2261 u32 vfs_num = qm->vfs_num;
2262 struct qm_mailbox mailbox;
2268 qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, QM_MB_PING_ALL_VFS, 0);
2269 mutex_lock(&qm->mailbox_lock);
2270 /* PF sends command to all VFs by mailbox */
2271 ret = qm_mb_nolock(qm, &mailbox);
2273 dev_err(dev, "failed to send command to VFs!\n");
2274 mutex_unlock(&qm->mailbox_lock);
2278 qm_trigger_vf_interrupt(qm, QM_IFC_SEND_ALL_VFS);
2280 msleep(QM_WAIT_DST_ACK);
2281 val = readq(qm->io_base + QM_IFC_READY_STATUS);
2282 /* If all VFs acked, PF notifies VFs successfully. */
2283 if (!(val & GENMASK(vfs_num, 1))) {
2284 mutex_unlock(&qm->mailbox_lock);
2288 if (++cnt > QM_MAX_PF_WAIT_COUNT)
2292 mutex_unlock(&qm->mailbox_lock);
2294 /* Check which vf respond timeout. */
2295 for (i = 1; i <= vfs_num; i++) {
2297 dev_err(dev, "failed to get response from VF(%u)!\n", i);
2303 static int qm_ping_pf(struct hisi_qm *qm, u64 cmd)
2305 struct qm_mailbox mailbox;
2310 qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, 0, 0);
2311 mutex_lock(&qm->mailbox_lock);
2312 ret = qm_mb_nolock(qm, &mailbox);
2314 dev_err(&qm->pdev->dev, "failed to send command to PF!\n");
2318 qm_trigger_pf_interrupt(qm);
2319 /* Waiting for PF response */
2321 msleep(QM_WAIT_DST_ACK);
2322 val = readl(qm->io_base + QM_IFC_INT_SET_V);
2323 if (!(val & QM_IFC_INT_STATUS_MASK))
2326 if (++cnt > QM_MAX_VF_WAIT_COUNT) {
2333 mutex_unlock(&qm->mailbox_lock);
2337 static int qm_stop_qp(struct hisi_qp *qp)
2339 return qm_mb(qp->qm, QM_MB_CMD_STOP_QP, 0, qp->qp_id, 0);
2342 static int qm_set_msi(struct hisi_qm *qm, bool set)
2344 struct pci_dev *pdev = qm->pdev;
2347 pci_write_config_dword(pdev, pdev->msi_cap + PCI_MSI_MASK_64,
2350 pci_write_config_dword(pdev, pdev->msi_cap + PCI_MSI_MASK_64,
2351 ACC_PEH_MSI_DISABLE);
2352 if (qm->err_status.is_qm_ecc_mbit ||
2353 qm->err_status.is_dev_ecc_mbit)
2357 if (readl(qm->io_base + QM_PEH_DFX_INFO0))
2364 static void qm_wait_msi_finish(struct hisi_qm *qm)
2366 struct pci_dev *pdev = qm->pdev;
2373 pci_read_config_dword(pdev, pdev->msi_cap +
2374 PCI_MSI_PENDING_64, &cmd);
2378 if (++cnt > MAX_WAIT_COUNTS) {
2379 pci_warn(pdev, "failed to empty MSI PENDING!\n");
2386 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_DFX_INFO0,
2387 val, !(val & QM_PEH_DFX_MASK),
2388 POLL_PERIOD, POLL_TIMEOUT);
2390 pci_warn(pdev, "failed to empty PEH MSI!\n");
2392 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_DFX_INFO1,
2393 val, !(val & QM_PEH_MSI_FINISH_MASK),
2394 POLL_PERIOD, POLL_TIMEOUT);
2396 pci_warn(pdev, "failed to finish MSI operation!\n");
2399 static int qm_set_msi_v3(struct hisi_qm *qm, bool set)
2401 struct pci_dev *pdev = qm->pdev;
2402 int ret = -ETIMEDOUT;
2405 pci_read_config_dword(pdev, pdev->msi_cap, &cmd);
2407 cmd |= QM_MSI_CAP_ENABLE;
2409 cmd &= ~QM_MSI_CAP_ENABLE;
2411 pci_write_config_dword(pdev, pdev->msi_cap, cmd);
2413 for (i = 0; i < MAX_WAIT_COUNTS; i++) {
2414 pci_read_config_dword(pdev, pdev->msi_cap, &cmd);
2415 if (cmd & QM_MSI_CAP_ENABLE)
2421 udelay(WAIT_PERIOD_US_MIN);
2422 qm_wait_msi_finish(qm);
2429 static const struct hisi_qm_hw_ops qm_hw_ops_v1 = {
2431 .get_irq_num = qm_get_irq_num_v1,
2432 .hw_error_init = qm_hw_error_init_v1,
2433 .set_msi = qm_set_msi,
2436 static const struct hisi_qm_hw_ops qm_hw_ops_v2 = {
2437 .get_vft = qm_get_vft_v2,
2439 .get_irq_num = qm_get_irq_num_v2,
2440 .hw_error_init = qm_hw_error_init_v2,
2441 .hw_error_uninit = qm_hw_error_uninit_v2,
2442 .hw_error_handle = qm_hw_error_handle_v2,
2443 .set_msi = qm_set_msi,
2446 static const struct hisi_qm_hw_ops qm_hw_ops_v3 = {
2447 .get_vft = qm_get_vft_v2,
2449 .get_irq_num = qm_get_irq_num_v3,
2450 .hw_error_init = qm_hw_error_init_v3,
2451 .hw_error_uninit = qm_hw_error_uninit_v3,
2452 .hw_error_handle = qm_hw_error_handle_v2,
2453 .stop_qp = qm_stop_qp,
2454 .set_msi = qm_set_msi_v3,
2455 .ping_all_vfs = qm_ping_all_vfs,
2456 .ping_pf = qm_ping_pf,
2459 static void *qm_get_avail_sqe(struct hisi_qp *qp)
2461 struct hisi_qp_status *qp_status = &qp->qp_status;
2462 u16 sq_tail = qp_status->sq_tail;
2464 if (unlikely(atomic_read(&qp->qp_status.used) == QM_Q_DEPTH - 1))
2467 return qp->sqe + sq_tail * qp->qm->sqe_size;
2470 static struct hisi_qp *qm_create_qp_nolock(struct hisi_qm *qm, u8 alg_type)
2472 struct device *dev = &qm->pdev->dev;
2476 if (!qm_qp_avail_state(qm, NULL, QP_INIT))
2477 return ERR_PTR(-EPERM);
2479 if (qm->qp_in_used == qm->qp_num) {
2480 dev_info_ratelimited(dev, "All %u queues of QM are busy!\n",
2482 atomic64_inc(&qm->debug.dfx.create_qp_err_cnt);
2483 return ERR_PTR(-EBUSY);
2486 qp_id = idr_alloc_cyclic(&qm->qp_idr, NULL, 0, qm->qp_num, GFP_ATOMIC);
2488 dev_info_ratelimited(dev, "All %u queues of QM are busy!\n",
2490 atomic64_inc(&qm->debug.dfx.create_qp_err_cnt);
2491 return ERR_PTR(-EBUSY);
2494 qp = &qm->qp_array[qp_id];
2496 memset(qp->cqe, 0, sizeof(struct qm_cqe) * QM_Q_DEPTH);
2498 qp->event_cb = NULL;
2501 qp->alg_type = alg_type;
2502 qp->is_in_kernel = true;
2504 atomic_set(&qp->qp_status.flags, QP_INIT);
2510 * hisi_qm_create_qp() - Create a queue pair from qm.
2511 * @qm: The qm we create a qp from.
2512 * @alg_type: Accelerator specific algorithm type in sqc.
2514 * return created qp, -EBUSY if all qps in qm allocated, -ENOMEM if allocating
2517 struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type)
2522 ret = qm_pm_get_sync(qm);
2524 return ERR_PTR(ret);
2526 down_write(&qm->qps_lock);
2527 qp = qm_create_qp_nolock(qm, alg_type);
2528 up_write(&qm->qps_lock);
2535 EXPORT_SYMBOL_GPL(hisi_qm_create_qp);
2538 * hisi_qm_release_qp() - Release a qp back to its qm.
2539 * @qp: The qp we want to release.
2541 * This function releases the resource of a qp.
2543 void hisi_qm_release_qp(struct hisi_qp *qp)
2545 struct hisi_qm *qm = qp->qm;
2547 down_write(&qm->qps_lock);
2549 if (!qm_qp_avail_state(qm, qp, QP_CLOSE)) {
2550 up_write(&qm->qps_lock);
2555 idr_remove(&qm->qp_idr, qp->qp_id);
2557 up_write(&qm->qps_lock);
2561 EXPORT_SYMBOL_GPL(hisi_qm_release_qp);
2563 static int qm_sq_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
2565 struct hisi_qm *qm = qp->qm;
2566 struct device *dev = &qm->pdev->dev;
2567 enum qm_hw_ver ver = qm->ver;
2572 sqc = kzalloc(sizeof(struct qm_sqc), GFP_KERNEL);
2576 INIT_QC_COMMON(sqc, qp->sqe_dma, pasid);
2577 if (ver == QM_HW_V1) {
2578 sqc->dw3 = cpu_to_le32(QM_MK_SQC_DW3_V1(0, 0, 0, qm->sqe_size));
2579 sqc->w8 = cpu_to_le16(QM_Q_DEPTH - 1);
2581 sqc->dw3 = cpu_to_le32(QM_MK_SQC_DW3_V2(qm->sqe_size));
2582 sqc->w8 = 0; /* rand_qc */
2584 sqc->cq_num = cpu_to_le16(qp_id);
2585 sqc->w13 = cpu_to_le16(QM_MK_SQC_W13(0, 1, qp->alg_type));
2587 if (ver >= QM_HW_V3 && qm->use_sva && !qp->is_in_kernel)
2588 sqc->w11 = cpu_to_le16(QM_QC_PASID_ENABLE <<
2589 QM_QC_PASID_ENABLE_SHIFT);
2591 sqc_dma = dma_map_single(dev, sqc, sizeof(struct qm_sqc),
2593 if (dma_mapping_error(dev, sqc_dma)) {
2598 ret = qm_mb(qm, QM_MB_CMD_SQC, sqc_dma, qp_id, 0);
2599 dma_unmap_single(dev, sqc_dma, sizeof(struct qm_sqc), DMA_TO_DEVICE);
2605 static int qm_cq_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
2607 struct hisi_qm *qm = qp->qm;
2608 struct device *dev = &qm->pdev->dev;
2609 enum qm_hw_ver ver = qm->ver;
2614 cqc = kzalloc(sizeof(struct qm_cqc), GFP_KERNEL);
2618 INIT_QC_COMMON(cqc, qp->cqe_dma, pasid);
2619 if (ver == QM_HW_V1) {
2620 cqc->dw3 = cpu_to_le32(QM_MK_CQC_DW3_V1(0, 0, 0,
2622 cqc->w8 = cpu_to_le16(QM_Q_DEPTH - 1);
2624 cqc->dw3 = cpu_to_le32(QM_MK_CQC_DW3_V2(QM_QC_CQE_SIZE));
2625 cqc->w8 = 0; /* rand_qc */
2627 cqc->dw6 = cpu_to_le32(1 << QM_CQ_PHASE_SHIFT | 1 << QM_CQ_FLAG_SHIFT);
2629 if (ver >= QM_HW_V3 && qm->use_sva && !qp->is_in_kernel)
2630 cqc->w11 = cpu_to_le16(QM_QC_PASID_ENABLE);
2632 cqc_dma = dma_map_single(dev, cqc, sizeof(struct qm_cqc),
2634 if (dma_mapping_error(dev, cqc_dma)) {
2639 ret = qm_mb(qm, QM_MB_CMD_CQC, cqc_dma, qp_id, 0);
2640 dma_unmap_single(dev, cqc_dma, sizeof(struct qm_cqc), DMA_TO_DEVICE);
2646 static int qm_qp_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
2650 qm_init_qp_status(qp);
2652 ret = qm_sq_ctx_cfg(qp, qp_id, pasid);
2656 return qm_cq_ctx_cfg(qp, qp_id, pasid);
2659 static int qm_start_qp_nolock(struct hisi_qp *qp, unsigned long arg)
2661 struct hisi_qm *qm = qp->qm;
2662 struct device *dev = &qm->pdev->dev;
2663 int qp_id = qp->qp_id;
2667 if (!qm_qp_avail_state(qm, qp, QP_START))
2670 ret = qm_qp_ctx_cfg(qp, qp_id, pasid);
2674 atomic_set(&qp->qp_status.flags, QP_START);
2675 dev_dbg(dev, "queue %d started\n", qp_id);
2681 * hisi_qm_start_qp() - Start a qp into running.
2682 * @qp: The qp we want to start to run.
2683 * @arg: Accelerator specific argument.
2685 * After this function, qp can receive request from user. Return 0 if
2686 * successful, Return -EBUSY if failed.
2688 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg)
2690 struct hisi_qm *qm = qp->qm;
2693 down_write(&qm->qps_lock);
2694 ret = qm_start_qp_nolock(qp, arg);
2695 up_write(&qm->qps_lock);
2699 EXPORT_SYMBOL_GPL(hisi_qm_start_qp);
2702 * qp_stop_fail_cb() - call request cb.
2703 * @qp: stopped failed qp.
2705 * Callback function should be called whether task completed or not.
2707 static void qp_stop_fail_cb(struct hisi_qp *qp)
2709 int qp_used = atomic_read(&qp->qp_status.used);
2710 u16 cur_tail = qp->qp_status.sq_tail;
2711 u16 cur_head = (cur_tail + QM_Q_DEPTH - qp_used) % QM_Q_DEPTH;
2712 struct hisi_qm *qm = qp->qm;
2716 for (i = 0; i < qp_used; i++) {
2717 pos = (i + cur_head) % QM_Q_DEPTH;
2718 qp->req_cb(qp, qp->sqe + (u32)(qm->sqe_size * pos));
2719 atomic_dec(&qp->qp_status.used);
2724 * qm_drain_qp() - Drain a qp.
2725 * @qp: The qp we want to drain.
2727 * Determine whether the queue is cleared by judging the tail pointers of
2730 static int qm_drain_qp(struct hisi_qp *qp)
2732 size_t size = sizeof(struct qm_sqc) + sizeof(struct qm_cqc);
2733 struct hisi_qm *qm = qp->qm;
2734 struct device *dev = &qm->pdev->dev;
2737 dma_addr_t dma_addr;
2741 /* No need to judge if master OOO is blocked. */
2742 if (qm_check_dev_error(qm))
2745 /* Kunpeng930 supports drain qp by device */
2746 if (qm->ops->stop_qp) {
2747 ret = qm->ops->stop_qp(qp);
2749 dev_err(dev, "Failed to stop qp(%u)!\n", qp->qp_id);
2753 addr = qm_ctx_alloc(qm, size, &dma_addr);
2755 dev_err(dev, "Failed to alloc ctx for sqc and cqc!\n");
2760 ret = qm_dump_sqc_raw(qm, dma_addr, qp->qp_id);
2762 dev_err_ratelimited(dev, "Failed to dump sqc!\n");
2767 ret = qm_dump_cqc_raw(qm, (dma_addr + sizeof(struct qm_sqc)),
2770 dev_err_ratelimited(dev, "Failed to dump cqc!\n");
2773 cqc = addr + sizeof(struct qm_sqc);
2775 if ((sqc->tail == cqc->tail) &&
2776 (QM_SQ_TAIL_IDX(sqc) == QM_CQ_TAIL_IDX(cqc)))
2779 if (i == MAX_WAIT_COUNTS) {
2780 dev_err(dev, "Fail to empty queue %u!\n", qp->qp_id);
2785 usleep_range(WAIT_PERIOD_US_MIN, WAIT_PERIOD_US_MAX);
2788 qm_ctx_free(qm, size, addr, &dma_addr);
2793 static int qm_stop_qp_nolock(struct hisi_qp *qp)
2795 struct device *dev = &qp->qm->pdev->dev;
2799 * It is allowed to stop and release qp when reset, If the qp is
2800 * stopped when reset but still want to be released then, the
2801 * is_resetting flag should be set negative so that this qp will not
2802 * be restarted after reset.
2804 if (atomic_read(&qp->qp_status.flags) == QP_STOP) {
2805 qp->is_resetting = false;
2809 if (!qm_qp_avail_state(qp->qm, qp, QP_STOP))
2812 atomic_set(&qp->qp_status.flags, QP_STOP);
2814 ret = qm_drain_qp(qp);
2816 dev_err(dev, "Failed to drain out data for stopping!\n");
2819 flush_workqueue(qp->qm->wq);
2821 flush_work(&qp->qm->work);
2823 if (unlikely(qp->is_resetting && atomic_read(&qp->qp_status.used)))
2824 qp_stop_fail_cb(qp);
2826 dev_dbg(dev, "stop queue %u!", qp->qp_id);
2832 * hisi_qm_stop_qp() - Stop a qp in qm.
2833 * @qp: The qp we want to stop.
2835 * This function is reverse of hisi_qm_start_qp. Return 0 if successful.
2837 int hisi_qm_stop_qp(struct hisi_qp *qp)
2841 down_write(&qp->qm->qps_lock);
2842 ret = qm_stop_qp_nolock(qp);
2843 up_write(&qp->qm->qps_lock);
2847 EXPORT_SYMBOL_GPL(hisi_qm_stop_qp);
2850 * hisi_qp_send() - Queue up a task in the hardware queue.
2851 * @qp: The qp in which to put the message.
2852 * @msg: The message.
2854 * This function will return -EBUSY if qp is currently full, and -EAGAIN
2855 * if qp related qm is resetting.
2857 * Note: This function may run with qm_irq_thread and ACC reset at same time.
2858 * It has no race with qm_irq_thread. However, during hisi_qp_send, ACC
2859 * reset may happen, we have no lock here considering performance. This
2860 * causes current qm_db sending fail or can not receive sended sqe. QM
2861 * sync/async receive function should handle the error sqe. ACC reset
2862 * done function should clear used sqe to 0.
2864 int hisi_qp_send(struct hisi_qp *qp, const void *msg)
2866 struct hisi_qp_status *qp_status = &qp->qp_status;
2867 u16 sq_tail = qp_status->sq_tail;
2868 u16 sq_tail_next = (sq_tail + 1) % QM_Q_DEPTH;
2869 void *sqe = qm_get_avail_sqe(qp);
2871 if (unlikely(atomic_read(&qp->qp_status.flags) == QP_STOP ||
2872 atomic_read(&qp->qm->status.flags) == QM_STOP ||
2873 qp->is_resetting)) {
2874 dev_info_ratelimited(&qp->qm->pdev->dev, "QP is stopped or resetting\n");
2881 memcpy(sqe, msg, qp->qm->sqe_size);
2883 qm_db(qp->qm, qp->qp_id, QM_DOORBELL_CMD_SQ, sq_tail_next, 0);
2884 atomic_inc(&qp->qp_status.used);
2885 qp_status->sq_tail = sq_tail_next;
2889 EXPORT_SYMBOL_GPL(hisi_qp_send);
2891 static void hisi_qm_cache_wb(struct hisi_qm *qm)
2895 if (qm->ver == QM_HW_V1)
2898 writel(0x1, qm->io_base + QM_CACHE_WB_START);
2899 if (readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE,
2900 val, val & BIT(0), POLL_PERIOD,
2902 dev_err(&qm->pdev->dev, "QM writeback sqc cache fail!\n");
2905 static void qm_qp_event_notifier(struct hisi_qp *qp)
2907 wake_up_interruptible(&qp->uacce_q->wait);
2910 static int hisi_qm_get_available_instances(struct uacce_device *uacce)
2912 return hisi_qm_get_free_qp_num(uacce->priv);
2915 static int hisi_qm_uacce_get_queue(struct uacce_device *uacce,
2917 struct uacce_queue *q)
2919 struct hisi_qm *qm = uacce->priv;
2923 qp = hisi_qm_create_qp(qm, alg_type);
2930 qp->event_cb = qm_qp_event_notifier;
2932 qp->is_in_kernel = false;
2937 static void hisi_qm_uacce_put_queue(struct uacce_queue *q)
2939 struct hisi_qp *qp = q->priv;
2941 hisi_qm_cache_wb(qp->qm);
2942 hisi_qm_release_qp(qp);
2945 /* map sq/cq/doorbell to user space */
2946 static int hisi_qm_uacce_mmap(struct uacce_queue *q,
2947 struct vm_area_struct *vma,
2948 struct uacce_qfile_region *qfr)
2950 struct hisi_qp *qp = q->priv;
2951 struct hisi_qm *qm = qp->qm;
2952 resource_size_t phys_base = qm->db_phys_base +
2953 qp->qp_id * qm->db_interval;
2954 size_t sz = vma->vm_end - vma->vm_start;
2955 struct pci_dev *pdev = qm->pdev;
2956 struct device *dev = &pdev->dev;
2957 unsigned long vm_pgoff;
2960 switch (qfr->type) {
2961 case UACCE_QFRT_MMIO:
2962 if (qm->ver == QM_HW_V1) {
2963 if (sz > PAGE_SIZE * QM_DOORBELL_PAGE_NR)
2965 } else if (qm->ver == QM_HW_V2 || !qm->use_db_isolation) {
2966 if (sz > PAGE_SIZE * (QM_DOORBELL_PAGE_NR +
2967 QM_DOORBELL_SQ_CQ_BASE_V2 / PAGE_SIZE))
2970 if (sz > qm->db_interval)
2974 vma->vm_flags |= VM_IO;
2976 return remap_pfn_range(vma, vma->vm_start,
2977 phys_base >> PAGE_SHIFT,
2978 sz, pgprot_noncached(vma->vm_page_prot));
2979 case UACCE_QFRT_DUS:
2980 if (sz != qp->qdma.size)
2984 * dma_mmap_coherent() requires vm_pgoff as 0
2985 * restore vm_pfoff to initial value for mmap()
2987 vm_pgoff = vma->vm_pgoff;
2989 ret = dma_mmap_coherent(dev, vma, qp->qdma.va,
2991 vma->vm_pgoff = vm_pgoff;
2999 static int hisi_qm_uacce_start_queue(struct uacce_queue *q)
3001 struct hisi_qp *qp = q->priv;
3003 return hisi_qm_start_qp(qp, qp->pasid);
3006 static void hisi_qm_uacce_stop_queue(struct uacce_queue *q)
3008 hisi_qm_stop_qp(q->priv);
3011 static int hisi_qm_is_q_updated(struct uacce_queue *q)
3013 struct hisi_qp *qp = q->priv;
3014 struct qm_cqe *cqe = qp->cqe + qp->qp_status.cq_head;
3017 while (QM_CQE_PHASE(cqe) == qp->qp_status.cqc_phase) {
3018 /* make sure to read data from memory */
3020 qm_cq_head_update(qp);
3021 cqe = qp->cqe + qp->qp_status.cq_head;
3028 static void qm_set_sqctype(struct uacce_queue *q, u16 type)
3030 struct hisi_qm *qm = q->uacce->priv;
3031 struct hisi_qp *qp = q->priv;
3033 down_write(&qm->qps_lock);
3034 qp->alg_type = type;
3035 up_write(&qm->qps_lock);
3038 static long hisi_qm_uacce_ioctl(struct uacce_queue *q, unsigned int cmd,
3041 struct hisi_qp *qp = q->priv;
3042 struct hisi_qp_ctx qp_ctx;
3044 if (cmd == UACCE_CMD_QM_SET_QP_CTX) {
3045 if (copy_from_user(&qp_ctx, (void __user *)arg,
3046 sizeof(struct hisi_qp_ctx)))
3049 if (qp_ctx.qc_type != 0 && qp_ctx.qc_type != 1)
3052 qm_set_sqctype(q, qp_ctx.qc_type);
3053 qp_ctx.id = qp->qp_id;
3055 if (copy_to_user((void __user *)arg, &qp_ctx,
3056 sizeof(struct hisi_qp_ctx)))
3065 static const struct uacce_ops uacce_qm_ops = {
3066 .get_available_instances = hisi_qm_get_available_instances,
3067 .get_queue = hisi_qm_uacce_get_queue,
3068 .put_queue = hisi_qm_uacce_put_queue,
3069 .start_queue = hisi_qm_uacce_start_queue,
3070 .stop_queue = hisi_qm_uacce_stop_queue,
3071 .mmap = hisi_qm_uacce_mmap,
3072 .ioctl = hisi_qm_uacce_ioctl,
3073 .is_q_updated = hisi_qm_is_q_updated,
3076 static int qm_alloc_uacce(struct hisi_qm *qm)
3078 struct pci_dev *pdev = qm->pdev;
3079 struct uacce_device *uacce;
3080 unsigned long mmio_page_nr;
3081 unsigned long dus_page_nr;
3082 struct uacce_interface interface = {
3083 .flags = UACCE_DEV_SVA,
3084 .ops = &uacce_qm_ops,
3088 ret = strscpy(interface.name, pdev->driver->name,
3089 sizeof(interface.name));
3091 return -ENAMETOOLONG;
3093 uacce = uacce_alloc(&pdev->dev, &interface);
3095 return PTR_ERR(uacce);
3097 if (uacce->flags & UACCE_DEV_SVA && qm->mode == UACCE_MODE_SVA) {
3100 /* only consider sva case */
3101 uacce_remove(uacce);
3106 uacce->is_vf = pdev->is_virtfn;
3108 uacce->algs = qm->algs;
3110 if (qm->ver == QM_HW_V1)
3111 uacce->api_ver = HISI_QM_API_VER_BASE;
3112 else if (qm->ver == QM_HW_V2)
3113 uacce->api_ver = HISI_QM_API_VER2_BASE;
3115 uacce->api_ver = HISI_QM_API_VER3_BASE;
3117 if (qm->ver == QM_HW_V1)
3118 mmio_page_nr = QM_DOORBELL_PAGE_NR;
3119 else if (qm->ver == QM_HW_V2 || !qm->use_db_isolation)
3120 mmio_page_nr = QM_DOORBELL_PAGE_NR +
3121 QM_DOORBELL_SQ_CQ_BASE_V2 / PAGE_SIZE;
3123 mmio_page_nr = qm->db_interval / PAGE_SIZE;
3125 dus_page_nr = (PAGE_SIZE - 1 + qm->sqe_size * QM_Q_DEPTH +
3126 sizeof(struct qm_cqe) * QM_Q_DEPTH) >> PAGE_SHIFT;
3128 uacce->qf_pg_num[UACCE_QFRT_MMIO] = mmio_page_nr;
3129 uacce->qf_pg_num[UACCE_QFRT_DUS] = dus_page_nr;
3137 * qm_frozen() - Try to froze QM to cut continuous queue request. If
3138 * there is user on the QM, return failure without doing anything.
3139 * @qm: The qm needed to be fronzen.
3141 * This function frozes QM, then we can do SRIOV disabling.
3143 static int qm_frozen(struct hisi_qm *qm)
3145 if (test_bit(QM_DRIVER_REMOVING, &qm->misc_ctl))
3148 down_write(&qm->qps_lock);
3150 if (!qm->qp_in_used) {
3151 qm->qp_in_used = qm->qp_num;
3152 up_write(&qm->qps_lock);
3153 set_bit(QM_DRIVER_REMOVING, &qm->misc_ctl);
3157 up_write(&qm->qps_lock);
3162 static int qm_try_frozen_vfs(struct pci_dev *pdev,
3163 struct hisi_qm_list *qm_list)
3165 struct hisi_qm *qm, *vf_qm;
3166 struct pci_dev *dev;
3169 if (!qm_list || !pdev)
3172 /* Try to frozen all the VFs as disable SRIOV */
3173 mutex_lock(&qm_list->lock);
3174 list_for_each_entry(qm, &qm_list->list, list) {
3178 if (pci_physfn(dev) == pdev) {
3179 vf_qm = pci_get_drvdata(dev);
3180 ret = qm_frozen(vf_qm);
3187 mutex_unlock(&qm_list->lock);
3193 * hisi_qm_wait_task_finish() - Wait until the task is finished
3194 * when removing the driver.
3195 * @qm: The qm needed to wait for the task to finish.
3196 * @qm_list: The list of all available devices.
3198 void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
3200 while (qm_frozen(qm) ||
3201 ((qm->fun_type == QM_HW_PF) &&
3202 qm_try_frozen_vfs(qm->pdev, qm_list))) {
3203 msleep(WAIT_PERIOD);
3206 while (test_bit(QM_RST_SCHED, &qm->misc_ctl) ||
3207 test_bit(QM_RESETTING, &qm->misc_ctl))
3208 msleep(WAIT_PERIOD);
3210 udelay(REMOVE_WAIT_DELAY);
3212 EXPORT_SYMBOL_GPL(hisi_qm_wait_task_finish);
3215 * hisi_qm_get_free_qp_num() - Get free number of qp in qm.
3216 * @qm: The qm which want to get free qp.
3218 * This function return free number of qp in qm.
3220 int hisi_qm_get_free_qp_num(struct hisi_qm *qm)
3224 down_read(&qm->qps_lock);
3225 ret = qm->qp_num - qm->qp_in_used;
3226 up_read(&qm->qps_lock);
3230 EXPORT_SYMBOL_GPL(hisi_qm_get_free_qp_num);
3232 static void hisi_qp_memory_uninit(struct hisi_qm *qm, int num)
3234 struct device *dev = &qm->pdev->dev;
3235 struct qm_dma *qdma;
3238 for (i = num - 1; i >= 0; i--) {
3239 qdma = &qm->qp_array[i].qdma;
3240 dma_free_coherent(dev, qdma->size, qdma->va, qdma->dma);
3243 kfree(qm->qp_array);
3246 static int hisi_qp_memory_init(struct hisi_qm *qm, size_t dma_size, int id)
3248 struct device *dev = &qm->pdev->dev;
3249 size_t off = qm->sqe_size * QM_Q_DEPTH;
3252 qp = &qm->qp_array[id];
3253 qp->qdma.va = dma_alloc_coherent(dev, dma_size, &qp->qdma.dma,
3258 qp->sqe = qp->qdma.va;
3259 qp->sqe_dma = qp->qdma.dma;
3260 qp->cqe = qp->qdma.va + off;
3261 qp->cqe_dma = qp->qdma.dma + off;
3262 qp->qdma.size = dma_size;
3269 static void hisi_qm_pre_init(struct hisi_qm *qm)
3271 struct pci_dev *pdev = qm->pdev;
3273 if (qm->ver == QM_HW_V1)
3274 qm->ops = &qm_hw_ops_v1;
3275 else if (qm->ver == QM_HW_V2)
3276 qm->ops = &qm_hw_ops_v2;
3278 qm->ops = &qm_hw_ops_v3;
3280 pci_set_drvdata(pdev, qm);
3281 mutex_init(&qm->mailbox_lock);
3282 init_rwsem(&qm->qps_lock);
3284 qm->misc_ctl = false;
3285 if (qm->fun_type == QM_HW_PF && qm->ver > QM_HW_V2) {
3286 if (!acpi_device_power_manageable(ACPI_COMPANION(&pdev->dev)))
3287 dev_info(&pdev->dev, "_PS0 and _PR0 are not defined");
3291 static void qm_cmd_uninit(struct hisi_qm *qm)
3295 if (qm->ver < QM_HW_V3)
3298 val = readl(qm->io_base + QM_IFC_INT_MASK);
3299 val |= QM_IFC_INT_DISABLE;
3300 writel(val, qm->io_base + QM_IFC_INT_MASK);
3303 static void qm_cmd_init(struct hisi_qm *qm)
3307 if (qm->ver < QM_HW_V3)
3310 /* Clear communication interrupt source */
3311 qm_clear_cmd_interrupt(qm, QM_IFC_INT_SOURCE_CLR);
3313 /* Enable pf to vf communication reg. */
3314 val = readl(qm->io_base + QM_IFC_INT_MASK);
3315 val &= ~QM_IFC_INT_DISABLE;
3316 writel(val, qm->io_base + QM_IFC_INT_MASK);
3319 static void qm_put_pci_res(struct hisi_qm *qm)
3321 struct pci_dev *pdev = qm->pdev;
3323 if (qm->use_db_isolation)
3324 iounmap(qm->db_io_base);
3326 iounmap(qm->io_base);
3327 pci_release_mem_regions(pdev);
3330 static void hisi_qm_pci_uninit(struct hisi_qm *qm)
3332 struct pci_dev *pdev = qm->pdev;
3334 pci_free_irq_vectors(pdev);
3336 pci_disable_device(pdev);
3340 * hisi_qm_uninit() - Uninitialize qm.
3341 * @qm: The qm needed uninit.
3343 * This function uninits qm related device resources.
3345 void hisi_qm_uninit(struct hisi_qm *qm)
3347 struct pci_dev *pdev = qm->pdev;
3348 struct device *dev = &pdev->dev;
3352 down_write(&qm->qps_lock);
3354 if (!qm_avail_state(qm, QM_CLOSE)) {
3355 up_write(&qm->qps_lock);
3359 hisi_qp_memory_uninit(qm, qm->qp_num);
3360 idr_destroy(&qm->qp_idr);
3363 hisi_qm_cache_wb(qm);
3364 dma_free_coherent(dev, qm->qdma.size,
3365 qm->qdma.va, qm->qdma.dma);
3368 qm_irq_unregister(qm);
3369 hisi_qm_pci_uninit(qm);
3370 uacce_remove(qm->uacce);
3373 up_write(&qm->qps_lock);
3375 EXPORT_SYMBOL_GPL(hisi_qm_uninit);
3378 * hisi_qm_get_vft() - Get vft from a qm.
3379 * @qm: The qm we want to get its vft.
3380 * @base: The base number of queue in vft.
3381 * @number: The number of queues in vft.
3383 * We can allocate multiple queues to a qm by configuring virtual function
3384 * table. We get related configures by this function. Normally, we call this
3385 * function in VF driver to get the queue information.
3387 * qm hw v1 does not support this interface.
3389 int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number)
3391 if (!base || !number)
3394 if (!qm->ops->get_vft) {
3395 dev_err(&qm->pdev->dev, "Don't support vft read!\n");
3399 return qm->ops->get_vft(qm, base, number);
3401 EXPORT_SYMBOL_GPL(hisi_qm_get_vft);
3404 * hisi_qm_set_vft() - Set vft to a qm.
3405 * @qm: The qm we want to set its vft.
3406 * @fun_num: The function number.
3407 * @base: The base number of queue in vft.
3408 * @number: The number of queues in vft.
3410 * This function is alway called in PF driver, it is used to assign queues
3413 * Assign queues A~B to PF: hisi_qm_set_vft(qm, 0, A, B - A + 1)
3414 * Assign queues A~B to VF: hisi_qm_set_vft(qm, 2, A, B - A + 1)
3415 * (VF function number 0x2)
3417 static int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base,
3420 u32 max_q_num = qm->ctrl_qp_num;
3422 if (base >= max_q_num || number > max_q_num ||
3423 (base + number) > max_q_num)
3426 return qm_set_sqc_cqc_vft(qm, fun_num, base, number);
3429 static void qm_init_eq_aeq_status(struct hisi_qm *qm)
3431 struct hisi_qm_status *status = &qm->status;
3433 status->eq_head = 0;
3434 status->aeq_head = 0;
3435 status->eqc_phase = true;
3436 status->aeqc_phase = true;
3439 static int qm_eq_ctx_cfg(struct hisi_qm *qm)
3441 struct device *dev = &qm->pdev->dev;
3446 eqc = kzalloc(sizeof(struct qm_eqc), GFP_KERNEL);
3450 eqc->base_l = cpu_to_le32(lower_32_bits(qm->eqe_dma));
3451 eqc->base_h = cpu_to_le32(upper_32_bits(qm->eqe_dma));
3452 if (qm->ver == QM_HW_V1)
3453 eqc->dw3 = cpu_to_le32(QM_EQE_AEQE_SIZE);
3454 eqc->dw6 = cpu_to_le32((QM_EQ_DEPTH - 1) | (1 << QM_EQC_PHASE_SHIFT));
3456 eqc_dma = dma_map_single(dev, eqc, sizeof(struct qm_eqc),
3458 if (dma_mapping_error(dev, eqc_dma)) {
3463 ret = qm_mb(qm, QM_MB_CMD_EQC, eqc_dma, 0, 0);
3464 dma_unmap_single(dev, eqc_dma, sizeof(struct qm_eqc), DMA_TO_DEVICE);
3470 static int qm_aeq_ctx_cfg(struct hisi_qm *qm)
3472 struct device *dev = &qm->pdev->dev;
3473 struct qm_aeqc *aeqc;
3474 dma_addr_t aeqc_dma;
3477 aeqc = kzalloc(sizeof(struct qm_aeqc), GFP_KERNEL);
3481 aeqc->base_l = cpu_to_le32(lower_32_bits(qm->aeqe_dma));
3482 aeqc->base_h = cpu_to_le32(upper_32_bits(qm->aeqe_dma));
3483 aeqc->dw6 = cpu_to_le32((QM_Q_DEPTH - 1) | (1 << QM_EQC_PHASE_SHIFT));
3485 aeqc_dma = dma_map_single(dev, aeqc, sizeof(struct qm_aeqc),
3487 if (dma_mapping_error(dev, aeqc_dma)) {
3492 ret = qm_mb(qm, QM_MB_CMD_AEQC, aeqc_dma, 0, 0);
3493 dma_unmap_single(dev, aeqc_dma, sizeof(struct qm_aeqc), DMA_TO_DEVICE);
3499 static int qm_eq_aeq_ctx_cfg(struct hisi_qm *qm)
3501 struct device *dev = &qm->pdev->dev;
3504 qm_init_eq_aeq_status(qm);
3506 ret = qm_eq_ctx_cfg(qm);
3508 dev_err(dev, "Set eqc failed!\n");
3512 return qm_aeq_ctx_cfg(qm);
3515 static int __hisi_qm_start(struct hisi_qm *qm)
3519 WARN_ON(!qm->qdma.va);
3521 if (qm->fun_type == QM_HW_PF) {
3522 ret = qm_dev_mem_reset(qm);
3526 ret = hisi_qm_set_vft(qm, 0, qm->qp_base, qm->qp_num);
3531 ret = qm_eq_aeq_ctx_cfg(qm);
3535 ret = qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);
3539 ret = qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);
3543 qm_init_prefetch(qm);
3545 writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK);
3546 writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK);
3552 * hisi_qm_start() - start qm
3553 * @qm: The qm to be started.
3555 * This function starts a qm, then we can allocate qp from this qm.
3557 int hisi_qm_start(struct hisi_qm *qm)
3559 struct device *dev = &qm->pdev->dev;
3562 down_write(&qm->qps_lock);
3564 if (!qm_avail_state(qm, QM_START)) {
3565 up_write(&qm->qps_lock);
3569 dev_dbg(dev, "qm start with %u queue pairs\n", qm->qp_num);
3572 dev_err(dev, "qp_num should not be 0\n");
3577 ret = __hisi_qm_start(qm);
3579 atomic_set(&qm->status.flags, QM_START);
3582 up_write(&qm->qps_lock);
3585 EXPORT_SYMBOL_GPL(hisi_qm_start);
3587 static int qm_restart(struct hisi_qm *qm)
3589 struct device *dev = &qm->pdev->dev;
3593 ret = hisi_qm_start(qm);
3597 down_write(&qm->qps_lock);
3598 for (i = 0; i < qm->qp_num; i++) {
3599 qp = &qm->qp_array[i];
3600 if (atomic_read(&qp->qp_status.flags) == QP_STOP &&
3601 qp->is_resetting == true) {
3602 ret = qm_start_qp_nolock(qp, 0);
3604 dev_err(dev, "Failed to start qp%d!\n", i);
3606 up_write(&qm->qps_lock);
3609 qp->is_resetting = false;
3612 up_write(&qm->qps_lock);
3617 /* Stop started qps in reset flow */
3618 static int qm_stop_started_qp(struct hisi_qm *qm)
3620 struct device *dev = &qm->pdev->dev;
3624 for (i = 0; i < qm->qp_num; i++) {
3625 qp = &qm->qp_array[i];
3626 if (qp && atomic_read(&qp->qp_status.flags) == QP_START) {
3627 qp->is_resetting = true;
3628 ret = qm_stop_qp_nolock(qp);
3630 dev_err(dev, "Failed to stop qp%d!\n", i);
3641 * qm_clear_queues() - Clear all queues memory in a qm.
3642 * @qm: The qm in which the queues will be cleared.
3644 * This function clears all queues memory in a qm. Reset of accelerator can
3645 * use this to clear queues.
3647 static void qm_clear_queues(struct hisi_qm *qm)
3652 for (i = 0; i < qm->qp_num; i++) {
3653 qp = &qm->qp_array[i];
3654 if (qp->is_resetting)
3655 memset(qp->qdma.va, 0, qp->qdma.size);
3658 memset(qm->qdma.va, 0, qm->qdma.size);
3662 * hisi_qm_stop() - Stop a qm.
3663 * @qm: The qm which will be stopped.
3664 * @r: The reason to stop qm.
3666 * This function stops qm and its qps, then qm can not accept request.
3667 * Related resources are not released at this state, we can use hisi_qm_start
3668 * to let qm start again.
3670 int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r)
3672 struct device *dev = &qm->pdev->dev;
3675 down_write(&qm->qps_lock);
3677 qm->status.stop_reason = r;
3678 if (!qm_avail_state(qm, QM_STOP)) {
3683 if (qm->status.stop_reason == QM_SOFT_RESET ||
3684 qm->status.stop_reason == QM_FLR) {
3685 ret = qm_stop_started_qp(qm);
3687 dev_err(dev, "Failed to stop started qp!\n");
3692 /* Mask eq and aeq irq */
3693 writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK);
3694 writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK);
3696 if (qm->fun_type == QM_HW_PF) {
3697 ret = hisi_qm_set_vft(qm, 0, 0, 0);
3699 dev_err(dev, "Failed to set vft!\n");
3705 qm_clear_queues(qm);
3706 atomic_set(&qm->status.flags, QM_STOP);
3709 up_write(&qm->qps_lock);
3712 EXPORT_SYMBOL_GPL(hisi_qm_stop);
3714 static ssize_t qm_status_read(struct file *filp, char __user *buffer,
3715 size_t count, loff_t *pos)
3717 struct hisi_qm *qm = filp->private_data;
3718 char buf[QM_DBG_READ_LEN];
3721 val = atomic_read(&qm->status.flags);
3722 len = scnprintf(buf, QM_DBG_READ_LEN, "%s\n", qm_s[val]);
3724 return simple_read_from_buffer(buffer, count, pos, buf, len);
3727 static const struct file_operations qm_status_fops = {
3728 .owner = THIS_MODULE,
3729 .open = simple_open,
3730 .read = qm_status_read,
3733 static int qm_debugfs_atomic64_set(void *data, u64 val)
3738 atomic64_set((atomic64_t *)data, 0);
3743 static int qm_debugfs_atomic64_get(void *data, u64 *val)
3745 *val = atomic64_read((atomic64_t *)data);
3750 DEFINE_DEBUGFS_ATTRIBUTE(qm_atomic64_ops, qm_debugfs_atomic64_get,
3751 qm_debugfs_atomic64_set, "%llu\n");
3753 static void qm_hw_error_init(struct hisi_qm *qm)
3755 struct hisi_qm_err_info *err_info = &qm->err_info;
3757 if (!qm->ops->hw_error_init) {
3758 dev_err(&qm->pdev->dev, "QM doesn't support hw error handling!\n");
3762 qm->ops->hw_error_init(qm, err_info->ce, err_info->nfe, err_info->fe);
3765 static void qm_hw_error_uninit(struct hisi_qm *qm)
3767 if (!qm->ops->hw_error_uninit) {
3768 dev_err(&qm->pdev->dev, "Unexpected QM hw error uninit!\n");
3772 qm->ops->hw_error_uninit(qm);
3775 static enum acc_err_result qm_hw_error_handle(struct hisi_qm *qm)
3777 if (!qm->ops->hw_error_handle) {
3778 dev_err(&qm->pdev->dev, "QM doesn't support hw error report!\n");
3779 return ACC_ERR_NONE;
3782 return qm->ops->hw_error_handle(qm);
3786 * hisi_qm_dev_err_init() - Initialize device error configuration.
3787 * @qm: The qm for which we want to do error initialization.
3789 * Initialize QM and device error related configuration.
3791 void hisi_qm_dev_err_init(struct hisi_qm *qm)
3793 if (qm->fun_type == QM_HW_VF)
3796 qm_hw_error_init(qm);
3798 if (!qm->err_ini->hw_err_enable) {
3799 dev_err(&qm->pdev->dev, "Device doesn't support hw error init!\n");
3802 qm->err_ini->hw_err_enable(qm);
3804 EXPORT_SYMBOL_GPL(hisi_qm_dev_err_init);
3807 * hisi_qm_dev_err_uninit() - Uninitialize device error configuration.
3808 * @qm: The qm for which we want to do error uninitialization.
3810 * Uninitialize QM and device error related configuration.
3812 void hisi_qm_dev_err_uninit(struct hisi_qm *qm)
3814 if (qm->fun_type == QM_HW_VF)
3817 qm_hw_error_uninit(qm);
3819 if (!qm->err_ini->hw_err_disable) {
3820 dev_err(&qm->pdev->dev, "Unexpected device hw error uninit!\n");
3823 qm->err_ini->hw_err_disable(qm);
3825 EXPORT_SYMBOL_GPL(hisi_qm_dev_err_uninit);
3828 * hisi_qm_free_qps() - free multiple queue pairs.
3829 * @qps: The queue pairs need to be freed.
3830 * @qp_num: The num of queue pairs.
3832 void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num)
3836 if (!qps || qp_num <= 0)
3839 for (i = qp_num - 1; i >= 0; i--)
3840 hisi_qm_release_qp(qps[i]);
3842 EXPORT_SYMBOL_GPL(hisi_qm_free_qps);
3844 static void free_list(struct list_head *head)
3846 struct hisi_qm_resource *res, *tmp;
3848 list_for_each_entry_safe(res, tmp, head, list) {
3849 list_del(&res->list);
3854 static int hisi_qm_sort_devices(int node, struct list_head *head,
3855 struct hisi_qm_list *qm_list)
3857 struct hisi_qm_resource *res, *tmp;
3859 struct list_head *n;
3863 list_for_each_entry(qm, &qm_list->list, list) {
3864 dev = &qm->pdev->dev;
3866 if (IS_ENABLED(CONFIG_NUMA)) {
3867 dev_node = dev_to_node(dev);
3872 res = kzalloc(sizeof(*res), GFP_KERNEL);
3877 res->distance = node_distance(dev_node, node);
3879 list_for_each_entry(tmp, head, list) {
3880 if (res->distance < tmp->distance) {
3885 list_add_tail(&res->list, n);
3892 * hisi_qm_alloc_qps_node() - Create multiple queue pairs.
3893 * @qm_list: The list of all available devices.
3894 * @qp_num: The number of queue pairs need created.
3895 * @alg_type: The algorithm type.
3896 * @node: The numa node.
3897 * @qps: The queue pairs need created.
3899 * This function will sort all available device according to numa distance.
3900 * Then try to create all queue pairs from one device, if all devices do
3901 * not meet the requirements will return error.
3903 int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
3904 u8 alg_type, int node, struct hisi_qp **qps)
3906 struct hisi_qm_resource *tmp;
3911 if (!qps || !qm_list || qp_num <= 0)
3914 mutex_lock(&qm_list->lock);
3915 if (hisi_qm_sort_devices(node, &head, qm_list)) {
3916 mutex_unlock(&qm_list->lock);
3920 list_for_each_entry(tmp, &head, list) {
3921 for (i = 0; i < qp_num; i++) {
3922 qps[i] = hisi_qm_create_qp(tmp->qm, alg_type);
3923 if (IS_ERR(qps[i])) {
3924 hisi_qm_free_qps(qps, i);
3935 mutex_unlock(&qm_list->lock);
3937 pr_info("Failed to create qps, node[%d], alg[%u], qp[%d]!\n",
3938 node, alg_type, qp_num);
3944 EXPORT_SYMBOL_GPL(hisi_qm_alloc_qps_node);
3946 static int qm_vf_q_assign(struct hisi_qm *qm, u32 num_vfs)
3948 u32 remain_q_num, vfs_q_num, act_q_num, q_num, i, j;
3949 u32 max_qp_num = qm->max_qp_num;
3950 u32 q_base = qm->qp_num;
3956 vfs_q_num = qm->ctrl_qp_num - qm->qp_num;
3958 /* If vfs_q_num is less than num_vfs, return error. */
3959 if (vfs_q_num < num_vfs)
3962 q_num = vfs_q_num / num_vfs;
3963 remain_q_num = vfs_q_num % num_vfs;
3965 for (i = num_vfs; i > 0; i--) {
3967 * if q_num + remain_q_num > max_qp_num in last vf, divide the
3968 * remaining queues equally.
3970 if (i == num_vfs && q_num + remain_q_num <= max_qp_num) {
3971 act_q_num = q_num + remain_q_num;
3973 } else if (remain_q_num > 0) {
3974 act_q_num = q_num + 1;
3980 act_q_num = min_t(int, act_q_num, max_qp_num);
3981 ret = hisi_qm_set_vft(qm, i, q_base, act_q_num);
3983 for (j = num_vfs; j > i; j--)
3984 hisi_qm_set_vft(qm, j, 0, 0);
3987 q_base += act_q_num;
3993 static int qm_clear_vft_config(struct hisi_qm *qm)
3998 for (i = 1; i <= qm->vfs_num; i++) {
3999 ret = hisi_qm_set_vft(qm, i, 0, 0);
4008 static int qm_func_shaper_enable(struct hisi_qm *qm, u32 fun_index, u32 qos)
4010 struct device *dev = &qm->pdev->dev;
4011 u32 ir = qos * QM_QOS_RATE;
4012 int ret, total_vfs, i;
4014 total_vfs = pci_sriov_get_totalvfs(qm->pdev);
4015 if (fun_index > total_vfs)
4018 qm->factor[fun_index].func_qos = qos;
4020 ret = qm_get_shaper_para(ir, &qm->factor[fun_index]);
4022 dev_err(dev, "failed to calculate shaper parameter!\n");
4026 for (i = ALG_TYPE_0; i <= ALG_TYPE_1; i++) {
4027 /* The base number of queue reuse for different alg type */
4028 ret = qm_set_vft_common(qm, SHAPER_VFT, fun_index, i, 1);
4030 dev_err(dev, "type: %d, failed to set shaper vft!\n", i);
4038 static u32 qm_get_shaper_vft_qos(struct hisi_qm *qm, u32 fun_index)
4040 u64 cir_u = 0, cir_b = 0, cir_s = 0;
4041 u64 shaper_vft, ir_calc, ir;
4046 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
4047 val & BIT(0), POLL_PERIOD,
4052 writel(0x1, qm->io_base + QM_VFT_CFG_OP_WR);
4053 writel(SHAPER_VFT, qm->io_base + QM_VFT_CFG_TYPE);
4054 writel(fun_index, qm->io_base + QM_VFT_CFG);
4056 writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
4057 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
4059 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
4060 val & BIT(0), POLL_PERIOD,
4065 shaper_vft = readl(qm->io_base + QM_VFT_CFG_DATA_L) |
4066 ((u64)readl(qm->io_base + QM_VFT_CFG_DATA_H) << 32);
4068 cir_b = shaper_vft & QM_SHAPER_CIR_B_MASK;
4069 cir_u = shaper_vft & QM_SHAPER_CIR_U_MASK;
4070 cir_u = cir_u >> QM_SHAPER_FACTOR_CIR_U_SHIFT;
4072 cir_s = shaper_vft & QM_SHAPER_CIR_S_MASK;
4073 cir_s = cir_s >> QM_SHAPER_FACTOR_CIR_S_SHIFT;
4075 ir_calc = acc_shaper_para_calc(cir_b, cir_u, cir_s);
4077 ir = qm->factor[fun_index].func_qos * QM_QOS_RATE;
4079 error_rate = QM_QOS_EXPAND_RATE * (u32)abs(ir_calc - ir) / ir;
4080 if (error_rate > QM_QOS_MIN_ERROR_RATE) {
4081 pci_err(qm->pdev, "error_rate: %u, get function qos is error!\n", error_rate);
4088 static void qm_vf_get_qos(struct hisi_qm *qm, u32 fun_num)
4090 struct device *dev = &qm->pdev->dev;
4095 qos = qm_get_shaper_vft_qos(qm, fun_num);
4097 dev_err(dev, "function(%u) failed to get qos by PF!\n", fun_num);
4101 mb_cmd = QM_PF_SET_QOS | (u64)qos << QM_MB_CMD_DATA_SHIFT;
4102 ret = qm_ping_single_vf(qm, mb_cmd, fun_num);
4104 dev_err(dev, "failed to send cmd to VF(%u)!\n", fun_num);
4107 static int qm_vf_read_qos(struct hisi_qm *qm)
4112 /* reset mailbox qos val */
4115 /* vf ping pf to get function qos */
4116 if (qm->ops->ping_pf) {
4117 ret = qm->ops->ping_pf(qm, QM_VF_GET_QOS);
4119 pci_err(qm->pdev, "failed to send cmd to PF to get qos!\n");
4125 msleep(QM_WAIT_DST_ACK);
4129 if (++cnt > QM_MAX_VF_WAIT_COUNT) {
4130 pci_err(qm->pdev, "PF ping VF timeout!\n");
4138 static ssize_t qm_algqos_read(struct file *filp, char __user *buf,
4139 size_t count, loff_t *pos)
4141 struct hisi_qm *qm = filp->private_data;
4142 char tbuf[QM_DBG_READ_LEN];
4146 ret = hisi_qm_get_dfx_access(qm);
4150 /* Mailbox and reset cannot be operated at the same time */
4151 if (test_and_set_bit(QM_RESETTING, &qm->misc_ctl)) {
4152 pci_err(qm->pdev, "dev resetting, read alg qos failed!\n");
4154 goto err_put_dfx_access;
4157 if (qm->fun_type == QM_HW_PF) {
4158 ir = qm_get_shaper_vft_qos(qm, 0);
4160 ret = qm_vf_read_qos(qm);
4162 goto err_get_status;
4166 qos_val = ir / QM_QOS_RATE;
4167 ret = scnprintf(tbuf, QM_DBG_READ_LEN, "%u\n", qos_val);
4169 ret = simple_read_from_buffer(buf, count, pos, tbuf, ret);
4172 clear_bit(QM_RESETTING, &qm->misc_ctl);
4174 hisi_qm_put_dfx_access(qm);
4178 static ssize_t qm_qos_value_init(const char *buf, unsigned long *val)
4180 int buflen = strlen(buf);
4183 for (i = 0; i < buflen; i++) {
4184 if (!isdigit(buf[i]))
4188 ret = sscanf(buf, "%ld", val);
4189 if (ret != QM_QOS_VAL_NUM)
4195 static ssize_t qm_algqos_write(struct file *filp, const char __user *buf,
4196 size_t count, loff_t *pos)
4198 struct hisi_qm *qm = filp->private_data;
4199 char tbuf[QM_DBG_READ_LEN];
4200 int tmp1, bus, device, function;
4201 char tbuf_bdf[QM_DBG_READ_LEN] = {0};
4202 char val_buf[QM_QOS_VAL_MAX_LEN] = {0};
4203 unsigned int fun_index;
4204 unsigned long val = 0;
4207 if (qm->fun_type == QM_HW_VF)
4210 /* Mailbox and reset cannot be operated at the same time */
4211 if (test_and_set_bit(QM_RESETTING, &qm->misc_ctl)) {
4212 pci_err(qm->pdev, "dev resetting, write alg qos failed!\n");
4218 goto err_get_status;
4221 if (count >= QM_DBG_READ_LEN) {
4223 goto err_get_status;
4226 len = simple_write_to_buffer(tbuf, QM_DBG_READ_LEN - 1, pos, buf, count);
4229 goto err_get_status;
4233 ret = sscanf(tbuf, "%s %s", tbuf_bdf, val_buf);
4234 if (ret != QM_QOS_PARAM_NUM) {
4236 goto err_get_status;
4239 ret = qm_qos_value_init(val_buf, &val);
4240 if (val == 0 || val > QM_QOS_MAX_VAL || ret) {
4241 pci_err(qm->pdev, "input qos value is error, please set 1~1000!\n");
4243 goto err_get_status;
4246 ret = sscanf(tbuf_bdf, "%d:%x:%d.%d", &tmp1, &bus, &device, &function);
4247 if (ret != QM_QOS_BDF_PARAM_NUM) {
4248 pci_err(qm->pdev, "input pci bdf value is error!\n");
4250 goto err_get_status;
4253 fun_index = device * 8 + function;
4255 ret = qm_pm_get_sync(qm);
4258 goto err_get_status;
4261 ret = qm_func_shaper_enable(qm, fun_index, val);
4263 pci_err(qm->pdev, "failed to enable function shaper!\n");
4273 clear_bit(QM_RESETTING, &qm->misc_ctl);
4277 static const struct file_operations qm_algqos_fops = {
4278 .owner = THIS_MODULE,
4279 .open = simple_open,
4280 .read = qm_algqos_read,
4281 .write = qm_algqos_write,
4285 * hisi_qm_set_algqos_init() - Initialize function qos debugfs files.
4286 * @qm: The qm for which we want to add debugfs files.
4288 * Create function qos debugfs files.
4290 static void hisi_qm_set_algqos_init(struct hisi_qm *qm)
4292 if (qm->fun_type == QM_HW_PF)
4293 debugfs_create_file("alg_qos", 0644, qm->debug.debug_root,
4294 qm, &qm_algqos_fops);
4296 debugfs_create_file("alg_qos", 0444, qm->debug.debug_root,
4297 qm, &qm_algqos_fops);
4301 * hisi_qm_debug_init() - Initialize qm related debugfs files.
4302 * @qm: The qm for which we want to add debugfs files.
4304 * Create qm related debugfs files.
4306 void hisi_qm_debug_init(struct hisi_qm *qm)
4308 struct qm_dfx *dfx = &qm->debug.dfx;
4309 struct dentry *qm_d;
4313 qm_d = debugfs_create_dir("qm", qm->debug.debug_root);
4314 qm->debug.qm_d = qm_d;
4316 /* only show this in PF */
4317 if (qm->fun_type == QM_HW_PF) {
4318 qm_create_debugfs_file(qm, qm->debug.debug_root, CURRENT_QM);
4319 for (i = CURRENT_Q; i < DEBUG_FILE_NUM; i++)
4320 qm_create_debugfs_file(qm, qm->debug.qm_d, i);
4323 debugfs_create_file("regs", 0444, qm->debug.qm_d, qm, &qm_regs_fops);
4325 debugfs_create_file("cmd", 0600, qm->debug.qm_d, qm, &qm_cmd_fops);
4327 debugfs_create_file("status", 0444, qm->debug.qm_d, qm,
4329 for (i = 0; i < ARRAY_SIZE(qm_dfx_files); i++) {
4330 data = (atomic64_t *)((uintptr_t)dfx + qm_dfx_files[i].offset);
4331 debugfs_create_file(qm_dfx_files[i].name,
4338 if (qm->ver >= QM_HW_V3)
4339 hisi_qm_set_algqos_init(qm);
4341 EXPORT_SYMBOL_GPL(hisi_qm_debug_init);
4344 * hisi_qm_debug_regs_clear() - clear qm debug related registers.
4345 * @qm: The qm for which we want to clear its debug registers.
4347 void hisi_qm_debug_regs_clear(struct hisi_qm *qm)
4349 const struct debugfs_reg32 *regs;
4352 /* clear current_qm */
4353 writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
4354 writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
4356 /* clear current_q */
4357 writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
4358 writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
4361 * these registers are reading and clearing, so clear them after
4364 writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE);
4367 for (i = 0; i < CNT_CYC_REGS_NUM; i++) {
4368 readl(qm->io_base + regs->offset);
4372 /* clear clear_enable */
4373 writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE);
4375 EXPORT_SYMBOL_GPL(hisi_qm_debug_regs_clear);
4378 * hisi_qm_sriov_enable() - enable virtual functions
4379 * @pdev: the PCIe device
4380 * @max_vfs: the number of virtual functions to enable
4382 * Returns the number of enabled VFs. If there are VFs enabled already or
4383 * max_vfs is more than the total number of device can be enabled, returns
4386 int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs)
4388 struct hisi_qm *qm = pci_get_drvdata(pdev);
4389 int pre_existing_vfs, num_vfs, total_vfs, ret;
4391 ret = qm_pm_get_sync(qm);
4395 total_vfs = pci_sriov_get_totalvfs(pdev);
4396 pre_existing_vfs = pci_num_vf(pdev);
4397 if (pre_existing_vfs) {
4398 pci_err(pdev, "%d VFs already enabled. Please disable pre-enabled VFs!\n",
4403 num_vfs = min_t(int, max_vfs, total_vfs);
4404 ret = qm_vf_q_assign(qm, num_vfs);
4406 pci_err(pdev, "Can't assign queues for VF!\n");
4410 qm->vfs_num = num_vfs;
4412 ret = pci_enable_sriov(pdev, num_vfs);
4414 pci_err(pdev, "Can't enable VF!\n");
4415 qm_clear_vft_config(qm);
4419 pci_info(pdev, "VF enabled, vfs_num(=%d)!\n", num_vfs);
4427 EXPORT_SYMBOL_GPL(hisi_qm_sriov_enable);
4430 * hisi_qm_sriov_disable - disable virtual functions
4431 * @pdev: the PCI device.
4432 * @is_frozen: true when all the VFs are frozen.
4434 * Return failure if there are VFs assigned already or VF is in used.
4436 int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen)
4438 struct hisi_qm *qm = pci_get_drvdata(pdev);
4439 int total_vfs = pci_sriov_get_totalvfs(qm->pdev);
4442 if (pci_vfs_assigned(pdev)) {
4443 pci_err(pdev, "Failed to disable VFs as VFs are assigned!\n");
4447 /* While VF is in used, SRIOV cannot be disabled. */
4448 if (!is_frozen && qm_try_frozen_vfs(pdev, qm->qm_list)) {
4449 pci_err(pdev, "Task is using its VF!\n");
4453 pci_disable_sriov(pdev);
4454 /* clear vf function shaper configure array */
4455 memset(qm->factor + 1, 0, sizeof(struct qm_shaper_factor) * total_vfs);
4456 ret = qm_clear_vft_config(qm);
4464 EXPORT_SYMBOL_GPL(hisi_qm_sriov_disable);
4467 * hisi_qm_sriov_configure - configure the number of VFs
4468 * @pdev: The PCI device
4469 * @num_vfs: The number of VFs need enabled
4471 * Enable SR-IOV according to num_vfs, 0 means disable.
4473 int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs)
4476 return hisi_qm_sriov_disable(pdev, false);
4478 return hisi_qm_sriov_enable(pdev, num_vfs);
4480 EXPORT_SYMBOL_GPL(hisi_qm_sriov_configure);
4482 static enum acc_err_result qm_dev_err_handle(struct hisi_qm *qm)
4486 if (!qm->err_ini->get_dev_hw_err_status) {
4487 dev_err(&qm->pdev->dev, "Device doesn't support get hw error status!\n");
4488 return ACC_ERR_NONE;
4491 /* get device hardware error status */
4492 err_sts = qm->err_ini->get_dev_hw_err_status(qm);
4494 if (err_sts & qm->err_info.ecc_2bits_mask)
4495 qm->err_status.is_dev_ecc_mbit = true;
4497 if (qm->err_ini->log_dev_hw_err)
4498 qm->err_ini->log_dev_hw_err(qm, err_sts);
4500 /* ce error does not need to be reset */
4501 if ((err_sts | qm->err_info.dev_ce_mask) ==
4502 qm->err_info.dev_ce_mask) {
4503 if (qm->err_ini->clear_dev_hw_err_status)
4504 qm->err_ini->clear_dev_hw_err_status(qm,
4507 return ACC_ERR_RECOVERED;
4510 return ACC_ERR_NEED_RESET;
4513 return ACC_ERR_RECOVERED;
4516 static enum acc_err_result qm_process_dev_error(struct hisi_qm *qm)
4518 enum acc_err_result qm_ret, dev_ret;
4521 qm_ret = qm_hw_error_handle(qm);
4523 /* log device error */
4524 dev_ret = qm_dev_err_handle(qm);
4526 return (qm_ret == ACC_ERR_NEED_RESET ||
4527 dev_ret == ACC_ERR_NEED_RESET) ?
4528 ACC_ERR_NEED_RESET : ACC_ERR_RECOVERED;
4532 * hisi_qm_dev_err_detected() - Get device and qm error status then log it.
4533 * @pdev: The PCI device which need report error.
4534 * @state: The connectivity between CPU and device.
4536 * We register this function into PCIe AER handlers, It will report device or
4537 * qm hardware error status when error occur.
4539 pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
4540 pci_channel_state_t state)
4542 struct hisi_qm *qm = pci_get_drvdata(pdev);
4543 enum acc_err_result ret;
4545 if (pdev->is_virtfn)
4546 return PCI_ERS_RESULT_NONE;
4548 pci_info(pdev, "PCI error detected, state(=%u)!!\n", state);
4549 if (state == pci_channel_io_perm_failure)
4550 return PCI_ERS_RESULT_DISCONNECT;
4552 ret = qm_process_dev_error(qm);
4553 if (ret == ACC_ERR_NEED_RESET)
4554 return PCI_ERS_RESULT_NEED_RESET;
4556 return PCI_ERS_RESULT_RECOVERED;
4558 EXPORT_SYMBOL_GPL(hisi_qm_dev_err_detected);
4560 static int qm_check_req_recv(struct hisi_qm *qm)
4562 struct pci_dev *pdev = qm->pdev;
4566 if (qm->ver >= QM_HW_V3)
4569 writel(ACC_VENDOR_ID_VALUE, qm->io_base + QM_PEH_VENDOR_ID);
4570 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
4571 (val == ACC_VENDOR_ID_VALUE),
4572 POLL_PERIOD, POLL_TIMEOUT);
4574 dev_err(&pdev->dev, "Fails to read QM reg!\n");
4578 writel(PCI_VENDOR_ID_HUAWEI, qm->io_base + QM_PEH_VENDOR_ID);
4579 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
4580 (val == PCI_VENDOR_ID_HUAWEI),
4581 POLL_PERIOD, POLL_TIMEOUT);
4583 dev_err(&pdev->dev, "Fails to read QM reg in the second time!\n");
4588 static int qm_set_pf_mse(struct hisi_qm *qm, bool set)
4590 struct pci_dev *pdev = qm->pdev;
4594 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
4596 cmd |= PCI_COMMAND_MEMORY;
4598 cmd &= ~PCI_COMMAND_MEMORY;
4600 pci_write_config_word(pdev, PCI_COMMAND, cmd);
4601 for (i = 0; i < MAX_WAIT_COUNTS; i++) {
4602 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
4603 if (set == ((cmd & PCI_COMMAND_MEMORY) >> 1))
4612 static int qm_set_vf_mse(struct hisi_qm *qm, bool set)
4614 struct pci_dev *pdev = qm->pdev;
4619 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
4620 pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &sriov_ctrl);
4622 sriov_ctrl |= PCI_SRIOV_CTRL_MSE;
4624 sriov_ctrl &= ~PCI_SRIOV_CTRL_MSE;
4625 pci_write_config_word(pdev, pos + PCI_SRIOV_CTRL, sriov_ctrl);
4627 for (i = 0; i < MAX_WAIT_COUNTS; i++) {
4628 pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &sriov_ctrl);
4629 if (set == (sriov_ctrl & PCI_SRIOV_CTRL_MSE) >>
4630 ACC_PEH_SRIOV_CTRL_VF_MSE_SHIFT)
4639 static int qm_vf_reset_prepare(struct hisi_qm *qm,
4640 enum qm_stop_reason stop_reason)
4642 struct hisi_qm_list *qm_list = qm->qm_list;
4643 struct pci_dev *pdev = qm->pdev;
4644 struct pci_dev *virtfn;
4645 struct hisi_qm *vf_qm;
4648 mutex_lock(&qm_list->lock);
4649 list_for_each_entry(vf_qm, &qm_list->list, list) {
4650 virtfn = vf_qm->pdev;
4654 if (pci_physfn(virtfn) == pdev) {
4655 /* save VFs PCIE BAR configuration */
4656 pci_save_state(virtfn);
4658 ret = hisi_qm_stop(vf_qm, stop_reason);
4665 mutex_unlock(&qm_list->lock);
4669 static int qm_try_stop_vfs(struct hisi_qm *qm, u64 cmd,
4670 enum qm_stop_reason stop_reason)
4672 struct pci_dev *pdev = qm->pdev;
4678 /* Kunpeng930 supports to notify VFs to stop before PF reset */
4679 if (qm->ops->ping_all_vfs) {
4680 ret = qm->ops->ping_all_vfs(qm, cmd);
4682 pci_err(pdev, "failed to send cmd to all VFs before PF reset!\n");
4684 ret = qm_vf_reset_prepare(qm, stop_reason);
4686 pci_err(pdev, "failed to prepare reset, ret = %d.\n", ret);
4692 static int qm_wait_reset_finish(struct hisi_qm *qm)
4696 /* All reset requests need to be queued for processing */
4697 while (test_and_set_bit(QM_RESETTING, &qm->misc_ctl)) {
4699 if (delay > QM_RESET_WAIT_TIMEOUT)
4706 static int qm_reset_prepare_ready(struct hisi_qm *qm)
4708 struct pci_dev *pdev = qm->pdev;
4709 struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
4712 * PF and VF on host doesnot support resetting at the
4713 * same time on Kunpeng920.
4715 if (qm->ver < QM_HW_V3)
4716 return qm_wait_reset_finish(pf_qm);
4718 return qm_wait_reset_finish(qm);
4721 static void qm_reset_bit_clear(struct hisi_qm *qm)
4723 struct pci_dev *pdev = qm->pdev;
4724 struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
4726 if (qm->ver < QM_HW_V3)
4727 clear_bit(QM_RESETTING, &pf_qm->misc_ctl);
4729 clear_bit(QM_RESETTING, &qm->misc_ctl);
4732 static int qm_controller_reset_prepare(struct hisi_qm *qm)
4734 struct pci_dev *pdev = qm->pdev;
4737 ret = qm_reset_prepare_ready(qm);
4739 pci_err(pdev, "Controller reset not ready!\n");
4743 /* PF obtains the information of VF by querying the register. */
4746 /* Whether VFs stop successfully, soft reset will continue. */
4747 ret = qm_try_stop_vfs(qm, QM_PF_SRST_PREPARE, QM_SOFT_RESET);
4749 pci_err(pdev, "failed to stop vfs by pf in soft reset.\n");
4751 ret = hisi_qm_stop(qm, QM_SOFT_RESET);
4753 pci_err(pdev, "Fails to stop QM!\n");
4754 qm_reset_bit_clear(qm);
4758 ret = qm_wait_vf_prepare_finish(qm);
4760 pci_err(pdev, "failed to stop by vfs in soft reset!\n");
4762 clear_bit(QM_RST_SCHED, &qm->misc_ctl);
4767 static void qm_dev_ecc_mbit_handle(struct hisi_qm *qm)
4771 /* Kunpeng930 hardware automatically close master ooo when NFE occurs */
4772 if (qm->ver >= QM_HW_V3)
4775 if (!qm->err_status.is_dev_ecc_mbit &&
4776 qm->err_status.is_qm_ecc_mbit &&
4777 qm->err_ini->close_axi_master_ooo) {
4779 qm->err_ini->close_axi_master_ooo(qm);
4781 } else if (qm->err_status.is_dev_ecc_mbit &&
4782 !qm->err_status.is_qm_ecc_mbit &&
4783 !qm->err_ini->close_axi_master_ooo) {
4785 nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE);
4786 writel(nfe_enb & QM_RAS_NFE_MBIT_DISABLE,
4787 qm->io_base + QM_RAS_NFE_ENABLE);
4788 writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SET);
4792 static int qm_soft_reset(struct hisi_qm *qm)
4794 struct pci_dev *pdev = qm->pdev;
4798 /* Ensure all doorbells and mailboxes received by QM */
4799 ret = qm_check_req_recv(qm);
4804 ret = qm_set_vf_mse(qm, false);
4806 pci_err(pdev, "Fails to disable vf MSE bit.\n");
4811 ret = qm->ops->set_msi(qm, false);
4813 pci_err(pdev, "Fails to disable PEH MSI bit.\n");
4817 qm_dev_ecc_mbit_handle(qm);
4819 /* OOO register set and check */
4820 writel(ACC_MASTER_GLOBAL_CTRL_SHUTDOWN,
4821 qm->io_base + ACC_MASTER_GLOBAL_CTRL);
4823 /* If bus lock, reset chip */
4824 ret = readl_relaxed_poll_timeout(qm->io_base + ACC_MASTER_TRANS_RETURN,
4826 (val == ACC_MASTER_TRANS_RETURN_RW),
4827 POLL_PERIOD, POLL_TIMEOUT);
4829 pci_emerg(pdev, "Bus lock! Please reset system.\n");
4833 if (qm->err_ini->close_sva_prefetch)
4834 qm->err_ini->close_sva_prefetch(qm);
4836 ret = qm_set_pf_mse(qm, false);
4838 pci_err(pdev, "Fails to disable pf MSE bit.\n");
4842 /* The reset related sub-control registers are not in PCI BAR */
4843 if (ACPI_HANDLE(&pdev->dev)) {
4844 unsigned long long value = 0;
4847 s = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
4848 qm->err_info.acpi_rst,
4850 if (ACPI_FAILURE(s)) {
4851 pci_err(pdev, "NO controller reset method!\n");
4856 pci_err(pdev, "Reset step %llu failed!\n", value);
4860 pci_err(pdev, "No reset method!\n");
4867 static int qm_vf_reset_done(struct hisi_qm *qm)
4869 struct hisi_qm_list *qm_list = qm->qm_list;
4870 struct pci_dev *pdev = qm->pdev;
4871 struct pci_dev *virtfn;
4872 struct hisi_qm *vf_qm;
4875 mutex_lock(&qm_list->lock);
4876 list_for_each_entry(vf_qm, &qm_list->list, list) {
4877 virtfn = vf_qm->pdev;
4881 if (pci_physfn(virtfn) == pdev) {
4882 /* enable VFs PCIE BAR configuration */
4883 pci_restore_state(virtfn);
4885 ret = qm_restart(vf_qm);
4892 mutex_unlock(&qm_list->lock);
4896 static int qm_try_start_vfs(struct hisi_qm *qm, enum qm_mb_cmd cmd)
4898 struct pci_dev *pdev = qm->pdev;
4904 ret = qm_vf_q_assign(qm, qm->vfs_num);
4906 pci_err(pdev, "failed to assign VFs, ret = %d.\n", ret);
4910 /* Kunpeng930 supports to notify VFs to start after PF reset. */
4911 if (qm->ops->ping_all_vfs) {
4912 ret = qm->ops->ping_all_vfs(qm, cmd);
4914 pci_warn(pdev, "failed to send cmd to all VFs after PF reset!\n");
4916 ret = qm_vf_reset_done(qm);
4918 pci_warn(pdev, "failed to start vfs, ret = %d.\n", ret);
4924 static int qm_dev_hw_init(struct hisi_qm *qm)
4926 return qm->err_ini->hw_init(qm);
4929 static void qm_restart_prepare(struct hisi_qm *qm)
4933 if (qm->err_ini->open_sva_prefetch)
4934 qm->err_ini->open_sva_prefetch(qm);
4936 if (qm->ver >= QM_HW_V3)
4939 if (!qm->err_status.is_qm_ecc_mbit &&
4940 !qm->err_status.is_dev_ecc_mbit)
4943 /* temporarily close the OOO port used for PEH to write out MSI */
4944 value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4945 writel(value & ~qm->err_info.msi_wr_port,
4946 qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4948 /* clear dev ecc 2bit error source if having */
4949 value = qm_get_dev_err_status(qm) & qm->err_info.ecc_2bits_mask;
4950 if (value && qm->err_ini->clear_dev_hw_err_status)
4951 qm->err_ini->clear_dev_hw_err_status(qm, value);
4953 /* clear QM ecc mbit error source */
4954 writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SOURCE);
4956 /* clear AM Reorder Buffer ecc mbit source */
4957 writel(ACC_ROB_ECC_ERR_MULTPL, qm->io_base + ACC_AM_ROB_ECC_INT_STS);
4960 static void qm_restart_done(struct hisi_qm *qm)
4964 if (qm->ver >= QM_HW_V3)
4967 if (!qm->err_status.is_qm_ecc_mbit &&
4968 !qm->err_status.is_dev_ecc_mbit)
4971 /* open the OOO port for PEH to write out MSI */
4972 value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4973 value |= qm->err_info.msi_wr_port;
4974 writel(value, qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4977 qm->err_status.is_qm_ecc_mbit = false;
4978 qm->err_status.is_dev_ecc_mbit = false;
4981 static int qm_controller_reset_done(struct hisi_qm *qm)
4983 struct pci_dev *pdev = qm->pdev;
4986 ret = qm->ops->set_msi(qm, true);
4988 pci_err(pdev, "Fails to enable PEH MSI bit!\n");
4992 ret = qm_set_pf_mse(qm, true);
4994 pci_err(pdev, "Fails to enable pf MSE bit!\n");
4999 ret = qm_set_vf_mse(qm, true);
5001 pci_err(pdev, "Fails to enable vf MSE bit!\n");
5006 ret = qm_dev_hw_init(qm);
5008 pci_err(pdev, "Failed to init device\n");
5012 qm_restart_prepare(qm);
5013 hisi_qm_dev_err_init(qm);
5014 if (qm->err_ini->open_axi_master_ooo)
5015 qm->err_ini->open_axi_master_ooo(qm);
5017 ret = qm_restart(qm);
5019 pci_err(pdev, "Failed to start QM!\n");
5023 ret = qm_try_start_vfs(qm, QM_PF_RESET_DONE);
5025 pci_err(pdev, "failed to start vfs by pf in soft reset.\n");
5027 ret = qm_wait_vf_prepare_finish(qm);
5029 pci_err(pdev, "failed to start by vfs in soft reset!\n");
5032 qm_restart_done(qm);
5034 qm_reset_bit_clear(qm);
5039 static int qm_controller_reset(struct hisi_qm *qm)
5041 struct pci_dev *pdev = qm->pdev;
5044 pci_info(pdev, "Controller resetting...\n");
5046 ret = qm_controller_reset_prepare(qm);
5048 clear_bit(QM_RST_SCHED, &qm->misc_ctl);
5052 ret = qm_soft_reset(qm);
5054 pci_err(pdev, "Controller reset failed (%d)\n", ret);
5055 qm_reset_bit_clear(qm);
5059 ret = qm_controller_reset_done(qm);
5061 qm_reset_bit_clear(qm);
5065 pci_info(pdev, "Controller reset complete\n");
5071 * hisi_qm_dev_slot_reset() - slot reset
5072 * @pdev: the PCIe device
5074 * This function offers QM relate PCIe device reset interface. Drivers which
5075 * use QM can use this function as slot_reset in its struct pci_error_handlers.
5077 pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev)
5079 struct hisi_qm *qm = pci_get_drvdata(pdev);
5082 if (pdev->is_virtfn)
5083 return PCI_ERS_RESULT_RECOVERED;
5085 pci_aer_clear_nonfatal_status(pdev);
5087 /* reset pcie device controller */
5088 ret = qm_controller_reset(qm);
5090 pci_err(pdev, "Controller reset failed (%d)\n", ret);
5091 return PCI_ERS_RESULT_DISCONNECT;
5094 return PCI_ERS_RESULT_RECOVERED;
5096 EXPORT_SYMBOL_GPL(hisi_qm_dev_slot_reset);
5098 void hisi_qm_reset_prepare(struct pci_dev *pdev)
5100 struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
5101 struct hisi_qm *qm = pci_get_drvdata(pdev);
5105 hisi_qm_dev_err_uninit(pf_qm);
5108 * Check whether there is an ECC mbit error, If it occurs, need to
5109 * wait for soft reset to fix it.
5111 while (qm_check_dev_error(pf_qm)) {
5113 if (delay > QM_RESET_WAIT_TIMEOUT)
5117 ret = qm_reset_prepare_ready(qm);
5119 pci_err(pdev, "FLR not ready!\n");
5123 /* PF obtains the information of VF by querying the register. */
5124 if (qm->fun_type == QM_HW_PF)
5127 ret = qm_try_stop_vfs(qm, QM_PF_FLR_PREPARE, QM_FLR);
5129 pci_err(pdev, "failed to stop vfs by pf in FLR.\n");
5131 ret = hisi_qm_stop(qm, QM_FLR);
5133 pci_err(pdev, "Failed to stop QM, ret = %d.\n", ret);
5137 ret = qm_wait_vf_prepare_finish(qm);
5139 pci_err(pdev, "failed to stop by vfs in FLR!\n");
5141 pci_info(pdev, "FLR resetting...\n");
5143 EXPORT_SYMBOL_GPL(hisi_qm_reset_prepare);
5145 static bool qm_flr_reset_complete(struct pci_dev *pdev)
5147 struct pci_dev *pf_pdev = pci_physfn(pdev);
5148 struct hisi_qm *qm = pci_get_drvdata(pf_pdev);
5151 pci_read_config_dword(qm->pdev, PCI_COMMAND, &id);
5152 if (id == QM_PCI_COMMAND_INVALID) {
5153 pci_err(pdev, "Device can not be used!\n");
5160 void hisi_qm_reset_done(struct pci_dev *pdev)
5162 struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
5163 struct hisi_qm *qm = pci_get_drvdata(pdev);
5166 if (qm->fun_type == QM_HW_PF) {
5167 ret = qm_dev_hw_init(qm);
5169 pci_err(pdev, "Failed to init PF, ret = %d.\n", ret);
5174 hisi_qm_dev_err_init(pf_qm);
5176 ret = qm_restart(qm);
5178 pci_err(pdev, "Failed to start QM, ret = %d.\n", ret);
5182 ret = qm_try_start_vfs(qm, QM_PF_RESET_DONE);
5184 pci_err(pdev, "failed to start vfs by pf in FLR.\n");
5186 ret = qm_wait_vf_prepare_finish(qm);
5188 pci_err(pdev, "failed to start by vfs in FLR!\n");
5191 if (qm->fun_type == QM_HW_PF)
5194 if (qm_flr_reset_complete(pdev))
5195 pci_info(pdev, "FLR reset complete\n");
5197 qm_reset_bit_clear(qm);
5199 EXPORT_SYMBOL_GPL(hisi_qm_reset_done);
5201 static irqreturn_t qm_abnormal_irq(int irq, void *data)
5203 struct hisi_qm *qm = data;
5204 enum acc_err_result ret;
5206 atomic64_inc(&qm->debug.dfx.abnormal_irq_cnt);
5207 ret = qm_process_dev_error(qm);
5208 if (ret == ACC_ERR_NEED_RESET &&
5209 !test_bit(QM_DRIVER_REMOVING, &qm->misc_ctl) &&
5210 !test_and_set_bit(QM_RST_SCHED, &qm->misc_ctl))
5211 schedule_work(&qm->rst_work);
5216 static int qm_irq_register(struct hisi_qm *qm)
5218 struct pci_dev *pdev = qm->pdev;
5221 ret = request_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR),
5222 qm_irq, 0, qm->dev_name, qm);
5226 if (qm->ver > QM_HW_V1) {
5227 ret = request_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR),
5228 qm_aeq_irq, 0, qm->dev_name, qm);
5232 if (qm->fun_type == QM_HW_PF) {
5233 ret = request_irq(pci_irq_vector(pdev,
5234 QM_ABNORMAL_EVENT_IRQ_VECTOR),
5235 qm_abnormal_irq, 0, qm->dev_name, qm);
5237 goto err_abonormal_irq;
5241 if (qm->ver > QM_HW_V2) {
5242 ret = request_irq(pci_irq_vector(pdev, QM_CMD_EVENT_IRQ_VECTOR),
5243 qm_mb_cmd_irq, 0, qm->dev_name, qm);
5245 goto err_mb_cmd_irq;
5251 if (qm->fun_type == QM_HW_PF)
5252 free_irq(pci_irq_vector(pdev, QM_ABNORMAL_EVENT_IRQ_VECTOR), qm);
5254 free_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR), qm);
5256 free_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR), qm);
5261 * hisi_qm_dev_shutdown() - Shutdown device.
5262 * @pdev: The device will be shutdown.
5264 * This function will stop qm when OS shutdown or rebooting.
5266 void hisi_qm_dev_shutdown(struct pci_dev *pdev)
5268 struct hisi_qm *qm = pci_get_drvdata(pdev);
5271 ret = hisi_qm_stop(qm, QM_NORMAL);
5273 dev_err(&pdev->dev, "Fail to stop qm in shutdown!\n");
5275 EXPORT_SYMBOL_GPL(hisi_qm_dev_shutdown);
5277 static void hisi_qm_controller_reset(struct work_struct *rst_work)
5279 struct hisi_qm *qm = container_of(rst_work, struct hisi_qm, rst_work);
5282 ret = qm_pm_get_sync(qm);
5284 clear_bit(QM_RST_SCHED, &qm->misc_ctl);
5288 /* reset pcie device controller */
5289 ret = qm_controller_reset(qm);
5291 dev_err(&qm->pdev->dev, "controller reset failed (%d)\n", ret);
5296 static void qm_pf_reset_vf_prepare(struct hisi_qm *qm,
5297 enum qm_stop_reason stop_reason)
5299 enum qm_mb_cmd cmd = QM_VF_PREPARE_DONE;
5300 struct pci_dev *pdev = qm->pdev;
5303 ret = qm_reset_prepare_ready(qm);
5305 dev_err(&pdev->dev, "reset prepare not ready!\n");
5306 atomic_set(&qm->status.flags, QM_STOP);
5307 cmd = QM_VF_PREPARE_FAIL;
5311 ret = hisi_qm_stop(qm, stop_reason);
5313 dev_err(&pdev->dev, "failed to stop QM, ret = %d.\n", ret);
5314 atomic_set(&qm->status.flags, QM_STOP);
5315 cmd = QM_VF_PREPARE_FAIL;
5320 pci_save_state(pdev);
5321 ret = qm->ops->ping_pf(qm, cmd);
5323 dev_warn(&pdev->dev, "PF responds timeout in reset prepare!\n");
5326 static void qm_pf_reset_vf_done(struct hisi_qm *qm)
5328 enum qm_mb_cmd cmd = QM_VF_START_DONE;
5329 struct pci_dev *pdev = qm->pdev;
5332 pci_restore_state(pdev);
5333 ret = hisi_qm_start(qm);
5335 dev_err(&pdev->dev, "failed to start QM, ret = %d.\n", ret);
5336 cmd = QM_VF_START_FAIL;
5339 ret = qm->ops->ping_pf(qm, cmd);
5341 dev_warn(&pdev->dev, "PF responds timeout in reset done!\n");
5343 qm_reset_bit_clear(qm);
5346 static int qm_wait_pf_reset_finish(struct hisi_qm *qm)
5348 struct device *dev = &qm->pdev->dev;
5353 /* Wait for reset to finish */
5354 ret = readl_relaxed_poll_timeout(qm->io_base + QM_IFC_INT_SOURCE_V, val,
5355 val == BIT(0), QM_VF_RESET_WAIT_US,
5356 QM_VF_RESET_WAIT_TIMEOUT_US);
5357 /* hardware completion status should be available by this time */
5359 dev_err(dev, "couldn't get reset done status from PF, timeout!\n");
5364 * Whether message is got successfully,
5365 * VF needs to ack PF by clearing the interrupt.
5367 ret = qm_get_mb_cmd(qm, &msg, 0);
5368 qm_clear_cmd_interrupt(qm, 0);
5370 dev_err(dev, "failed to get msg from PF in reset done!\n");
5374 cmd = msg & QM_MB_CMD_DATA_MASK;
5375 if (cmd != QM_PF_RESET_DONE) {
5376 dev_err(dev, "the cmd(%u) is not reset done!\n", cmd);
5383 static void qm_pf_reset_vf_process(struct hisi_qm *qm,
5384 enum qm_stop_reason stop_reason)
5386 struct device *dev = &qm->pdev->dev;
5389 dev_info(dev, "device reset start...\n");
5391 /* The message is obtained by querying the register during resetting */
5393 qm_pf_reset_vf_prepare(qm, stop_reason);
5395 ret = qm_wait_pf_reset_finish(qm);
5397 goto err_get_status;
5399 qm_pf_reset_vf_done(qm);
5402 dev_info(dev, "device reset done.\n");
5408 qm_reset_bit_clear(qm);
5411 static void qm_handle_cmd_msg(struct hisi_qm *qm, u32 fun_num)
5413 struct device *dev = &qm->pdev->dev;
5419 * Get the msg from source by sending mailbox. Whether message is got
5420 * successfully, destination needs to ack source by clearing the interrupt.
5422 ret = qm_get_mb_cmd(qm, &msg, fun_num);
5423 qm_clear_cmd_interrupt(qm, BIT(fun_num));
5425 dev_err(dev, "failed to get msg from source!\n");
5429 cmd = msg & QM_MB_CMD_DATA_MASK;
5431 case QM_PF_FLR_PREPARE:
5432 qm_pf_reset_vf_process(qm, QM_FLR);
5434 case QM_PF_SRST_PREPARE:
5435 qm_pf_reset_vf_process(qm, QM_SOFT_RESET);
5438 qm_vf_get_qos(qm, fun_num);
5441 qm->mb_qos = msg >> QM_MB_CMD_DATA_SHIFT;
5444 dev_err(dev, "unsupported cmd %u sent by function(%u)!\n", cmd, fun_num);
5449 static void qm_cmd_process(struct work_struct *cmd_process)
5451 struct hisi_qm *qm = container_of(cmd_process,
5452 struct hisi_qm, cmd_process);
5453 u32 vfs_num = qm->vfs_num;
5457 if (qm->fun_type == QM_HW_PF) {
5458 val = readq(qm->io_base + QM_IFC_INT_SOURCE_P);
5462 for (i = 1; i <= vfs_num; i++) {
5464 qm_handle_cmd_msg(qm, i);
5470 qm_handle_cmd_msg(qm, 0);
5474 * hisi_qm_alg_register() - Register alg to crypto and add qm to qm_list.
5475 * @qm: The qm needs add.
5476 * @qm_list: The qm list.
5478 * This function adds qm to qm list, and will register algorithm to
5479 * crypto when the qm list is empty.
5481 int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
5483 struct device *dev = &qm->pdev->dev;
5487 mutex_lock(&qm_list->lock);
5488 if (list_empty(&qm_list->list))
5490 list_add_tail(&qm->list, &qm_list->list);
5491 mutex_unlock(&qm_list->lock);
5493 if (qm->ver <= QM_HW_V2 && qm->use_sva) {
5494 dev_info(dev, "HW V2 not both use uacce sva mode and hardware crypto algs.\n");
5499 ret = qm_list->register_to_crypto(qm);
5501 mutex_lock(&qm_list->lock);
5502 list_del(&qm->list);
5503 mutex_unlock(&qm_list->lock);
5509 EXPORT_SYMBOL_GPL(hisi_qm_alg_register);
5512 * hisi_qm_alg_unregister() - Unregister alg from crypto and delete qm from
5514 * @qm: The qm needs delete.
5515 * @qm_list: The qm list.
5517 * This function deletes qm from qm list, and will unregister algorithm
5518 * from crypto when the qm list is empty.
5520 void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
5522 mutex_lock(&qm_list->lock);
5523 list_del(&qm->list);
5524 mutex_unlock(&qm_list->lock);
5526 if (qm->ver <= QM_HW_V2 && qm->use_sva)
5529 if (list_empty(&qm_list->list))
5530 qm_list->unregister_from_crypto(qm);
5532 EXPORT_SYMBOL_GPL(hisi_qm_alg_unregister);
5534 static int qm_get_qp_num(struct hisi_qm *qm)
5536 if (qm->ver == QM_HW_V1)
5537 qm->ctrl_qp_num = QM_QNUM_V1;
5538 else if (qm->ver == QM_HW_V2)
5539 qm->ctrl_qp_num = QM_QNUM_V2;
5541 qm->ctrl_qp_num = readl(qm->io_base + QM_CAPBILITY) &
5544 if (qm->use_db_isolation)
5545 qm->max_qp_num = (readl(qm->io_base + QM_CAPBILITY) >>
5546 QM_QP_MAX_NUM_SHIFT) & QM_QP_NUN_MASK;
5548 qm->max_qp_num = qm->ctrl_qp_num;
5550 /* check if qp number is valid */
5551 if (qm->qp_num > qm->max_qp_num) {
5552 dev_err(&qm->pdev->dev, "qp num(%u) is more than max qp num(%u)!\n",
5553 qm->qp_num, qm->max_qp_num);
5560 static int qm_get_pci_res(struct hisi_qm *qm)
5562 struct pci_dev *pdev = qm->pdev;
5563 struct device *dev = &pdev->dev;
5566 ret = pci_request_mem_regions(pdev, qm->dev_name);
5568 dev_err(dev, "Failed to request mem regions!\n");
5572 qm->phys_base = pci_resource_start(pdev, PCI_BAR_2);
5573 qm->io_base = ioremap(qm->phys_base, pci_resource_len(pdev, PCI_BAR_2));
5576 goto err_request_mem_regions;
5579 if (qm->ver > QM_HW_V2) {
5580 if (qm->fun_type == QM_HW_PF)
5581 qm->use_db_isolation = readl(qm->io_base +
5582 QM_QUE_ISO_EN) & BIT(0);
5584 qm->use_db_isolation = readl(qm->io_base +
5585 QM_QUE_ISO_CFG_V) & BIT(0);
5588 if (qm->use_db_isolation) {
5589 qm->db_interval = QM_QP_DB_INTERVAL;
5590 qm->db_phys_base = pci_resource_start(pdev, PCI_BAR_4);
5591 qm->db_io_base = ioremap(qm->db_phys_base,
5592 pci_resource_len(pdev, PCI_BAR_4));
5593 if (!qm->db_io_base) {
5598 qm->db_phys_base = qm->phys_base;
5599 qm->db_io_base = qm->io_base;
5600 qm->db_interval = 0;
5603 if (qm->fun_type == QM_HW_PF) {
5604 ret = qm_get_qp_num(qm);
5606 goto err_db_ioremap;
5612 if (qm->use_db_isolation)
5613 iounmap(qm->db_io_base);
5615 iounmap(qm->io_base);
5616 err_request_mem_regions:
5617 pci_release_mem_regions(pdev);
5621 static int hisi_qm_pci_init(struct hisi_qm *qm)
5623 struct pci_dev *pdev = qm->pdev;
5624 struct device *dev = &pdev->dev;
5625 unsigned int num_vec;
5628 ret = pci_enable_device_mem(pdev);
5630 dev_err(dev, "Failed to enable device mem!\n");
5634 ret = qm_get_pci_res(qm);
5636 goto err_disable_pcidev;
5638 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
5640 goto err_get_pci_res;
5641 pci_set_master(pdev);
5643 if (!qm->ops->get_irq_num) {
5645 goto err_get_pci_res;
5647 num_vec = qm->ops->get_irq_num(qm);
5648 ret = pci_alloc_irq_vectors(pdev, num_vec, num_vec, PCI_IRQ_MSI);
5650 dev_err(dev, "Failed to enable MSI vectors!\n");
5651 goto err_get_pci_res;
5659 pci_disable_device(pdev);
5663 static void hisi_qm_init_work(struct hisi_qm *qm)
5665 INIT_WORK(&qm->work, qm_work_process);
5666 if (qm->fun_type == QM_HW_PF)
5667 INIT_WORK(&qm->rst_work, hisi_qm_controller_reset);
5669 if (qm->ver > QM_HW_V2)
5670 INIT_WORK(&qm->cmd_process, qm_cmd_process);
5673 static int hisi_qp_alloc_memory(struct hisi_qm *qm)
5675 struct device *dev = &qm->pdev->dev;
5679 qm->qp_array = kcalloc(qm->qp_num, sizeof(struct hisi_qp), GFP_KERNEL);
5683 /* one more page for device or qp statuses */
5684 qp_dma_size = qm->sqe_size * QM_Q_DEPTH +
5685 sizeof(struct qm_cqe) * QM_Q_DEPTH;
5686 qp_dma_size = PAGE_ALIGN(qp_dma_size) + PAGE_SIZE;
5687 for (i = 0; i < qm->qp_num; i++) {
5688 ret = hisi_qp_memory_init(qm, qp_dma_size, i);
5690 goto err_init_qp_mem;
5692 dev_dbg(dev, "allocate qp dma buf size=%zx)\n", qp_dma_size);
5697 hisi_qp_memory_uninit(qm, i);
5702 static int hisi_qm_memory_init(struct hisi_qm *qm)
5704 struct device *dev = &qm->pdev->dev;
5708 total_vfs = pci_sriov_get_totalvfs(qm->pdev);
5709 qm->factor = kcalloc(total_vfs + 1, sizeof(struct qm_shaper_factor), GFP_KERNEL);
5713 #define QM_INIT_BUF(qm, type, num) do { \
5714 (qm)->type = ((qm)->qdma.va + (off)); \
5715 (qm)->type##_dma = (qm)->qdma.dma + (off); \
5716 off += QMC_ALIGN(sizeof(struct qm_##type) * (num)); \
5719 idr_init(&qm->qp_idr);
5720 qm->qdma.size = QMC_ALIGN(sizeof(struct qm_eqe) * QM_EQ_DEPTH) +
5721 QMC_ALIGN(sizeof(struct qm_aeqe) * QM_Q_DEPTH) +
5722 QMC_ALIGN(sizeof(struct qm_sqc) * qm->qp_num) +
5723 QMC_ALIGN(sizeof(struct qm_cqc) * qm->qp_num);
5724 qm->qdma.va = dma_alloc_coherent(dev, qm->qdma.size, &qm->qdma.dma,
5726 dev_dbg(dev, "allocate qm dma buf size=%zx)\n", qm->qdma.size);
5729 goto err_alloc_qdma;
5732 QM_INIT_BUF(qm, eqe, QM_EQ_DEPTH);
5733 QM_INIT_BUF(qm, aeqe, QM_Q_DEPTH);
5734 QM_INIT_BUF(qm, sqc, qm->qp_num);
5735 QM_INIT_BUF(qm, cqc, qm->qp_num);
5737 ret = hisi_qp_alloc_memory(qm);
5739 goto err_alloc_qp_array;
5744 dma_free_coherent(dev, qm->qdma.size, qm->qdma.va, qm->qdma.dma);
5752 * hisi_qm_init() - Initialize configures about qm.
5753 * @qm: The qm needing init.
5755 * This function init qm, then we can call hisi_qm_start to put qm into work.
5757 int hisi_qm_init(struct hisi_qm *qm)
5759 struct pci_dev *pdev = qm->pdev;
5760 struct device *dev = &pdev->dev;
5763 hisi_qm_pre_init(qm);
5765 ret = hisi_qm_pci_init(qm);
5769 ret = qm_irq_register(qm);
5773 if (qm->fun_type == QM_HW_VF && qm->ver != QM_HW_V1) {
5774 /* v2 starts to support get vft by mailbox */
5775 ret = hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
5777 goto err_irq_register;
5780 ret = qm_alloc_uacce(qm);
5782 dev_warn(dev, "fail to alloc uacce (%d)\n", ret);
5784 ret = hisi_qm_memory_init(qm);
5786 goto err_alloc_uacce;
5788 hisi_qm_init_work(qm);
5790 atomic_set(&qm->status.flags, QM_INIT);
5795 uacce_remove(qm->uacce);
5798 qm_irq_unregister(qm);
5800 hisi_qm_pci_uninit(qm);
5803 EXPORT_SYMBOL_GPL(hisi_qm_init);
5806 * hisi_qm_get_dfx_access() - Try to get dfx access.
5807 * @qm: pointer to accelerator device.
5809 * Try to get dfx access, then user can get message.
5811 * If device is in suspended, return failure, otherwise
5812 * bump up the runtime PM usage counter.
5814 int hisi_qm_get_dfx_access(struct hisi_qm *qm)
5816 struct device *dev = &qm->pdev->dev;
5818 if (pm_runtime_suspended(dev)) {
5819 dev_info(dev, "can not read/write - device in suspended.\n");
5823 return qm_pm_get_sync(qm);
5825 EXPORT_SYMBOL_GPL(hisi_qm_get_dfx_access);
5828 * hisi_qm_put_dfx_access() - Put dfx access.
5829 * @qm: pointer to accelerator device.
5831 * Put dfx access, drop runtime PM usage counter.
5833 void hisi_qm_put_dfx_access(struct hisi_qm *qm)
5837 EXPORT_SYMBOL_GPL(hisi_qm_put_dfx_access);
5840 * hisi_qm_pm_init() - Initialize qm runtime PM.
5841 * @qm: pointer to accelerator device.
5843 * Function that initialize qm runtime PM.
5845 void hisi_qm_pm_init(struct hisi_qm *qm)
5847 struct device *dev = &qm->pdev->dev;
5849 if (qm->fun_type == QM_HW_VF || qm->ver < QM_HW_V3)
5852 pm_runtime_set_autosuspend_delay(dev, QM_AUTOSUSPEND_DELAY);
5853 pm_runtime_use_autosuspend(dev);
5854 pm_runtime_put_noidle(dev);
5856 EXPORT_SYMBOL_GPL(hisi_qm_pm_init);
5859 * hisi_qm_pm_uninit() - Uninitialize qm runtime PM.
5860 * @qm: pointer to accelerator device.
5862 * Function that uninitialize qm runtime PM.
5864 void hisi_qm_pm_uninit(struct hisi_qm *qm)
5866 struct device *dev = &qm->pdev->dev;
5868 if (qm->fun_type == QM_HW_VF || qm->ver < QM_HW_V3)
5871 pm_runtime_get_noresume(dev);
5872 pm_runtime_dont_use_autosuspend(dev);
5874 EXPORT_SYMBOL_GPL(hisi_qm_pm_uninit);
5876 static int qm_prepare_for_suspend(struct hisi_qm *qm)
5878 struct pci_dev *pdev = qm->pdev;
5882 ret = qm->ops->set_msi(qm, false);
5884 pci_err(pdev, "failed to disable MSI before suspending!\n");
5888 /* shutdown OOO register */
5889 writel(ACC_MASTER_GLOBAL_CTRL_SHUTDOWN,
5890 qm->io_base + ACC_MASTER_GLOBAL_CTRL);
5892 ret = readl_relaxed_poll_timeout(qm->io_base + ACC_MASTER_TRANS_RETURN,
5894 (val == ACC_MASTER_TRANS_RETURN_RW),
5895 POLL_PERIOD, POLL_TIMEOUT);
5897 pci_emerg(pdev, "Bus lock! Please reset system.\n");
5901 ret = qm_set_pf_mse(qm, false);
5903 pci_err(pdev, "failed to disable MSE before suspending!\n");
5908 static int qm_rebuild_for_resume(struct hisi_qm *qm)
5910 struct pci_dev *pdev = qm->pdev;
5913 ret = qm_set_pf_mse(qm, true);
5915 pci_err(pdev, "failed to enable MSE after resuming!\n");
5919 ret = qm->ops->set_msi(qm, true);
5921 pci_err(pdev, "failed to enable MSI after resuming!\n");
5925 ret = qm_dev_hw_init(qm);
5927 pci_err(pdev, "failed to init device after resuming\n");
5932 hisi_qm_dev_err_init(qm);
5938 * hisi_qm_suspend() - Runtime suspend of given device.
5939 * @dev: device to suspend.
5941 * Function that suspend the device.
5943 int hisi_qm_suspend(struct device *dev)
5945 struct pci_dev *pdev = to_pci_dev(dev);
5946 struct hisi_qm *qm = pci_get_drvdata(pdev);
5949 pci_info(pdev, "entering suspended state\n");
5951 ret = hisi_qm_stop(qm, QM_NORMAL);
5953 pci_err(pdev, "failed to stop qm(%d)\n", ret);
5957 ret = qm_prepare_for_suspend(qm);
5959 pci_err(pdev, "failed to prepare suspended(%d)\n", ret);
5963 EXPORT_SYMBOL_GPL(hisi_qm_suspend);
5966 * hisi_qm_resume() - Runtime resume of given device.
5967 * @dev: device to resume.
5969 * Function that resume the device.
5971 int hisi_qm_resume(struct device *dev)
5973 struct pci_dev *pdev = to_pci_dev(dev);
5974 struct hisi_qm *qm = pci_get_drvdata(pdev);
5977 pci_info(pdev, "resuming from suspend state\n");
5979 ret = qm_rebuild_for_resume(qm);
5981 pci_err(pdev, "failed to rebuild resume(%d)\n", ret);
5985 ret = hisi_qm_start(qm);
5987 pci_err(pdev, "failed to start qm(%d)\n", ret);
5991 EXPORT_SYMBOL_GPL(hisi_qm_resume);
5993 MODULE_LICENSE("GPL v2");
5994 MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
5995 MODULE_DESCRIPTION("HiSilicon Accelerator queue manager driver");