drivers/crypto/hifn_795x.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
   4  * All rights reserved.
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/module.h>
   9 #include <linux/moduleparam.h>
  10 #include <linux/mod_devicetable.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/pci.h>
  13 #include <linux/slab.h>
  14 #include <linux/delay.h>
  15 #include <linux/mm.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/scatterlist.h>
  18 #include <linux/highmem.h>
  19 #include <linux/crypto.h>
  20 #include <linux/hw_random.h>
  21 #include <linux/ktime.h>
  22
  23 #include <crypto/algapi.h>
  24 #include <crypto/internal/des.h>
  25 #include <crypto/internal/skcipher.h>
  26
  27 static char hifn_pll_ref[sizeof("extNNN")] = "ext";
  28 module_param_string(hifn_pll_ref, hifn_pll_ref, sizeof(hifn_pll_ref), 0444);
  29 MODULE_PARM_DESC(hifn_pll_ref,
  30                  "PLL reference clock (pci[freq] or ext[freq], default ext)");
  31
  32 static atomic_t hifn_dev_number;
  33
  34 #define ACRYPTO_OP_DECRYPT      0
  35 #define ACRYPTO_OP_ENCRYPT      1
  36 #define ACRYPTO_OP_HMAC         2
  37 #define ACRYPTO_OP_RNG          3
  38
  39 #define ACRYPTO_MODE_ECB                0
  40 #define ACRYPTO_MODE_CBC                1
  41 #define ACRYPTO_MODE_CFB                2
  42 #define ACRYPTO_MODE_OFB                3
  43
  44 #define ACRYPTO_TYPE_AES_128    0
  45 #define ACRYPTO_TYPE_AES_192    1
  46 #define ACRYPTO_TYPE_AES_256    2
  47 #define ACRYPTO_TYPE_3DES       3
  48 #define ACRYPTO_TYPE_DES        4
  49
  50 #define PCI_VENDOR_ID_HIFN              0x13A3
  51 #define PCI_DEVICE_ID_HIFN_7955         0x0020
  52 #define PCI_DEVICE_ID_HIFN_7956         0x001d
  53
  54 /* I/O region sizes */
  55
  56 #define HIFN_BAR0_SIZE                  0x1000
  57 #define HIFN_BAR1_SIZE                  0x2000
  58 #define HIFN_BAR2_SIZE                  0x8000
  59
  60 /* DMA registres */
  61
  62 #define HIFN_DMA_CRA                    0x0C    /* DMA Command Ring Address */
  63 #define HIFN_DMA_SDRA                   0x1C    /* DMA Source Data Ring Address */
  64 #define HIFN_DMA_RRA                    0x2C    /* DMA Result Ring Address */
  65 #define HIFN_DMA_DDRA                   0x3C    /* DMA Destination Data Ring Address */
  66 #define HIFN_DMA_STCTL                  0x40    /* DMA Status and Control */
  67 #define HIFN_DMA_INTREN                 0x44    /* DMA Interrupt Enable */
  68 #define HIFN_DMA_CFG1                   0x48    /* DMA Configuration #1 */
  69 #define HIFN_DMA_CFG2                   0x6C    /* DMA Configuration #2 */
  70 #define HIFN_CHIP_ID                    0x98    /* Chip ID */
  71
  72 /*
  73  * Processing Unit Registers (offset from BASEREG0)
  74  */
  75 #define HIFN_0_PUDATA           0x00    /* Processing Unit Data */
  76 #define HIFN_0_PUCTRL           0x04    /* Processing Unit Control */
  77 #define HIFN_0_PUISR            0x08    /* Processing Unit Interrupt Status */
  78 #define HIFN_0_PUCNFG           0x0c    /* Processing Unit Configuration */
  79 #define HIFN_0_PUIER            0x10    /* Processing Unit Interrupt Enable */
  80 #define HIFN_0_PUSTAT           0x14    /* Processing Unit Status/Chip ID */
  81 #define HIFN_0_FIFOSTAT         0x18    /* FIFO Status */
  82 #define HIFN_0_FIFOCNFG         0x1c    /* FIFO Configuration */
  83 #define HIFN_0_SPACESIZE        0x20    /* Register space size */
  84
  85 /* Processing Unit Control Register (HIFN_0_PUCTRL) */
  86 #define HIFN_PUCTRL_CLRSRCFIFO  0x0010  /* clear source fifo */
  87 #define HIFN_PUCTRL_STOP        0x0008  /* stop pu */
  88 #define HIFN_PUCTRL_LOCKRAM     0x0004  /* lock ram */
  89 #define HIFN_PUCTRL_DMAENA      0x0002  /* enable dma */
  90 #define HIFN_PUCTRL_RESET       0x0001  /* Reset processing unit */
  91
  92 /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
  93 #define HIFN_PUISR_CMDINVAL     0x8000  /* Invalid command interrupt */
  94 #define HIFN_PUISR_DATAERR      0x4000  /* Data error interrupt */
  95 #define HIFN_PUISR_SRCFIFO      0x2000  /* Source FIFO ready interrupt */
  96 #define HIFN_PUISR_DSTFIFO      0x1000  /* Destination FIFO ready interrupt */
  97 #define HIFN_PUISR_DSTOVER      0x0200  /* Destination overrun interrupt */
  98 #define HIFN_PUISR_SRCCMD       0x0080  /* Source command interrupt */
  99 #define HIFN_PUISR_SRCCTX       0x0040  /* Source context interrupt */
 100 #define HIFN_PUISR_SRCDATA      0x0020  /* Source data interrupt */
 101 #define HIFN_PUISR_DSTDATA      0x0010  /* Destination data interrupt */
 102 #define HIFN_PUISR_DSTRESULT    0x0004  /* Destination result interrupt */
 103
 104 /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
 105 #define HIFN_PUCNFG_DRAMMASK    0xe000  /* DRAM size mask */
 106 #define HIFN_PUCNFG_DSZ_256K    0x0000  /* 256k dram */
 107 #define HIFN_PUCNFG_DSZ_512K    0x2000  /* 512k dram */
 108 #define HIFN_PUCNFG_DSZ_1M      0x4000  /* 1m dram */
 109 #define HIFN_PUCNFG_DSZ_2M      0x6000  /* 2m dram */
 110 #define HIFN_PUCNFG_DSZ_4M      0x8000  /* 4m dram */
 111 #define HIFN_PUCNFG_DSZ_8M      0xa000  /* 8m dram */
 112 #define HIFN_PUNCFG_DSZ_16M     0xc000  /* 16m dram */
 113 #define HIFN_PUCNFG_DSZ_32M     0xe000  /* 32m dram */
 114 #define HIFN_PUCNFG_DRAMREFRESH 0x1800  /* DRAM refresh rate mask */
 115 #define HIFN_PUCNFG_DRFR_512    0x0000  /* 512 divisor of ECLK */
 116 #define HIFN_PUCNFG_DRFR_256    0x0800  /* 256 divisor of ECLK */
 117 #define HIFN_PUCNFG_DRFR_128    0x1000  /* 128 divisor of ECLK */
 118 #define HIFN_PUCNFG_TCALLPHASES 0x0200  /* your guess is as good as mine... */
 119 #define HIFN_PUCNFG_TCDRVTOTEM  0x0100  /* your guess is as good as mine... */
 120 #define HIFN_PUCNFG_BIGENDIAN   0x0080  /* DMA big endian mode */
 121 #define HIFN_PUCNFG_BUS32       0x0040  /* Bus width 32bits */
 122 #define HIFN_PUCNFG_BUS16       0x0000  /* Bus width 16 bits */
 123 #define HIFN_PUCNFG_CHIPID      0x0020  /* Allow chipid from PUSTAT */
 124 #define HIFN_PUCNFG_DRAM        0x0010  /* Context RAM is DRAM */
 125 #define HIFN_PUCNFG_SRAM        0x0000  /* Context RAM is SRAM */
 126 #define HIFN_PUCNFG_COMPSING    0x0004  /* Enable single compression context */
 127 #define HIFN_PUCNFG_ENCCNFG     0x0002  /* Encryption configuration */
 128
 129 /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
 130 #define HIFN_PUIER_CMDINVAL     0x8000  /* Invalid command interrupt */
 131 #define HIFN_PUIER_DATAERR      0x4000  /* Data error interrupt */
 132 #define HIFN_PUIER_SRCFIFO      0x2000  /* Source FIFO ready interrupt */
 133 #define HIFN_PUIER_DSTFIFO      0x1000  /* Destination FIFO ready interrupt */
 134 #define HIFN_PUIER_DSTOVER      0x0200  /* Destination overrun interrupt */
 135 #define HIFN_PUIER_SRCCMD       0x0080  /* Source command interrupt */
 136 #define HIFN_PUIER_SRCCTX       0x0040  /* Source context interrupt */
 137 #define HIFN_PUIER_SRCDATA      0x0020  /* Source data interrupt */
 138 #define HIFN_PUIER_DSTDATA      0x0010  /* Destination data interrupt */
 139 #define HIFN_PUIER_DSTRESULT    0x0004  /* Destination result interrupt */
 140
 141 /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
 142 #define HIFN_PUSTAT_CMDINVAL    0x8000  /* Invalid command interrupt */
 143 #define HIFN_PUSTAT_DATAERR     0x4000  /* Data error interrupt */
 144 #define HIFN_PUSTAT_SRCFIFO     0x2000  /* Source FIFO ready interrupt */
 145 #define HIFN_PUSTAT_DSTFIFO     0x1000  /* Destination FIFO ready interrupt */
 146 #define HIFN_PUSTAT_DSTOVER     0x0200  /* Destination overrun interrupt */
 147 #define HIFN_PUSTAT_SRCCMD      0x0080  /* Source command interrupt */
 148 #define HIFN_PUSTAT_SRCCTX      0x0040  /* Source context interrupt */
 149 #define HIFN_PUSTAT_SRCDATA     0x0020  /* Source data interrupt */
 150 #define HIFN_PUSTAT_DSTDATA     0x0010  /* Destination data interrupt */
 151 #define HIFN_PUSTAT_DSTRESULT   0x0004  /* Destination result interrupt */
 152 #define HIFN_PUSTAT_CHIPREV     0x00ff  /* Chip revision mask */
 153 #define HIFN_PUSTAT_CHIPENA     0xff00  /* Chip enabled mask */
 154 #define HIFN_PUSTAT_ENA_2       0x1100  /* Level 2 enabled */
 155 #define HIFN_PUSTAT_ENA_1       0x1000  /* Level 1 enabled */
 156 #define HIFN_PUSTAT_ENA_0       0x3000  /* Level 0 enabled */
 157 #define HIFN_PUSTAT_REV_2       0x0020  /* 7751 PT6/2 */
 158 #define HIFN_PUSTAT_REV_3       0x0030  /* 7751 PT6/3 */
 159
 160 /* FIFO Status Register (HIFN_0_FIFOSTAT) */
 161 #define HIFN_FIFOSTAT_SRC       0x7f00  /* Source FIFO available */
 162 #define HIFN_FIFOSTAT_DST       0x007f  /* Destination FIFO available */
 163
 164 /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
 165 #define HIFN_FIFOCNFG_THRESHOLD 0x0400  /* must be written as 1 */
 166
 167 /*
 168  * DMA Interface Registers (offset from BASEREG1)
 169  */
 170 #define HIFN_1_DMA_CRAR         0x0c    /* DMA Command Ring Address */
 171 #define HIFN_1_DMA_SRAR         0x1c    /* DMA Source Ring Address */
 172 #define HIFN_1_DMA_RRAR         0x2c    /* DMA Result Ring Address */
 173 #define HIFN_1_DMA_DRAR         0x3c    /* DMA Destination Ring Address */
 174 #define HIFN_1_DMA_CSR          0x40    /* DMA Status and Control */
 175 #define HIFN_1_DMA_IER          0x44    /* DMA Interrupt Enable */
 176 #define HIFN_1_DMA_CNFG         0x48    /* DMA Configuration */
 177 #define HIFN_1_PLL              0x4c    /* 795x: PLL config */
 178 #define HIFN_1_7811_RNGENA      0x60    /* 7811: rng enable */
 179 #define HIFN_1_7811_RNGCFG      0x64    /* 7811: rng config */
 180 #define HIFN_1_7811_RNGDAT      0x68    /* 7811: rng data */
 181 #define HIFN_1_7811_RNGSTS      0x6c    /* 7811: rng status */
 182 #define HIFN_1_7811_MIPSRST     0x94    /* 7811: MIPS reset */
 183 #define HIFN_1_REVID            0x98    /* Revision ID */
 184 #define HIFN_1_UNLOCK_SECRET1   0xf4
 185 #define HIFN_1_UNLOCK_SECRET2   0xfc
 186 #define HIFN_1_PUB_RESET        0x204   /* Public/RNG Reset */
 187 #define HIFN_1_PUB_BASE         0x300   /* Public Base Address */
 188 #define HIFN_1_PUB_OPLEN        0x304   /* Public Operand Length */
 189 #define HIFN_1_PUB_OP           0x308   /* Public Operand */
 190 #define HIFN_1_PUB_STATUS       0x30c   /* Public Status */
 191 #define HIFN_1_PUB_IEN          0x310   /* Public Interrupt enable */
 192 #define HIFN_1_RNG_CONFIG       0x314   /* RNG config */
 193 #define HIFN_1_RNG_DATA         0x318   /* RNG data */
 194 #define HIFN_1_PUB_MEM          0x400   /* start of Public key memory */
 195 #define HIFN_1_PUB_MEMEND       0xbff   /* end of Public key memory */
 196
 197 /* DMA Status and Control Register (HIFN_1_DMA_CSR) */
 198 #define HIFN_DMACSR_D_CTRLMASK  0xc0000000      /* Destinition Ring Control */
 199 #define HIFN_DMACSR_D_CTRL_NOP  0x00000000      /* Dest. Control: no-op */
 200 #define HIFN_DMACSR_D_CTRL_DIS  0x40000000      /* Dest. Control: disable */
 201 #define HIFN_DMACSR_D_CTRL_ENA  0x80000000      /* Dest. Control: enable */
 202 #define HIFN_DMACSR_D_ABORT     0x20000000      /* Destinition Ring PCIAbort */
 203 #define HIFN_DMACSR_D_DONE      0x10000000      /* Destinition Ring Done */
 204 #define HIFN_DMACSR_D_LAST      0x08000000      /* Destinition Ring Last */
 205 #define HIFN_DMACSR_D_WAIT      0x04000000      /* Destinition Ring Waiting */
 206 #define HIFN_DMACSR_D_OVER      0x02000000      /* Destinition Ring Overflow */
 207 #define HIFN_DMACSR_R_CTRL      0x00c00000      /* Result Ring Control */
 208 #define HIFN_DMACSR_R_CTRL_NOP  0x00000000      /* Result Control: no-op */
 209 #define HIFN_DMACSR_R_CTRL_DIS  0x00400000      /* Result Control: disable */
 210 #define HIFN_DMACSR_R_CTRL_ENA  0x00800000      /* Result Control: enable */
 211 #define HIFN_DMACSR_R_ABORT     0x00200000      /* Result Ring PCI Abort */
 212 #define HIFN_DMACSR_R_DONE      0x00100000      /* Result Ring Done */
 213 #define HIFN_DMACSR_R_LAST      0x00080000      /* Result Ring Last */
 214 #define HIFN_DMACSR_R_WAIT      0x00040000      /* Result Ring Waiting */
 215 #define HIFN_DMACSR_R_OVER      0x00020000      /* Result Ring Overflow */
 216 #define HIFN_DMACSR_S_CTRL      0x0000c000      /* Source Ring Control */
 217 #define HIFN_DMACSR_S_CTRL_NOP  0x00000000      /* Source Control: no-op */
 218 #define HIFN_DMACSR_S_CTRL_DIS  0x00004000      /* Source Control: disable */
 219 #define HIFN_DMACSR_S_CTRL_ENA  0x00008000      /* Source Control: enable */
 220 #define HIFN_DMACSR_S_ABORT     0x00002000      /* Source Ring PCI Abort */
 221 #define HIFN_DMACSR_S_DONE      0x00001000      /* Source Ring Done */
 222 #define HIFN_DMACSR_S_LAST      0x00000800      /* Source Ring Last */
 223 #define HIFN_DMACSR_S_WAIT      0x00000400      /* Source Ring Waiting */
 224 #define HIFN_DMACSR_ILLW        0x00000200      /* Illegal write (7811 only) */
 225 #define HIFN_DMACSR_ILLR        0x00000100      /* Illegal read (7811 only) */
 226 #define HIFN_DMACSR_C_CTRL      0x000000c0      /* Command Ring Control */
 227 #define HIFN_DMACSR_C_CTRL_NOP  0x00000000      /* Command Control: no-op */
 228 #define HIFN_DMACSR_C_CTRL_DIS  0x00000040      /* Command Control: disable */
 229 #define HIFN_DMACSR_C_CTRL_ENA  0x00000080      /* Command Control: enable */
 230 #define HIFN_DMACSR_C_ABORT     0x00000020      /* Command Ring PCI Abort */
 231 #define HIFN_DMACSR_C_DONE      0x00000010      /* Command Ring Done */
 232 #define HIFN_DMACSR_C_LAST      0x00000008      /* Command Ring Last */
 233 #define HIFN_DMACSR_C_WAIT      0x00000004      /* Command Ring Waiting */
 234 #define HIFN_DMACSR_PUBDONE     0x00000002      /* Public op done (7951 only) */
 235 #define HIFN_DMACSR_ENGINE      0x00000001      /* Command Ring Engine IRQ */
 236
 237 /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
 238 #define HIFN_DMAIER_D_ABORT     0x20000000      /* Destination Ring PCIAbort */
 239 #define HIFN_DMAIER_D_DONE      0x10000000      /* Destination Ring Done */
 240 #define HIFN_DMAIER_D_LAST      0x08000000      /* Destination Ring Last */
 241 #define HIFN_DMAIER_D_WAIT      0x04000000      /* Destination Ring Waiting */
 242 #define HIFN_DMAIER_D_OVER      0x02000000      /* Destination Ring Overflow */
 243 #define HIFN_DMAIER_R_ABORT     0x00200000      /* Result Ring PCI Abort */
 244 #define HIFN_DMAIER_R_DONE      0x00100000      /* Result Ring Done */
 245 #define HIFN_DMAIER_R_LAST      0x00080000      /* Result Ring Last */
 246 #define HIFN_DMAIER_R_WAIT      0x00040000      /* Result Ring Waiting */
 247 #define HIFN_DMAIER_R_OVER      0x00020000      /* Result Ring Overflow */
 248 #define HIFN_DMAIER_S_ABORT     0x00002000      /* Source Ring PCI Abort */
 249 #define HIFN_DMAIER_S_DONE      0x00001000      /* Source Ring Done */
 250 #define HIFN_DMAIER_S_LAST      0x00000800      /* Source Ring Last */
 251 #define HIFN_DMAIER_S_WAIT      0x00000400      /* Source Ring Waiting */
 252 #define HIFN_DMAIER_ILLW        0x00000200      /* Illegal write (7811 only) */
 253 #define HIFN_DMAIER_ILLR        0x00000100      /* Illegal read (7811 only) */
 254 #define HIFN_DMAIER_C_ABORT     0x00000020      /* Command Ring PCI Abort */
 255 #define HIFN_DMAIER_C_DONE      0x00000010      /* Command Ring Done */
 256 #define HIFN_DMAIER_C_LAST      0x00000008      /* Command Ring Last */
 257 #define HIFN_DMAIER_C_WAIT      0x00000004      /* Command Ring Waiting */
 258 #define HIFN_DMAIER_PUBDONE     0x00000002      /* public op done (7951 only) */
 259 #define HIFN_DMAIER_ENGINE      0x00000001      /* Engine IRQ */
 260
 261 /* DMA Configuration Register (HIFN_1_DMA_CNFG) */
 262 #define HIFN_DMACNFG_BIGENDIAN  0x10000000      /* big endian mode */
 263 #define HIFN_DMACNFG_POLLFREQ   0x00ff0000      /* Poll frequency mask */
 264 #define HIFN_DMACNFG_UNLOCK     0x00000800
 265 #define HIFN_DMACNFG_POLLINVAL  0x00000700      /* Invalid Poll Scalar */
 266 #define HIFN_DMACNFG_LAST       0x00000010      /* Host control LAST bit */
 267 #define HIFN_DMACNFG_MODE       0x00000004      /* DMA mode */
 268 #define HIFN_DMACNFG_DMARESET   0x00000002      /* DMA Reset # */
 269 #define HIFN_DMACNFG_MSTRESET   0x00000001      /* Master Reset # */
 270
 271 /* PLL configuration register */
 272 #define HIFN_PLL_REF_CLK_HBI    0x00000000      /* HBI reference clock */
 273 #define HIFN_PLL_REF_CLK_PLL    0x00000001      /* PLL reference clock */
 274 #define HIFN_PLL_BP             0x00000002      /* Reference clock bypass */
 275 #define HIFN_PLL_PK_CLK_HBI     0x00000000      /* PK engine HBI clock */
 276 #define HIFN_PLL_PK_CLK_PLL     0x00000008      /* PK engine PLL clock */
 277 #define HIFN_PLL_PE_CLK_HBI     0x00000000      /* PE engine HBI clock */
 278 #define HIFN_PLL_PE_CLK_PLL     0x00000010      /* PE engine PLL clock */
 279 #define HIFN_PLL_RESERVED_1     0x00000400      /* Reserved bit, must be 1 */
 280 #define HIFN_PLL_ND_SHIFT       11              /* Clock multiplier shift */
 281 #define HIFN_PLL_ND_MULT_2      0x00000000      /* PLL clock multiplier 2 */
 282 #define HIFN_PLL_ND_MULT_4      0x00000800      /* PLL clock multiplier 4 */
 283 #define HIFN_PLL_ND_MULT_6      0x00001000      /* PLL clock multiplier 6 */
 284 #define HIFN_PLL_ND_MULT_8      0x00001800      /* PLL clock multiplier 8 */
 285 #define HIFN_PLL_ND_MULT_10     0x00002000      /* PLL clock multiplier 10 */
 286 #define HIFN_PLL_ND_MULT_12     0x00002800      /* PLL clock multiplier 12 */
 287 #define HIFN_PLL_IS_1_8         0x00000000      /* charge pump (mult. 1-8) */
 288 #define HIFN_PLL_IS_9_12        0x00010000      /* charge pump (mult. 9-12) */
 289
 290 #define HIFN_PLL_FCK_MAX        266             /* Maximum PLL frequency */
 291
 292 /* Public key reset register (HIFN_1_PUB_RESET) */
 293 #define HIFN_PUBRST_RESET       0x00000001      /* reset public/rng unit */
 294
 295 /* Public base address register (HIFN_1_PUB_BASE) */
 296 #define HIFN_PUBBASE_ADDR       0x00003fff      /* base address */
 297
 298 /* Public operand length register (HIFN_1_PUB_OPLEN) */
 299 #define HIFN_PUBOPLEN_MOD_M     0x0000007f      /* modulus length mask */
 300 #define HIFN_PUBOPLEN_MOD_S     0               /* modulus length shift */
 301 #define HIFN_PUBOPLEN_EXP_M     0x0003ff80      /* exponent length mask */
 302 #define HIFN_PUBOPLEN_EXP_S     7               /* exponent length shift */
 303 #define HIFN_PUBOPLEN_RED_M     0x003c0000      /* reducend length mask */
 304 #define HIFN_PUBOPLEN_RED_S     18              /* reducend length shift */
 305
 306 /* Public operation register (HIFN_1_PUB_OP) */
 307 #define HIFN_PUBOP_AOFFSET_M    0x0000007f      /* A offset mask */
 308 #define HIFN_PUBOP_AOFFSET_S    0               /* A offset shift */
 309 #define HIFN_PUBOP_BOFFSET_M    0x00000f80      /* B offset mask */
 310 #define HIFN_PUBOP_BOFFSET_S    7               /* B offset shift */
 311 #define HIFN_PUBOP_MOFFSET_M    0x0003f000      /* M offset mask */
 312 #define HIFN_PUBOP_MOFFSET_S    12              /* M offset shift */
 313 #define HIFN_PUBOP_OP_MASK      0x003c0000      /* Opcode: */
 314 #define HIFN_PUBOP_OP_NOP       0x00000000      /*  NOP */
 315 #define HIFN_PUBOP_OP_ADD       0x00040000      /*  ADD */
 316 #define HIFN_PUBOP_OP_ADDC      0x00080000      /*  ADD w/carry */
 317 #define HIFN_PUBOP_OP_SUB       0x000c0000      /*  SUB */
 318 #define HIFN_PUBOP_OP_SUBC      0x00100000      /*  SUB w/carry */
 319 #define HIFN_PUBOP_OP_MODADD    0x00140000      /*  Modular ADD */
 320 #define HIFN_PUBOP_OP_MODSUB    0x00180000      /*  Modular SUB */
 321 #define HIFN_PUBOP_OP_INCA      0x001c0000      /*  INC A */
 322 #define HIFN_PUBOP_OP_DECA      0x00200000      /*  DEC A */
 323 #define HIFN_PUBOP_OP_MULT      0x00240000      /*  MULT */
 324 #define HIFN_PUBOP_OP_MODMULT   0x00280000      /*  Modular MULT */
 325 #define HIFN_PUBOP_OP_MODRED    0x002c0000      /*  Modular RED */
 326 #define HIFN_PUBOP_OP_MODEXP    0x00300000      /*  Modular EXP */
 327
 328 /* Public status register (HIFN_1_PUB_STATUS) */
 329 #define HIFN_PUBSTS_DONE        0x00000001      /* operation done */
 330 #define HIFN_PUBSTS_CARRY       0x00000002      /* carry */
 331
 332 /* Public interrupt enable register (HIFN_1_PUB_IEN) */
 333 #define HIFN_PUBIEN_DONE        0x00000001      /* operation done interrupt */
 334
 335 /* Random number generator config register (HIFN_1_RNG_CONFIG) */
 336 #define HIFN_RNGCFG_ENA         0x00000001      /* enable rng */
 337
 338 #define HIFN_NAMESIZE                   32
 339 #define HIFN_MAX_RESULT_ORDER           5
 340
 341 #define HIFN_D_CMD_RSIZE                (24 * 1)
 342 #define HIFN_D_SRC_RSIZE                (80 * 1)
 343 #define HIFN_D_DST_RSIZE                (80 * 1)
 344 #define HIFN_D_RES_RSIZE                (24 * 1)
 345
 346 #define HIFN_D_DST_DALIGN               4
 347
 348 #define HIFN_QUEUE_LENGTH               (HIFN_D_CMD_RSIZE - 1)
 349
 350 #define AES_MIN_KEY_SIZE                16
 351 #define AES_MAX_KEY_SIZE                32
 352
 353 #define HIFN_DES_KEY_LENGTH             8
 354 #define HIFN_3DES_KEY_LENGTH            24
 355 #define HIFN_MAX_CRYPT_KEY_LENGTH       AES_MAX_KEY_SIZE
 356 #define HIFN_IV_LENGTH                  8
 357 #define HIFN_AES_IV_LENGTH              16
 358 #define HIFN_MAX_IV_LENGTH              HIFN_AES_IV_LENGTH
 359
 360 #define HIFN_MAC_KEY_LENGTH             64
 361 #define HIFN_MD5_LENGTH                 16
 362 #define HIFN_SHA1_LENGTH                20
 363 #define HIFN_MAC_TRUNC_LENGTH           12
 364
 365 #define HIFN_MAX_COMMAND                (8 + 8 + 8 + 64 + 260)
 366 #define HIFN_MAX_RESULT                 (8 + 4 + 4 + 20 + 4)
 367 #define HIFN_USED_RESULT                12
 368
 369 struct hifn_desc {
 370         volatile __le32         l;
 371         volatile __le32         p;
 372 };
 373
 374 struct hifn_dma {
 375         struct hifn_desc        cmdr[HIFN_D_CMD_RSIZE + 1];
 376         struct hifn_desc        srcr[HIFN_D_SRC_RSIZE + 1];
 377         struct hifn_desc        dstr[HIFN_D_DST_RSIZE + 1];
 378         struct hifn_desc        resr[HIFN_D_RES_RSIZE + 1];
 379
 380         u8                      command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND];
 381         u8                      result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT];
 382
 383         /*
 384          *  Our current positions for insertion and removal from the descriptor
 385          *  rings.
 386          */
 387         volatile int            cmdi, srci, dsti, resi;
 388         volatile int            cmdu, srcu, dstu, resu;
 389         int                     cmdk, srck, dstk, resk;
 390 };
 391
 392 #define HIFN_FLAG_CMD_BUSY      (1 << 0)
 393 #define HIFN_FLAG_SRC_BUSY      (1 << 1)
 394 #define HIFN_FLAG_DST_BUSY      (1 << 2)
 395 #define HIFN_FLAG_RES_BUSY      (1 << 3)
 396 #define HIFN_FLAG_OLD_KEY       (1 << 4)
 397
 398 #define HIFN_DEFAULT_ACTIVE_NUM 5
 399
 400 struct hifn_device {
 401         char                    name[HIFN_NAMESIZE];
 402
 403         int                     irq;
 404
 405         struct pci_dev          *pdev;
 406         void __iomem            *bar[3];
 407
 408         void                    *desc_virt;
 409         dma_addr_t              desc_dma;
 410
 411         u32                     dmareg;
 412
 413         void                    *sa[HIFN_D_RES_RSIZE];
 414
 415         spinlock_t              lock;
 416
 417         u32                     flags;
 418         int                     active, started;
 419         struct delayed_work     work;
 420         unsigned long           reset;
 421         unsigned long           success;
 422         unsigned long           prev_success;
 423
 424         u8                      snum;
 425
 426         struct tasklet_struct   tasklet;
 427
 428         struct crypto_queue     queue;
 429         struct list_head        alg_list;
 430
 431         unsigned int            pk_clk_freq;
 432
 433 #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
 434         unsigned int            rng_wait_time;
 435         ktime_t                 rngtime;
 436         struct hwrng            rng;
 437 #endif
 438 };
 439
 440 #define HIFN_D_LENGTH                   0x0000ffff
 441 #define HIFN_D_NOINVALID                0x01000000
 442 #define HIFN_D_MASKDONEIRQ              0x02000000
 443 #define HIFN_D_DESTOVER                 0x04000000
 444 #define HIFN_D_OVER                     0x08000000
 445 #define HIFN_D_LAST                     0x20000000
 446 #define HIFN_D_JUMP                     0x40000000
 447 #define HIFN_D_VALID                    0x80000000
 448
 449 struct hifn_base_command {
 450         volatile __le16         masks;
 451         volatile __le16         session_num;
 452         volatile __le16         total_source_count;
 453         volatile __le16         total_dest_count;
 454 };
 455
 456 #define HIFN_BASE_CMD_COMP              0x0100  /* enable compression engine */
 457 #define HIFN_BASE_CMD_PAD               0x0200  /* enable padding engine */
 458 #define HIFN_BASE_CMD_MAC               0x0400  /* enable MAC engine */
 459 #define HIFN_BASE_CMD_CRYPT             0x0800  /* enable crypt engine */
 460 #define HIFN_BASE_CMD_DECODE            0x2000
 461 #define HIFN_BASE_CMD_SRCLEN_M          0xc000
 462 #define HIFN_BASE_CMD_SRCLEN_S          14
 463 #define HIFN_BASE_CMD_DSTLEN_M          0x3000
 464 #define HIFN_BASE_CMD_DSTLEN_S          12
 465 #define HIFN_BASE_CMD_LENMASK_HI        0x30000
 466 #define HIFN_BASE_CMD_LENMASK_LO        0x0ffff
 467
 468 /*
 469  * Structure to help build up the command data structure.
 470  */
 471 struct hifn_crypt_command {
 472         volatile __le16         masks;
 473         volatile __le16         header_skip;
 474         volatile __le16         source_count;
 475         volatile __le16         reserved;
 476 };
 477
 478 #define HIFN_CRYPT_CMD_ALG_MASK         0x0003          /* algorithm: */
 479 #define HIFN_CRYPT_CMD_ALG_DES          0x0000          /*   DES */
 480 #define HIFN_CRYPT_CMD_ALG_3DES         0x0001          /*   3DES */
 481 #define HIFN_CRYPT_CMD_ALG_RC4          0x0002          /*   RC4 */
 482 #define HIFN_CRYPT_CMD_ALG_AES          0x0003          /*   AES */
 483 #define HIFN_CRYPT_CMD_MODE_MASK        0x0018          /* Encrypt mode: */
 484 #define HIFN_CRYPT_CMD_MODE_ECB         0x0000          /*   ECB */
 485 #define HIFN_CRYPT_CMD_MODE_CBC         0x0008          /*   CBC */
 486 #define HIFN_CRYPT_CMD_MODE_CFB         0x0010          /*   CFB */
 487 #define HIFN_CRYPT_CMD_MODE_OFB         0x0018          /*   OFB */
 488 #define HIFN_CRYPT_CMD_CLR_CTX          0x0040          /* clear context */
 489 #define HIFN_CRYPT_CMD_KSZ_MASK         0x0600          /* AES key size: */
 490 #define HIFN_CRYPT_CMD_KSZ_128          0x0000          /*  128 bit */
 491 #define HIFN_CRYPT_CMD_KSZ_192          0x0200          /*  192 bit */
 492 #define HIFN_CRYPT_CMD_KSZ_256          0x0400          /*  256 bit */
 493 #define HIFN_CRYPT_CMD_NEW_KEY          0x0800          /* expect new key */
 494 #define HIFN_CRYPT_CMD_NEW_IV           0x1000          /* expect new iv */
 495 #define HIFN_CRYPT_CMD_SRCLEN_M         0xc000
 496 #define HIFN_CRYPT_CMD_SRCLEN_S         14
 497
 498 /*
 499  * Structure to help build up the command data structure.
 500  */
 501 struct hifn_mac_command {
 502         volatile __le16 masks;
 503         volatile __le16 header_skip;
 504         volatile __le16 source_count;
 505         volatile __le16 reserved;
 506 };
 507
 508 #define HIFN_MAC_CMD_ALG_MASK           0x0001
 509 #define HIFN_MAC_CMD_ALG_SHA1           0x0000
 510 #define HIFN_MAC_CMD_ALG_MD5            0x0001
 511 #define HIFN_MAC_CMD_MODE_MASK          0x000c
 512 #define HIFN_MAC_CMD_MODE_HMAC          0x0000
 513 #define HIFN_MAC_CMD_MODE_SSL_MAC       0x0004
 514 #define HIFN_MAC_CMD_MODE_HASH          0x0008
 515 #define HIFN_MAC_CMD_MODE_FULL          0x0004
 516 #define HIFN_MAC_CMD_TRUNC              0x0010
 517 #define HIFN_MAC_CMD_RESULT             0x0020
 518 #define HIFN_MAC_CMD_APPEND             0x0040
 519 #define HIFN_MAC_CMD_SRCLEN_M           0xc000
 520 #define HIFN_MAC_CMD_SRCLEN_S           14
 521
 522 /*
 523  * MAC POS IPsec initiates authentication after encryption on encodes
 524  * and before decryption on decodes.
 525  */
 526 #define HIFN_MAC_CMD_POS_IPSEC          0x0200
 527 #define HIFN_MAC_CMD_NEW_KEY            0x0800
 528
 529 struct hifn_comp_command {
 530         volatile __le16         masks;
 531         volatile __le16         header_skip;
 532         volatile __le16         source_count;
 533         volatile __le16         reserved;
 534 };
 535
 536 #define HIFN_COMP_CMD_SRCLEN_M          0xc000
 537 #define HIFN_COMP_CMD_SRCLEN_S          14
 538 #define HIFN_COMP_CMD_ONE               0x0100  /* must be one */
 539 #define HIFN_COMP_CMD_CLEARHIST         0x0010  /* clear history */
 540 #define HIFN_COMP_CMD_UPDATEHIST        0x0008  /* update history */
 541 #define HIFN_COMP_CMD_LZS_STRIP0        0x0004  /* LZS: strip zero */
 542 #define HIFN_COMP_CMD_MPPC_RESTART      0x0004  /* MPPC: restart */
 543 #define HIFN_COMP_CMD_ALG_MASK          0x0001  /* compression mode: */
 544 #define HIFN_COMP_CMD_ALG_MPPC          0x0001  /*   MPPC */
 545 #define HIFN_COMP_CMD_ALG_LZS           0x0000  /*   LZS */
 546
 547 struct hifn_base_result {
 548         volatile __le16         flags;
 549         volatile __le16         session;
 550         volatile __le16         src_cnt;                /* 15:0 of source count */
 551         volatile __le16         dst_cnt;                /* 15:0 of dest count */
 552 };
 553
 554 #define HIFN_BASE_RES_DSTOVERRUN        0x0200  /* destination overrun */
 555 #define HIFN_BASE_RES_SRCLEN_M          0xc000  /* 17:16 of source count */
 556 #define HIFN_BASE_RES_SRCLEN_S          14
 557 #define HIFN_BASE_RES_DSTLEN_M          0x3000  /* 17:16 of dest count */
 558 #define HIFN_BASE_RES_DSTLEN_S          12
 559
 560 struct hifn_comp_result {
 561         volatile __le16         flags;
 562         volatile __le16         crc;
 563 };
 564
 565 #define HIFN_COMP_RES_LCB_M             0xff00  /* longitudinal check byte */
 566 #define HIFN_COMP_RES_LCB_S             8
 567 #define HIFN_COMP_RES_RESTART           0x0004  /* MPPC: restart */
 568 #define HIFN_COMP_RES_ENDMARKER         0x0002  /* LZS: end marker seen */
 569 #define HIFN_COMP_RES_SRC_NOTZERO       0x0001  /* source expired */
 570
 571 struct hifn_mac_result {
 572         volatile __le16         flags;
 573         volatile __le16         reserved;
 574         /* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */
 575 };
 576
 577 #define HIFN_MAC_RES_MISCOMPARE         0x0002  /* compare failed */
 578 #define HIFN_MAC_RES_SRC_NOTZERO        0x0001  /* source expired */
 579
 580 struct hifn_crypt_result {
 581         volatile __le16         flags;
 582         volatile __le16         reserved;
 583 };
 584
 585 #define HIFN_CRYPT_RES_SRC_NOTZERO      0x0001  /* source expired */
 586
 587 #ifndef HIFN_POLL_FREQUENCY
 588 #define HIFN_POLL_FREQUENCY     0x1
 589 #endif
 590
 591 #ifndef HIFN_POLL_SCALAR
 592 #define HIFN_POLL_SCALAR        0x0
 593 #endif
 594
 595 #define HIFN_MAX_SEGLEN         0xffff          /* maximum dma segment len */
 596 #define HIFN_MAX_DMALEN         0x3ffff         /* maximum dma length */
 597
 598 struct hifn_crypto_alg {
 599         struct list_head        entry;
 600         struct skcipher_alg     alg;
 601         struct hifn_device      *dev;
 602 };
 603
 604 #define ASYNC_SCATTERLIST_CACHE 16
 605
 606 #define ASYNC_FLAGS_MISALIGNED  (1 << 0)
 607
 608 struct hifn_cipher_walk {
 609         struct scatterlist      cache[ASYNC_SCATTERLIST_CACHE];
 610         u32                     flags;
 611         int                     num;
 612 };
 613
 614 struct hifn_context {
 615         u8                      key[HIFN_MAX_CRYPT_KEY_LENGTH];
 616         struct hifn_device      *dev;
 617         unsigned int            keysize;
 618 };
 619
 620 struct hifn_request_context {
 621         u8                      *iv;
 622         unsigned int            ivsize;
 623         u8                      op, type, mode, unused;
 624         struct hifn_cipher_walk walk;
 625 };
 626
 627 #define crypto_alg_to_hifn(a)   container_of(a, struct hifn_crypto_alg, alg)
 628
 629 static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg)
 630 {
 631         return readl(dev->bar[0] + reg);
 632 }
 633
 634 static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg)
 635 {
 636         return readl(dev->bar[1] + reg);
 637 }
 638
 639 static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val)
 640 {
 641         writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg);
 642 }
 643
 644 static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val)
 645 {
 646         writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg);
 647 }
 648
 649 static void hifn_wait_puc(struct hifn_device *dev)
 650 {
 651         int i;
 652         u32 ret;
 653
 654         for (i = 10000; i > 0; --i) {
 655                 ret = hifn_read_0(dev, HIFN_0_PUCTRL);
 656                 if (!(ret & HIFN_PUCTRL_RESET))
 657                         break;
 658
 659                 udelay(1);
 660         }
 661
 662         if (!i)
 663                 dev_err(&dev->pdev->dev, "Failed to reset PUC unit.\n");
 664 }
 665
 666 static void hifn_reset_puc(struct hifn_device *dev)
 667 {
 668         hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
 669         hifn_wait_puc(dev);
 670 }
 671
 672 static void hifn_stop_device(struct hifn_device *dev)
 673 {
 674         hifn_write_1(dev, HIFN_1_DMA_CSR,
 675                 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
 676                 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS);
 677         hifn_write_0(dev, HIFN_0_PUIER, 0);
 678         hifn_write_1(dev, HIFN_1_DMA_IER, 0);
 679 }
 680
 681 static void hifn_reset_dma(struct hifn_device *dev, int full)
 682 {
 683         hifn_stop_device(dev);
 684
 685         /*
 686          * Setting poll frequency and others to 0.
 687          */
 688         hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 689                         HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 690         mdelay(1);
 691
 692         /*
 693          * Reset DMA.
 694          */
 695         if (full) {
 696                 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
 697                 mdelay(1);
 698         } else {
 699                 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |
 700                                 HIFN_DMACNFG_MSTRESET);
 701                 hifn_reset_puc(dev);
 702         }
 703
 704         hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
 705                         HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 706
 707         hifn_reset_puc(dev);
 708 }
 709
 710 static u32 hifn_next_signature(u32 a, u_int cnt)
 711 {
 712         int i;
 713         u32 v;
 714
 715         for (i = 0; i < cnt; i++) {
 716                 /* get the parity */
 717                 v = a & 0x80080125;
 718                 v ^= v >> 16;
 719                 v ^= v >> 8;
 720                 v ^= v >> 4;
 721                 v ^= v >> 2;
 722                 v ^= v >> 1;
 723
 724                 a = (v & 1) ^ (a << 1);
 725         }
 726
 727         return a;
 728 }
 729
 730 static struct pci2id {
 731         u_short         pci_vendor;
 732         u_short         pci_prod;
 733         char            card_id[13];
 734 } pci2id[] = {
 735         {
 736                 PCI_VENDOR_ID_HIFN,
 737                 PCI_DEVICE_ID_HIFN_7955,
 738                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 739                   0x00, 0x00, 0x00, 0x00, 0x00 }
 740         },
 741         {
 742                 PCI_VENDOR_ID_HIFN,
 743                 PCI_DEVICE_ID_HIFN_7956,
 744                 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 745                   0x00, 0x00, 0x00, 0x00, 0x00 }
 746         }
 747 };
 748
 749 #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
 750 static int hifn_rng_data_present(struct hwrng *rng, int wait)
 751 {
 752         struct hifn_device *dev = (struct hifn_device *)rng->priv;
 753         s64 nsec;
 754
 755         nsec = ktime_to_ns(ktime_sub(ktime_get(), dev->rngtime));
 756         nsec -= dev->rng_wait_time;
 757         if (nsec <= 0)
 758                 return 1;
 759         if (!wait)
 760                 return 0;
 761         ndelay(nsec);
 762         return 1;
 763 }
 764
 765 static int hifn_rng_data_read(struct hwrng *rng, u32 *data)
 766 {
 767         struct hifn_device *dev = (struct hifn_device *)rng->priv;
 768
 769         *data = hifn_read_1(dev, HIFN_1_RNG_DATA);
 770         dev->rngtime = ktime_get();
 771         return 4;
 772 }
 773
 774 static int hifn_register_rng(struct hifn_device *dev)
 775 {
 776         /*
 777          * We must wait at least 256 Pk_clk cycles between two reads of the rng.
 778          */
 779         dev->rng_wait_time      = DIV_ROUND_UP_ULL(NSEC_PER_SEC,
 780                                                    dev->pk_clk_freq) * 256;
 781
 782         dev->rng.name           = dev->name;
 783         dev->rng.data_present   = hifn_rng_data_present,
 784         dev->rng.data_read      = hifn_rng_data_read,
 785         dev->rng.priv           = (unsigned long)dev;
 786
 787         return hwrng_register(&dev->rng);
 788 }
 789
 790 static void hifn_unregister_rng(struct hifn_device *dev)
 791 {
 792         hwrng_unregister(&dev->rng);
 793 }
 794 #else
 795 #define hifn_register_rng(dev)          0
 796 #define hifn_unregister_rng(dev)
 797 #endif
 798
 799 static int hifn_init_pubrng(struct hifn_device *dev)
 800 {
 801         int i;
 802
 803         hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |
 804                         HIFN_PUBRST_RESET);
 805
 806         for (i = 100; i > 0; --i) {
 807                 mdelay(1);
 808
 809                 if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0)
 810                         break;
 811         }
 812
 813         if (!i) {
 814                 dev_err(&dev->pdev->dev, "Failed to initialise public key engine.\n");
 815         } else {
 816                 hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
 817                 dev->dmareg |= HIFN_DMAIER_PUBDONE;
 818                 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
 819
 820                 dev_dbg(&dev->pdev->dev, "Public key engine has been successfully initialised.\n");
 821         }
 822
 823         /* Enable RNG engine. */
 824
 825         hifn_write_1(dev, HIFN_1_RNG_CONFIG,
 826                         hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA);
 827         dev_dbg(&dev->pdev->dev, "RNG engine has been successfully initialised.\n");
 828
 829 #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
 830         /* First value must be discarded */
 831         hifn_read_1(dev, HIFN_1_RNG_DATA);
 832         dev->rngtime = ktime_get();
 833 #endif
 834         return 0;
 835 }
 836
 837 static int hifn_enable_crypto(struct hifn_device *dev)
 838 {
 839         u32 dmacfg, addr;
 840         char *offtbl = NULL;
 841         int i;
 842
 843         for (i = 0; i < ARRAY_SIZE(pci2id); i++) {
 844                 if (pci2id[i].pci_vendor == dev->pdev->vendor &&
 845                                 pci2id[i].pci_prod == dev->pdev->device) {
 846                         offtbl = pci2id[i].card_id;
 847                         break;
 848                 }
 849         }
 850
 851         if (!offtbl) {
 852                 dev_err(&dev->pdev->dev, "Unknown card!\n");
 853                 return -ENODEV;
 854         }
 855
 856         dmacfg = hifn_read_1(dev, HIFN_1_DMA_CNFG);
 857
 858         hifn_write_1(dev, HIFN_1_DMA_CNFG,
 859                         HIFN_DMACNFG_UNLOCK | HIFN_DMACNFG_MSTRESET |
 860                         HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
 861         mdelay(1);
 862         addr = hifn_read_1(dev, HIFN_1_UNLOCK_SECRET1);
 863         mdelay(1);
 864         hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);
 865         mdelay(1);
 866
 867         for (i = 0; i < 12; ++i) {
 868                 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
 869                 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);
 870
 871                 mdelay(1);
 872         }
 873         hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);
 874
 875         dev_dbg(&dev->pdev->dev, "%s %s.\n", dev->name, pci_name(dev->pdev));
 876
 877         return 0;
 878 }
 879
 880 static void hifn_init_dma(struct hifn_device *dev)
 881 {
 882         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
 883         u32 dptr = dev->desc_dma;
 884         int i;
 885
 886         for (i = 0; i < HIFN_D_CMD_RSIZE; ++i)
 887                 dma->cmdr[i].p = __cpu_to_le32(dptr +
 888                                 offsetof(struct hifn_dma, command_bufs[i][0]));
 889         for (i = 0; i < HIFN_D_RES_RSIZE; ++i)
 890                 dma->resr[i].p = __cpu_to_le32(dptr +
 891                                 offsetof(struct hifn_dma, result_bufs[i][0]));
 892
 893         /* Setup LAST descriptors. */
 894         dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr +
 895                         offsetof(struct hifn_dma, cmdr[0]));
 896         dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr +
 897                         offsetof(struct hifn_dma, srcr[0]));
 898         dma->dstr[HIFN_D_DST_RSIZE].p = __cpu_to_le32(dptr +
 899                         offsetof(struct hifn_dma, dstr[0]));
 900         dma->resr[HIFN_D_RES_RSIZE].p = __cpu_to_le32(dptr +
 901                         offsetof(struct hifn_dma, resr[0]));
 902
 903         dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
 904         dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
 905         dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
 906 }
 907
 908 /*
 909  * Initialize the PLL. We need to know the frequency of the reference clock
 910  * to calculate the optimal multiplier. For PCI we assume 66MHz, since that
 911  * allows us to operate without the risk of overclocking the chip. If it
 912  * actually uses 33MHz, the chip will operate at half the speed, this can be
 913  * overridden by specifying the frequency as module parameter (pci33).
 914  *
 915  * Unfortunately the PCI clock is not very suitable since the HIFN needs a
 916  * stable clock and the PCI clock frequency may vary, so the default is the
 917  * external clock. There is no way to find out its frequency, we default to
 918  * 66MHz since according to Mike Ham of HiFn, almost every board in existence
 919  * has an external crystal populated at 66MHz.
 920  */
 921 static void hifn_init_pll(struct hifn_device *dev)
 922 {
 923         unsigned int freq, m;
 924         u32 pllcfg;
 925
 926         pllcfg = HIFN_1_PLL | HIFN_PLL_RESERVED_1;
 927
 928         if (strncmp(hifn_pll_ref, "ext", 3) == 0)
 929                 pllcfg |= HIFN_PLL_REF_CLK_PLL;
 930         else
 931                 pllcfg |= HIFN_PLL_REF_CLK_HBI;
 932
 933         if (hifn_pll_ref[3] != '\0')
 934                 freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
 935         else {
 936                 freq = 66;
 937                 dev_info(&dev->pdev->dev, "assuming %uMHz clock speed, override with hifn_pll_ref=%.3s<frequency>\n",
 938                          freq, hifn_pll_ref);
 939         }
 940
 941         m = HIFN_PLL_FCK_MAX / freq;
 942
 943         pllcfg |= (m / 2 - 1) << HIFN_PLL_ND_SHIFT;
 944         if (m <= 8)
 945                 pllcfg |= HIFN_PLL_IS_1_8;
 946         else
 947                 pllcfg |= HIFN_PLL_IS_9_12;
 948
 949         /* Select clock source and enable clock bypass */
 950         hifn_write_1(dev, HIFN_1_PLL, pllcfg |
 951                      HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI | HIFN_PLL_BP);
 952
 953         /* Let the chip lock to the input clock */
 954         mdelay(10);
 955
 956         /* Disable clock bypass */
 957         hifn_write_1(dev, HIFN_1_PLL, pllcfg |
 958                      HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI);
 959
 960         /* Switch the engines to the PLL */
 961         hifn_write_1(dev, HIFN_1_PLL, pllcfg |
 962                      HIFN_PLL_PK_CLK_PLL | HIFN_PLL_PE_CLK_PLL);
 963
 964         /*
 965          * The Fpk_clk runs at half the total speed. Its frequency is needed to
 966          * calculate the minimum time between two reads of the rng. Since 33MHz
 967          * is actually 33.333... we overestimate the frequency here, resulting
 968          * in slightly larger intervals.
 969          */
 970         dev->pk_clk_freq = 1000000 * (freq + 1) * m / 2;
 971 }
 972
 973 static void hifn_init_registers(struct hifn_device *dev)
 974 {
 975         u32 dptr = dev->desc_dma;
 976
 977         /* Initialization magic... */
 978         hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
 979         hifn_write_0(dev, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
 980         hifn_write_0(dev, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
 981
 982         /* write all 4 ring address registers */
 983         hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr +
 984                                 offsetof(struct hifn_dma, cmdr[0]));
 985         hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr +
 986                                 offsetof(struct hifn_dma, srcr[0]));
 987         hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr +
 988                                 offsetof(struct hifn_dma, dstr[0]));
 989         hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr +
 990                                 offsetof(struct hifn_dma, resr[0]));
 991
 992         mdelay(2);
 993 #if 0
 994         hifn_write_1(dev, HIFN_1_DMA_CSR,
 995             HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
 996             HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
 997             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
 998             HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
 999             HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1000             HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1001             HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1002             HIFN_DMACSR_S_WAIT |
1003             HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1004             HIFN_DMACSR_C_WAIT |
1005             HIFN_DMACSR_ENGINE |
1006             HIFN_DMACSR_PUBDONE);
1007 #else
1008         hifn_write_1(dev, HIFN_1_DMA_CSR,
1009             HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1010             HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA |
1011             HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1012             HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1013             HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1014             HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1015             HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1016             HIFN_DMACSR_S_WAIT |
1017             HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1018             HIFN_DMACSR_C_WAIT |
1019             HIFN_DMACSR_ENGINE |
1020             HIFN_DMACSR_PUBDONE);
1021 #endif
1022         hifn_read_1(dev, HIFN_1_DMA_CSR);
1023
1024         dev->dmareg |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1025             HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1026             HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1027             HIFN_DMAIER_ENGINE;
1028         dev->dmareg &= ~HIFN_DMAIER_C_WAIT;
1029
1030         hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1031         hifn_read_1(dev, HIFN_1_DMA_IER);
1032 #if 0
1033         hifn_write_0(dev, HIFN_0_PUCNFG, HIFN_PUCNFG_ENCCNFG |
1034                     HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1035                     HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1036                     HIFN_PUCNFG_DRAM);
1037 #else
1038         hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342);
1039 #endif
1040         hifn_init_pll(dev);
1041
1042         hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1043         hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1044             HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1045             ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1046             ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1047 }
1048
1049 static int hifn_setup_base_command(struct hifn_device *dev, u8 *buf,
1050                 unsigned dlen, unsigned slen, u16 mask, u8 snum)
1051 {
1052         struct hifn_base_command *base_cmd;
1053         u8 *buf_pos = buf;
1054
1055         base_cmd = (struct hifn_base_command *)buf_pos;
1056         base_cmd->masks = __cpu_to_le16(mask);
1057         base_cmd->total_source_count =
1058                 __cpu_to_le16(slen & HIFN_BASE_CMD_LENMASK_LO);
1059         base_cmd->total_dest_count =
1060                 __cpu_to_le16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1061
1062         dlen >>= 16;
1063         slen >>= 16;
1064         base_cmd->session_num = __cpu_to_le16(snum |
1065             ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1066             ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1067
1068         return sizeof(struct hifn_base_command);
1069 }
1070
1071 static int hifn_setup_crypto_command(struct hifn_device *dev,
1072                 u8 *buf, unsigned dlen, unsigned slen,
1073                 u8 *key, int keylen, u8 *iv, int ivsize, u16 mode)
1074 {
1075         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1076         struct hifn_crypt_command *cry_cmd;
1077         u8 *buf_pos = buf;
1078         u16 cmd_len;
1079
1080         cry_cmd = (struct hifn_crypt_command *)buf_pos;
1081
1082         cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff);
1083         dlen >>= 16;
1084         cry_cmd->masks = __cpu_to_le16(mode |
1085                         ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) &
1086                          HIFN_CRYPT_CMD_SRCLEN_M));
1087         cry_cmd->header_skip = 0;
1088         cry_cmd->reserved = 0;
1089
1090         buf_pos += sizeof(struct hifn_crypt_command);
1091
1092         dma->cmdu++;
1093         if (dma->cmdu > 1) {
1094                 dev->dmareg |= HIFN_DMAIER_C_WAIT;
1095                 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1096         }
1097
1098         if (keylen) {
1099                 memcpy(buf_pos, key, keylen);
1100                 buf_pos += keylen;
1101         }
1102         if (ivsize) {
1103                 memcpy(buf_pos, iv, ivsize);
1104                 buf_pos += ivsize;
1105         }
1106
1107         cmd_len = buf_pos - buf;
1108
1109         return cmd_len;
1110 }
1111
1112 static int hifn_setup_cmd_desc(struct hifn_device *dev,
1113                 struct hifn_context *ctx, struct hifn_request_context *rctx,
1114                 void *priv, unsigned int nbytes)
1115 {
1116         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1117         int cmd_len, sa_idx;
1118         u8 *buf, *buf_pos;
1119         u16 mask;
1120
1121         sa_idx = dma->cmdi;
1122         buf_pos = buf = dma->command_bufs[dma->cmdi];
1123
1124         mask = 0;
1125         switch (rctx->op) {
1126         case ACRYPTO_OP_DECRYPT:
1127                 mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE;
1128                 break;
1129         case ACRYPTO_OP_ENCRYPT:
1130                 mask = HIFN_BASE_CMD_CRYPT;
1131                 break;
1132         case ACRYPTO_OP_HMAC:
1133                 mask = HIFN_BASE_CMD_MAC;
1134                 break;
1135         default:
1136                 goto err_out;
1137         }
1138
1139         buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes,
1140                         nbytes, mask, dev->snum);
1141
1142         if (rctx->op == ACRYPTO_OP_ENCRYPT || rctx->op == ACRYPTO_OP_DECRYPT) {
1143                 u16 md = 0;
1144
1145                 if (ctx->keysize)
1146                         md |= HIFN_CRYPT_CMD_NEW_KEY;
1147                 if (rctx->iv && rctx->mode != ACRYPTO_MODE_ECB)
1148                         md |= HIFN_CRYPT_CMD_NEW_IV;
1149
1150                 switch (rctx->mode) {
1151                 case ACRYPTO_MODE_ECB:
1152                         md |= HIFN_CRYPT_CMD_MODE_ECB;
1153                         break;
1154                 case ACRYPTO_MODE_CBC:
1155                         md |= HIFN_CRYPT_CMD_MODE_CBC;
1156                         break;
1157                 case ACRYPTO_MODE_CFB:
1158                         md |= HIFN_CRYPT_CMD_MODE_CFB;
1159                         break;
1160                 case ACRYPTO_MODE_OFB:
1161                         md |= HIFN_CRYPT_CMD_MODE_OFB;
1162                         break;
1163                 default:
1164                         goto err_out;
1165                 }
1166
1167                 switch (rctx->type) {
1168                 case ACRYPTO_TYPE_AES_128:
1169                         if (ctx->keysize != 16)
1170                                 goto err_out;
1171                         md |= HIFN_CRYPT_CMD_KSZ_128 |
1172                                 HIFN_CRYPT_CMD_ALG_AES;
1173                         break;
1174                 case ACRYPTO_TYPE_AES_192:
1175                         if (ctx->keysize != 24)
1176                                 goto err_out;
1177                         md |= HIFN_CRYPT_CMD_KSZ_192 |
1178                                 HIFN_CRYPT_CMD_ALG_AES;
1179                         break;
1180                 case ACRYPTO_TYPE_AES_256:
1181                         if (ctx->keysize != 32)
1182                                 goto err_out;
1183                         md |= HIFN_CRYPT_CMD_KSZ_256 |
1184                                 HIFN_CRYPT_CMD_ALG_AES;
1185                         break;
1186                 case ACRYPTO_TYPE_3DES:
1187                         if (ctx->keysize != 24)
1188                                 goto err_out;
1189                         md |= HIFN_CRYPT_CMD_ALG_3DES;
1190                         break;
1191                 case ACRYPTO_TYPE_DES:
1192                         if (ctx->keysize != 8)
1193                                 goto err_out;
1194                         md |= HIFN_CRYPT_CMD_ALG_DES;
1195                         break;
1196                 default:
1197                         goto err_out;
1198                 }
1199
1200                 buf_pos += hifn_setup_crypto_command(dev, buf_pos,
1201                                 nbytes, nbytes, ctx->key, ctx->keysize,
1202                                 rctx->iv, rctx->ivsize, md);
1203         }
1204
1205         dev->sa[sa_idx] = priv;
1206         dev->started++;
1207
1208         cmd_len = buf_pos - buf;
1209         dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID |
1210                         HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
1211
1212         if (++dma->cmdi == HIFN_D_CMD_RSIZE) {
1213                 dma->cmdr[dma->cmdi].l = __cpu_to_le32(
1214                         HIFN_D_VALID | HIFN_D_LAST |
1215                         HIFN_D_MASKDONEIRQ | HIFN_D_JUMP);
1216                 dma->cmdi = 0;
1217         } else {
1218                 dma->cmdr[dma->cmdi - 1].l |= __cpu_to_le32(HIFN_D_VALID);
1219         }
1220
1221         if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) {
1222                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
1223                 dev->flags |= HIFN_FLAG_CMD_BUSY;
1224         }
1225         return 0;
1226
1227 err_out:
1228         return -EINVAL;
1229 }
1230
1231 static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page,
1232                 unsigned int offset, unsigned int size, int last)
1233 {
1234         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1235         int idx;
1236         dma_addr_t addr;
1237
1238         addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE);
1239
1240         idx = dma->srci;
1241
1242         dma->srcr[idx].p = __cpu_to_le32(addr);
1243         dma->srcr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
1244                         HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));
1245
1246         if (++idx == HIFN_D_SRC_RSIZE) {
1247                 dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1248                                 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
1249                                 (last ? HIFN_D_LAST : 0));
1250                 idx = 0;
1251         }
1252
1253         dma->srci = idx;
1254         dma->srcu++;
1255
1256         if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) {
1257                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
1258                 dev->flags |= HIFN_FLAG_SRC_BUSY;
1259         }
1260
1261         return size;
1262 }
1263
1264 static void hifn_setup_res_desc(struct hifn_device *dev)
1265 {
1266         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1267
1268         dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT |
1269                         HIFN_D_VALID | HIFN_D_LAST);
1270         /*
1271          * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID |
1272          *                                      HIFN_D_LAST);
1273          */
1274
1275         if (++dma->resi == HIFN_D_RES_RSIZE) {
1276                 dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID |
1277                                 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST);
1278                 dma->resi = 0;
1279         }
1280
1281         dma->resu++;
1282
1283         if (!(dev->flags & HIFN_FLAG_RES_BUSY)) {
1284                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
1285                 dev->flags |= HIFN_FLAG_RES_BUSY;
1286         }
1287 }
1288
1289 static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page,
1290                 unsigned offset, unsigned size, int last)
1291 {
1292         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1293         int idx;
1294         dma_addr_t addr;
1295
1296         addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE);
1297
1298         idx = dma->dsti;
1299         dma->dstr[idx].p = __cpu_to_le32(addr);
1300         dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
1301                         HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));
1302
1303         if (++idx == HIFN_D_DST_RSIZE) {
1304                 dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID |
1305                                 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
1306                                 (last ? HIFN_D_LAST : 0));
1307                 idx = 0;
1308         }
1309         dma->dsti = idx;
1310         dma->dstu++;
1311
1312         if (!(dev->flags & HIFN_FLAG_DST_BUSY)) {
1313                 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
1314                 dev->flags |= HIFN_FLAG_DST_BUSY;
1315         }
1316 }
1317
1318 static int hifn_setup_dma(struct hifn_device *dev,
1319                 struct hifn_context *ctx, struct hifn_request_context *rctx,
1320                 struct scatterlist *src, struct scatterlist *dst,
1321                 unsigned int nbytes, void *priv)
1322 {
1323         struct scatterlist *t;
1324         struct page *spage, *dpage;
1325         unsigned int soff, doff;
1326         unsigned int n, len;
1327
1328         n = nbytes;
1329         while (n) {
1330                 spage = sg_page(src);
1331                 soff = src->offset;
1332                 len = min(src->length, n);
1333
1334                 hifn_setup_src_desc(dev, spage, soff, len, n - len == 0);
1335
1336                 src++;
1337                 n -= len;
1338         }
1339
1340         t = &rctx->walk.cache[0];
1341         n = nbytes;
1342         while (n) {
1343                 if (t->length && rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1344                         BUG_ON(!sg_page(t));
1345                         dpage = sg_page(t);
1346                         doff = 0;
1347                         len = t->length;
1348                 } else {
1349                         BUG_ON(!sg_page(dst));
1350                         dpage = sg_page(dst);
1351                         doff = dst->offset;
1352                         len = dst->length;
1353                 }
1354                 len = min(len, n);
1355
1356                 hifn_setup_dst_desc(dev, dpage, doff, len, n - len == 0);
1357
1358                 dst++;
1359                 t++;
1360                 n -= len;
1361         }
1362
1363         hifn_setup_cmd_desc(dev, ctx, rctx, priv, nbytes);
1364         hifn_setup_res_desc(dev);
1365         return 0;
1366 }
1367
1368 static int hifn_cipher_walk_init(struct hifn_cipher_walk *w,
1369                 int num, gfp_t gfp_flags)
1370 {
1371         int i;
1372
1373         num = min(ASYNC_SCATTERLIST_CACHE, num);
1374         sg_init_table(w->cache, num);
1375
1376         w->num = 0;
1377         for (i = 0; i < num; ++i) {
1378                 struct page *page = alloc_page(gfp_flags);
1379                 struct scatterlist *s;
1380
1381                 if (!page)
1382                         break;
1383
1384                 s = &w->cache[i];
1385
1386                 sg_set_page(s, page, PAGE_SIZE, 0);
1387                 w->num++;
1388         }
1389
1390         return i;
1391 }
1392
1393 static void hifn_cipher_walk_exit(struct hifn_cipher_walk *w)
1394 {
1395         int i;
1396
1397         for (i = 0; i < w->num; ++i) {
1398                 struct scatterlist *s = &w->cache[i];
1399
1400                 __free_page(sg_page(s));
1401
1402                 s->length = 0;
1403         }
1404
1405         w->num = 0;
1406 }
1407
1408 static int skcipher_add(unsigned int *drestp, struct scatterlist *dst,
1409                 unsigned int size, unsigned int *nbytesp)
1410 {
1411         unsigned int copy, drest = *drestp, nbytes = *nbytesp;
1412         int idx = 0;
1413
1414         if (drest < size || size > nbytes)
1415                 return -EINVAL;
1416
1417         while (size) {
1418                 copy = min3(drest, size, dst->length);
1419
1420                 size -= copy;
1421                 drest -= copy;
1422                 nbytes -= copy;
1423
1424                 pr_debug("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n",
1425                          __func__, copy, size, drest, nbytes);
1426
1427                 dst++;
1428                 idx++;
1429         }
1430
1431         *nbytesp = nbytes;
1432         *drestp = drest;
1433
1434         return idx;
1435 }
1436
1437 static int hifn_cipher_walk(struct skcipher_request *req,
1438                 struct hifn_cipher_walk *w)
1439 {
1440         struct scatterlist *dst, *t;
1441         unsigned int nbytes = req->cryptlen, offset, copy, diff;
1442         int idx, tidx, err;
1443
1444         tidx = idx = 0;
1445         offset = 0;
1446         while (nbytes) {
1447                 if (idx >= w->num && (w->flags & ASYNC_FLAGS_MISALIGNED))
1448                         return -EINVAL;
1449
1450                 dst = &req->dst[idx];
1451
1452                 pr_debug("\n%s: dlen: %u, doff: %u, offset: %u, nbytes: %u.\n",
1453                          __func__, dst->length, dst->offset, offset, nbytes);
1454
1455                 if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
1456                     !IS_ALIGNED(dst->length, HIFN_D_DST_DALIGN) ||
1457                     offset) {
1458                         unsigned slen = min(dst->length - offset, nbytes);
1459                         unsigned dlen = PAGE_SIZE;
1460
1461                         t = &w->cache[idx];
1462
1463                         err = skcipher_add(&dlen, dst, slen, &nbytes);
1464                         if (err < 0)
1465                                 return err;
1466
1467                         idx += err;
1468
1469                         copy = slen & ~(HIFN_D_DST_DALIGN - 1);
1470                         diff = slen & (HIFN_D_DST_DALIGN - 1);
1471
1472                         if (dlen < nbytes) {
1473                                 /*
1474                                  * Destination page does not have enough space
1475                                  * to put there additional blocksized chunk,
1476                                  * so we mark that page as containing only
1477                                  * blocksize aligned chunks:
1478                                  *      t->length = (slen & ~(HIFN_D_DST_DALIGN - 1));
1479                                  * and increase number of bytes to be processed
1480                                  * in next chunk:
1481                                  *      nbytes += diff;
1482                                  */
1483                                 nbytes += diff;
1484
1485                                 /*
1486                                  * Temporary of course...
1487                                  * Kick author if you will catch this one.
1488                                  */
1489                                 pr_err("%s: dlen: %u, nbytes: %u, slen: %u, offset: %u.\n",
1490                                        __func__, dlen, nbytes, slen, offset);
1491                                 pr_err("%s: please contact author to fix this "
1492                                        "issue, generally you should not catch "
1493                                        "this path under any condition but who "
1494                                        "knows how did you use crypto code.\n"
1495                                        "Thank you.\n",  __func__);
1496                                 BUG();
1497                         } else {
1498                                 copy += diff + nbytes;
1499
1500                                 dst = &req->dst[idx];
1501
1502                                 err = skcipher_add(&dlen, dst, nbytes, &nbytes);
1503                                 if (err < 0)
1504                                         return err;
1505
1506                                 idx += err;
1507                         }
1508
1509                         t->length = copy;
1510                         t->offset = offset;
1511                 } else {
1512                         nbytes -= min(dst->length, nbytes);
1513                         idx++;
1514                 }
1515
1516                 tidx++;
1517         }
1518
1519         return tidx;
1520 }
1521
1522 static int hifn_setup_session(struct skcipher_request *req)
1523 {
1524         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1525         struct hifn_request_context *rctx = skcipher_request_ctx(req);
1526         struct hifn_device *dev = ctx->dev;
1527         unsigned long dlen, flags;
1528         unsigned int nbytes = req->cryptlen, idx = 0;
1529         int err = -EINVAL, sg_num;
1530         struct scatterlist *dst;
1531
1532         if (rctx->iv && !rctx->ivsize && rctx->mode != ACRYPTO_MODE_ECB)
1533                 goto err_out_exit;
1534
1535         rctx->walk.flags = 0;
1536
1537         while (nbytes) {
1538                 dst = &req->dst[idx];
1539                 dlen = min(dst->length, nbytes);
1540
1541                 if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
1542                     !IS_ALIGNED(dlen, HIFN_D_DST_DALIGN))
1543                         rctx->walk.flags |= ASYNC_FLAGS_MISALIGNED;
1544
1545                 nbytes -= dlen;
1546                 idx++;
1547         }
1548
1549         if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1550                 err = hifn_cipher_walk_init(&rctx->walk, idx, GFP_ATOMIC);
1551                 if (err < 0)
1552                         return err;
1553         }
1554
1555         sg_num = hifn_cipher_walk(req, &rctx->walk);
1556         if (sg_num < 0) {
1557                 err = sg_num;
1558                 goto err_out_exit;
1559         }
1560
1561         spin_lock_irqsave(&dev->lock, flags);
1562         if (dev->started + sg_num > HIFN_QUEUE_LENGTH) {
1563                 err = -EAGAIN;
1564                 goto err_out;
1565         }
1566
1567         err = hifn_setup_dma(dev, ctx, rctx, req->src, req->dst, req->cryptlen, req);
1568         if (err)
1569                 goto err_out;
1570
1571         dev->snum++;
1572
1573         dev->active = HIFN_DEFAULT_ACTIVE_NUM;
1574         spin_unlock_irqrestore(&dev->lock, flags);
1575
1576         return 0;
1577
1578 err_out:
1579         spin_unlock_irqrestore(&dev->lock, flags);
1580 err_out_exit:
1581         if (err) {
1582                 dev_info(&dev->pdev->dev, "iv: %p [%d], key: %p [%d], mode: %u, op: %u, "
1583                          "type: %u, err: %d.\n",
1584                          rctx->iv, rctx->ivsize,
1585                          ctx->key, ctx->keysize,
1586                          rctx->mode, rctx->op, rctx->type, err);
1587         }
1588
1589         return err;
1590 }
1591
1592 static int hifn_start_device(struct hifn_device *dev)
1593 {
1594         int err;
1595
1596         dev->started = dev->active = 0;
1597         hifn_reset_dma(dev, 1);
1598
1599         err = hifn_enable_crypto(dev);
1600         if (err)
1601                 return err;
1602
1603         hifn_reset_puc(dev);
1604
1605         hifn_init_dma(dev);
1606
1607         hifn_init_registers(dev);
1608
1609         hifn_init_pubrng(dev);
1610
1611         return 0;
1612 }
1613
1614 static int skcipher_get(void *saddr, unsigned int *srestp, unsigned int offset,
1615                 struct scatterlist *dst, unsigned int size, unsigned int *nbytesp)
1616 {
1617         unsigned int srest = *srestp, nbytes = *nbytesp, copy;
1618         void *daddr;
1619         int idx = 0;
1620
1621         if (srest < size || size > nbytes)
1622                 return -EINVAL;
1623
1624         while (size) {
1625                 copy = min3(srest, dst->length, size);
1626
1627                 daddr = kmap_atomic(sg_page(dst));
1628                 memcpy(daddr + dst->offset + offset, saddr, copy);
1629                 kunmap_atomic(daddr);
1630
1631                 nbytes -= copy;
1632                 size -= copy;
1633                 srest -= copy;
1634                 saddr += copy;
1635                 offset = 0;
1636
1637                 pr_debug("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n",
1638                          __func__, copy, size, srest, nbytes);
1639
1640                 dst++;
1641                 idx++;
1642         }
1643
1644         *nbytesp = nbytes;
1645         *srestp = srest;
1646
1647         return idx;
1648 }
1649
1650 static inline void hifn_complete_sa(struct hifn_device *dev, int i)
1651 {
1652         unsigned long flags;
1653
1654         spin_lock_irqsave(&dev->lock, flags);
1655         dev->sa[i] = NULL;
1656         dev->started--;
1657         if (dev->started < 0)
1658                 dev_info(&dev->pdev->dev, "%s: started: %d.\n", __func__,
1659                          dev->started);
1660         spin_unlock_irqrestore(&dev->lock, flags);
1661         BUG_ON(dev->started < 0);
1662 }
1663
1664 static void hifn_process_ready(struct skcipher_request *req, int error)
1665 {
1666         struct hifn_request_context *rctx = skcipher_request_ctx(req);
1667
1668         if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
1669                 unsigned int nbytes = req->cryptlen;
1670                 int idx = 0, err;
1671                 struct scatterlist *dst, *t;
1672                 void *saddr;
1673
1674                 while (nbytes) {
1675                         t = &rctx->walk.cache[idx];
1676                         dst = &req->dst[idx];
1677
1678                         pr_debug("\n%s: sg_page(t): %p, t->length: %u, "
1679                                 "sg_page(dst): %p, dst->length: %u, "
1680                                 "nbytes: %u.\n",
1681                                 __func__, sg_page(t), t->length,
1682                                 sg_page(dst), dst->length, nbytes);
1683
1684                         if (!t->length) {
1685                                 nbytes -= min(dst->length, nbytes);
1686                                 idx++;
1687                                 continue;
1688                         }
1689
1690                         saddr = kmap_atomic(sg_page(t));
1691
1692                         err = skcipher_get(saddr, &t->length, t->offset,
1693                                         dst, nbytes, &nbytes);
1694                         if (err < 0) {
1695                                 kunmap_atomic(saddr);
1696                                 break;
1697                         }
1698
1699                         idx += err;
1700                         kunmap_atomic(saddr);
1701                 }
1702
1703                 hifn_cipher_walk_exit(&rctx->walk);
1704         }
1705
1706         req->base.complete(&req->base, error);
1707 }
1708
1709 static void hifn_clear_rings(struct hifn_device *dev, int error)
1710 {
1711         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1712         int i, u;
1713
1714         dev_dbg(&dev->pdev->dev, "ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1715                         "k: %d.%d.%d.%d.\n",
1716                         dma->cmdi, dma->srci, dma->dsti, dma->resi,
1717                         dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1718                         dma->cmdk, dma->srck, dma->dstk, dma->resk);
1719
1720         i = dma->resk; u = dma->resu;
1721         while (u != 0) {
1722                 if (dma->resr[i].l & __cpu_to_le32(HIFN_D_VALID))
1723                         break;
1724
1725                 if (dev->sa[i]) {
1726                         dev->success++;
1727                         dev->reset = 0;
1728                         hifn_process_ready(dev->sa[i], error);
1729                         hifn_complete_sa(dev, i);
1730                 }
1731
1732                 if (++i == HIFN_D_RES_RSIZE)
1733                         i = 0;
1734                 u--;
1735         }
1736         dma->resk = i; dma->resu = u;
1737
1738         i = dma->srck; u = dma->srcu;
1739         while (u != 0) {
1740                 if (dma->srcr[i].l & __cpu_to_le32(HIFN_D_VALID))
1741                         break;
1742                 if (++i == HIFN_D_SRC_RSIZE)
1743                         i = 0;
1744                 u--;
1745         }
1746         dma->srck = i; dma->srcu = u;
1747
1748         i = dma->cmdk; u = dma->cmdu;
1749         while (u != 0) {
1750                 if (dma->cmdr[i].l & __cpu_to_le32(HIFN_D_VALID))
1751                         break;
1752                 if (++i == HIFN_D_CMD_RSIZE)
1753                         i = 0;
1754                 u--;
1755         }
1756         dma->cmdk = i; dma->cmdu = u;
1757
1758         i = dma->dstk; u = dma->dstu;
1759         while (u != 0) {
1760                 if (dma->dstr[i].l & __cpu_to_le32(HIFN_D_VALID))
1761                         break;
1762                 if (++i == HIFN_D_DST_RSIZE)
1763                         i = 0;
1764                 u--;
1765         }
1766         dma->dstk = i; dma->dstu = u;
1767
1768         dev_dbg(&dev->pdev->dev, "ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
1769                         "k: %d.%d.%d.%d.\n",
1770                         dma->cmdi, dma->srci, dma->dsti, dma->resi,
1771                         dma->cmdu, dma->srcu, dma->dstu, dma->resu,
1772                         dma->cmdk, dma->srck, dma->dstk, dma->resk);
1773 }
1774
1775 static void hifn_work(struct work_struct *work)
1776 {
1777         struct delayed_work *dw = to_delayed_work(work);
1778         struct hifn_device *dev = container_of(dw, struct hifn_device, work);
1779         unsigned long flags;
1780         int reset = 0;
1781         u32 r = 0;
1782
1783         spin_lock_irqsave(&dev->lock, flags);
1784         if (dev->active == 0) {
1785                 struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1786
1787                 if (dma->cmdu == 0 && (dev->flags & HIFN_FLAG_CMD_BUSY)) {
1788                         dev->flags &= ~HIFN_FLAG_CMD_BUSY;
1789                         r |= HIFN_DMACSR_C_CTRL_DIS;
1790                 }
1791                 if (dma->srcu == 0 && (dev->flags & HIFN_FLAG_SRC_BUSY)) {
1792                         dev->flags &= ~HIFN_FLAG_SRC_BUSY;
1793                         r |= HIFN_DMACSR_S_CTRL_DIS;
1794                 }
1795                 if (dma->dstu == 0 && (dev->flags & HIFN_FLAG_DST_BUSY)) {
1796                         dev->flags &= ~HIFN_FLAG_DST_BUSY;
1797                         r |= HIFN_DMACSR_D_CTRL_DIS;
1798                 }
1799                 if (dma->resu == 0 && (dev->flags & HIFN_FLAG_RES_BUSY)) {
1800                         dev->flags &= ~HIFN_FLAG_RES_BUSY;
1801                         r |= HIFN_DMACSR_R_CTRL_DIS;
1802                 }
1803                 if (r)
1804                         hifn_write_1(dev, HIFN_1_DMA_CSR, r);
1805         } else
1806                 dev->active--;
1807
1808         if ((dev->prev_success == dev->success) && dev->started)
1809                 reset = 1;
1810         dev->prev_success = dev->success;
1811         spin_unlock_irqrestore(&dev->lock, flags);
1812
1813         if (reset) {
1814                 if (++dev->reset >= 5) {
1815                         int i;
1816                         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1817
1818                         dev_info(&dev->pdev->dev,
1819                                  "r: %08x, active: %d, started: %d, "
1820                                  "success: %lu: qlen: %u/%u, reset: %d.\n",
1821                                  r, dev->active, dev->started,
1822                                  dev->success, dev->queue.qlen, dev->queue.max_qlen,
1823                                  reset);
1824
1825                         dev_info(&dev->pdev->dev, "%s: res: ", __func__);
1826                         for (i = 0; i < HIFN_D_RES_RSIZE; ++i) {
1827                                 pr_info("%x.%p ", dma->resr[i].l, dev->sa[i]);
1828                                 if (dev->sa[i]) {
1829                                         hifn_process_ready(dev->sa[i], -ENODEV);
1830                                         hifn_complete_sa(dev, i);
1831                                 }
1832                         }
1833                         pr_info("\n");
1834
1835                         hifn_reset_dma(dev, 1);
1836                         hifn_stop_device(dev);
1837                         hifn_start_device(dev);
1838                         dev->reset = 0;
1839                 }
1840
1841                 tasklet_schedule(&dev->tasklet);
1842         }
1843
1844         schedule_delayed_work(&dev->work, HZ);
1845 }
1846
1847 static irqreturn_t hifn_interrupt(int irq, void *data)
1848 {
1849         struct hifn_device *dev = (struct hifn_device *)data;
1850         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1851         u32 dmacsr, restart;
1852
1853         dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR);
1854
1855         dev_dbg(&dev->pdev->dev, "1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], "
1856                         "i: %d.%d.%d.%d, u: %d.%d.%d.%d.\n",
1857                 dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi,
1858                 dma->cmdi, dma->srci, dma->dsti, dma->resi,
1859                 dma->cmdu, dma->srcu, dma->dstu, dma->resu);
1860
1861         if ((dmacsr & dev->dmareg) == 0)
1862                 return IRQ_NONE;
1863
1864         hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg);
1865
1866         if (dmacsr & HIFN_DMACSR_ENGINE)
1867                 hifn_write_0(dev, HIFN_0_PUISR, hifn_read_0(dev, HIFN_0_PUISR));
1868         if (dmacsr & HIFN_DMACSR_PUBDONE)
1869                 hifn_write_1(dev, HIFN_1_PUB_STATUS,
1870                         hifn_read_1(dev, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
1871
1872         restart = dmacsr & (HIFN_DMACSR_R_OVER | HIFN_DMACSR_D_OVER);
1873         if (restart) {
1874                 u32 puisr = hifn_read_0(dev, HIFN_0_PUISR);
1875
1876                 dev_warn(&dev->pdev->dev, "overflow: r: %d, d: %d, puisr: %08x, d: %u.\n",
1877                          !!(dmacsr & HIFN_DMACSR_R_OVER),
1878                          !!(dmacsr & HIFN_DMACSR_D_OVER),
1879                         puisr, !!(puisr & HIFN_PUISR_DSTOVER));
1880                 if (!!(puisr & HIFN_PUISR_DSTOVER))
1881                         hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1882                 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER |
1883                                         HIFN_DMACSR_D_OVER));
1884         }
1885
1886         restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
1887                         HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
1888         if (restart) {
1889                 dev_warn(&dev->pdev->dev, "abort: c: %d, s: %d, d: %d, r: %d.\n",
1890                          !!(dmacsr & HIFN_DMACSR_C_ABORT),
1891                          !!(dmacsr & HIFN_DMACSR_S_ABORT),
1892                          !!(dmacsr & HIFN_DMACSR_D_ABORT),
1893                          !!(dmacsr & HIFN_DMACSR_R_ABORT));
1894                 hifn_reset_dma(dev, 1);
1895                 hifn_init_dma(dev);
1896                 hifn_init_registers(dev);
1897         }
1898
1899         if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
1900                 dev_dbg(&dev->pdev->dev, "wait on command.\n");
1901                 dev->dmareg &= ~(HIFN_DMAIER_C_WAIT);
1902                 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1903         }
1904
1905         tasklet_schedule(&dev->tasklet);
1906
1907         return IRQ_HANDLED;
1908 }
1909
1910 static void hifn_flush(struct hifn_device *dev)
1911 {
1912         unsigned long flags;
1913         struct crypto_async_request *async_req;
1914         struct skcipher_request *req;
1915         struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
1916         int i;
1917
1918         for (i = 0; i < HIFN_D_RES_RSIZE; ++i) {
1919                 struct hifn_desc *d = &dma->resr[i];
1920
1921                 if (dev->sa[i]) {
1922                         hifn_process_ready(dev->sa[i],
1923                                 (d->l & __cpu_to_le32(HIFN_D_VALID)) ? -ENODEV : 0);
1924                         hifn_complete_sa(dev, i);
1925                 }
1926         }
1927
1928         spin_lock_irqsave(&dev->lock, flags);
1929         while ((async_req = crypto_dequeue_request(&dev->queue))) {
1930                 req = skcipher_request_cast(async_req);
1931                 spin_unlock_irqrestore(&dev->lock, flags);
1932
1933                 hifn_process_ready(req, -ENODEV);
1934
1935                 spin_lock_irqsave(&dev->lock, flags);
1936         }
1937         spin_unlock_irqrestore(&dev->lock, flags);
1938 }
1939
1940 static int hifn_setkey(struct crypto_skcipher *cipher, const u8 *key,
1941                 unsigned int len)
1942 {
1943         struct hifn_context *ctx = crypto_skcipher_ctx(cipher);
1944         struct hifn_device *dev = ctx->dev;
1945         int err;
1946
1947         err = verify_skcipher_des_key(cipher, key);
1948         if (err)
1949                 return err;
1950
1951         dev->flags &= ~HIFN_FLAG_OLD_KEY;
1952
1953         memcpy(ctx->key, key, len);
1954         ctx->keysize = len;
1955
1956         return 0;
1957 }
1958
1959 static int hifn_des3_setkey(struct crypto_skcipher *cipher, const u8 *key,
1960                             unsigned int len)
1961 {
1962         struct hifn_context *ctx = crypto_skcipher_ctx(cipher);
1963         struct hifn_device *dev = ctx->dev;
1964         int err;
1965
1966         err = verify_skcipher_des3_key(cipher, key);
1967         if (err)
1968                 return err;
1969
1970         dev->flags &= ~HIFN_FLAG_OLD_KEY;
1971
1972         memcpy(ctx->key, key, len);
1973         ctx->keysize = len;
1974
1975         return 0;
1976 }
1977
1978 static int hifn_handle_req(struct skcipher_request *req)
1979 {
1980         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
1981         struct hifn_device *dev = ctx->dev;
1982         int err = -EAGAIN;
1983
1984         if (dev->started + DIV_ROUND_UP(req->cryptlen, PAGE_SIZE) <= HIFN_QUEUE_LENGTH)
1985                 err = hifn_setup_session(req);
1986
1987         if (err == -EAGAIN) {
1988                 unsigned long flags;
1989
1990                 spin_lock_irqsave(&dev->lock, flags);
1991                 err = crypto_enqueue_request(&dev->queue, &req->base);
1992                 spin_unlock_irqrestore(&dev->lock, flags);
1993         }
1994
1995         return err;
1996 }
1997
1998 static int hifn_setup_crypto_req(struct skcipher_request *req, u8 op,
1999                 u8 type, u8 mode)
2000 {
2001         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2002         struct hifn_request_context *rctx = skcipher_request_ctx(req);
2003         unsigned ivsize;
2004
2005         ivsize = crypto_skcipher_ivsize(crypto_skcipher_reqtfm(req));
2006
2007         if (req->iv && mode != ACRYPTO_MODE_ECB) {
2008                 if (type == ACRYPTO_TYPE_AES_128)
2009                         ivsize = HIFN_AES_IV_LENGTH;
2010                 else if (type == ACRYPTO_TYPE_DES)
2011                         ivsize = HIFN_DES_KEY_LENGTH;
2012                 else if (type == ACRYPTO_TYPE_3DES)
2013                         ivsize = HIFN_3DES_KEY_LENGTH;
2014         }
2015
2016         if (ctx->keysize != 16 && type == ACRYPTO_TYPE_AES_128) {
2017                 if (ctx->keysize == 24)
2018                         type = ACRYPTO_TYPE_AES_192;
2019                 else if (ctx->keysize == 32)
2020                         type = ACRYPTO_TYPE_AES_256;
2021         }
2022
2023         rctx->op = op;
2024         rctx->mode = mode;
2025         rctx->type = type;
2026         rctx->iv = req->iv;
2027         rctx->ivsize = ivsize;
2028
2029         /*
2030          * HEAVY TODO: needs to kick Herbert XU to write documentation.
2031          * HEAVY TODO: needs to kick Herbert XU to write documentation.
2032          * HEAVY TODO: needs to kick Herbert XU to write documentation.
2033          */
2034
2035         return hifn_handle_req(req);
2036 }
2037
2038 static int hifn_process_queue(struct hifn_device *dev)
2039 {
2040         struct crypto_async_request *async_req, *backlog;
2041         struct skcipher_request *req;
2042         unsigned long flags;
2043         int err = 0;
2044
2045         while (dev->started < HIFN_QUEUE_LENGTH) {
2046                 spin_lock_irqsave(&dev->lock, flags);
2047                 backlog = crypto_get_backlog(&dev->queue);
2048                 async_req = crypto_dequeue_request(&dev->queue);
2049                 spin_unlock_irqrestore(&dev->lock, flags);
2050
2051                 if (!async_req)
2052                         break;
2053
2054                 if (backlog)
2055                         backlog->complete(backlog, -EINPROGRESS);
2056
2057                 req = skcipher_request_cast(async_req);
2058
2059                 err = hifn_handle_req(req);
2060                 if (err)
2061                         break;
2062         }
2063
2064         return err;
2065 }
2066
2067 static int hifn_setup_crypto(struct skcipher_request *req, u8 op,
2068                 u8 type, u8 mode)
2069 {
2070         int err;
2071         struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
2072         struct hifn_device *dev = ctx->dev;
2073
2074         err = hifn_setup_crypto_req(req, op, type, mode);
2075         if (err)
2076                 return err;
2077
2078         if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
2079                 hifn_process_queue(dev);
2080
2081         return -EINPROGRESS;
2082 }
2083
2084 /*
2085  * AES ecryption functions.
2086  */
2087 static inline int hifn_encrypt_aes_ecb(struct skcipher_request *req)
2088 {
2089         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2090                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2091 }
2092 static inline int hifn_encrypt_aes_cbc(struct skcipher_request *req)
2093 {
2094         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2095                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2096 }
2097 static inline int hifn_encrypt_aes_cfb(struct skcipher_request *req)
2098 {
2099         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2100                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2101 }
2102 static inline int hifn_encrypt_aes_ofb(struct skcipher_request *req)
2103 {
2104         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2105                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2106 }
2107
2108 /*
2109  * AES decryption functions.
2110  */
2111 static inline int hifn_decrypt_aes_ecb(struct skcipher_request *req)
2112 {
2113         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2114                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
2115 }
2116 static inline int hifn_decrypt_aes_cbc(struct skcipher_request *req)
2117 {
2118         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2119                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
2120 }
2121 static inline int hifn_decrypt_aes_cfb(struct skcipher_request *req)
2122 {
2123         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2124                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
2125 }
2126 static inline int hifn_decrypt_aes_ofb(struct skcipher_request *req)
2127 {
2128         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2129                         ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
2130 }
2131
2132 /*
2133  * DES ecryption functions.
2134  */
2135 static inline int hifn_encrypt_des_ecb(struct skcipher_request *req)
2136 {
2137         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2138                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2139 }
2140 static inline int hifn_encrypt_des_cbc(struct skcipher_request *req)
2141 {
2142         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2143                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2144 }
2145 static inline int hifn_encrypt_des_cfb(struct skcipher_request *req)
2146 {
2147         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2148                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2149 }
2150 static inline int hifn_encrypt_des_ofb(struct skcipher_request *req)
2151 {
2152         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2153                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2154 }
2155
2156 /*
2157  * DES decryption functions.
2158  */
2159 static inline int hifn_decrypt_des_ecb(struct skcipher_request *req)
2160 {
2161         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2162                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
2163 }
2164 static inline int hifn_decrypt_des_cbc(struct skcipher_request *req)
2165 {
2166         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2167                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
2168 }
2169 static inline int hifn_decrypt_des_cfb(struct skcipher_request *req)
2170 {
2171         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2172                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
2173 }
2174 static inline int hifn_decrypt_des_ofb(struct skcipher_request *req)
2175 {
2176         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2177                         ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
2178 }
2179
2180 /*
2181  * 3DES ecryption functions.
2182  */
2183 static inline int hifn_encrypt_3des_ecb(struct skcipher_request *req)
2184 {
2185         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2186                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2187 }
2188 static inline int hifn_encrypt_3des_cbc(struct skcipher_request *req)
2189 {
2190         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2191                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2192 }
2193 static inline int hifn_encrypt_3des_cfb(struct skcipher_request *req)
2194 {
2195         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2196                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2197 }
2198 static inline int hifn_encrypt_3des_ofb(struct skcipher_request *req)
2199 {
2200         return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
2201                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2202 }
2203
2204 /* 3DES decryption functions. */
2205 static inline int hifn_decrypt_3des_ecb(struct skcipher_request *req)
2206 {
2207         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2208                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
2209 }
2210 static inline int hifn_decrypt_3des_cbc(struct skcipher_request *req)
2211 {
2212         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2213                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
2214 }
2215 static inline int hifn_decrypt_3des_cfb(struct skcipher_request *req)
2216 {
2217         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2218                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
2219 }
2220 static inline int hifn_decrypt_3des_ofb(struct skcipher_request *req)
2221 {
2222         return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
2223                         ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
2224 }
2225
2226 struct hifn_alg_template {
2227         char name[CRYPTO_MAX_ALG_NAME];
2228         char drv_name[CRYPTO_MAX_ALG_NAME];
2229         unsigned int bsize;
2230         struct skcipher_alg skcipher;
2231 };
2232
2233 static const struct hifn_alg_template hifn_alg_templates[] = {
2234         /*
2235          * 3DES ECB, CBC, CFB and OFB modes.
2236          */
2237         {
2238                 .name = "cfb(des3_ede)", .drv_name = "cfb-3des", .bsize = 8,
2239                 .skcipher = {
2240                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2241                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2242                         .setkey         =       hifn_des3_setkey,
2243                         .encrypt        =       hifn_encrypt_3des_cfb,
2244                         .decrypt        =       hifn_decrypt_3des_cfb,
2245                 },
2246         },
2247         {
2248                 .name = "ofb(des3_ede)", .drv_name = "ofb-3des", .bsize = 8,
2249                 .skcipher = {
2250                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2251                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2252                         .setkey         =       hifn_des3_setkey,
2253                         .encrypt        =       hifn_encrypt_3des_ofb,
2254                         .decrypt        =       hifn_decrypt_3des_ofb,
2255                 },
2256         },
2257         {
2258                 .name = "cbc(des3_ede)", .drv_name = "cbc-3des", .bsize = 8,
2259                 .skcipher = {
2260                         .ivsize         =       HIFN_IV_LENGTH,
2261                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2262                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2263                         .setkey         =       hifn_des3_setkey,
2264                         .encrypt        =       hifn_encrypt_3des_cbc,
2265                         .decrypt        =       hifn_decrypt_3des_cbc,
2266                 },
2267         },
2268         {
2269                 .name = "ecb(des3_ede)", .drv_name = "ecb-3des", .bsize = 8,
2270                 .skcipher = {
2271                         .min_keysize    =       HIFN_3DES_KEY_LENGTH,
2272                         .max_keysize    =       HIFN_3DES_KEY_LENGTH,
2273                         .setkey         =       hifn_des3_setkey,
2274                         .encrypt        =       hifn_encrypt_3des_ecb,
2275                         .decrypt        =       hifn_decrypt_3des_ecb,
2276                 },
2277         },
2278
2279         /*
2280          * DES ECB, CBC, CFB and OFB modes.
2281          */
2282         {
2283                 .name = "cfb(des)", .drv_name = "cfb-des", .bsize = 8,
2284                 .skcipher = {
2285                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2286                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2287                         .setkey         =       hifn_setkey,
2288                         .encrypt        =       hifn_encrypt_des_cfb,
2289                         .decrypt        =       hifn_decrypt_des_cfb,
2290                 },
2291         },
2292         {
2293                 .name = "ofb(des)", .drv_name = "ofb-des", .bsize = 8,
2294                 .skcipher = {
2295                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2296                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2297                         .setkey         =       hifn_setkey,
2298                         .encrypt        =       hifn_encrypt_des_ofb,
2299                         .decrypt        =       hifn_decrypt_des_ofb,
2300                 },
2301         },
2302         {
2303                 .name = "cbc(des)", .drv_name = "cbc-des", .bsize = 8,
2304                 .skcipher = {
2305                         .ivsize         =       HIFN_IV_LENGTH,
2306                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2307                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2308                         .setkey         =       hifn_setkey,
2309                         .encrypt        =       hifn_encrypt_des_cbc,
2310                         .decrypt        =       hifn_decrypt_des_cbc,
2311                 },
2312         },
2313         {
2314                 .name = "ecb(des)", .drv_name = "ecb-des", .bsize = 8,
2315                 .skcipher = {
2316                         .min_keysize    =       HIFN_DES_KEY_LENGTH,
2317                         .max_keysize    =       HIFN_DES_KEY_LENGTH,
2318                         .setkey         =       hifn_setkey,
2319                         .encrypt        =       hifn_encrypt_des_ecb,
2320                         .decrypt        =       hifn_decrypt_des_ecb,
2321                 },
2322         },
2323
2324         /*
2325          * AES ECB, CBC, CFB and OFB modes.
2326          */
2327         {
2328                 .name = "ecb(aes)", .drv_name = "ecb-aes", .bsize = 16,
2329                 .skcipher = {
2330                         .min_keysize    =       AES_MIN_KEY_SIZE,
2331                         .max_keysize    =       AES_MAX_KEY_SIZE,
2332                         .setkey         =       hifn_setkey,
2333                         .encrypt        =       hifn_encrypt_aes_ecb,
2334                         .decrypt        =       hifn_decrypt_aes_ecb,
2335                 },
2336         },
2337         {
2338                 .name = "cbc(aes)", .drv_name = "cbc-aes", .bsize = 16,
2339                 .skcipher = {
2340                         .ivsize         =       HIFN_AES_IV_LENGTH,
2341                         .min_keysize    =       AES_MIN_KEY_SIZE,
2342                         .max_keysize    =       AES_MAX_KEY_SIZE,
2343                         .setkey         =       hifn_setkey,
2344                         .encrypt        =       hifn_encrypt_aes_cbc,
2345                         .decrypt        =       hifn_decrypt_aes_cbc,
2346                 },
2347         },
2348         {
2349                 .name = "cfb(aes)", .drv_name = "cfb-aes", .bsize = 16,
2350                 .skcipher = {
2351                         .min_keysize    =       AES_MIN_KEY_SIZE,
2352                         .max_keysize    =       AES_MAX_KEY_SIZE,
2353                         .setkey         =       hifn_setkey,
2354                         .encrypt        =       hifn_encrypt_aes_cfb,
2355                         .decrypt        =       hifn_decrypt_aes_cfb,
2356                 },
2357         },
2358         {
2359                 .name = "ofb(aes)", .drv_name = "ofb-aes", .bsize = 16,
2360                 .skcipher = {
2361                         .min_keysize    =       AES_MIN_KEY_SIZE,
2362                         .max_keysize    =       AES_MAX_KEY_SIZE,
2363                         .setkey         =       hifn_setkey,
2364                         .encrypt        =       hifn_encrypt_aes_ofb,
2365                         .decrypt        =       hifn_decrypt_aes_ofb,
2366                 },
2367         },
2368 };
2369
2370 static int hifn_init_tfm(struct crypto_skcipher *tfm)
2371 {
2372         struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
2373         struct hifn_crypto_alg *ha = crypto_alg_to_hifn(alg);
2374         struct hifn_context *ctx = crypto_skcipher_ctx(tfm);
2375
2376         ctx->dev = ha->dev;
2377         crypto_skcipher_set_reqsize(tfm, sizeof(struct hifn_request_context));
2378
2379         return 0;
2380 }
2381
2382 static int hifn_alg_alloc(struct hifn_device *dev, const struct hifn_alg_template *t)
2383 {
2384         struct hifn_crypto_alg *alg;
2385         int err;
2386
2387         alg = kzalloc(sizeof(*alg), GFP_KERNEL);
2388         if (!alg)
2389                 return -ENOMEM;
2390
2391         alg->alg = t->skcipher;
2392         alg->alg.init = hifn_init_tfm;
2393
2394         snprintf(alg->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", t->name);
2395         snprintf(alg->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-%s",
2396                  t->drv_name, dev->name);
2397
2398         alg->alg.base.cra_priority = 300;
2399         alg->alg.base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC;
2400         alg->alg.base.cra_blocksize = t->bsize;
2401         alg->alg.base.cra_ctxsize = sizeof(struct hifn_context);
2402         alg->alg.base.cra_alignmask = 0;
2403         alg->alg.base.cra_module = THIS_MODULE;
2404
2405         alg->dev = dev;
2406
2407         list_add_tail(&alg->entry, &dev->alg_list);
2408
2409         err = crypto_register_skcipher(&alg->alg);
2410         if (err) {
2411                 list_del(&alg->entry);
2412                 kfree(alg);
2413         }
2414
2415         return err;
2416 }
2417
2418 static void hifn_unregister_alg(struct hifn_device *dev)
2419 {
2420         struct hifn_crypto_alg *a, *n;
2421
2422         list_for_each_entry_safe(a, n, &dev->alg_list, entry) {
2423                 list_del(&a->entry);
2424                 crypto_unregister_skcipher(&a->alg);
2425                 kfree(a);
2426         }
2427 }
2428
2429 static int hifn_register_alg(struct hifn_device *dev)
2430 {
2431         int i, err;
2432
2433         for (i = 0; i < ARRAY_SIZE(hifn_alg_templates); ++i) {
2434                 err = hifn_alg_alloc(dev, &hifn_alg_templates[i]);
2435                 if (err)
2436                         goto err_out_exit;
2437         }
2438
2439         return 0;
2440
2441 err_out_exit:
2442         hifn_unregister_alg(dev);
2443         return err;
2444 }
2445
2446 static void hifn_tasklet_callback(unsigned long data)
2447 {
2448         struct hifn_device *dev = (struct hifn_device *)data;
2449
2450         /*
2451          * This is ok to call this without lock being held,
2452          * althogh it modifies some parameters used in parallel,
2453          * (like dev->success), but they are used in process
2454          * context or update is atomic (like setting dev->sa[i] to NULL).
2455          */
2456         hifn_clear_rings(dev, 0);
2457
2458         if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
2459                 hifn_process_queue(dev);
2460 }
2461
2462 static int hifn_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2463 {
2464         int err, i;
2465         struct hifn_device *dev;
2466         char name[8];
2467
2468         err = pci_enable_device(pdev);
2469         if (err)
2470                 return err;
2471         pci_set_master(pdev);
2472
2473         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2474         if (err)
2475                 goto err_out_disable_pci_device;
2476
2477         snprintf(name, sizeof(name), "hifn%d",
2478                         atomic_inc_return(&hifn_dev_number) - 1);
2479
2480         err = pci_request_regions(pdev, name);
2481         if (err)
2482                 goto err_out_disable_pci_device;
2483
2484         if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE ||
2485             pci_resource_len(pdev, 1) < HIFN_BAR1_SIZE ||
2486             pci_resource_len(pdev, 2) < HIFN_BAR2_SIZE) {
2487                 dev_err(&pdev->dev, "Broken hardware - I/O regions are too small.\n");
2488                 err = -ENODEV;
2489                 goto err_out_free_regions;
2490         }
2491
2492         dev = kzalloc(sizeof(struct hifn_device) + sizeof(struct crypto_alg),
2493                         GFP_KERNEL);
2494         if (!dev) {
2495                 err = -ENOMEM;
2496                 goto err_out_free_regions;
2497         }
2498
2499         INIT_LIST_HEAD(&dev->alg_list);
2500
2501         snprintf(dev->name, sizeof(dev->name), "%s", name);
2502         spin_lock_init(&dev->lock);
2503
2504         for (i = 0; i < 3; ++i) {
2505                 unsigned long addr, size;
2506
2507                 addr = pci_resource_start(pdev, i);
2508                 size = pci_resource_len(pdev, i);
2509
2510                 dev->bar[i] = ioremap_nocache(addr, size);
2511                 if (!dev->bar[i]) {
2512                         err = -ENOMEM;
2513                         goto err_out_unmap_bars;
2514                 }
2515         }
2516
2517         dev->desc_virt = pci_zalloc_consistent(pdev, sizeof(struct hifn_dma),
2518                                                &dev->desc_dma);
2519         if (!dev->desc_virt) {
2520                 dev_err(&pdev->dev, "Failed to allocate descriptor rings.\n");
2521                 err = -ENOMEM;
2522                 goto err_out_unmap_bars;
2523         }
2524
2525         dev->pdev = pdev;
2526         dev->irq = pdev->irq;
2527
2528         for (i = 0; i < HIFN_D_RES_RSIZE; ++i)
2529                 dev->sa[i] = NULL;
2530
2531         pci_set_drvdata(pdev, dev);
2532
2533         tasklet_init(&dev->tasklet, hifn_tasklet_callback, (unsigned long)dev);
2534
2535         crypto_init_queue(&dev->queue, 1);
2536
2537         err = request_irq(dev->irq, hifn_interrupt, IRQF_SHARED, dev->name, dev);
2538         if (err) {
2539                 dev_err(&pdev->dev, "Failed to request IRQ%d: err: %d.\n",
2540                         dev->irq, err);
2541                 dev->irq = 0;
2542                 goto err_out_free_desc;
2543         }
2544
2545         err = hifn_start_device(dev);
2546         if (err)
2547                 goto err_out_free_irq;
2548
2549         err = hifn_register_rng(dev);
2550         if (err)
2551                 goto err_out_stop_device;
2552
2553         err = hifn_register_alg(dev);
2554         if (err)
2555                 goto err_out_unregister_rng;
2556
2557         INIT_DELAYED_WORK(&dev->work, hifn_work);
2558         schedule_delayed_work(&dev->work, HZ);
2559
2560         dev_dbg(&pdev->dev, "HIFN crypto accelerator card at %s has been "
2561                 "successfully registered as %s.\n",
2562                 pci_name(pdev), dev->name);
2563
2564         return 0;
2565
2566 err_out_unregister_rng:
2567         hifn_unregister_rng(dev);
2568 err_out_stop_device:
2569         hifn_reset_dma(dev, 1);
2570         hifn_stop_device(dev);
2571 err_out_free_irq:
2572         free_irq(dev->irq, dev);
2573         tasklet_kill(&dev->tasklet);
2574 err_out_free_desc:
2575         pci_free_consistent(pdev, sizeof(struct hifn_dma),
2576                         dev->desc_virt, dev->desc_dma);
2577
2578 err_out_unmap_bars:
2579         for (i = 0; i < 3; ++i)
2580                 if (dev->bar[i])
2581                         iounmap(dev->bar[i]);
2582         kfree(dev);
2583
2584 err_out_free_regions:
2585         pci_release_regions(pdev);
2586
2587 err_out_disable_pci_device:
2588         pci_disable_device(pdev);
2589
2590         return err;
2591 }
2592
2593 static void hifn_remove(struct pci_dev *pdev)
2594 {
2595         int i;
2596         struct hifn_device *dev;
2597
2598         dev = pci_get_drvdata(pdev);
2599
2600         if (dev) {
2601                 cancel_delayed_work_sync(&dev->work);
2602
2603                 hifn_unregister_rng(dev);
2604                 hifn_unregister_alg(dev);
2605                 hifn_reset_dma(dev, 1);
2606                 hifn_stop_device(dev);
2607
2608                 free_irq(dev->irq, dev);
2609                 tasklet_kill(&dev->tasklet);
2610
2611                 hifn_flush(dev);
2612
2613                 pci_free_consistent(pdev, sizeof(struct hifn_dma),
2614                                 dev->desc_virt, dev->desc_dma);
2615                 for (i = 0; i < 3; ++i)
2616                         if (dev->bar[i])
2617                                 iounmap(dev->bar[i]);
2618
2619                 kfree(dev);
2620         }
2621
2622         pci_release_regions(pdev);
2623         pci_disable_device(pdev);
2624 }
2625
2626 static struct pci_device_id hifn_pci_tbl[] = {
2627         { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7955) },
2628         { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7956) },
2629         { 0 }
2630 };
2631 MODULE_DEVICE_TABLE(pci, hifn_pci_tbl);
2632
2633 static struct pci_driver hifn_pci_driver = {
2634         .name     = "hifn795x",
2635         .id_table = hifn_pci_tbl,
2636         .probe    = hifn_probe,
2637         .remove   = hifn_remove,
2638 };
2639
2640 static int __init hifn_init(void)
2641 {
2642         unsigned int freq;
2643         int err;
2644
2645         /* HIFN supports only 32-bit addresses */
2646         BUILD_BUG_ON(sizeof(dma_addr_t) != 4);
2647
2648         if (strncmp(hifn_pll_ref, "ext", 3) &&
2649             strncmp(hifn_pll_ref, "pci", 3)) {
2650                 pr_err("hifn795x: invalid hifn_pll_ref clock, must be pci or ext");
2651                 return -EINVAL;
2652         }
2653
2654         /*
2655          * For the 7955/7956 the reference clock frequency must be in the
2656          * range of 20MHz-100MHz. For the 7954 the upper bound is 66.67MHz,
2657          * but this chip is currently not supported.
2658          */
2659         if (hifn_pll_ref[3] != '\0') {
2660                 freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
2661                 if (freq < 20 || freq > 100) {
2662                         pr_err("hifn795x: invalid hifn_pll_ref frequency, must"
2663                                "be in the range of 20-100");
2664                         return -EINVAL;
2665                 }
2666         }
2667
2668         err = pci_register_driver(&hifn_pci_driver);
2669         if (err < 0) {
2670                 pr_err("Failed to register PCI driver for %s device.\n",
2671                        hifn_pci_driver.name);
2672                 return -ENODEV;
2673         }
2674
2675         pr_info("Driver for HIFN 795x crypto accelerator chip "
2676                 "has been successfully registered.\n");
2677
2678         return 0;
2679 }
2680
2681 static void __exit hifn_fini(void)
2682 {
2683         pci_unregister_driver(&hifn_pci_driver);
2684
2685         pr_info("Driver for HIFN 795x crypto accelerator chip "
2686                 "has been successfully unregistered.\n");
2687 }
2688
2689 module_init(hifn_init);
2690 module_exit(hifn_fini);
2691
2692 MODULE_LICENSE("GPL");
2693 MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>");
2694 MODULE_DESCRIPTION("Driver for HIFN 795x crypto accelerator chip.");