1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sl3516-ce.h - hardware cryptographic offloader for cortina/gemini SoC
5 * Copyright (C) 2021 Corentin LABBE <clabbe@baylibre.com>
7 * General notes on this driver:
8 * Called either Crypto Acceleration Engine Module, Security Acceleration Engine
9 * or IPSEC module in the datasheet, it will be called Crypto Engine for short
11 * The CE was designed to handle IPSEC and wifi(TKIP WEP) protocol.
12 * It can handle AES, DES, 3DES, MD5, WEP, TKIP, SHA1, HMAC(MD5), HMAC(SHA1),
13 * Michael cipher/digest suites.
14 * It acts the same as a network hw, with both RX and TX chained descriptors.
16 #include <crypto/aes.h>
17 #include <crypto/engine.h>
18 #include <crypto/scatterwalk.h>
19 #include <crypto/skcipher.h>
20 #include <linux/crypto.h>
21 #include <linux/debugfs.h>
22 #include <linux/hw_random.h>
24 #define TQ0_TYPE_DATA 0
25 #define TQ0_TYPE_CTRL BIT(0)
26 #define TQ1_CIPHER BIT(1)
27 #define TQ2_AUTH BIT(2)
29 #define TQ4_KEY0 BIT(4)
30 #define TQ5_KEY4 BIT(5)
31 #define TQ6_KEY6 BIT(6)
32 #define TQ7_AKEY0 BIT(7)
33 #define TQ8_AKEY2 BIT(8)
34 #define TQ9_AKEY2 BIT(9)
38 #define DESC_LAST 0x01
39 #define DESC_FIRST 0x02
41 #define IPSEC_ID 0x0000
42 #define IPSEC_STATUS_REG 0x00a8
43 #define IPSEC_RAND_NUM_REG 0x00ac
44 #define IPSEC_DMA_DEVICE_ID 0xff00
45 #define IPSEC_DMA_STATUS 0xff04
46 #define IPSEC_TXDMA_CTRL 0xff08
47 #define IPSEC_TXDMA_FIRST_DESC 0xff0c
48 #define IPSEC_TXDMA_CURR_DESC 0xff10
49 #define IPSEC_RXDMA_CTRL 0xff14
50 #define IPSEC_RXDMA_FIRST_DESC 0xff18
51 #define IPSEC_RXDMA_CURR_DESC 0xff1c
52 #define IPSEC_TXDMA_BUF_ADDR 0xff28
53 #define IPSEC_RXDMA_BUF_ADDR 0xff38
54 #define IPSEC_RXDMA_BUF_SIZE 0xff30
56 #define CE_ENCRYPTION 0x01
57 #define CE_DECRYPTION 0x03
61 #define DMA_STATUS_RS_EOFI BIT(22)
62 #define DMA_STATUS_RS_PERR BIT(24)
63 #define DMA_STATUS_RS_DERR BIT(25)
64 #define DMA_STATUS_TS_EOFI BIT(27)
65 #define DMA_STATUS_TS_PERR BIT(29)
66 #define DMA_STATUS_TS_DERR BIT(30)
68 #define TXDMA_CTRL_START BIT(31)
69 #define TXDMA_CTRL_CONTINUE BIT(30)
70 #define TXDMA_CTRL_CHAIN_MODE BIT(29)
71 /* the burst value is not documented in the datasheet */
72 #define TXDMA_CTRL_BURST_UNK BIT(22)
73 #define TXDMA_CTRL_INT_FAIL BIT(17)
74 #define TXDMA_CTRL_INT_PERR BIT(16)
76 #define RXDMA_CTRL_START BIT(31)
77 #define RXDMA_CTRL_CONTINUE BIT(30)
78 #define RXDMA_CTRL_CHAIN_MODE BIT(29)
79 /* the burst value is not documented in the datasheet */
80 #define RXDMA_CTRL_BURST_UNK BIT(22)
81 #define RXDMA_CTRL_INT_FINISH BIT(18)
82 #define RXDMA_CTRL_INT_FAIL BIT(17)
83 #define RXDMA_CTRL_INT_PERR BIT(16)
84 #define RXDMA_CTRL_INT_EOD BIT(15)
85 #define RXDMA_CTRL_INT_EOF BIT(14)
91 * struct sl3516_ce_descriptor - descriptor for CE operations
92 * @frame_ctrl: Information for the current descriptor
93 * @flag_status: For send packet, describe flag of operations.
94 * @buf_adr: pointer to a send/recv buffer for data packet
95 * @next_desc: control linking to other descriptors
101 * struct desc_frame_ctrl - Information for the current descriptor
102 * @buffer_size: the size of buffer at buf_adr
103 * @desc_count: Upon completion of a DMA operation, DMA
104 * write the number of descriptors used
105 * for the current frame
108 * @perr: Protocol error during processing this descriptor
109 * @derr: Data error during processing this descriptor
110 * @own: 0 if owned by CPU, 1 for DMA
112 struct desc_frame_ctrl {
126 * struct desc_flag_status - flag for this descriptor
127 * @tqflag: list of flag describing the type of operation
130 struct desc_tx_flag_status {
141 * struct desc_next - describe chaining of descriptors
142 * @sof_eof: does the descriptor is first (0x11),
143 * the last (0x01), middle of a chan (0x00)
144 * or the only one (0x11)
145 * @dec: AHB bus address increase (0), decrease (1)
146 * @eofie: End of frame interrupt enable
147 * @ndar: Next descriptor address
159 * struct control - The value of this register is used to set the
160 * operation mode of the IPSec Module.
161 * @process_id: Used to identify the process. The number will be copied
162 * to the descriptor status of the received packet.
163 * @auth_check_len: Number of 32-bit words to be checked or appended by the
164 * authentication module
166 * @auth_mode: 0:append 1:Check Authentication Result
167 * @fcs_stream_copy: 0:enable 1:disable authentication stream copy
168 * @mix_key_sel: 0:use rCipherKey0-3 1:use Key Mixer
169 * @aesnk: AES Key Size
170 * @cipher_algorithm: choice of CBC/ECE and AES/DES/3DES
171 * @op_mode: Operation Mode for the IPSec Module
173 struct pkt_control_header {
175 u32 auth_check_len :3;
177 u32 auth_algorithm :3;
179 u32 fcs_stream_copy :1;
183 u32 cipher_algorithm :3;
188 struct pkt_control_cipher {
189 u32 algorithm_len :16;
194 * struct pkt_control_ecb - control packet for ECB
196 struct pkt_control_ecb {
197 struct pkt_control_header control;
198 struct pkt_control_cipher cipher;
199 unsigned char key[AES_MAX_KEY_SIZE];
203 * struct sl3516_ce_dev - main container for all this driver information
204 * @base: base address
206 * @reset: pointer to reset controller
207 * @dev: the platform device
208 * @engine: ptr to the crypto/crypto_engine
209 * @complete: completion for the current task on this flow
210 * @status: set to 1 by interrupt if task is done
211 * @dtx: base DMA address for TX descriptors
212 * @tx base address of TX descriptors
213 * @drx: base DMA address for RX descriptors
214 * @rx base address of RX descriptors
215 * @ctx current used TX descriptor
216 * @crx current used RX descriptor
217 * @trng hw_random structure for RNG
218 * @hwrng_stat_req number of HWRNG requests
219 * @hwrng_stat_bytes total number of bytes generated by RNG
220 * @stat_irq number of IRQ handled by CE
221 * @stat_irq_tx number of TX IRQ handled by CE
222 * @stat_irq_rx number of RX IRQ handled by CE
223 * @stat_req number of requests handled by CE
224 * @fallbak_sg_count_tx number of fallback due to destination SG count
225 * @fallbak_sg_count_rx number of fallback due to source SG count
226 * @fallbak_not_same_len number of fallback due to difference in SG length
227 * @dbgfs_dir: Debugfs dentry for statistic directory
228 * @dbgfs_stats: Debugfs dentry for statistic counters
230 struct sl3516_ce_dev {
233 struct reset_control *reset;
235 struct crypto_engine *engine;
236 struct completion complete;
239 struct descriptor *tx;
241 struct descriptor *rx;
245 unsigned long hwrng_stat_req;
246 unsigned long hwrng_stat_bytes;
247 unsigned long stat_irq;
248 unsigned long stat_irq_tx;
249 unsigned long stat_irq_rx;
250 unsigned long stat_req;
251 unsigned long fallback_sg_count_tx;
252 unsigned long fallback_sg_count_rx;
253 unsigned long fallback_not_same_len;
254 unsigned long fallback_mod16;
255 unsigned long fallback_align16;
256 #ifdef CONFIG_CRYPTO_DEV_SL3516_DEBUG
257 struct dentry *dbgfs_dir;
258 struct dentry *dbgfs_stats;
270 * struct sl3516_ce_cipher_req_ctx - context for a skcipher request
271 * @t_src: list of mapped SGs with their size
272 * @t_dst: list of mapped SGs with their size
273 * @op_dir: direction (encrypt vs decrypt) for this request
274 * @pctrllen: the length of the ctrl packet
275 * @tqflag: the TQflag to set in data packet
276 * @h pointer to the pkt_control_cipher header
277 * @nr_sgs: number of source SG
278 * @nr_sgd: number of destination SG
279 * @fallback_req: request struct for invoking the fallback skcipher TFM
281 struct sl3516_ce_cipher_req_ctx {
282 struct sginfo t_src[MAXDESC];
283 struct sginfo t_dst[MAXDESC];
285 unsigned int pctrllen;
287 struct pkt_control_cipher *h;
290 struct skcipher_request fallback_req; // keep at the end
294 * struct sl3516_ce_cipher_tfm_ctx - context for a skcipher TFM
295 * @enginectx: crypto_engine used by this TFM
296 * @key: pointer to key data
297 * @keylen: len of the key
298 * @ce: pointer to the private data of driver handling this TFM
299 * @fallback_tfm: pointer to the fallback TFM
301 * enginectx must be the first element
303 struct sl3516_ce_cipher_tfm_ctx {
304 struct crypto_engine_ctx enginectx;
307 struct sl3516_ce_dev *ce;
308 struct crypto_skcipher *fallback_tfm;
312 * struct sl3516_ce_alg_template - crypto_alg template
313 * @type: the CRYPTO_ALG_TYPE for this template
314 * @mode: value to be used in control packet for this algorithm
315 * @ce: pointer to the sl3516_ce_dev structure associated with
317 * @alg: one of sub struct must be used
318 * @stat_req: number of request done on this template
319 * @stat_fb: number of request which has fallbacked
320 * @stat_bytes: total data size done by this template
322 struct sl3516_ce_alg_template {
325 struct sl3516_ce_dev *ce;
327 struct skcipher_alg skcipher;
329 unsigned long stat_req;
330 unsigned long stat_fb;
331 unsigned long stat_bytes;
334 int sl3516_ce_enqueue(struct crypto_async_request *areq, u32 type);
336 int sl3516_ce_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
337 unsigned int keylen);
338 int sl3516_ce_cipher_init(struct crypto_tfm *tfm);
339 void sl3516_ce_cipher_exit(struct crypto_tfm *tfm);
340 int sl3516_ce_skdecrypt(struct skcipher_request *areq);
341 int sl3516_ce_skencrypt(struct skcipher_request *areq);
343 int sl3516_ce_run_task(struct sl3516_ce_dev *ce,
344 struct sl3516_ce_cipher_req_ctx *rctx, const char *name);
346 int sl3516_ce_rng_register(struct sl3516_ce_dev *ce);
347 void sl3516_ce_rng_unregister(struct sl3516_ce_dev *ce);