1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
5 * ARM CryptoCell Linux Crypto Driver
8 #ifndef __CC_DRIVER_H__
9 #define __CC_DRIVER_H__
12 #include <linux/workqueue.h>
14 #include <linux/interrupt.h>
16 #include <linux/dma-mapping.h>
17 #include <crypto/algapi.h>
18 #include <crypto/internal/skcipher.h>
19 #include <crypto/aes.h>
20 #include <crypto/sha1.h>
21 #include <crypto/sha2.h>
22 #include <crypto/aead.h>
23 #include <crypto/authenc.h>
24 #include <crypto/hash.h>
25 #include <crypto/skcipher.h>
26 #include <linux/version.h>
27 #include <linux/clk.h>
28 #include <linux/platform_device.h>
30 #include "cc_host_regs.h"
31 #include "cc_crypto_ctx.h"
32 #include "cc_hw_queue_defs.h"
33 #include "cc_sram_mgr.h"
35 extern bool cc_dump_desc;
36 extern bool cc_dump_bytes;
38 #define DRV_MODULE_VERSION "5.0"
53 #define CC_PINS_FULL 0x0
54 #define CC_PINS_SLIM 0x9F
56 /* Maximum DMA mask supported by IP */
57 #define DMA_BIT_MASK_LEN 48
59 #define CC_AXI_IRQ_MASK ((1 << CC_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \
60 (1 << CC_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \
61 (1 << CC_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \
62 (1 << CC_AXIM_CFG_COMPMASK_BIT_SHIFT))
64 #define CC_AXI_ERR_IRQ_MASK BIT(CC_HOST_IRR_AXI_ERR_INT_BIT_SHIFT)
66 #define CC_COMP_IRQ_MASK BIT(CC_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)
68 #define CC_SECURITY_DISABLED_MASK BIT(CC_SECURITY_DISABLED_VALUE_BIT_SHIFT)
70 #define CC_NVM_IS_IDLE_MASK BIT(CC_NVM_IS_IDLE_VALUE_BIT_SHIFT)
72 #define AXIM_MON_COMP_VALUE CC_GENMASK(CC_AXIM_MON_COMP_VALUE)
74 #define CC_CPP_AES_ABORT_MASK ( \
75 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_0_MASK_BIT_SHIFT) | \
76 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_1_MASK_BIT_SHIFT) | \
77 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_2_MASK_BIT_SHIFT) | \
78 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_3_MASK_BIT_SHIFT) | \
79 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_4_MASK_BIT_SHIFT) | \
80 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_5_MASK_BIT_SHIFT) | \
81 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_6_MASK_BIT_SHIFT) | \
82 BIT(CC_HOST_IMR_REE_OP_ABORTED_AES_7_MASK_BIT_SHIFT))
84 #define CC_CPP_SM4_ABORT_MASK ( \
85 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_0_MASK_BIT_SHIFT) | \
86 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_1_MASK_BIT_SHIFT) | \
87 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_2_MASK_BIT_SHIFT) | \
88 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_3_MASK_BIT_SHIFT) | \
89 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_4_MASK_BIT_SHIFT) | \
90 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_5_MASK_BIT_SHIFT) | \
91 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_6_MASK_BIT_SHIFT) | \
92 BIT(CC_HOST_IMR_REE_OP_ABORTED_SM_7_MASK_BIT_SHIFT))
94 /* Register name mangling macro */
95 #define CC_REG(reg_name) CC_ ## reg_name ## _REG_OFFSET
97 /* TEE FIPS status interrupt */
98 #define CC_GPR0_IRQ_MASK BIT(CC_HOST_IRR_GPR0_BIT_SHIFT)
100 #define CC_CRA_PRIO 400
102 #define MIN_HW_QUEUE_SIZE 50 /* Minimum size required for proper function */
104 #define MAX_REQUEST_QUEUE_SIZE 4096
105 #define MAX_MLLI_BUFF_SIZE 2080
107 /* Definitions for HW descriptors DIN/DOUT fields */
110 /* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID
111 * field in the HW descriptor. The DMA engine +8 that value.
120 #define CC_MAX_IVGEN_DMA_ADDRESSES 3
121 struct cc_crypto_req {
122 void (*user_cb)(struct device *dev, void *req, int err);
124 struct completion seq_compl; /* request completion */
125 struct cc_cpp_req cpp;
129 * struct cc_drvdata - driver private data context
130 * @cc_base: virt address of the CC registers
131 * @irq: bitmap indicating source of last interrupt
134 void __iomem *cc_base;
136 struct completion hw_queue_avail; /* wait for HW queue availability */
137 struct platform_device *plat_dev;
139 struct dma_pool *mlli_buffs_pool;
140 struct list_head alg_list;
143 void *request_mgr_handle;
145 u32 sram_free_offset; /* offset to non-allocated area in SRAM */
146 struct dentry *dir; /* for debugfs */
150 enum cc_hw_rev hw_rev;
161 struct cc_crypto_alg {
162 struct list_head entry;
164 int flow_mode; /* Note: currently, refers to the cipher mode only. */
166 struct cc_drvdata *drvdata;
167 struct skcipher_alg skcipher_alg;
168 struct aead_alg aead_alg;
171 struct cc_alg_template {
172 char name[CRYPTO_MAX_ALG_NAME];
173 char driver_name[CRYPTO_MAX_ALG_NAME];
174 unsigned int blocksize;
176 struct skcipher_alg skcipher;
177 struct aead_alg aead;
180 int flow_mode; /* Note: currently, refers to the cipher mode only. */
183 enum cc_std_body std_body;
185 unsigned int data_unit;
186 struct cc_drvdata *drvdata;
189 struct async_gen_req_ctx {
190 dma_addr_t iv_dma_addr;
192 enum drv_crypto_direction op_type;
195 static inline struct device *drvdata_to_dev(struct cc_drvdata *drvdata)
197 return &drvdata->plat_dev->dev;
200 void __dump_byte_array(const char *name, const u8 *buf, size_t len);
201 static inline void dump_byte_array(const char *name, const u8 *the_array,
205 __dump_byte_array(name, the_array, size);
208 bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata);
209 int init_cc_regs(struct cc_drvdata *drvdata);
210 void fini_cc_regs(struct cc_drvdata *drvdata);
211 unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata);
213 static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val)
215 iowrite32(val, (drvdata->cc_base + reg));
218 static inline u32 cc_ioread(struct cc_drvdata *drvdata, u32 reg)
220 return ioread32(drvdata->cc_base + reg);
223 static inline gfp_t cc_gfp_flags(struct crypto_async_request *req)
225 return (req->flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
226 GFP_KERNEL : GFP_ATOMIC;
229 static inline void set_queue_last_ind(struct cc_drvdata *drvdata,
230 struct cc_hw_desc *pdesc)
232 if (drvdata->hw_rev >= CC_HW_REV_712)
233 set_queue_last_ind_bit(pdesc);
236 #endif /*__CC_DRIVER_H__*/