drivers/crypto/caam/dpseci_cmd.h

   1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
   2 /*
   3  * Copyright 2013-2016 Freescale Semiconductor Inc.
   4  * Copyright 2017-2018 NXP
   5  */
   6
   7 #ifndef _DPSECI_CMD_H_
   8 #define _DPSECI_CMD_H_
   9
  10 /* DPSECI Version */
  11 #define DPSECI_VER_MAJOR                                5
  12 #define DPSECI_VER_MINOR                                3
  13
  14 #define DPSECI_VER(maj, min)    (((maj) << 16) | (min))
  15 #define DPSECI_VERSION          DPSECI_VER(DPSECI_VER_MAJOR, DPSECI_VER_MINOR)
  16
  17 /* Command versioning */
  18 #define DPSECI_CMD_BASE_VERSION         1
  19 #define DPSECI_CMD_BASE_VERSION_V2      2
  20 #define DPSECI_CMD_ID_OFFSET            4
  21
  22 #define DPSECI_CMD_V1(id)       (((id) << DPSECI_CMD_ID_OFFSET) | \
  23                                  DPSECI_CMD_BASE_VERSION)
  24
  25 #define DPSECI_CMD_V2(id)       (((id) << DPSECI_CMD_ID_OFFSET) | \
  26                                  DPSECI_CMD_BASE_VERSION_V2)
  27
  28 /* Command IDs */
  29 #define DPSECI_CMDID_CLOSE                              DPSECI_CMD_V1(0x800)
  30 #define DPSECI_CMDID_OPEN                               DPSECI_CMD_V1(0x809)
  31 #define DPSECI_CMDID_GET_API_VERSION                    DPSECI_CMD_V1(0xa09)
  32
  33 #define DPSECI_CMDID_ENABLE                             DPSECI_CMD_V1(0x002)
  34 #define DPSECI_CMDID_DISABLE                            DPSECI_CMD_V1(0x003)
  35 #define DPSECI_CMDID_GET_ATTR                           DPSECI_CMD_V1(0x004)
  36 #define DPSECI_CMDID_IS_ENABLED                         DPSECI_CMD_V1(0x006)
  37
  38 #define DPSECI_CMDID_SET_RX_QUEUE                       DPSECI_CMD_V1(0x194)
  39 #define DPSECI_CMDID_GET_RX_QUEUE                       DPSECI_CMD_V1(0x196)
  40 #define DPSECI_CMDID_GET_TX_QUEUE                       DPSECI_CMD_V1(0x197)
  41 #define DPSECI_CMDID_GET_SEC_ATTR                       DPSECI_CMD_V2(0x198)
  42 #define DPSECI_CMDID_SET_CONGESTION_NOTIFICATION        DPSECI_CMD_V1(0x170)
  43 #define DPSECI_CMDID_GET_CONGESTION_NOTIFICATION        DPSECI_CMD_V1(0x171)
  44
  45 /* Macros for accessing command fields smaller than 1 byte */
  46 #define DPSECI_MASK(field)      \
  47         GENMASK(DPSECI_##field##_SHIFT + DPSECI_##field##_SIZE - 1,     \
  48                 DPSECI_##field##_SHIFT)
  49
  50 #define dpseci_set_field(var, field, val)       \
  51         ((var) |= (((val) << DPSECI_##field##_SHIFT) & DPSECI_MASK(field)))
  52
  53 #define dpseci_get_field(var, field)    \
  54         (((var) & DPSECI_MASK(field)) >> DPSECI_##field##_SHIFT)
  55
  56 struct dpseci_cmd_open {
  57         __le32 dpseci_id;
  58 };
  59
  60 #define DPSECI_ENABLE_SHIFT     0
  61 #define DPSECI_ENABLE_SIZE      1
  62
  63 struct dpseci_rsp_is_enabled {
  64         u8 is_enabled;
  65 };
  66
  67 struct dpseci_rsp_get_attributes {
  68         __le32 id;
  69         __le32 pad0;
  70         u8 num_tx_queues;
  71         u8 num_rx_queues;
  72         u8 pad1[6];
  73         __le32 options;
  74 };
  75
  76 #define DPSECI_DEST_TYPE_SHIFT  0
  77 #define DPSECI_DEST_TYPE_SIZE   4
  78
  79 #define DPSECI_ORDER_PRESERVATION_SHIFT 0
  80 #define DPSECI_ORDER_PRESERVATION_SIZE  1
  81
  82 struct dpseci_cmd_queue {
  83         __le32 dest_id;
  84         u8 priority;
  85         u8 queue;
  86         u8 dest_type;
  87         u8 pad;
  88         __le64 user_ctx;
  89         union {
  90                 __le32 options;
  91                 __le32 fqid;
  92         };
  93         u8 order_preservation_en;
  94 };
  95
  96 struct dpseci_rsp_get_tx_queue {
  97         __le32 pad;
  98         __le32 fqid;
  99         u8 priority;
 100 };
 101
 102 struct dpseci_rsp_get_sec_attr {
 103         __le16 ip_id;
 104         u8 major_rev;
 105         u8 minor_rev;
 106         u8 era;
 107         u8 pad0[3];
 108         u8 deco_num;
 109         u8 zuc_auth_acc_num;
 110         u8 zuc_enc_acc_num;
 111         u8 pad1;
 112         u8 snow_f8_acc_num;
 113         u8 snow_f9_acc_num;
 114         u8 crc_acc_num;
 115         u8 pad2;
 116         u8 pk_acc_num;
 117         u8 kasumi_acc_num;
 118         u8 rng_acc_num;
 119         u8 pad3;
 120         u8 md_acc_num;
 121         u8 arc4_acc_num;
 122         u8 des_acc_num;
 123         u8 aes_acc_num;
 124         u8 ccha_acc_num;
 125         u8 ptha_acc_num;
 126 };
 127
 128 struct dpseci_rsp_get_api_version {
 129         __le16 major;
 130         __le16 minor;
 131 };
 132
 133 #define DPSECI_CGN_DEST_TYPE_SHIFT      0
 134 #define DPSECI_CGN_DEST_TYPE_SIZE       4
 135 #define DPSECI_CGN_UNITS_SHIFT          4
 136 #define DPSECI_CGN_UNITS_SIZE           2
 137
 138 struct dpseci_cmd_congestion_notification {
 139         __le32 dest_id;
 140         __le16 notification_mode;
 141         u8 priority;
 142         u8 options;
 143         __le64 message_iova;
 144         __le64 message_ctx;
 145         __le32 threshold_entry;
 146         __le32 threshold_exit;
 147 };
 148
 149 #endif /* _DPSECI_CMD_H_ */