1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved
7 #include <linux/cpufreq.h>
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/module.h>
12 #include <linux/of_platform.h>
13 #include <linux/platform_device.h>
14 #include <linux/slab.h>
16 #include <asm/smp_plat.h>
18 #include <soc/tegra/bpmp.h>
19 #include <soc/tegra/bpmp-abi.h>
22 #define REF_CLK_MHZ 408 /* 408 MHz */
24 #define US_DELAY_MIN 2
25 #define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ)
28 /* cpufreq transisition latency */
29 #define TEGRA_CPUFREQ_TRANSITION_LATENCY (300 * 1000) /* unit in nanoseconds */
39 struct tegra194_cpufreq_data {
42 struct cpufreq_frequency_table **tables;
45 struct tegra_cpu_ctr {
48 u32 coreclk_cnt, last_coreclk_cnt;
49 u32 refclk_cnt, last_refclk_cnt;
52 struct read_counters_work {
53 struct work_struct work;
54 struct tegra_cpu_ctr c;
57 static struct workqueue_struct *read_counters_wq;
59 static enum cluster get_cpu_cluster(u8 cpu)
61 return MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 1);
65 * Read per-core Read-only system register NVFREQ_FEEDBACK_EL1.
66 * The register provides frequency feedback information to
67 * determine the average actual frequency a core has run at over
69 * [31:0] PLLP counter: Counts at fixed frequency (408 MHz)
70 * [63:32] Core clock counter: counts on every core clock cycle
71 * where the core is architecturally clocking
73 static u64 read_freq_feedback(void)
77 asm volatile("mrs %0, s3_0_c15_c0_5" : "=r" (val) : );
82 static inline u32 map_ndiv_to_freq(struct mrq_cpu_ndiv_limits_response
85 return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv);
88 static void tegra_read_counters(struct work_struct *work)
90 struct read_counters_work *read_counters_work;
91 struct tegra_cpu_ctr *c;
95 * ref_clk_counter(32 bit counter) runs on constant clk,
97 * It will take = 2 ^ 32 / 408 MHz to overflow ref clk counter
98 * = 10526880 usec = 10.527 sec to overflow
100 * Like wise core_clk_counter(32 bit counter) runs on core clock.
101 * It's synchronized to crab_clk (cpu_crab_clk) which runs at
102 * freq of cluster. Assuming max cluster clock ~2000MHz,
103 * It will take = 2 ^ 32 / 2000 MHz to overflow core clk counter
104 * = ~2.147 sec to overflow
106 read_counters_work = container_of(work, struct read_counters_work,
108 c = &read_counters_work->c;
110 val = read_freq_feedback();
111 c->last_refclk_cnt = lower_32_bits(val);
112 c->last_coreclk_cnt = upper_32_bits(val);
114 val = read_freq_feedback();
115 c->refclk_cnt = lower_32_bits(val);
116 c->coreclk_cnt = upper_32_bits(val);
120 * Return instantaneous cpu speed
121 * Instantaneous freq is calculated as -
122 * -Takes sample on every query of getting the freq.
123 * - Read core and ref clock counters;
125 * - Read above cycle counters again
126 * - Calculates freq by subtracting current and previous counters
127 * divided by the delay time or eqv. of ref_clk_counter in delta time
128 * - Return Kcycles/second, freq in KHz
130 * delta time period = x sec
131 * = delta ref_clk_counter / (408 * 10^6) sec
132 * freq in Hz = cycles/sec
133 * = (delta cycles / x sec
134 * = (delta cycles * 408 * 10^6) / delta ref_clk_counter
135 * in KHz = (delta cycles * 408 * 10^3) / delta ref_clk_counter
137 * @cpu - logical cpu whose freq to be updated
138 * Returns freq in KHz on success, 0 if cpu is offline
140 static unsigned int tegra194_get_speed_common(u32 cpu, u32 delay)
142 struct read_counters_work read_counters_work;
143 struct tegra_cpu_ctr c;
149 * udelay() is required to reconstruct cpu frequency over an
150 * observation window. Using workqueue to call udelay() with
151 * interrupts enabled.
153 read_counters_work.c.cpu = cpu;
154 read_counters_work.c.delay = delay;
155 INIT_WORK_ONSTACK(&read_counters_work.work, tegra_read_counters);
156 queue_work_on(cpu, read_counters_wq, &read_counters_work.work);
157 flush_work(&read_counters_work.work);
158 c = read_counters_work.c;
160 if (c.coreclk_cnt < c.last_coreclk_cnt)
161 delta_ccnt = c.coreclk_cnt + (MAX_CNT - c.last_coreclk_cnt);
163 delta_ccnt = c.coreclk_cnt - c.last_coreclk_cnt;
167 /* ref clock is 32 bits */
168 if (c.refclk_cnt < c.last_refclk_cnt)
169 delta_refcnt = c.refclk_cnt + (MAX_CNT - c.last_refclk_cnt);
171 delta_refcnt = c.refclk_cnt - c.last_refclk_cnt;
173 pr_debug("cpufreq: %d is idle, delta_refcnt: 0\n", cpu);
176 rate_mhz = ((unsigned long)(delta_ccnt * REF_CLK_MHZ)) / delta_refcnt;
178 return (rate_mhz * KHZ); /* in KHz */
181 static unsigned int tegra194_get_speed(u32 cpu)
183 return tegra194_get_speed_common(cpu, US_DELAY);
186 static int tegra194_cpufreq_init(struct cpufreq_policy *policy)
188 struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
189 int cl = get_cpu_cluster(policy->cpu);
192 if (cl >= data->num_clusters)
196 policy->cur = tegra194_get_speed_common(policy->cpu, US_DELAY_MIN);
198 /* set same policy for all cpus in a cluster */
199 for (cpu = (cl * 2); cpu < ((cl + 1) * 2); cpu++)
200 cpumask_set_cpu(cpu, policy->cpus);
202 policy->freq_table = data->tables[cl];
203 policy->cpuinfo.transition_latency = TEGRA_CPUFREQ_TRANSITION_LATENCY;
208 static void set_cpu_ndiv(void *data)
210 struct cpufreq_frequency_table *tbl = data;
211 u64 ndiv_val = (u64)tbl->driver_data;
213 asm volatile("msr s3_0_c15_c0_4, %0" : : "r" (ndiv_val));
216 static int tegra194_cpufreq_set_target(struct cpufreq_policy *policy,
219 struct cpufreq_frequency_table *tbl = policy->freq_table + index;
222 * Each core writes frequency in per core register. Then both cores
223 * in a cluster run at same frequency which is the maximum frequency
224 * request out of the values requested by both cores in that cluster.
226 on_each_cpu_mask(policy->cpus, set_cpu_ndiv, tbl, true);
231 static struct cpufreq_driver tegra194_cpufreq_driver = {
233 .flags = CPUFREQ_STICKY | CPUFREQ_CONST_LOOPS |
234 CPUFREQ_NEED_INITIAL_FREQ_CHECK,
235 .verify = cpufreq_generic_frequency_table_verify,
236 .target_index = tegra194_cpufreq_set_target,
237 .get = tegra194_get_speed,
238 .init = tegra194_cpufreq_init,
239 .attr = cpufreq_generic_attr,
242 static void tegra194_cpufreq_free_resources(void)
244 destroy_workqueue(read_counters_wq);
247 static struct cpufreq_frequency_table *
248 init_freq_table(struct platform_device *pdev, struct tegra_bpmp *bpmp,
249 unsigned int cluster_id)
251 struct cpufreq_frequency_table *freq_table;
252 struct mrq_cpu_ndiv_limits_response resp;
253 unsigned int num_freqs, ndiv, delta_ndiv;
254 struct mrq_cpu_ndiv_limits_request req;
255 struct tegra_bpmp_message msg;
256 u16 freq_table_step_size;
259 memset(&req, 0, sizeof(req));
260 req.cluster_id = cluster_id;
262 memset(&msg, 0, sizeof(msg));
263 msg.mrq = MRQ_CPU_NDIV_LIMITS;
265 msg.tx.size = sizeof(req);
267 msg.rx.size = sizeof(resp);
269 err = tegra_bpmp_transfer(bpmp, &msg);
274 * Make sure frequency table step is a multiple of mdiv to match
275 * vhint table granularity.
277 freq_table_step_size = resp.mdiv *
278 DIV_ROUND_UP(CPUFREQ_TBL_STEP_HZ, resp.ref_clk_hz);
280 dev_dbg(&pdev->dev, "cluster %d: frequency table step size: %d\n",
281 cluster_id, freq_table_step_size);
283 delta_ndiv = resp.ndiv_max - resp.ndiv_min;
285 if (unlikely(delta_ndiv == 0)) {
288 /* We store both ndiv_min and ndiv_max hence the +1 */
289 num_freqs = delta_ndiv / freq_table_step_size + 1;
292 num_freqs += (delta_ndiv % freq_table_step_size) ? 1 : 0;
294 freq_table = devm_kcalloc(&pdev->dev, num_freqs + 1,
295 sizeof(*freq_table), GFP_KERNEL);
297 return ERR_PTR(-ENOMEM);
299 for (index = 0, ndiv = resp.ndiv_min;
300 ndiv < resp.ndiv_max;
301 index++, ndiv += freq_table_step_size) {
302 freq_table[index].driver_data = ndiv;
303 freq_table[index].frequency = map_ndiv_to_freq(&resp, ndiv);
306 freq_table[index].driver_data = resp.ndiv_max;
307 freq_table[index++].frequency = map_ndiv_to_freq(&resp, resp.ndiv_max);
308 freq_table[index].frequency = CPUFREQ_TABLE_END;
313 static int tegra194_cpufreq_probe(struct platform_device *pdev)
315 struct tegra194_cpufreq_data *data;
316 struct tegra_bpmp *bpmp;
319 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
323 data->num_clusters = MAX_CLUSTERS;
324 data->tables = devm_kcalloc(&pdev->dev, data->num_clusters,
325 sizeof(*data->tables), GFP_KERNEL);
329 platform_set_drvdata(pdev, data);
331 bpmp = tegra_bpmp_get(&pdev->dev);
333 return PTR_ERR(bpmp);
335 read_counters_wq = alloc_workqueue("read_counters_wq", __WQ_LEGACY, 1);
336 if (!read_counters_wq) {
337 dev_err(&pdev->dev, "fail to create_workqueue\n");
342 for (i = 0; i < data->num_clusters; i++) {
343 data->tables[i] = init_freq_table(pdev, bpmp, i);
344 if (IS_ERR(data->tables[i])) {
345 err = PTR_ERR(data->tables[i]);
350 tegra194_cpufreq_driver.driver_data = data;
352 err = cpufreq_register_driver(&tegra194_cpufreq_driver);
357 tegra194_cpufreq_free_resources();
359 tegra_bpmp_put(bpmp);
363 static int tegra194_cpufreq_remove(struct platform_device *pdev)
365 cpufreq_unregister_driver(&tegra194_cpufreq_driver);
366 tegra194_cpufreq_free_resources();
371 static const struct of_device_id tegra194_cpufreq_of_match[] = {
372 { .compatible = "nvidia,tegra194-ccplex", },
375 MODULE_DEVICE_TABLE(of, tegra194_cpufreq_of_match);
377 static struct platform_driver tegra194_ccplex_driver = {
379 .name = "tegra194-cpufreq",
380 .of_match_table = tegra194_cpufreq_of_match,
382 .probe = tegra194_cpufreq_probe,
383 .remove = tegra194_cpufreq_remove,
385 module_platform_driver(tegra194_ccplex_driver);
387 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
388 MODULE_AUTHOR("Sumit Gupta <sumitg@nvidia.com>");
389 MODULE_DESCRIPTION("NVIDIA Tegra194 cpufreq driver");
390 MODULE_LICENSE("GPL v2");