1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved
6 #include <linux/cpufreq.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/module.h>
10 #include <linux/platform_device.h>
12 #include <soc/tegra/bpmp.h>
13 #include <soc/tegra/bpmp-abi.h>
15 #define EDVD_CORE_VOLT_FREQ(core) (0x20 + (core) * 0x4)
16 #define EDVD_CORE_VOLT_FREQ_F_SHIFT 0
17 #define EDVD_CORE_VOLT_FREQ_F_MASK 0xffff
18 #define EDVD_CORE_VOLT_FREQ_V_SHIFT 16
20 struct tegra186_cpufreq_cluster_info {
23 unsigned int bpmp_cluster_id;
27 static const struct tegra186_cpufreq_cluster_info tegra186_clusters[] = {
31 .cpus = { 1, 2, NO_CPU, NO_CPU },
37 .cpus = { 0, 3, 4, 5 },
42 struct tegra186_cpufreq_cluster {
43 const struct tegra186_cpufreq_cluster_info *info;
44 struct cpufreq_frequency_table *table;
47 struct tegra186_cpufreq_data {
51 struct tegra186_cpufreq_cluster *clusters;
54 static int tegra186_cpufreq_init(struct cpufreq_policy *policy)
56 struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
59 for (i = 0; i < data->num_clusters; i++) {
60 struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
61 const struct tegra186_cpufreq_cluster_info *info =
65 for (core = 0; core < ARRAY_SIZE(info->cpus); core++) {
66 if (info->cpus[core] == policy->cpu)
69 if (core == ARRAY_SIZE(info->cpus))
73 data->regs + info->offset + EDVD_CORE_VOLT_FREQ(core);
74 policy->freq_table = cluster->table;
78 policy->cpuinfo.transition_latency = 300 * 1000;
83 static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy,
86 struct cpufreq_frequency_table *tbl = policy->freq_table + index;
87 void __iomem *edvd_reg = policy->driver_data;
88 u32 edvd_val = tbl->driver_data;
90 writel(edvd_val, edvd_reg);
95 static unsigned int tegra186_cpufreq_get(unsigned int cpu)
97 struct cpufreq_frequency_table *tbl;
98 struct cpufreq_policy *policy;
99 void __iomem *edvd_reg;
100 unsigned int i, freq = 0;
103 policy = cpufreq_cpu_get(cpu);
107 tbl = policy->freq_table;
108 edvd_reg = policy->driver_data;
109 ndiv = readl(edvd_reg) & EDVD_CORE_VOLT_FREQ_F_MASK;
111 for (i = 0; tbl[i].frequency != CPUFREQ_TABLE_END; i++) {
112 if ((tbl[i].driver_data & EDVD_CORE_VOLT_FREQ_F_MASK) == ndiv) {
113 freq = tbl[i].frequency;
118 cpufreq_cpu_put(policy);
123 static struct cpufreq_driver tegra186_cpufreq_driver = {
125 .flags = CPUFREQ_STICKY | CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
126 CPUFREQ_NEED_INITIAL_FREQ_CHECK,
127 .get = tegra186_cpufreq_get,
128 .verify = cpufreq_generic_frequency_table_verify,
129 .target_index = tegra186_cpufreq_set_target,
130 .init = tegra186_cpufreq_init,
131 .attr = cpufreq_generic_attr,
134 static struct cpufreq_frequency_table *init_vhint_table(
135 struct platform_device *pdev, struct tegra_bpmp *bpmp,
136 unsigned int cluster_id)
138 struct cpufreq_frequency_table *table;
139 struct mrq_cpu_vhint_request req;
140 struct tegra_bpmp_message msg;
141 struct cpu_vhint_data *data;
142 int err, i, j, num_rates = 0;
146 virt = dma_alloc_coherent(bpmp->dev, sizeof(*data), &phys,
149 return ERR_PTR(-ENOMEM);
151 data = (struct cpu_vhint_data *)virt;
153 memset(&req, 0, sizeof(req));
155 req.cluster_id = cluster_id;
157 memset(&msg, 0, sizeof(msg));
158 msg.mrq = MRQ_CPU_VHINT;
160 msg.tx.size = sizeof(req);
162 err = tegra_bpmp_transfer(bpmp, &msg);
164 table = ERR_PTR(err);
168 for (i = data->vfloor; i <= data->vceil; i++) {
169 u16 ndiv = data->ndiv[i];
171 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
174 /* Only store lowest voltage index for each rate */
175 if (i > 0 && ndiv == data->ndiv[i - 1])
181 table = devm_kcalloc(&pdev->dev, num_rates + 1, sizeof(*table),
184 table = ERR_PTR(-ENOMEM);
188 for (i = data->vfloor, j = 0; i <= data->vceil; i++) {
189 struct cpufreq_frequency_table *point;
190 u16 ndiv = data->ndiv[i];
193 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
196 /* Only store lowest voltage index for each rate */
197 if (i > 0 && ndiv == data->ndiv[i - 1])
200 edvd_val |= i << EDVD_CORE_VOLT_FREQ_V_SHIFT;
201 edvd_val |= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT;
204 point->driver_data = edvd_val;
205 point->frequency = data->ref_clk_hz * ndiv / data->pdiv /
209 table[j].frequency = CPUFREQ_TABLE_END;
212 dma_free_coherent(bpmp->dev, sizeof(*data), virt, phys);
217 static int tegra186_cpufreq_probe(struct platform_device *pdev)
219 struct tegra186_cpufreq_data *data;
220 struct tegra_bpmp *bpmp;
221 unsigned int i = 0, err;
223 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
227 data->clusters = devm_kcalloc(&pdev->dev, ARRAY_SIZE(tegra186_clusters),
228 sizeof(*data->clusters), GFP_KERNEL);
232 data->num_clusters = ARRAY_SIZE(tegra186_clusters);
234 bpmp = tegra_bpmp_get(&pdev->dev);
236 return PTR_ERR(bpmp);
238 data->regs = devm_platform_ioremap_resource(pdev, 0);
239 if (IS_ERR(data->regs)) {
240 err = PTR_ERR(data->regs);
244 for (i = 0; i < data->num_clusters; i++) {
245 struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
247 cluster->info = &tegra186_clusters[i];
248 cluster->table = init_vhint_table(
249 pdev, bpmp, cluster->info->bpmp_cluster_id);
250 if (IS_ERR(cluster->table)) {
251 err = PTR_ERR(cluster->table);
256 tegra186_cpufreq_driver.driver_data = data;
258 err = cpufreq_register_driver(&tegra186_cpufreq_driver);
261 tegra_bpmp_put(bpmp);
266 static int tegra186_cpufreq_remove(struct platform_device *pdev)
268 cpufreq_unregister_driver(&tegra186_cpufreq_driver);
273 static const struct of_device_id tegra186_cpufreq_of_match[] = {
274 { .compatible = "nvidia,tegra186-ccplex-cluster", },
277 MODULE_DEVICE_TABLE(of, tegra186_cpufreq_of_match);
279 static struct platform_driver tegra186_cpufreq_platform_driver = {
281 .name = "tegra186-cpufreq",
282 .of_match_table = tegra186_cpufreq_of_match,
284 .probe = tegra186_cpufreq_probe,
285 .remove = tegra186_cpufreq_remove,
287 module_platform_driver(tegra186_cpufreq_platform_driver);
289 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
290 MODULE_DESCRIPTION("NVIDIA Tegra186 cpufreq driver");
291 MODULE_LICENSE("GPL v2");