drivers/cpufreq/tegra186-cpufreq.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved
   4  */
   5
   6 #include <linux/cpufreq.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/platform_device.h>
  11
  12 #include <soc/tegra/bpmp.h>
  13 #include <soc/tegra/bpmp-abi.h>
  14
  15 #define EDVD_CORE_VOLT_FREQ(core)               (0x20 + (core) * 0x4)
  16 #define EDVD_CORE_VOLT_FREQ_F_SHIFT             0
  17 #define EDVD_CORE_VOLT_FREQ_F_MASK              0xffff
  18 #define EDVD_CORE_VOLT_FREQ_V_SHIFT             16
  19
  20 struct tegra186_cpufreq_cluster_info {
  21         unsigned long offset;
  22         int cpus[4];
  23         unsigned int bpmp_cluster_id;
  24 };
  25
  26 #define NO_CPU -1
  27 static const struct tegra186_cpufreq_cluster_info tegra186_clusters[] = {
  28         /* Denver cluster */
  29         {
  30                 .offset = SZ_64K * 7,
  31                 .cpus = { 1, 2, NO_CPU, NO_CPU },
  32                 .bpmp_cluster_id = 0,
  33         },
  34         /* A57 cluster */
  35         {
  36                 .offset = SZ_64K * 6,
  37                 .cpus = { 0, 3, 4, 5 },
  38                 .bpmp_cluster_id = 1,
  39         },
  40 };
  41
  42 struct tegra186_cpufreq_cluster {
  43         const struct tegra186_cpufreq_cluster_info *info;
  44         struct cpufreq_frequency_table *table;
  45 };
  46
  47 struct tegra186_cpufreq_data {
  48         void __iomem *regs;
  49
  50         size_t num_clusters;
  51         struct tegra186_cpufreq_cluster *clusters;
  52 };
  53
  54 static int tegra186_cpufreq_init(struct cpufreq_policy *policy)
  55 {
  56         struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
  57         unsigned int i;
  58
  59         for (i = 0; i < data->num_clusters; i++) {
  60                 struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
  61                 const struct tegra186_cpufreq_cluster_info *info =
  62                         cluster->info;
  63                 int core;
  64
  65                 for (core = 0; core < ARRAY_SIZE(info->cpus); core++) {
  66                         if (info->cpus[core] == policy->cpu)
  67                                 break;
  68                 }
  69                 if (core == ARRAY_SIZE(info->cpus))
  70                         continue;
  71
  72                 policy->driver_data =
  73                         data->regs + info->offset + EDVD_CORE_VOLT_FREQ(core);
  74                 policy->freq_table = cluster->table;
  75                 break;
  76         }
  77
  78         policy->cpuinfo.transition_latency = 300 * 1000;
  79
  80         return 0;
  81 }
  82
  83 static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy,
  84                                        unsigned int index)
  85 {
  86         struct cpufreq_frequency_table *tbl = policy->freq_table + index;
  87         void __iomem *edvd_reg = policy->driver_data;
  88         u32 edvd_val = tbl->driver_data;
  89
  90         writel(edvd_val, edvd_reg);
  91
  92         return 0;
  93 }
  94
  95 static unsigned int tegra186_cpufreq_get(unsigned int cpu)
  96 {
  97         struct cpufreq_frequency_table *tbl;
  98         struct cpufreq_policy *policy;
  99         void __iomem *edvd_reg;
 100         unsigned int i, freq = 0;
 101         u32 ndiv;
 102
 103         policy = cpufreq_cpu_get(cpu);
 104         if (!policy)
 105                 return 0;
 106
 107         tbl = policy->freq_table;
 108         edvd_reg = policy->driver_data;
 109         ndiv = readl(edvd_reg) & EDVD_CORE_VOLT_FREQ_F_MASK;
 110
 111         for (i = 0; tbl[i].frequency != CPUFREQ_TABLE_END; i++) {
 112                 if ((tbl[i].driver_data & EDVD_CORE_VOLT_FREQ_F_MASK) == ndiv) {
 113                         freq = tbl[i].frequency;
 114                         break;
 115                 }
 116         }
 117
 118         cpufreq_cpu_put(policy);
 119
 120         return freq;
 121 }
 122
 123 static struct cpufreq_driver tegra186_cpufreq_driver = {
 124         .name = "tegra186",
 125         .flags = CPUFREQ_STICKY | CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
 126                         CPUFREQ_NEED_INITIAL_FREQ_CHECK,
 127         .get = tegra186_cpufreq_get,
 128         .verify = cpufreq_generic_frequency_table_verify,
 129         .target_index = tegra186_cpufreq_set_target,
 130         .init = tegra186_cpufreq_init,
 131         .attr = cpufreq_generic_attr,
 132 };
 133
 134 static struct cpufreq_frequency_table *init_vhint_table(
 135         struct platform_device *pdev, struct tegra_bpmp *bpmp,
 136         unsigned int cluster_id)
 137 {
 138         struct cpufreq_frequency_table *table;
 139         struct mrq_cpu_vhint_request req;
 140         struct tegra_bpmp_message msg;
 141         struct cpu_vhint_data *data;
 142         int err, i, j, num_rates = 0;
 143         dma_addr_t phys;
 144         void *virt;
 145
 146         virt = dma_alloc_coherent(bpmp->dev, sizeof(*data), &phys,
 147                                   GFP_KERNEL);
 148         if (!virt)
 149                 return ERR_PTR(-ENOMEM);
 150
 151         data = (struct cpu_vhint_data *)virt;
 152
 153         memset(&req, 0, sizeof(req));
 154         req.addr = phys;
 155         req.cluster_id = cluster_id;
 156
 157         memset(&msg, 0, sizeof(msg));
 158         msg.mrq = MRQ_CPU_VHINT;
 159         msg.tx.data = &req;
 160         msg.tx.size = sizeof(req);
 161
 162         err = tegra_bpmp_transfer(bpmp, &msg);
 163         if (err) {
 164                 table = ERR_PTR(err);
 165                 goto free;
 166         }
 167
 168         for (i = data->vfloor; i <= data->vceil; i++) {
 169                 u16 ndiv = data->ndiv[i];
 170
 171                 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
 172                         continue;
 173
 174                 /* Only store lowest voltage index for each rate */
 175                 if (i > 0 && ndiv == data->ndiv[i - 1])
 176                         continue;
 177
 178                 num_rates++;
 179         }
 180
 181         table = devm_kcalloc(&pdev->dev, num_rates + 1, sizeof(*table),
 182                              GFP_KERNEL);
 183         if (!table) {
 184                 table = ERR_PTR(-ENOMEM);
 185                 goto free;
 186         }
 187
 188         for (i = data->vfloor, j = 0; i <= data->vceil; i++) {
 189                 struct cpufreq_frequency_table *point;
 190                 u16 ndiv = data->ndiv[i];
 191                 u32 edvd_val = 0;
 192
 193                 if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
 194                         continue;
 195
 196                 /* Only store lowest voltage index for each rate */
 197                 if (i > 0 && ndiv == data->ndiv[i - 1])
 198                         continue;
 199
 200                 edvd_val |= i << EDVD_CORE_VOLT_FREQ_V_SHIFT;
 201                 edvd_val |= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT;
 202
 203                 point = &table[j++];
 204                 point->driver_data = edvd_val;
 205                 point->frequency = data->ref_clk_hz * ndiv / data->pdiv /
 206                         data->mdiv / 1000;
 207         }
 208
 209         table[j].frequency = CPUFREQ_TABLE_END;
 210
 211 free:
 212         dma_free_coherent(bpmp->dev, sizeof(*data), virt, phys);
 213
 214         return table;
 215 }
 216
 217 static int tegra186_cpufreq_probe(struct platform_device *pdev)
 218 {
 219         struct tegra186_cpufreq_data *data;
 220         struct tegra_bpmp *bpmp;
 221         unsigned int i = 0, err;
 222
 223         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 224         if (!data)
 225                 return -ENOMEM;
 226
 227         data->clusters = devm_kcalloc(&pdev->dev, ARRAY_SIZE(tegra186_clusters),
 228                                       sizeof(*data->clusters), GFP_KERNEL);
 229         if (!data->clusters)
 230                 return -ENOMEM;
 231
 232         data->num_clusters = ARRAY_SIZE(tegra186_clusters);
 233
 234         bpmp = tegra_bpmp_get(&pdev->dev);
 235         if (IS_ERR(bpmp))
 236                 return PTR_ERR(bpmp);
 237
 238         data->regs = devm_platform_ioremap_resource(pdev, 0);
 239         if (IS_ERR(data->regs)) {
 240                 err = PTR_ERR(data->regs);
 241                 goto put_bpmp;
 242         }
 243
 244         for (i = 0; i < data->num_clusters; i++) {
 245                 struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
 246
 247                 cluster->info = &tegra186_clusters[i];
 248                 cluster->table = init_vhint_table(
 249                         pdev, bpmp, cluster->info->bpmp_cluster_id);
 250                 if (IS_ERR(cluster->table)) {
 251                         err = PTR_ERR(cluster->table);
 252                         goto put_bpmp;
 253                 }
 254         }
 255
 256         tegra186_cpufreq_driver.driver_data = data;
 257
 258         err = cpufreq_register_driver(&tegra186_cpufreq_driver);
 259
 260 put_bpmp:
 261         tegra_bpmp_put(bpmp);
 262
 263         return err;
 264 }
 265
 266 static int tegra186_cpufreq_remove(struct platform_device *pdev)
 267 {
 268         cpufreq_unregister_driver(&tegra186_cpufreq_driver);
 269
 270         return 0;
 271 }
 272
 273 static const struct of_device_id tegra186_cpufreq_of_match[] = {
 274         { .compatible = "nvidia,tegra186-ccplex-cluster", },
 275         { }
 276 };
 277 MODULE_DEVICE_TABLE(of, tegra186_cpufreq_of_match);
 278
 279 static struct platform_driver tegra186_cpufreq_platform_driver = {
 280         .driver = {
 281                 .name = "tegra186-cpufreq",
 282                 .of_match_table = tegra186_cpufreq_of_match,
 283         },
 284         .probe = tegra186_cpufreq_probe,
 285         .remove = tegra186_cpufreq_remove,
 286 };
 287 module_platform_driver(tegra186_cpufreq_platform_driver);
 288
 289 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
 290 MODULE_DESCRIPTION("NVIDIA Tegra186 cpufreq driver");
 291 MODULE_LICENSE("GPL v2");