1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
7 * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
8 * the CPU frequency subset and voltage value of each OPP varies
9 * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
10 * defines the voltage and frequency value based on the msm-id in SMEM
11 * and speedbin blown in the efuse combination.
12 * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
13 * to provide the OPP framework with required information.
14 * This is used to determine the voltage and frequency value for each OPP of
15 * operating-points-v2 table when it is parsed by the OPP framework.
18 #include <linux/cpu.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/nvmem-consumer.h>
25 #include <linux/platform_device.h>
27 #include <linux/pm_domain.h>
28 #include <linux/pm_opp.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/slab.h>
31 #include <linux/soc/qcom/smem.h>
33 #include <dt-bindings/arm/qcom,ids.h>
35 enum ipq806x_versions {
41 #define IPQ6000_VERSION BIT(2)
43 enum ipq8074_versions {
44 IPQ8074_HAWKEYE_VERSION = 0,
45 IPQ8074_ACORN_VERSION,
48 struct qcom_cpufreq_drv;
50 struct qcom_cpufreq_match_data {
51 int (*get_version)(struct device *cpu_dev,
52 struct nvmem_cell *speedbin_nvmem,
54 struct qcom_cpufreq_drv *drv);
55 const char **genpd_names;
58 struct qcom_cpufreq_drv_cpu {
60 struct device **virt_devs;
63 struct qcom_cpufreq_drv {
65 const struct qcom_cpufreq_match_data *data;
66 struct qcom_cpufreq_drv_cpu cpus[];
69 static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
71 static int qcom_cpufreq_simple_get_version(struct device *cpu_dev,
72 struct nvmem_cell *speedbin_nvmem,
74 struct qcom_cpufreq_drv *drv)
79 speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
81 return PTR_ERR(speedbin);
83 dev_dbg(cpu_dev, "speedbin: %d\n", *speedbin);
84 drv->versions = 1 << *speedbin;
89 static void get_krait_bin_format_a(struct device *cpu_dev,
95 pte_efuse = *((u32 *)buf);
97 *speed = pte_efuse & 0xf;
99 *speed = (pte_efuse >> 4) & 0xf;
103 dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
105 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
108 *pvs = (pte_efuse >> 10) & 0x7;
110 *pvs = (pte_efuse >> 13) & 0x7;
114 dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
116 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
120 static void get_krait_bin_format_b(struct device *cpu_dev,
121 int *speed, int *pvs, int *pvs_ver,
124 u32 pte_efuse, redundant_sel;
126 pte_efuse = *((u32 *)buf);
127 redundant_sel = (pte_efuse >> 24) & 0x7;
129 *pvs_ver = (pte_efuse >> 4) & 0x3;
131 switch (redundant_sel) {
133 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
134 *speed = (pte_efuse >> 27) & 0xf;
137 *pvs = (pte_efuse >> 27) & 0xf;
138 *speed = pte_efuse & 0x7;
141 /* 4 bits of PVS are in efuse register bits 31, 8-6. */
142 *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
143 *speed = pte_efuse & 0x7;
146 /* Check SPEED_BIN_BLOW_STATUS */
147 if (pte_efuse & BIT(3)) {
148 dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
150 dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
154 /* Check PVS_BLOW_STATUS */
155 pte_efuse = *(((u32 *)buf) + 1);
156 pte_efuse &= BIT(21);
158 dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
160 dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
164 dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
167 static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
168 struct nvmem_cell *speedbin_nvmem,
170 struct qcom_cpufreq_drv *drv)
178 ret = qcom_smem_get_soc_id(&msm_id);
182 speedbin = nvmem_cell_read(speedbin_nvmem, &len);
183 if (IS_ERR(speedbin))
184 return PTR_ERR(speedbin);
187 case QCOM_ID_MSM8996:
188 case QCOM_ID_APQ8096:
189 case QCOM_ID_IPQ5332:
190 case QCOM_ID_IPQ5322:
191 case QCOM_ID_IPQ5312:
192 case QCOM_ID_IPQ5302:
193 case QCOM_ID_IPQ5300:
194 case QCOM_ID_IPQ9514:
195 case QCOM_ID_IPQ9550:
196 case QCOM_ID_IPQ9554:
197 case QCOM_ID_IPQ9570:
198 case QCOM_ID_IPQ9574:
199 drv->versions = 1 << (unsigned int)(*speedbin);
201 case QCOM_ID_MSM8996SG:
202 case QCOM_ID_APQ8096SG:
203 drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
214 static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
215 struct nvmem_cell *speedbin_nvmem,
217 struct qcom_cpufreq_drv *drv)
219 int speed = 0, pvs = 0, pvs_ver = 0;
224 speedbin = nvmem_cell_read(speedbin_nvmem, &len);
226 if (IS_ERR(speedbin))
227 return PTR_ERR(speedbin);
231 get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
234 get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
238 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
243 snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
244 speed, pvs, pvs_ver);
246 drv->versions = (1 << speed);
253 static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev,
254 struct nvmem_cell *speedbin_nvmem,
256 struct qcom_cpufreq_drv *drv)
258 int speed = 0, pvs = 0;
263 speedbin = nvmem_cell_read(speedbin_nvmem, &len);
264 if (IS_ERR(speedbin))
265 return PTR_ERR(speedbin);
268 dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
273 get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin);
275 ret = qcom_smem_get_soc_id(&msm_id);
280 case QCOM_ID_IPQ8062:
281 drv->versions = BIT(IPQ8062_VERSION);
283 case QCOM_ID_IPQ8064:
284 case QCOM_ID_IPQ8066:
285 case QCOM_ID_IPQ8068:
286 drv->versions = BIT(IPQ8064_VERSION);
288 case QCOM_ID_IPQ8065:
289 case QCOM_ID_IPQ8069:
290 drv->versions = BIT(IPQ8065_VERSION);
294 "SoC ID %u is not part of IPQ8064 family, limiting to 1.0GHz!\n",
296 drv->versions = BIT(IPQ8062_VERSION);
300 /* IPQ8064 speed is never fused. Only pvs values are fused. */
301 snprintf(*pvs_name, sizeof("speed0-pvsXX"), "speed0-pvs%d", pvs);
308 static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev,
309 struct nvmem_cell *speedbin_nvmem,
311 struct qcom_cpufreq_drv *drv)
318 ret = qcom_smem_get_soc_id(&msm_id);
322 speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
323 if (IS_ERR(speedbin))
324 return PTR_ERR(speedbin);
327 case QCOM_ID_IPQ6005:
328 case QCOM_ID_IPQ6010:
329 case QCOM_ID_IPQ6018:
330 case QCOM_ID_IPQ6028:
331 /* Fuse Value Freq BIT to set
332 * ---------------------------------
333 * 2’b0 No Limit BIT(0)
334 * 2’b1 1.5 GHz BIT(1)
336 drv->versions = 1 << (unsigned int)(*speedbin);
338 case QCOM_ID_IPQ6000:
340 * IPQ6018 family only has one bit to advertise the CPU
341 * speed-bin, but that is not enough for IPQ6000 which
342 * is only rated up to 1.2GHz.
343 * So for IPQ6000 manually set BIT(2) based on SMEM ID.
345 drv->versions = IPQ6000_VERSION;
349 "SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n",
351 drv->versions = IPQ6000_VERSION;
359 static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
360 struct nvmem_cell *speedbin_nvmem,
362 struct qcom_cpufreq_drv *drv)
368 ret = qcom_smem_get_soc_id(&msm_id);
373 case QCOM_ID_IPQ8070A:
374 case QCOM_ID_IPQ8071A:
375 case QCOM_ID_IPQ8172:
376 case QCOM_ID_IPQ8173:
377 case QCOM_ID_IPQ8174:
378 drv->versions = BIT(IPQ8074_ACORN_VERSION);
380 case QCOM_ID_IPQ8072A:
381 case QCOM_ID_IPQ8074A:
382 case QCOM_ID_IPQ8076A:
383 case QCOM_ID_IPQ8078A:
384 drv->versions = BIT(IPQ8074_HAWKEYE_VERSION);
388 "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n",
390 drv->versions = BIT(IPQ8074_ACORN_VERSION);
397 static const char *generic_genpd_names[] = { "perf", NULL };
399 static const struct qcom_cpufreq_match_data match_data_kryo = {
400 .get_version = qcom_cpufreq_kryo_name_version,
403 static const struct qcom_cpufreq_match_data match_data_krait = {
404 .get_version = qcom_cpufreq_krait_name_version,
407 static const struct qcom_cpufreq_match_data match_data_msm8909 = {
408 .get_version = qcom_cpufreq_simple_get_version,
409 .genpd_names = generic_genpd_names,
412 static const char *qcs404_genpd_names[] = { "cpr", NULL };
414 static const struct qcom_cpufreq_match_data match_data_qcs404 = {
415 .genpd_names = qcs404_genpd_names,
418 static const struct qcom_cpufreq_match_data match_data_ipq6018 = {
419 .get_version = qcom_cpufreq_ipq6018_name_version,
422 static const struct qcom_cpufreq_match_data match_data_ipq8064 = {
423 .get_version = qcom_cpufreq_ipq8064_name_version,
426 static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
427 .get_version = qcom_cpufreq_ipq8074_name_version,
430 static void qcom_cpufreq_suspend_virt_devs(struct qcom_cpufreq_drv *drv, unsigned int cpu)
432 const char * const *name = drv->data->genpd_names;
435 if (!drv->cpus[cpu].virt_devs)
438 for (i = 0; *name; i++, name++)
439 device_set_awake_path(drv->cpus[cpu].virt_devs[i]);
442 static void qcom_cpufreq_put_virt_devs(struct qcom_cpufreq_drv *drv, unsigned int cpu)
444 const char * const *name = drv->data->genpd_names;
447 if (!drv->cpus[cpu].virt_devs)
450 for (i = 0; *name; i++, name++)
451 pm_runtime_put(drv->cpus[cpu].virt_devs[i]);
454 static int qcom_cpufreq_probe(struct platform_device *pdev)
456 struct qcom_cpufreq_drv *drv;
457 struct nvmem_cell *speedbin_nvmem;
458 struct device_node *np;
459 struct device *cpu_dev;
460 char pvs_name_buffer[] = "speedXX-pvsXX-vXX";
461 char *pvs_name = pvs_name_buffer;
463 const struct of_device_id *match;
466 cpu_dev = get_cpu_device(0);
470 np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
474 ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") ||
475 of_device_is_compatible(np, "operating-points-v2-krait-cpu");
481 drv = devm_kzalloc(&pdev->dev, struct_size(drv, cpus, num_possible_cpus()),
486 match = pdev->dev.platform_data;
487 drv->data = match->data;
491 if (drv->data->get_version) {
492 speedbin_nvmem = of_nvmem_cell_get(np, NULL);
493 if (IS_ERR(speedbin_nvmem))
494 return dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem),
495 "Could not get nvmem cell\n");
497 ret = drv->data->get_version(cpu_dev,
498 speedbin_nvmem, &pvs_name, drv);
500 nvmem_cell_put(speedbin_nvmem);
503 nvmem_cell_put(speedbin_nvmem);
507 for_each_possible_cpu(cpu) {
508 struct device **virt_devs = NULL;
509 struct dev_pm_opp_config config = {
510 .supported_hw = NULL,
513 cpu_dev = get_cpu_device(cpu);
514 if (NULL == cpu_dev) {
519 if (drv->data->get_version) {
520 config.supported_hw = &drv->versions;
521 config.supported_hw_count = 1;
524 config.prop_name = pvs_name;
527 if (drv->data->genpd_names) {
528 config.genpd_names = drv->data->genpd_names;
529 config.virt_devs = &virt_devs;
532 if (config.supported_hw || config.genpd_names) {
533 drv->cpus[cpu].opp_token = dev_pm_opp_set_config(cpu_dev, &config);
534 if (drv->cpus[cpu].opp_token < 0) {
535 ret = drv->cpus[cpu].opp_token;
536 dev_err(cpu_dev, "Failed to set OPP config\n");
542 const char * const *name = config.genpd_names;
545 for (i = 0; *name; i++, name++) {
546 ret = pm_runtime_resume_and_get(virt_devs[i]);
548 dev_err(cpu_dev, "failed to resume %s: %d\n",
551 /* Rollback previous PM runtime calls */
552 name = config.genpd_names;
553 for (j = 0; *name && j < i; j++, name++)
554 pm_runtime_put(virt_devs[j]);
559 drv->cpus[cpu].virt_devs = virt_devs;
563 cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
565 if (!IS_ERR(cpufreq_dt_pdev)) {
566 platform_set_drvdata(pdev, drv);
570 ret = PTR_ERR(cpufreq_dt_pdev);
571 dev_err(cpu_dev, "Failed to register platform device\n");
574 for_each_possible_cpu(cpu) {
575 qcom_cpufreq_put_virt_devs(drv, cpu);
576 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token);
581 static void qcom_cpufreq_remove(struct platform_device *pdev)
583 struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev);
586 platform_device_unregister(cpufreq_dt_pdev);
588 for_each_possible_cpu(cpu) {
589 qcom_cpufreq_put_virt_devs(drv, cpu);
590 dev_pm_opp_clear_config(drv->cpus[cpu].opp_token);
594 static int qcom_cpufreq_suspend(struct device *dev)
596 struct qcom_cpufreq_drv *drv = dev_get_drvdata(dev);
599 for_each_possible_cpu(cpu)
600 qcom_cpufreq_suspend_virt_devs(drv, cpu);
605 static DEFINE_SIMPLE_DEV_PM_OPS(qcom_cpufreq_pm_ops, qcom_cpufreq_suspend, NULL);
607 static struct platform_driver qcom_cpufreq_driver = {
608 .probe = qcom_cpufreq_probe,
609 .remove_new = qcom_cpufreq_remove,
611 .name = "qcom-cpufreq-nvmem",
612 .pm = pm_sleep_ptr(&qcom_cpufreq_pm_ops),
616 static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
617 { .compatible = "qcom,apq8096", .data = &match_data_kryo },
618 { .compatible = "qcom,msm8909", .data = &match_data_msm8909 },
619 { .compatible = "qcom,msm8996", .data = &match_data_kryo },
620 { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
621 { .compatible = "qcom,ipq5332", .data = &match_data_kryo },
622 { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
623 { .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 },
624 { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
625 { .compatible = "qcom,apq8064", .data = &match_data_krait },
626 { .compatible = "qcom,ipq9574", .data = &match_data_kryo },
627 { .compatible = "qcom,msm8974", .data = &match_data_krait },
628 { .compatible = "qcom,msm8960", .data = &match_data_krait },
631 MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);
634 * Since the driver depends on smem and nvmem drivers, which may
635 * return EPROBE_DEFER, all the real activity is done in the probe,
636 * which may be defered as well. The init here is only registering
637 * the driver and the platform device.
639 static int __init qcom_cpufreq_init(void)
641 struct device_node *np = of_find_node_by_path("/");
642 const struct of_device_id *match;
648 match = of_match_node(qcom_cpufreq_match_list, np);
653 ret = platform_driver_register(&qcom_cpufreq_driver);
654 if (unlikely(ret < 0))
657 cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem",
658 -1, match, sizeof(*match));
659 ret = PTR_ERR_OR_ZERO(cpufreq_pdev);
663 platform_driver_unregister(&qcom_cpufreq_driver);
666 module_init(qcom_cpufreq_init);
668 static void __exit qcom_cpufreq_exit(void)
670 platform_device_unregister(cpufreq_pdev);
671 platform_driver_unregister(&qcom_cpufreq_driver);
673 module_exit(qcom_cpufreq_exit);
675 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver");
676 MODULE_LICENSE("GPL v2");