drivers/cpufreq/qcom-cpufreq-hw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/cpufreq.h>
   8 #include <linux/init.h>
   9 #include <linux/interconnect.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/of_address.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/pm_opp.h>
  15 #include <linux/slab.h>
  16
  17 #define LUT_MAX_ENTRIES                 40U
  18 #define LUT_SRC                         GENMASK(31, 30)
  19 #define LUT_L_VAL                       GENMASK(7, 0)
  20 #define LUT_CORE_COUNT                  GENMASK(18, 16)
  21 #define LUT_VOLT                        GENMASK(11, 0)
  22 #define LUT_ROW_SIZE                    32
  23 #define CLK_HW_DIV                      2
  24 #define LUT_TURBO_IND                   1
  25
  26 /* Register offsets */
  27 #define REG_ENABLE                      0x0
  28 #define REG_FREQ_LUT                    0x110
  29 #define REG_VOLT_LUT                    0x114
  30 #define REG_PERF_STATE                  0x920
  31
  32 static unsigned long cpu_hw_rate, xo_rate;
  33 static struct platform_device *global_pdev;
  34 static bool icc_scaling_enabled;
  35
  36 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
  37                                unsigned long freq_khz)
  38 {
  39         unsigned long freq_hz = freq_khz * 1000;
  40         struct dev_pm_opp *opp;
  41         struct device *dev;
  42         int ret;
  43
  44         dev = get_cpu_device(policy->cpu);
  45         if (!dev)
  46                 return -ENODEV;
  47
  48         opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
  49         if (IS_ERR(opp))
  50                 return PTR_ERR(opp);
  51
  52         ret = dev_pm_opp_set_bw(dev, opp);
  53         dev_pm_opp_put(opp);
  54         return ret;
  55 }
  56
  57 static int qcom_cpufreq_update_opp(struct device *cpu_dev,
  58                                    unsigned long freq_khz,
  59                                    unsigned long volt)
  60 {
  61         unsigned long freq_hz = freq_khz * 1000;
  62         int ret;
  63
  64         /* Skip voltage update if the opp table is not available */
  65         if (!icc_scaling_enabled)
  66                 return dev_pm_opp_add(cpu_dev, freq_hz, volt);
  67
  68         ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
  69         if (ret) {
  70                 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
  71                 return ret;
  72         }
  73
  74         return dev_pm_opp_enable(cpu_dev, freq_hz);
  75 }
  76
  77 static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
  78                                         unsigned int index)
  79 {
  80         void __iomem *perf_state_reg = policy->driver_data;
  81         unsigned long freq = policy->freq_table[index].frequency;
  82
  83         writel_relaxed(index, perf_state_reg);
  84
  85         if (icc_scaling_enabled)
  86                 qcom_cpufreq_set_bw(policy, freq);
  87
  88         return 0;
  89 }
  90
  91 static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
  92 {
  93         void __iomem *perf_state_reg;
  94         struct cpufreq_policy *policy;
  95         unsigned int index;
  96
  97         policy = cpufreq_cpu_get_raw(cpu);
  98         if (!policy)
  99                 return 0;
 100
 101         perf_state_reg = policy->driver_data;
 102
 103         index = readl_relaxed(perf_state_reg);
 104         index = min(index, LUT_MAX_ENTRIES - 1);
 105
 106         return policy->freq_table[index].frequency;
 107 }
 108
 109 static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
 110                                                 unsigned int target_freq)
 111 {
 112         void __iomem *perf_state_reg = policy->driver_data;
 113         unsigned int index;
 114
 115         index = policy->cached_resolved_idx;
 116         writel_relaxed(index, perf_state_reg);
 117
 118         return policy->freq_table[index].frequency;
 119 }
 120
 121 static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
 122                                     struct cpufreq_policy *policy,
 123                                     void __iomem *base)
 124 {
 125         u32 data, src, lval, i, core_count, prev_freq = 0, freq;
 126         u32 volt;
 127         struct cpufreq_frequency_table  *table;
 128         struct dev_pm_opp *opp;
 129         unsigned long rate;
 130         int ret;
 131
 132         table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
 133         if (!table)
 134                 return -ENOMEM;
 135
 136         ret = dev_pm_opp_of_add_table(cpu_dev);
 137         if (!ret) {
 138                 /* Disable all opps and cross-validate against LUT later */
 139                 icc_scaling_enabled = true;
 140                 for (rate = 0; ; rate++) {
 141                         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
 142                         if (IS_ERR(opp))
 143                                 break;
 144
 145                         dev_pm_opp_put(opp);
 146                         dev_pm_opp_disable(cpu_dev, rate);
 147                 }
 148         } else if (ret != -ENODEV) {
 149                 dev_err(cpu_dev, "Invalid opp table in device tree\n");
 150                 return ret;
 151         } else {
 152                 policy->fast_switch_possible = true;
 153                 icc_scaling_enabled = false;
 154         }
 155
 156         for (i = 0; i < LUT_MAX_ENTRIES; i++) {
 157                 data = readl_relaxed(base + REG_FREQ_LUT +
 158                                       i * LUT_ROW_SIZE);
 159                 src = FIELD_GET(LUT_SRC, data);
 160                 lval = FIELD_GET(LUT_L_VAL, data);
 161                 core_count = FIELD_GET(LUT_CORE_COUNT, data);
 162
 163                 data = readl_relaxed(base + REG_VOLT_LUT +
 164                                       i * LUT_ROW_SIZE);
 165                 volt = FIELD_GET(LUT_VOLT, data) * 1000;
 166
 167                 if (src)
 168                         freq = xo_rate * lval / 1000;
 169                 else
 170                         freq = cpu_hw_rate / 1000;
 171
 172                 if (freq != prev_freq && core_count != LUT_TURBO_IND) {
 173                         table[i].frequency = freq;
 174                         qcom_cpufreq_update_opp(cpu_dev, freq, volt);
 175                         dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
 176                                 freq, core_count);
 177                 } else if (core_count == LUT_TURBO_IND) {
 178                         table[i].frequency = CPUFREQ_ENTRY_INVALID;
 179                 }
 180
 181                 /*
 182                  * Two of the same frequencies with the same core counts means
 183                  * end of table
 184                  */
 185                 if (i > 0 && prev_freq == freq) {
 186                         struct cpufreq_frequency_table *prev = &table[i - 1];
 187
 188                         /*
 189                          * Only treat the last frequency that might be a boost
 190                          * as the boost frequency
 191                          */
 192                         if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
 193                                 prev->frequency = prev_freq;
 194                                 prev->flags = CPUFREQ_BOOST_FREQ;
 195                                 qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt);
 196                         }
 197
 198                         break;
 199                 }
 200
 201                 prev_freq = freq;
 202         }
 203
 204         table[i].frequency = CPUFREQ_TABLE_END;
 205         policy->freq_table = table;
 206         dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
 207
 208         return 0;
 209 }
 210
 211 static void qcom_get_related_cpus(int index, struct cpumask *m)
 212 {
 213         struct device_node *cpu_np;
 214         struct of_phandle_args args;
 215         int cpu, ret;
 216
 217         for_each_possible_cpu(cpu) {
 218                 cpu_np = of_cpu_device_node_get(cpu);
 219                 if (!cpu_np)
 220                         continue;
 221
 222                 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
 223                                                  "#freq-domain-cells", 0,
 224                                                  &args);
 225                 of_node_put(cpu_np);
 226                 if (ret < 0)
 227                         continue;
 228
 229                 if (index == args.args[0])
 230                         cpumask_set_cpu(cpu, m);
 231         }
 232 }
 233
 234 static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
 235 {
 236         struct device *dev = &global_pdev->dev;
 237         struct of_phandle_args args;
 238         struct device_node *cpu_np;
 239         struct device *cpu_dev;
 240         struct resource *res;
 241         void __iomem *base;
 242         int ret, index;
 243
 244         cpu_dev = get_cpu_device(policy->cpu);
 245         if (!cpu_dev) {
 246                 pr_err("%s: failed to get cpu%d device\n", __func__,
 247                        policy->cpu);
 248                 return -ENODEV;
 249         }
 250
 251         cpu_np = of_cpu_device_node_get(policy->cpu);
 252         if (!cpu_np)
 253                 return -EINVAL;
 254
 255         ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
 256                                          "#freq-domain-cells", 0, &args);
 257         of_node_put(cpu_np);
 258         if (ret)
 259                 return ret;
 260
 261         index = args.args[0];
 262
 263         res = platform_get_resource(global_pdev, IORESOURCE_MEM, index);
 264         if (!res)
 265                 return -ENODEV;
 266
 267         base = devm_ioremap(dev, res->start, resource_size(res));
 268         if (!base)
 269                 return -ENOMEM;
 270
 271         /* HW should be in enabled state to proceed */
 272         if (!(readl_relaxed(base + REG_ENABLE) & 0x1)) {
 273                 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
 274                 ret = -ENODEV;
 275                 goto error;
 276         }
 277
 278         qcom_get_related_cpus(index, policy->cpus);
 279         if (!cpumask_weight(policy->cpus)) {
 280                 dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
 281                 ret = -ENOENT;
 282                 goto error;
 283         }
 284
 285         policy->driver_data = base + REG_PERF_STATE;
 286
 287         ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy, base);
 288         if (ret) {
 289                 dev_err(dev, "Domain-%d failed to read LUT\n", index);
 290                 goto error;
 291         }
 292
 293         ret = dev_pm_opp_get_opp_count(cpu_dev);
 294         if (ret <= 0) {
 295                 dev_err(cpu_dev, "Failed to add OPPs\n");
 296                 ret = -ENODEV;
 297                 goto error;
 298         }
 299
 300         dev_pm_opp_of_register_em(cpu_dev, policy->cpus);
 301
 302         return 0;
 303 error:
 304         devm_iounmap(dev, base);
 305         return ret;
 306 }
 307
 308 static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
 309 {
 310         struct device *cpu_dev = get_cpu_device(policy->cpu);
 311         void __iomem *base = policy->driver_data - REG_PERF_STATE;
 312
 313         dev_pm_opp_remove_all_dynamic(cpu_dev);
 314         dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
 315         kfree(policy->freq_table);
 316         devm_iounmap(&global_pdev->dev, base);
 317
 318         return 0;
 319 }
 320
 321 static struct freq_attr *qcom_cpufreq_hw_attr[] = {
 322         &cpufreq_freq_attr_scaling_available_freqs,
 323         &cpufreq_freq_attr_scaling_boost_freqs,
 324         NULL
 325 };
 326
 327 static struct cpufreq_driver cpufreq_qcom_hw_driver = {
 328         .flags          = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
 329                           CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
 330                           CPUFREQ_IS_COOLING_DEV,
 331         .verify         = cpufreq_generic_frequency_table_verify,
 332         .target_index   = qcom_cpufreq_hw_target_index,
 333         .get            = qcom_cpufreq_hw_get,
 334         .init           = qcom_cpufreq_hw_cpu_init,
 335         .exit           = qcom_cpufreq_hw_cpu_exit,
 336         .fast_switch    = qcom_cpufreq_hw_fast_switch,
 337         .name           = "qcom-cpufreq-hw",
 338         .attr           = qcom_cpufreq_hw_attr,
 339 };
 340
 341 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
 342 {
 343         struct device *cpu_dev;
 344         struct clk *clk;
 345         int ret;
 346
 347         clk = clk_get(&pdev->dev, "xo");
 348         if (IS_ERR(clk))
 349                 return PTR_ERR(clk);
 350
 351         xo_rate = clk_get_rate(clk);
 352         clk_put(clk);
 353
 354         clk = clk_get(&pdev->dev, "alternate");
 355         if (IS_ERR(clk))
 356                 return PTR_ERR(clk);
 357
 358         cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
 359         clk_put(clk);
 360
 361         global_pdev = pdev;
 362
 363         /* Check for optional interconnect paths on CPU0 */
 364         cpu_dev = get_cpu_device(0);
 365         if (!cpu_dev)
 366                 return -EPROBE_DEFER;
 367
 368         ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
 369         if (ret)
 370                 return ret;
 371
 372         ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
 373         if (ret)
 374                 dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
 375         else
 376                 dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
 377
 378         return ret;
 379 }
 380
 381 static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
 382 {
 383         return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
 384 }
 385
 386 static const struct of_device_id qcom_cpufreq_hw_match[] = {
 387         { .compatible = "qcom,cpufreq-hw" },
 388         {}
 389 };
 390 MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
 391
 392 static struct platform_driver qcom_cpufreq_hw_driver = {
 393         .probe = qcom_cpufreq_hw_driver_probe,
 394         .remove = qcom_cpufreq_hw_driver_remove,
 395         .driver = {
 396                 .name = "qcom-cpufreq-hw",
 397                 .of_match_table = qcom_cpufreq_hw_match,
 398         },
 399 };
 400
 401 static int __init qcom_cpufreq_hw_init(void)
 402 {
 403         return platform_driver_register(&qcom_cpufreq_hw_driver);
 404 }
 405 postcore_initcall(qcom_cpufreq_hw_init);
 406
 407 static void __exit qcom_cpufreq_hw_exit(void)
 408 {
 409         platform_driver_unregister(&qcom_cpufreq_hw_driver);
 410 }
 411 module_exit(qcom_cpufreq_hw_exit);
 412
 413 MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
 414 MODULE_LICENSE("GPL v2");