1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 #include <linux/bitfield.h>
7 #include <linux/cpufreq.h>
8 #include <linux/init.h>
9 #include <linux/interconnect.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of_address.h>
13 #include <linux/of_platform.h>
14 #include <linux/pm_opp.h>
15 #include <linux/slab.h>
17 #define LUT_MAX_ENTRIES 40U
18 #define LUT_SRC GENMASK(31, 30)
19 #define LUT_L_VAL GENMASK(7, 0)
20 #define LUT_CORE_COUNT GENMASK(18, 16)
21 #define LUT_VOLT GENMASK(11, 0)
22 #define LUT_ROW_SIZE 32
24 #define LUT_TURBO_IND 1
26 /* Register offsets */
27 #define REG_ENABLE 0x0
28 #define REG_FREQ_LUT 0x110
29 #define REG_VOLT_LUT 0x114
30 #define REG_PERF_STATE 0x920
32 static unsigned long cpu_hw_rate, xo_rate;
33 static bool icc_scaling_enabled;
35 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
36 unsigned long freq_khz)
38 unsigned long freq_hz = freq_khz * 1000;
39 struct dev_pm_opp *opp;
43 dev = get_cpu_device(policy->cpu);
47 opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
51 ret = dev_pm_opp_set_bw(dev, opp);
56 static int qcom_cpufreq_update_opp(struct device *cpu_dev,
57 unsigned long freq_khz,
60 unsigned long freq_hz = freq_khz * 1000;
63 /* Skip voltage update if the opp table is not available */
64 if (!icc_scaling_enabled)
65 return dev_pm_opp_add(cpu_dev, freq_hz, volt);
67 ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
69 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
73 return dev_pm_opp_enable(cpu_dev, freq_hz);
76 static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
79 void __iomem *perf_state_reg = policy->driver_data;
80 unsigned long freq = policy->freq_table[index].frequency;
82 writel_relaxed(index, perf_state_reg);
84 if (icc_scaling_enabled)
85 qcom_cpufreq_set_bw(policy, freq);
87 arch_set_freq_scale(policy->related_cpus, freq,
88 policy->cpuinfo.max_freq);
92 static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
94 void __iomem *perf_state_reg;
95 struct cpufreq_policy *policy;
98 policy = cpufreq_cpu_get_raw(cpu);
102 perf_state_reg = policy->driver_data;
104 index = readl_relaxed(perf_state_reg);
105 index = min(index, LUT_MAX_ENTRIES - 1);
107 return policy->freq_table[index].frequency;
110 static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
111 unsigned int target_freq)
113 void __iomem *perf_state_reg = policy->driver_data;
117 index = policy->cached_resolved_idx;
118 writel_relaxed(index, perf_state_reg);
120 freq = policy->freq_table[index].frequency;
121 arch_set_freq_scale(policy->related_cpus, freq,
122 policy->cpuinfo.max_freq);
127 static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
128 struct cpufreq_policy *policy,
131 u32 data, src, lval, i, core_count, prev_freq = 0, freq;
133 struct cpufreq_frequency_table *table;
134 struct dev_pm_opp *opp;
138 table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
142 ret = dev_pm_opp_of_add_table(cpu_dev);
144 /* Disable all opps and cross-validate against LUT later */
145 icc_scaling_enabled = true;
146 for (rate = 0; ; rate++) {
147 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
152 dev_pm_opp_disable(cpu_dev, rate);
154 } else if (ret != -ENODEV) {
155 dev_err(cpu_dev, "Invalid opp table in device tree\n");
158 policy->fast_switch_possible = true;
159 icc_scaling_enabled = false;
162 for (i = 0; i < LUT_MAX_ENTRIES; i++) {
163 data = readl_relaxed(base + REG_FREQ_LUT +
165 src = FIELD_GET(LUT_SRC, data);
166 lval = FIELD_GET(LUT_L_VAL, data);
167 core_count = FIELD_GET(LUT_CORE_COUNT, data);
169 data = readl_relaxed(base + REG_VOLT_LUT +
171 volt = FIELD_GET(LUT_VOLT, data) * 1000;
174 freq = xo_rate * lval / 1000;
176 freq = cpu_hw_rate / 1000;
178 if (freq != prev_freq && core_count != LUT_TURBO_IND) {
179 table[i].frequency = freq;
180 qcom_cpufreq_update_opp(cpu_dev, freq, volt);
181 dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
183 } else if (core_count == LUT_TURBO_IND) {
184 table[i].frequency = CPUFREQ_ENTRY_INVALID;
188 * Two of the same frequencies with the same core counts means
191 if (i > 0 && prev_freq == freq) {
192 struct cpufreq_frequency_table *prev = &table[i - 1];
195 * Only treat the last frequency that might be a boost
196 * as the boost frequency
198 if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
199 prev->frequency = prev_freq;
200 prev->flags = CPUFREQ_BOOST_FREQ;
201 qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt);
210 table[i].frequency = CPUFREQ_TABLE_END;
211 policy->freq_table = table;
212 dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
217 static void qcom_get_related_cpus(int index, struct cpumask *m)
219 struct device_node *cpu_np;
220 struct of_phandle_args args;
223 for_each_possible_cpu(cpu) {
224 cpu_np = of_cpu_device_node_get(cpu);
228 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
229 "#freq-domain-cells", 0,
235 if (index == args.args[0])
236 cpumask_set_cpu(cpu, m);
240 static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
242 struct platform_device *pdev = cpufreq_get_driver_data();
243 struct device *dev = &pdev->dev;
244 struct of_phandle_args args;
245 struct device_node *cpu_np;
246 struct device *cpu_dev;
247 struct resource *res;
251 cpu_dev = get_cpu_device(policy->cpu);
253 pr_err("%s: failed to get cpu%d device\n", __func__,
258 cpu_np = of_cpu_device_node_get(policy->cpu);
262 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
263 "#freq-domain-cells", 0, &args);
268 index = args.args[0];
270 res = platform_get_resource(pdev, IORESOURCE_MEM, index);
274 base = devm_ioremap(dev, res->start, resource_size(res));
278 /* HW should be in enabled state to proceed */
279 if (!(readl_relaxed(base + REG_ENABLE) & 0x1)) {
280 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
285 qcom_get_related_cpus(index, policy->cpus);
286 if (!cpumask_weight(policy->cpus)) {
287 dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
292 policy->driver_data = base + REG_PERF_STATE;
294 ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy, base);
296 dev_err(dev, "Domain-%d failed to read LUT\n", index);
300 ret = dev_pm_opp_get_opp_count(cpu_dev);
302 dev_err(cpu_dev, "Failed to add OPPs\n");
307 dev_pm_opp_of_register_em(cpu_dev, policy->cpus);
311 devm_iounmap(dev, base);
315 static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
317 struct device *cpu_dev = get_cpu_device(policy->cpu);
318 void __iomem *base = policy->driver_data - REG_PERF_STATE;
319 struct platform_device *pdev = cpufreq_get_driver_data();
321 dev_pm_opp_remove_all_dynamic(cpu_dev);
322 dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
323 kfree(policy->freq_table);
324 devm_iounmap(&pdev->dev, base);
329 static struct freq_attr *qcom_cpufreq_hw_attr[] = {
330 &cpufreq_freq_attr_scaling_available_freqs,
331 &cpufreq_freq_attr_scaling_boost_freqs,
335 static struct cpufreq_driver cpufreq_qcom_hw_driver = {
336 .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
337 CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
338 CPUFREQ_IS_COOLING_DEV,
339 .verify = cpufreq_generic_frequency_table_verify,
340 .target_index = qcom_cpufreq_hw_target_index,
341 .get = qcom_cpufreq_hw_get,
342 .init = qcom_cpufreq_hw_cpu_init,
343 .exit = qcom_cpufreq_hw_cpu_exit,
344 .fast_switch = qcom_cpufreq_hw_fast_switch,
345 .name = "qcom-cpufreq-hw",
346 .attr = qcom_cpufreq_hw_attr,
349 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
351 struct device *cpu_dev;
355 clk = clk_get(&pdev->dev, "xo");
359 xo_rate = clk_get_rate(clk);
362 clk = clk_get(&pdev->dev, "alternate");
366 cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
369 cpufreq_qcom_hw_driver.driver_data = pdev;
371 /* Check for optional interconnect paths on CPU0 */
372 cpu_dev = get_cpu_device(0);
374 return -EPROBE_DEFER;
376 ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
380 ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
382 dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
384 dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
389 static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
391 return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
394 static const struct of_device_id qcom_cpufreq_hw_match[] = {
395 { .compatible = "qcom,cpufreq-hw" },
398 MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
400 static struct platform_driver qcom_cpufreq_hw_driver = {
401 .probe = qcom_cpufreq_hw_driver_probe,
402 .remove = qcom_cpufreq_hw_driver_remove,
404 .name = "qcom-cpufreq-hw",
405 .of_match_table = qcom_cpufreq_hw_match,
409 static int __init qcom_cpufreq_hw_init(void)
411 return platform_driver_register(&qcom_cpufreq_hw_driver);
413 postcore_initcall(qcom_cpufreq_hw_init);
415 static void __exit qcom_cpufreq_hw_exit(void)
417 platform_driver_unregister(&qcom_cpufreq_hw_driver);
419 module_exit(qcom_cpufreq_hw_exit);
421 MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
422 MODULE_LICENSE("GPL v2");