drivers/cpufreq/qcom-cpufreq-hw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/cpufreq.h>
   8 #include <linux/init.h>
   9 #include <linux/interconnect.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/of_address.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/pm_opp.h>
  15 #include <linux/slab.h>
  16
  17 #define LUT_MAX_ENTRIES                 40U
  18 #define LUT_SRC                         GENMASK(31, 30)
  19 #define LUT_L_VAL                       GENMASK(7, 0)
  20 #define LUT_CORE_COUNT                  GENMASK(18, 16)
  21 #define LUT_VOLT                        GENMASK(11, 0)
  22 #define CLK_HW_DIV                      2
  23 #define LUT_TURBO_IND                   1
  24
  25 struct qcom_cpufreq_soc_data {
  26         u32 reg_enable;
  27         u32 reg_freq_lut;
  28         u32 reg_volt_lut;
  29         u32 reg_perf_state;
  30         u8 lut_row_size;
  31 };
  32
  33 struct qcom_cpufreq_data {
  34         void __iomem *base;
  35         const struct qcom_cpufreq_soc_data *soc_data;
  36 };
  37
  38 static unsigned long cpu_hw_rate, xo_rate;
  39 static bool icc_scaling_enabled;
  40
  41 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
  42                                unsigned long freq_khz)
  43 {
  44         unsigned long freq_hz = freq_khz * 1000;
  45         struct dev_pm_opp *opp;
  46         struct device *dev;
  47         int ret;
  48
  49         dev = get_cpu_device(policy->cpu);
  50         if (!dev)
  51                 return -ENODEV;
  52
  53         opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
  54         if (IS_ERR(opp))
  55                 return PTR_ERR(opp);
  56
  57         ret = dev_pm_opp_set_bw(dev, opp);
  58         dev_pm_opp_put(opp);
  59         return ret;
  60 }
  61
  62 static int qcom_cpufreq_update_opp(struct device *cpu_dev,
  63                                    unsigned long freq_khz,
  64                                    unsigned long volt)
  65 {
  66         unsigned long freq_hz = freq_khz * 1000;
  67         int ret;
  68
  69         /* Skip voltage update if the opp table is not available */
  70         if (!icc_scaling_enabled)
  71                 return dev_pm_opp_add(cpu_dev, freq_hz, volt);
  72
  73         ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
  74         if (ret) {
  75                 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
  76                 return ret;
  77         }
  78
  79         return dev_pm_opp_enable(cpu_dev, freq_hz);
  80 }
  81
  82 static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
  83                                         unsigned int index)
  84 {
  85         struct qcom_cpufreq_data *data = policy->driver_data;
  86         const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
  87         unsigned long freq = policy->freq_table[index].frequency;
  88
  89         writel_relaxed(index, data->base + soc_data->reg_perf_state);
  90
  91         if (icc_scaling_enabled)
  92                 qcom_cpufreq_set_bw(policy, freq);
  93
  94         arch_set_freq_scale(policy->related_cpus, freq,
  95                             policy->cpuinfo.max_freq);
  96         return 0;
  97 }
  98
  99 static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
 100 {
 101         struct qcom_cpufreq_data *data;
 102         const struct qcom_cpufreq_soc_data *soc_data;
 103         struct cpufreq_policy *policy;
 104         unsigned int index;
 105
 106         policy = cpufreq_cpu_get_raw(cpu);
 107         if (!policy)
 108                 return 0;
 109
 110         data = policy->driver_data;
 111         soc_data = data->soc_data;
 112
 113         index = readl_relaxed(data->base + soc_data->reg_perf_state);
 114         index = min(index, LUT_MAX_ENTRIES - 1);
 115
 116         return policy->freq_table[index].frequency;
 117 }
 118
 119 static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
 120                                                 unsigned int target_freq)
 121 {
 122         struct qcom_cpufreq_data *data = policy->driver_data;
 123         const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
 124         unsigned int index;
 125         unsigned long freq;
 126
 127         index = policy->cached_resolved_idx;
 128         writel_relaxed(index, data->base + soc_data->reg_perf_state);
 129
 130         freq = policy->freq_table[index].frequency;
 131         arch_set_freq_scale(policy->related_cpus, freq,
 132                             policy->cpuinfo.max_freq);
 133
 134         return freq;
 135 }
 136
 137 static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
 138                                     struct cpufreq_policy *policy)
 139 {
 140         u32 data, src, lval, i, core_count, prev_freq = 0, freq;
 141         u32 volt;
 142         struct cpufreq_frequency_table  *table;
 143         struct dev_pm_opp *opp;
 144         unsigned long rate;
 145         int ret;
 146         struct qcom_cpufreq_data *drv_data = policy->driver_data;
 147         const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data;
 148
 149         table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
 150         if (!table)
 151                 return -ENOMEM;
 152
 153         ret = dev_pm_opp_of_add_table(cpu_dev);
 154         if (!ret) {
 155                 /* Disable all opps and cross-validate against LUT later */
 156                 icc_scaling_enabled = true;
 157                 for (rate = 0; ; rate++) {
 158                         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
 159                         if (IS_ERR(opp))
 160                                 break;
 161
 162                         dev_pm_opp_put(opp);
 163                         dev_pm_opp_disable(cpu_dev, rate);
 164                 }
 165         } else if (ret != -ENODEV) {
 166                 dev_err(cpu_dev, "Invalid opp table in device tree\n");
 167                 return ret;
 168         } else {
 169                 policy->fast_switch_possible = true;
 170                 icc_scaling_enabled = false;
 171         }
 172
 173         for (i = 0; i < LUT_MAX_ENTRIES; i++) {
 174                 data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut +
 175                                       i * soc_data->lut_row_size);
 176                 src = FIELD_GET(LUT_SRC, data);
 177                 lval = FIELD_GET(LUT_L_VAL, data);
 178                 core_count = FIELD_GET(LUT_CORE_COUNT, data);
 179
 180                 data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut +
 181                                       i * soc_data->lut_row_size);
 182                 volt = FIELD_GET(LUT_VOLT, data) * 1000;
 183
 184                 if (src)
 185                         freq = xo_rate * lval / 1000;
 186                 else
 187                         freq = cpu_hw_rate / 1000;
 188
 189                 if (freq != prev_freq && core_count != LUT_TURBO_IND) {
 190                         if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) {
 191                                 table[i].frequency = freq;
 192                                 dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
 193                                 freq, core_count);
 194                         } else {
 195                                 dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq);
 196                                 table[i].frequency = CPUFREQ_ENTRY_INVALID;
 197                         }
 198
 199                 } else if (core_count == LUT_TURBO_IND) {
 200                         table[i].frequency = CPUFREQ_ENTRY_INVALID;
 201                 }
 202
 203                 /*
 204                  * Two of the same frequencies with the same core counts means
 205                  * end of table
 206                  */
 207                 if (i > 0 && prev_freq == freq) {
 208                         struct cpufreq_frequency_table *prev = &table[i - 1];
 209
 210                         /*
 211                          * Only treat the last frequency that might be a boost
 212                          * as the boost frequency
 213                          */
 214                         if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
 215                                 if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) {
 216                                         prev->frequency = prev_freq;
 217                                         prev->flags = CPUFREQ_BOOST_FREQ;
 218                                 } else {
 219                                         dev_warn(cpu_dev, "failed to update OPP for freq=%d\n",
 220                                                  freq);
 221                                 }
 222                         }
 223
 224                         break;
 225                 }
 226
 227                 prev_freq = freq;
 228         }
 229
 230         table[i].frequency = CPUFREQ_TABLE_END;
 231         policy->freq_table = table;
 232         dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
 233
 234         return 0;
 235 }
 236
 237 static void qcom_get_related_cpus(int index, struct cpumask *m)
 238 {
 239         struct device_node *cpu_np;
 240         struct of_phandle_args args;
 241         int cpu, ret;
 242
 243         for_each_possible_cpu(cpu) {
 244                 cpu_np = of_cpu_device_node_get(cpu);
 245                 if (!cpu_np)
 246                         continue;
 247
 248                 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
 249                                                  "#freq-domain-cells", 0,
 250                                                  &args);
 251                 of_node_put(cpu_np);
 252                 if (ret < 0)
 253                         continue;
 254
 255                 if (index == args.args[0])
 256                         cpumask_set_cpu(cpu, m);
 257         }
 258 }
 259
 260 static const struct qcom_cpufreq_soc_data qcom_soc_data = {
 261         .reg_enable = 0x0,
 262         .reg_freq_lut = 0x110,
 263         .reg_volt_lut = 0x114,
 264         .reg_perf_state = 0x920,
 265         .lut_row_size = 32,
 266 };
 267
 268 static const struct qcom_cpufreq_soc_data epss_soc_data = {
 269         .reg_enable = 0x0,
 270         .reg_freq_lut = 0x100,
 271         .reg_volt_lut = 0x200,
 272         .reg_perf_state = 0x320,
 273         .lut_row_size = 4,
 274 };
 275
 276 static const struct of_device_id qcom_cpufreq_hw_match[] = {
 277         { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
 278         { .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
 279         {}
 280 };
 281 MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
 282
 283 static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
 284 {
 285         struct platform_device *pdev = cpufreq_get_driver_data();
 286         struct device *dev = &pdev->dev;
 287         struct of_phandle_args args;
 288         struct device_node *cpu_np;
 289         struct device *cpu_dev;
 290         void __iomem *base;
 291         struct qcom_cpufreq_data *data;
 292         int ret, index;
 293
 294         cpu_dev = get_cpu_device(policy->cpu);
 295         if (!cpu_dev) {
 296                 pr_err("%s: failed to get cpu%d device\n", __func__,
 297                        policy->cpu);
 298                 return -ENODEV;
 299         }
 300
 301         cpu_np = of_cpu_device_node_get(policy->cpu);
 302         if (!cpu_np)
 303                 return -EINVAL;
 304
 305         ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
 306                                          "#freq-domain-cells", 0, &args);
 307         of_node_put(cpu_np);
 308         if (ret)
 309                 return ret;
 310
 311         index = args.args[0];
 312
 313         base = devm_platform_ioremap_resource(pdev, index);
 314         if (IS_ERR(base))
 315                 return PTR_ERR(base);
 316
 317         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 318         if (!data) {
 319                 ret = -ENOMEM;
 320                 goto error;
 321         }
 322
 323         data->soc_data = of_device_get_match_data(&pdev->dev);
 324         data->base = base;
 325
 326         /* HW should be in enabled state to proceed */
 327         if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
 328                 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
 329                 ret = -ENODEV;
 330                 goto error;
 331         }
 332
 333         qcom_get_related_cpus(index, policy->cpus);
 334         if (!cpumask_weight(policy->cpus)) {
 335                 dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
 336                 ret = -ENOENT;
 337                 goto error;
 338         }
 339
 340         policy->driver_data = data;
 341
 342         ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy);
 343         if (ret) {
 344                 dev_err(dev, "Domain-%d failed to read LUT\n", index);
 345                 goto error;
 346         }
 347
 348         ret = dev_pm_opp_get_opp_count(cpu_dev);
 349         if (ret <= 0) {
 350                 dev_err(cpu_dev, "Failed to add OPPs\n");
 351                 ret = -ENODEV;
 352                 goto error;
 353         }
 354
 355         dev_pm_opp_of_register_em(cpu_dev, policy->cpus);
 356
 357         return 0;
 358 error:
 359         devm_iounmap(dev, base);
 360         return ret;
 361 }
 362
 363 static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
 364 {
 365         struct device *cpu_dev = get_cpu_device(policy->cpu);
 366         struct qcom_cpufreq_data *data = policy->driver_data;
 367         struct platform_device *pdev = cpufreq_get_driver_data();
 368
 369         dev_pm_opp_remove_all_dynamic(cpu_dev);
 370         dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
 371         kfree(policy->freq_table);
 372         devm_iounmap(&pdev->dev, data->base);
 373
 374         return 0;
 375 }
 376
 377 static struct freq_attr *qcom_cpufreq_hw_attr[] = {
 378         &cpufreq_freq_attr_scaling_available_freqs,
 379         &cpufreq_freq_attr_scaling_boost_freqs,
 380         NULL
 381 };
 382
 383 static struct cpufreq_driver cpufreq_qcom_hw_driver = {
 384         .flags          = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
 385                           CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
 386                           CPUFREQ_IS_COOLING_DEV,
 387         .verify         = cpufreq_generic_frequency_table_verify,
 388         .target_index   = qcom_cpufreq_hw_target_index,
 389         .get            = qcom_cpufreq_hw_get,
 390         .init           = qcom_cpufreq_hw_cpu_init,
 391         .exit           = qcom_cpufreq_hw_cpu_exit,
 392         .fast_switch    = qcom_cpufreq_hw_fast_switch,
 393         .name           = "qcom-cpufreq-hw",
 394         .attr           = qcom_cpufreq_hw_attr,
 395 };
 396
 397 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
 398 {
 399         struct device *cpu_dev;
 400         struct clk *clk;
 401         int ret;
 402
 403         clk = clk_get(&pdev->dev, "xo");
 404         if (IS_ERR(clk))
 405                 return PTR_ERR(clk);
 406
 407         xo_rate = clk_get_rate(clk);
 408         clk_put(clk);
 409
 410         clk = clk_get(&pdev->dev, "alternate");
 411         if (IS_ERR(clk))
 412                 return PTR_ERR(clk);
 413
 414         cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
 415         clk_put(clk);
 416
 417         cpufreq_qcom_hw_driver.driver_data = pdev;
 418
 419         /* Check for optional interconnect paths on CPU0 */
 420         cpu_dev = get_cpu_device(0);
 421         if (!cpu_dev)
 422                 return -EPROBE_DEFER;
 423
 424         ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
 425         if (ret)
 426                 return ret;
 427
 428         ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
 429         if (ret)
 430                 dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
 431         else
 432                 dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
 433
 434         return ret;
 435 }
 436
 437 static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
 438 {
 439         return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
 440 }
 441
 442 static struct platform_driver qcom_cpufreq_hw_driver = {
 443         .probe = qcom_cpufreq_hw_driver_probe,
 444         .remove = qcom_cpufreq_hw_driver_remove,
 445         .driver = {
 446                 .name = "qcom-cpufreq-hw",
 447                 .of_match_table = qcom_cpufreq_hw_match,
 448         },
 449 };
 450
 451 static int __init qcom_cpufreq_hw_init(void)
 452 {
 453         return platform_driver_register(&qcom_cpufreq_hw_driver);
 454 }
 455 postcore_initcall(qcom_cpufreq_hw_init);
 456
 457 static void __exit qcom_cpufreq_hw_exit(void)
 458 {
 459         platform_driver_unregister(&qcom_cpufreq_hw_driver);
 460 }
 461 module_exit(qcom_cpufreq_hw_exit);
 462
 463 MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
 464 MODULE_LICENSE("GPL v2");