drivers/cpufreq/qcom-cpufreq-hw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/cpufreq.h>
   8 #include <linux/init.h>
   9 #include <linux/interconnect.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/of_address.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/pm_opp.h>
  15 #include <linux/slab.h>
  16
  17 #define LUT_MAX_ENTRIES                 40U
  18 #define LUT_SRC                         GENMASK(31, 30)
  19 #define LUT_L_VAL                       GENMASK(7, 0)
  20 #define LUT_CORE_COUNT                  GENMASK(18, 16)
  21 #define LUT_VOLT                        GENMASK(11, 0)
  22 #define LUT_ROW_SIZE                    32
  23 #define CLK_HW_DIV                      2
  24 #define LUT_TURBO_IND                   1
  25
  26 /* Register offsets */
  27 #define REG_ENABLE                      0x0
  28 #define REG_FREQ_LUT                    0x110
  29 #define REG_VOLT_LUT                    0x114
  30 #define REG_PERF_STATE                  0x920
  31
  32 static unsigned long cpu_hw_rate, xo_rate;
  33 static bool icc_scaling_enabled;
  34
  35 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
  36                                unsigned long freq_khz)
  37 {
  38         unsigned long freq_hz = freq_khz * 1000;
  39         struct dev_pm_opp *opp;
  40         struct device *dev;
  41         int ret;
  42
  43         dev = get_cpu_device(policy->cpu);
  44         if (!dev)
  45                 return -ENODEV;
  46
  47         opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
  48         if (IS_ERR(opp))
  49                 return PTR_ERR(opp);
  50
  51         ret = dev_pm_opp_set_bw(dev, opp);
  52         dev_pm_opp_put(opp);
  53         return ret;
  54 }
  55
  56 static int qcom_cpufreq_update_opp(struct device *cpu_dev,
  57                                    unsigned long freq_khz,
  58                                    unsigned long volt)
  59 {
  60         unsigned long freq_hz = freq_khz * 1000;
  61         int ret;
  62
  63         /* Skip voltage update if the opp table is not available */
  64         if (!icc_scaling_enabled)
  65                 return dev_pm_opp_add(cpu_dev, freq_hz, volt);
  66
  67         ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
  68         if (ret) {
  69                 dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
  70                 return ret;
  71         }
  72
  73         return dev_pm_opp_enable(cpu_dev, freq_hz);
  74 }
  75
  76 static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
  77                                         unsigned int index)
  78 {
  79         void __iomem *perf_state_reg = policy->driver_data;
  80         unsigned long freq = policy->freq_table[index].frequency;
  81
  82         writel_relaxed(index, perf_state_reg);
  83
  84         if (icc_scaling_enabled)
  85                 qcom_cpufreq_set_bw(policy, freq);
  86
  87         arch_set_freq_scale(policy->related_cpus, freq,
  88                             policy->cpuinfo.max_freq);
  89         return 0;
  90 }
  91
  92 static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
  93 {
  94         void __iomem *perf_state_reg;
  95         struct cpufreq_policy *policy;
  96         unsigned int index;
  97
  98         policy = cpufreq_cpu_get_raw(cpu);
  99         if (!policy)
 100                 return 0;
 101
 102         perf_state_reg = policy->driver_data;
 103
 104         index = readl_relaxed(perf_state_reg);
 105         index = min(index, LUT_MAX_ENTRIES - 1);
 106
 107         return policy->freq_table[index].frequency;
 108 }
 109
 110 static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
 111                                                 unsigned int target_freq)
 112 {
 113         void __iomem *perf_state_reg = policy->driver_data;
 114         unsigned int index;
 115         unsigned long freq;
 116
 117         index = policy->cached_resolved_idx;
 118         writel_relaxed(index, perf_state_reg);
 119
 120         freq = policy->freq_table[index].frequency;
 121         arch_set_freq_scale(policy->related_cpus, freq,
 122                             policy->cpuinfo.max_freq);
 123
 124         return freq;
 125 }
 126
 127 static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
 128                                     struct cpufreq_policy *policy,
 129                                     void __iomem *base)
 130 {
 131         u32 data, src, lval, i, core_count, prev_freq = 0, freq;
 132         u32 volt;
 133         struct cpufreq_frequency_table  *table;
 134         struct dev_pm_opp *opp;
 135         unsigned long rate;
 136         int ret;
 137
 138         table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
 139         if (!table)
 140                 return -ENOMEM;
 141
 142         ret = dev_pm_opp_of_add_table(cpu_dev);
 143         if (!ret) {
 144                 /* Disable all opps and cross-validate against LUT later */
 145                 icc_scaling_enabled = true;
 146                 for (rate = 0; ; rate++) {
 147                         opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
 148                         if (IS_ERR(opp))
 149                                 break;
 150
 151                         dev_pm_opp_put(opp);
 152                         dev_pm_opp_disable(cpu_dev, rate);
 153                 }
 154         } else if (ret != -ENODEV) {
 155                 dev_err(cpu_dev, "Invalid opp table in device tree\n");
 156                 return ret;
 157         } else {
 158                 policy->fast_switch_possible = true;
 159                 icc_scaling_enabled = false;
 160         }
 161
 162         for (i = 0; i < LUT_MAX_ENTRIES; i++) {
 163                 data = readl_relaxed(base + REG_FREQ_LUT +
 164                                       i * LUT_ROW_SIZE);
 165                 src = FIELD_GET(LUT_SRC, data);
 166                 lval = FIELD_GET(LUT_L_VAL, data);
 167                 core_count = FIELD_GET(LUT_CORE_COUNT, data);
 168
 169                 data = readl_relaxed(base + REG_VOLT_LUT +
 170                                       i * LUT_ROW_SIZE);
 171                 volt = FIELD_GET(LUT_VOLT, data) * 1000;
 172
 173                 if (src)
 174                         freq = xo_rate * lval / 1000;
 175                 else
 176                         freq = cpu_hw_rate / 1000;
 177
 178                 if (freq != prev_freq && core_count != LUT_TURBO_IND) {
 179                         table[i].frequency = freq;
 180                         qcom_cpufreq_update_opp(cpu_dev, freq, volt);
 181                         dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
 182                                 freq, core_count);
 183                 } else if (core_count == LUT_TURBO_IND) {
 184                         table[i].frequency = CPUFREQ_ENTRY_INVALID;
 185                 }
 186
 187                 /*
 188                  * Two of the same frequencies with the same core counts means
 189                  * end of table
 190                  */
 191                 if (i > 0 && prev_freq == freq) {
 192                         struct cpufreq_frequency_table *prev = &table[i - 1];
 193
 194                         /*
 195                          * Only treat the last frequency that might be a boost
 196                          * as the boost frequency
 197                          */
 198                         if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
 199                                 prev->frequency = prev_freq;
 200                                 prev->flags = CPUFREQ_BOOST_FREQ;
 201                                 qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt);
 202                         }
 203
 204                         break;
 205                 }
 206
 207                 prev_freq = freq;
 208         }
 209
 210         table[i].frequency = CPUFREQ_TABLE_END;
 211         policy->freq_table = table;
 212         dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
 213
 214         return 0;
 215 }
 216
 217 static void qcom_get_related_cpus(int index, struct cpumask *m)
 218 {
 219         struct device_node *cpu_np;
 220         struct of_phandle_args args;
 221         int cpu, ret;
 222
 223         for_each_possible_cpu(cpu) {
 224                 cpu_np = of_cpu_device_node_get(cpu);
 225                 if (!cpu_np)
 226                         continue;
 227
 228                 ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
 229                                                  "#freq-domain-cells", 0,
 230                                                  &args);
 231                 of_node_put(cpu_np);
 232                 if (ret < 0)
 233                         continue;
 234
 235                 if (index == args.args[0])
 236                         cpumask_set_cpu(cpu, m);
 237         }
 238 }
 239
 240 static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
 241 {
 242         struct platform_device *pdev = cpufreq_get_driver_data();
 243         struct device *dev = &pdev->dev;
 244         struct of_phandle_args args;
 245         struct device_node *cpu_np;
 246         struct device *cpu_dev;
 247         struct resource *res;
 248         void __iomem *base;
 249         int ret, index;
 250
 251         cpu_dev = get_cpu_device(policy->cpu);
 252         if (!cpu_dev) {
 253                 pr_err("%s: failed to get cpu%d device\n", __func__,
 254                        policy->cpu);
 255                 return -ENODEV;
 256         }
 257
 258         cpu_np = of_cpu_device_node_get(policy->cpu);
 259         if (!cpu_np)
 260                 return -EINVAL;
 261
 262         ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
 263                                          "#freq-domain-cells", 0, &args);
 264         of_node_put(cpu_np);
 265         if (ret)
 266                 return ret;
 267
 268         index = args.args[0];
 269
 270         res = platform_get_resource(pdev, IORESOURCE_MEM, index);
 271         if (!res)
 272                 return -ENODEV;
 273
 274         base = devm_ioremap(dev, res->start, resource_size(res));
 275         if (!base)
 276                 return -ENOMEM;
 277
 278         /* HW should be in enabled state to proceed */
 279         if (!(readl_relaxed(base + REG_ENABLE) & 0x1)) {
 280                 dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
 281                 ret = -ENODEV;
 282                 goto error;
 283         }
 284
 285         qcom_get_related_cpus(index, policy->cpus);
 286         if (!cpumask_weight(policy->cpus)) {
 287                 dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
 288                 ret = -ENOENT;
 289                 goto error;
 290         }
 291
 292         policy->driver_data = base + REG_PERF_STATE;
 293
 294         ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy, base);
 295         if (ret) {
 296                 dev_err(dev, "Domain-%d failed to read LUT\n", index);
 297                 goto error;
 298         }
 299
 300         ret = dev_pm_opp_get_opp_count(cpu_dev);
 301         if (ret <= 0) {
 302                 dev_err(cpu_dev, "Failed to add OPPs\n");
 303                 ret = -ENODEV;
 304                 goto error;
 305         }
 306
 307         dev_pm_opp_of_register_em(cpu_dev, policy->cpus);
 308
 309         return 0;
 310 error:
 311         devm_iounmap(dev, base);
 312         return ret;
 313 }
 314
 315 static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
 316 {
 317         struct device *cpu_dev = get_cpu_device(policy->cpu);
 318         void __iomem *base = policy->driver_data - REG_PERF_STATE;
 319         struct platform_device *pdev = cpufreq_get_driver_data();
 320
 321         dev_pm_opp_remove_all_dynamic(cpu_dev);
 322         dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
 323         kfree(policy->freq_table);
 324         devm_iounmap(&pdev->dev, base);
 325
 326         return 0;
 327 }
 328
 329 static struct freq_attr *qcom_cpufreq_hw_attr[] = {
 330         &cpufreq_freq_attr_scaling_available_freqs,
 331         &cpufreq_freq_attr_scaling_boost_freqs,
 332         NULL
 333 };
 334
 335 static struct cpufreq_driver cpufreq_qcom_hw_driver = {
 336         .flags          = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
 337                           CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
 338                           CPUFREQ_IS_COOLING_DEV,
 339         .verify         = cpufreq_generic_frequency_table_verify,
 340         .target_index   = qcom_cpufreq_hw_target_index,
 341         .get            = qcom_cpufreq_hw_get,
 342         .init           = qcom_cpufreq_hw_cpu_init,
 343         .exit           = qcom_cpufreq_hw_cpu_exit,
 344         .fast_switch    = qcom_cpufreq_hw_fast_switch,
 345         .name           = "qcom-cpufreq-hw",
 346         .attr           = qcom_cpufreq_hw_attr,
 347 };
 348
 349 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
 350 {
 351         struct device *cpu_dev;
 352         struct clk *clk;
 353         int ret;
 354
 355         clk = clk_get(&pdev->dev, "xo");
 356         if (IS_ERR(clk))
 357                 return PTR_ERR(clk);
 358
 359         xo_rate = clk_get_rate(clk);
 360         clk_put(clk);
 361
 362         clk = clk_get(&pdev->dev, "alternate");
 363         if (IS_ERR(clk))
 364                 return PTR_ERR(clk);
 365
 366         cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
 367         clk_put(clk);
 368
 369         cpufreq_qcom_hw_driver.driver_data = pdev;
 370
 371         /* Check for optional interconnect paths on CPU0 */
 372         cpu_dev = get_cpu_device(0);
 373         if (!cpu_dev)
 374                 return -EPROBE_DEFER;
 375
 376         ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
 377         if (ret)
 378                 return ret;
 379
 380         ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
 381         if (ret)
 382                 dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
 383         else
 384                 dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
 385
 386         return ret;
 387 }
 388
 389 static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
 390 {
 391         return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
 392 }
 393
 394 static const struct of_device_id qcom_cpufreq_hw_match[] = {
 395         { .compatible = "qcom,cpufreq-hw" },
 396         {}
 397 };
 398 MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
 399
 400 static struct platform_driver qcom_cpufreq_hw_driver = {
 401         .probe = qcom_cpufreq_hw_driver_probe,
 402         .remove = qcom_cpufreq_hw_driver_remove,
 403         .driver = {
 404                 .name = "qcom-cpufreq-hw",
 405                 .of_match_table = qcom_cpufreq_hw_match,
 406         },
 407 };
 408
 409 static int __init qcom_cpufreq_hw_init(void)
 410 {
 411         return platform_driver_register(&qcom_cpufreq_hw_driver);
 412 }
 413 postcore_initcall(qcom_cpufreq_hw_init);
 414
 415 static void __exit qcom_cpufreq_hw_exit(void)
 416 {
 417         platform_driver_unregister(&qcom_cpufreq_hw_driver);
 418 }
 419 module_exit(qcom_cpufreq_hw_exit);
 420
 421 MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
 422 MODULE_LICENSE("GPL v2");