2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/debugfs.h>
30 #include <linux/acpi.h>
31 #include <linux/vmalloc.h>
32 #include <trace/events/power.h>
34 #include <asm/div64.h>
36 #include <asm/cpu_device_id.h>
37 #include <asm/cpufeature.h>
38 #include <asm/intel-family.h>
40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
42 #define ATOM_RATIOS 0x66a
43 #define ATOM_VIDS 0x66b
44 #define ATOM_TURBO_RATIOS 0x66c
45 #define ATOM_TURBO_VIDS 0x66d
48 #include <acpi/processor.h>
49 #include <acpi/cppc_acpi.h>
53 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
54 #define fp_toint(X) ((X) >> FRAC_BITS)
57 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
58 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
59 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
61 static inline int32_t mul_fp(int32_t x, int32_t y)
63 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
66 static inline int32_t div_fp(s64 x, s64 y)
68 return div64_s64((int64_t)x << FRAC_BITS, y);
71 static inline int ceiling_fp(int32_t x)
76 mask = (1 << FRAC_BITS) - 1;
82 static inline u64 mul_ext_fp(u64 x, u64 y)
84 return (x * y) >> EXT_FRAC_BITS;
87 static inline u64 div_ext_fp(u64 x, u64 y)
89 return div64_u64(x << EXT_FRAC_BITS, y);
93 * struct sample - Store performance sample
94 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
95 * performance during last sample period
96 * @busy_scaled: Scaled busy value which is used to calculate next
97 * P state. This can be different than core_avg_perf
98 * to account for cpu idle period
99 * @aperf: Difference of actual performance frequency clock count
100 * read from APERF MSR between last and current sample
101 * @mperf: Difference of maximum performance frequency clock count
102 * read from MPERF MSR between last and current sample
103 * @tsc: Difference of time stamp counter between last and
105 * @time: Current time from scheduler
107 * This structure is used in the cpudata structure to store performance sample
108 * data for choosing next P State.
111 int32_t core_avg_perf;
120 * struct pstate_data - Store P state data
121 * @current_pstate: Current requested P state
122 * @min_pstate: Min P state possible for this platform
123 * @max_pstate: Max P state possible for this platform
124 * @max_pstate_physical:This is physical Max P state for a processor
125 * This can be higher than the max_pstate which can
126 * be limited by platform thermal design power limits
127 * @scaling: Scaling factor to convert frequency to cpufreq
129 * @turbo_pstate: Max Turbo P state possible for this platform
130 * @max_freq: @max_pstate frequency in cpufreq units
131 * @turbo_freq: @turbo_pstate frequency in cpufreq units
133 * Stores the per cpu model P state limits and current P state.
139 int max_pstate_physical;
142 unsigned int max_freq;
143 unsigned int turbo_freq;
147 * struct vid_data - Stores voltage information data
148 * @min: VID data for this platform corresponding to
150 * @max: VID data corresponding to the highest P State.
151 * @turbo: VID data for turbo P state
152 * @ratio: Ratio of (vid max - vid min) /
153 * (max P state - Min P State)
155 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
156 * This data is used in Atom platforms, where in addition to target P state,
157 * the voltage data needs to be specified to select next P State.
167 * struct _pid - Stores PID data
168 * @setpoint: Target set point for busyness or performance
169 * @integral: Storage for accumulated error values
170 * @p_gain: PID proportional gain
171 * @i_gain: PID integral gain
172 * @d_gain: PID derivative gain
173 * @deadband: PID deadband
174 * @last_err: Last error storage for integral part of PID calculation
176 * Stores PID coefficients and last error for PID controller.
189 * struct perf_limits - Store user and policy limits
190 * @no_turbo: User requested turbo state from intel_pstate sysfs
191 * @turbo_disabled: Platform turbo status either from msr
192 * MSR_IA32_MISC_ENABLE or when maximum available pstate
193 * matches the maximum turbo pstate
194 * @max_perf_pct: Effective maximum performance limit in percentage, this
195 * is minimum of either limits enforced by cpufreq policy
196 * or limits from user set limits via intel_pstate sysfs
197 * @min_perf_pct: Effective minimum performance limit in percentage, this
198 * is maximum of either limits enforced by cpufreq policy
199 * or limits from user set limits via intel_pstate sysfs
200 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
201 * This value is used to limit max pstate
202 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
203 * This value is used to limit min pstate
204 * @max_policy_pct: The maximum performance in percentage enforced by
205 * cpufreq setpolicy interface
206 * @max_sysfs_pct: The maximum performance in percentage enforced by
207 * intel pstate sysfs interface, unused when per cpu
208 * controls are enforced
209 * @min_policy_pct: The minimum performance in percentage enforced by
210 * cpufreq setpolicy interface
211 * @min_sysfs_pct: The minimum performance in percentage enforced by
212 * intel pstate sysfs interface, unused when per cpu
213 * controls are enforced
215 * Storage for user and policy defined limits.
231 * struct cpudata - Per CPU instance data storage
232 * @cpu: CPU number for this instance data
233 * @policy: CPUFreq policy value
234 * @update_util: CPUFreq utility callback information
235 * @update_util_set: CPUFreq utility callback is set
236 * @iowait_boost: iowait-related boost fraction
237 * @last_update: Time of the last update.
238 * @pstate: Stores P state limits for this CPU
239 * @vid: Stores VID limits for this CPU
240 * @pid: Stores PID parameters for this CPU
241 * @last_sample_time: Last Sample time
242 * @prev_aperf: Last APERF value read from APERF MSR
243 * @prev_mperf: Last MPERF value read from MPERF MSR
244 * @prev_tsc: Last timestamp counter (TSC) value
245 * @prev_cummulative_iowait: IO Wait time difference from last and
247 * @sample: Storage for storing last Sample data
248 * @perf_limits: Pointer to perf_limit unique to this CPU
249 * Not all field in the structure are applicable
250 * when per cpu controls are enforced
251 * @acpi_perf_data: Stores ACPI perf information read from _PSS
252 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
253 * @epp_powersave: Last saved HWP energy performance preference
254 * (EPP) or energy performance bias (EPB),
255 * when policy switched to performance
256 * @epp_policy: Last saved policy used to set EPP/EPB
257 * @epp_default: Power on default HWP energy performance
259 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
262 * This structure stores per CPU instance data for all CPUs.
268 struct update_util_data update_util;
269 bool update_util_set;
271 struct pstate_data pstate;
276 u64 last_sample_time;
280 u64 prev_cummulative_iowait;
281 struct sample sample;
282 struct perf_limits *perf_limits;
284 struct acpi_processor_performance acpi_perf_data;
285 bool valid_pss_table;
287 unsigned int iowait_boost;
294 static struct cpudata **all_cpu_data;
297 * struct pstate_adjust_policy - Stores static PID configuration data
298 * @sample_rate_ms: PID calculation sample rate in ms
299 * @sample_rate_ns: Sample rate calculation in ns
300 * @deadband: PID deadband
301 * @setpoint: PID Setpoint
302 * @p_gain_pct: PID proportional gain
303 * @i_gain_pct: PID integral gain
304 * @d_gain_pct: PID derivative gain
306 * Stores per CPU model static PID configuration data.
308 struct pstate_adjust_policy {
319 * struct pstate_funcs - Per CPU model specific callbacks
320 * @get_max: Callback to get maximum non turbo effective P state
321 * @get_max_physical: Callback to get maximum non turbo physical P state
322 * @get_min: Callback to get minimum P state
323 * @get_turbo: Callback to get turbo P state
324 * @get_scaling: Callback to get frequency scaling factor
325 * @get_val: Callback to convert P state to actual MSR write value
326 * @get_vid: Callback to get VID data for Atom platforms
327 * @get_target_pstate: Callback to a function to calculate next P state to use
329 * Core and Atom CPU models have different way to get P State limits. This
330 * structure is used to store those callbacks.
332 struct pstate_funcs {
333 int (*get_max)(void);
334 int (*get_max_physical)(void);
335 int (*get_min)(void);
336 int (*get_turbo)(void);
337 int (*get_scaling)(void);
338 u64 (*get_val)(struct cpudata*, int pstate);
339 void (*get_vid)(struct cpudata *);
340 int32_t (*get_target_pstate)(struct cpudata *);
344 * struct cpu_defaults- Per CPU model default config data
345 * @pid_policy: PID config data
346 * @funcs: Callback function data
348 struct cpu_defaults {
349 struct pstate_adjust_policy pid_policy;
350 struct pstate_funcs funcs;
353 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
354 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
356 static struct pstate_adjust_policy pid_params __read_mostly;
357 static struct pstate_funcs pstate_funcs __read_mostly;
358 static int hwp_active __read_mostly;
359 static bool per_cpu_limits __read_mostly;
361 static bool driver_registered __read_mostly;
364 static bool acpi_ppc;
367 static struct perf_limits performance_limits;
368 static struct perf_limits powersave_limits;
369 static struct perf_limits *limits;
371 static void intel_pstate_init_limits(struct perf_limits *limits)
373 memset(limits, 0, sizeof(*limits));
374 limits->max_perf_pct = 100;
375 limits->max_perf = int_ext_tofp(1);
376 limits->max_policy_pct = 100;
377 limits->max_sysfs_pct = 100;
380 static void intel_pstate_set_performance_limits(struct perf_limits *limits)
382 intel_pstate_init_limits(limits);
383 limits->min_perf_pct = 100;
384 limits->min_perf = int_ext_tofp(1);
387 static DEFINE_MUTEX(intel_pstate_driver_lock);
388 static DEFINE_MUTEX(intel_pstate_limits_lock);
392 static bool intel_pstate_get_ppc_enable_status(void)
394 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
395 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
401 #ifdef CONFIG_ACPI_CPPC_LIB
403 /* The work item is needed to avoid CPU hotplug locking issues */
404 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
406 sched_set_itmt_support();
409 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
411 static void intel_pstate_set_itmt_prio(int cpu)
413 struct cppc_perf_caps cppc_perf;
414 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
417 ret = cppc_get_perf_caps(cpu, &cppc_perf);
422 * The priorities can be set regardless of whether or not
423 * sched_set_itmt_support(true) has been called and it is valid to
424 * update them at any time after it has been called.
426 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
428 if (max_highest_perf <= min_highest_perf) {
429 if (cppc_perf.highest_perf > max_highest_perf)
430 max_highest_perf = cppc_perf.highest_perf;
432 if (cppc_perf.highest_perf < min_highest_perf)
433 min_highest_perf = cppc_perf.highest_perf;
435 if (max_highest_perf > min_highest_perf) {
437 * This code can be run during CPU online under the
438 * CPU hotplug locks, so sched_set_itmt_support()
439 * cannot be called from here. Queue up a work item
442 schedule_work(&sched_itmt_work);
447 static void intel_pstate_set_itmt_prio(int cpu)
452 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
459 intel_pstate_set_itmt_prio(policy->cpu);
463 if (!intel_pstate_get_ppc_enable_status())
466 cpu = all_cpu_data[policy->cpu];
468 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
474 * Check if the control value in _PSS is for PERF_CTL MSR, which should
475 * guarantee that the states returned by it map to the states in our
478 if (cpu->acpi_perf_data.control_register.space_id !=
479 ACPI_ADR_SPACE_FIXED_HARDWARE)
483 * If there is only one entry _PSS, simply ignore _PSS and continue as
484 * usual without taking _PSS into account
486 if (cpu->acpi_perf_data.state_count < 2)
489 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
490 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
491 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
492 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
493 (u32) cpu->acpi_perf_data.states[i].core_frequency,
494 (u32) cpu->acpi_perf_data.states[i].power,
495 (u32) cpu->acpi_perf_data.states[i].control);
499 * The _PSS table doesn't contain whole turbo frequency range.
500 * This just contains +1 MHZ above the max non turbo frequency,
501 * with control value corresponding to max turbo ratio. But
502 * when cpufreq set policy is called, it will call with this
503 * max frequency, which will cause a reduced performance as
504 * this driver uses real max turbo frequency as the max
505 * frequency. So correct this frequency in _PSS table to
506 * correct max turbo frequency based on the turbo state.
507 * Also need to convert to MHz as _PSS freq is in MHz.
509 if (!limits->turbo_disabled)
510 cpu->acpi_perf_data.states[0].core_frequency =
511 policy->cpuinfo.max_freq / 1000;
512 cpu->valid_pss_table = true;
513 pr_debug("_PPC limits will be enforced\n");
518 cpu->valid_pss_table = false;
519 acpi_processor_unregister_performance(policy->cpu);
522 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
526 cpu = all_cpu_data[policy->cpu];
527 if (!cpu->valid_pss_table)
530 acpi_processor_unregister_performance(policy->cpu);
533 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
537 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
542 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
543 int deadband, int integral) {
544 pid->setpoint = int_tofp(setpoint);
545 pid->deadband = int_tofp(deadband);
546 pid->integral = int_tofp(integral);
547 pid->last_err = int_tofp(setpoint) - int_tofp(busy);
550 static inline void pid_p_gain_set(struct _pid *pid, int percent)
552 pid->p_gain = div_fp(percent, 100);
555 static inline void pid_i_gain_set(struct _pid *pid, int percent)
557 pid->i_gain = div_fp(percent, 100);
560 static inline void pid_d_gain_set(struct _pid *pid, int percent)
562 pid->d_gain = div_fp(percent, 100);
565 static signed int pid_calc(struct _pid *pid, int32_t busy)
568 int32_t pterm, dterm, fp_error;
569 int32_t integral_limit;
571 fp_error = pid->setpoint - busy;
573 if (abs(fp_error) <= pid->deadband)
576 pterm = mul_fp(pid->p_gain, fp_error);
578 pid->integral += fp_error;
581 * We limit the integral here so that it will never
582 * get higher than 30. This prevents it from becoming
583 * too large an input over long periods of time and allows
584 * it to get factored out sooner.
586 * The value of 30 was chosen through experimentation.
588 integral_limit = int_tofp(30);
589 if (pid->integral > integral_limit)
590 pid->integral = integral_limit;
591 if (pid->integral < -integral_limit)
592 pid->integral = -integral_limit;
594 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
595 pid->last_err = fp_error;
597 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
598 result = result + (1 << (FRAC_BITS-1));
599 return (signed int)fp_toint(result);
602 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
604 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
605 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
606 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
608 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
611 static inline void intel_pstate_reset_all_pid(void)
615 for_each_online_cpu(cpu) {
616 if (all_cpu_data[cpu])
617 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
621 static inline void update_turbo_state(void)
626 cpu = all_cpu_data[0];
627 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
628 limits->turbo_disabled =
629 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
630 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
633 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
638 if (!static_cpu_has(X86_FEATURE_EPB))
641 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
645 return (s16)(epb & 0x0f);
648 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
652 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
654 * When hwp_req_data is 0, means that caller didn't read
655 * MSR_HWP_REQUEST, so need to read and get EPP.
658 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
663 epp = (hwp_req_data >> 24) & 0xff;
665 /* When there is no EPP present, HWP uses EPB settings */
666 epp = intel_pstate_get_epb(cpu_data);
672 static int intel_pstate_set_epb(int cpu, s16 pref)
677 if (!static_cpu_has(X86_FEATURE_EPB))
680 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
684 epb = (epb & ~0x0f) | pref;
685 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
691 * EPP/EPB display strings corresponding to EPP index in the
692 * energy_perf_strings[]
694 *-------------------------------------
697 * 2 balance_performance
701 static const char * const energy_perf_strings[] = {
704 "balance_performance",
710 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
715 epp = intel_pstate_get_epp(cpu_data, 0);
719 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
722 * 0x00-0x3F : Performance
723 * 0x40-0x7F : Balance performance
724 * 0x80-0xBF : Balance power
726 * The EPP is a 8 bit value, but our ranges restrict the
727 * value which can be set. Here only using top two bits
730 index = (epp >> 6) + 1;
731 } else if (static_cpu_has(X86_FEATURE_EPB)) {
734 * 0x00-0x03 : Performance
735 * 0x04-0x07 : Balance performance
736 * 0x08-0x0B : Balance power
738 * The EPB is a 4 bit value, but our ranges restrict the
739 * value which can be set. Here only using top two bits
742 index = (epp >> 2) + 1;
748 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
755 epp = cpu_data->epp_default;
757 mutex_lock(&intel_pstate_limits_lock);
759 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
762 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
766 value &= ~GENMASK_ULL(31, 24);
769 * If epp is not default, convert from index into
770 * energy_perf_strings to epp value, by shifting 6
771 * bits left to use only top two bits in epp.
772 * The resultant epp need to shifted by 24 bits to
773 * epp position in MSR_HWP_REQUEST.
776 epp = (pref_index - 1) << 6;
778 value |= (u64)epp << 24;
779 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
782 epp = (pref_index - 1) << 2;
783 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
786 mutex_unlock(&intel_pstate_limits_lock);
791 static ssize_t show_energy_performance_available_preferences(
792 struct cpufreq_policy *policy, char *buf)
797 while (energy_perf_strings[i] != NULL)
798 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
800 ret += sprintf(&buf[ret], "\n");
805 cpufreq_freq_attr_ro(energy_performance_available_preferences);
807 static ssize_t store_energy_performance_preference(
808 struct cpufreq_policy *policy, const char *buf, size_t count)
810 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
811 char str_preference[21];
814 ret = sscanf(buf, "%20s", str_preference);
818 while (energy_perf_strings[i] != NULL) {
819 if (!strcmp(str_preference, energy_perf_strings[i])) {
820 intel_pstate_set_energy_pref_index(cpu_data, i);
829 static ssize_t show_energy_performance_preference(
830 struct cpufreq_policy *policy, char *buf)
832 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
835 preference = intel_pstate_get_energy_pref_index(cpu_data);
839 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
842 cpufreq_freq_attr_rw(energy_performance_preference);
844 static struct freq_attr *hwp_cpufreq_attrs[] = {
845 &energy_performance_preference,
846 &energy_performance_available_preferences,
850 static void intel_pstate_hwp_set(struct cpufreq_policy *policy)
852 int min, hw_min, max, hw_max, cpu, range, adj_range;
853 struct perf_limits *perf_limits = limits;
856 for_each_cpu(cpu, policy->cpus) {
857 int max_perf_pct, min_perf_pct;
858 struct cpudata *cpu_data = all_cpu_data[cpu];
862 perf_limits = all_cpu_data[cpu]->perf_limits;
864 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
865 hw_min = HWP_LOWEST_PERF(cap);
866 if (limits->no_turbo)
867 hw_max = HWP_GUARANTEED_PERF(cap);
869 hw_max = HWP_HIGHEST_PERF(cap);
870 range = hw_max - hw_min;
872 max_perf_pct = perf_limits->max_perf_pct;
873 min_perf_pct = perf_limits->min_perf_pct;
875 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
876 adj_range = min_perf_pct * range / 100;
877 min = hw_min + adj_range;
878 value &= ~HWP_MIN_PERF(~0L);
879 value |= HWP_MIN_PERF(min);
881 adj_range = max_perf_pct * range / 100;
882 max = hw_min + adj_range;
884 value &= ~HWP_MAX_PERF(~0L);
885 value |= HWP_MAX_PERF(max);
887 if (cpu_data->epp_policy == cpu_data->policy)
890 cpu_data->epp_policy = cpu_data->policy;
892 if (cpu_data->epp_saved >= 0) {
893 epp = cpu_data->epp_saved;
894 cpu_data->epp_saved = -EINVAL;
898 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
899 epp = intel_pstate_get_epp(cpu_data, value);
900 cpu_data->epp_powersave = epp;
901 /* If EPP read was failed, then don't try to write */
908 /* skip setting EPP, when saved value is invalid */
909 if (cpu_data->epp_powersave < 0)
913 * No need to restore EPP when it is not zero. This
915 * - Policy is not changed
916 * - user has manually changed
917 * - Error reading EPB
919 epp = intel_pstate_get_epp(cpu_data, value);
923 epp = cpu_data->epp_powersave;
926 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
927 value &= ~GENMASK_ULL(31, 24);
928 value |= (u64)epp << 24;
930 intel_pstate_set_epb(cpu, epp);
933 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
937 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy)
940 intel_pstate_hwp_set(policy);
945 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
947 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
952 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
957 static int intel_pstate_resume(struct cpufreq_policy *policy)
964 mutex_lock(&intel_pstate_limits_lock);
966 all_cpu_data[policy->cpu]->epp_policy = 0;
968 ret = intel_pstate_hwp_set_policy(policy);
970 mutex_unlock(&intel_pstate_limits_lock);
975 static void intel_pstate_update_policies(void)
976 __releases(&intel_pstate_limits_lock)
977 __acquires(&intel_pstate_limits_lock)
979 struct perf_limits *saved_limits = limits;
982 mutex_unlock(&intel_pstate_limits_lock);
984 for_each_possible_cpu(cpu)
985 cpufreq_update_policy(cpu);
987 mutex_lock(&intel_pstate_limits_lock);
989 limits = saved_limits;
992 /************************** debugfs begin ************************/
993 static int pid_param_set(void *data, u64 val)
996 intel_pstate_reset_all_pid();
1000 static int pid_param_get(void *data, u64 *val)
1002 *val = *(u32 *)data;
1005 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
1007 static struct dentry *debugfs_parent;
1012 struct dentry *dentry;
1015 static struct pid_param pid_files[] = {
1016 {"sample_rate_ms", &pid_params.sample_rate_ms, },
1017 {"d_gain_pct", &pid_params.d_gain_pct, },
1018 {"i_gain_pct", &pid_params.i_gain_pct, },
1019 {"deadband", &pid_params.deadband, },
1020 {"setpoint", &pid_params.setpoint, },
1021 {"p_gain_pct", &pid_params.p_gain_pct, },
1025 static void intel_pstate_debug_expose_params(void)
1029 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
1030 if (IS_ERR_OR_NULL(debugfs_parent))
1033 for (i = 0; pid_files[i].name; i++) {
1034 struct dentry *dentry;
1036 dentry = debugfs_create_file(pid_files[i].name, 0660,
1037 debugfs_parent, pid_files[i].value,
1039 if (!IS_ERR(dentry))
1040 pid_files[i].dentry = dentry;
1044 static void intel_pstate_debug_hide_params(void)
1048 if (IS_ERR_OR_NULL(debugfs_parent))
1051 for (i = 0; pid_files[i].name; i++) {
1052 debugfs_remove(pid_files[i].dentry);
1053 pid_files[i].dentry = NULL;
1056 debugfs_remove(debugfs_parent);
1057 debugfs_parent = NULL;
1060 /************************** debugfs end ************************/
1062 /************************** sysfs begin ************************/
1063 #define show_one(file_name, object) \
1064 static ssize_t show_##file_name \
1065 (struct kobject *kobj, struct attribute *attr, char *buf) \
1067 return sprintf(buf, "%u\n", limits->object); \
1070 static ssize_t intel_pstate_show_status(char *buf);
1071 static int intel_pstate_update_status(const char *buf, size_t size);
1073 static ssize_t show_status(struct kobject *kobj,
1074 struct attribute *attr, char *buf)
1078 mutex_lock(&intel_pstate_driver_lock);
1079 ret = intel_pstate_show_status(buf);
1080 mutex_unlock(&intel_pstate_driver_lock);
1085 static ssize_t store_status(struct kobject *a, struct attribute *b,
1086 const char *buf, size_t count)
1088 char *p = memchr(buf, '\n', count);
1091 mutex_lock(&intel_pstate_driver_lock);
1092 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1093 mutex_unlock(&intel_pstate_driver_lock);
1095 return ret < 0 ? ret : count;
1098 static ssize_t show_turbo_pct(struct kobject *kobj,
1099 struct attribute *attr, char *buf)
1101 struct cpudata *cpu;
1102 int total, no_turbo, turbo_pct;
1105 mutex_lock(&intel_pstate_driver_lock);
1107 if (!driver_registered) {
1108 mutex_unlock(&intel_pstate_driver_lock);
1112 cpu = all_cpu_data[0];
1114 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1115 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1116 turbo_fp = div_fp(no_turbo, total);
1117 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1119 mutex_unlock(&intel_pstate_driver_lock);
1121 return sprintf(buf, "%u\n", turbo_pct);
1124 static ssize_t show_num_pstates(struct kobject *kobj,
1125 struct attribute *attr, char *buf)
1127 struct cpudata *cpu;
1130 mutex_lock(&intel_pstate_driver_lock);
1132 if (!driver_registered) {
1133 mutex_unlock(&intel_pstate_driver_lock);
1137 cpu = all_cpu_data[0];
1138 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1140 mutex_unlock(&intel_pstate_driver_lock);
1142 return sprintf(buf, "%u\n", total);
1145 static ssize_t show_no_turbo(struct kobject *kobj,
1146 struct attribute *attr, char *buf)
1150 mutex_lock(&intel_pstate_driver_lock);
1152 if (!driver_registered) {
1153 mutex_unlock(&intel_pstate_driver_lock);
1157 update_turbo_state();
1158 if (limits->turbo_disabled)
1159 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
1161 ret = sprintf(buf, "%u\n", limits->no_turbo);
1163 mutex_unlock(&intel_pstate_driver_lock);
1168 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1169 const char *buf, size_t count)
1174 ret = sscanf(buf, "%u", &input);
1178 mutex_lock(&intel_pstate_driver_lock);
1180 if (!driver_registered) {
1181 mutex_unlock(&intel_pstate_driver_lock);
1185 mutex_lock(&intel_pstate_limits_lock);
1187 update_turbo_state();
1188 if (limits->turbo_disabled) {
1189 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1190 mutex_unlock(&intel_pstate_limits_lock);
1191 mutex_unlock(&intel_pstate_driver_lock);
1195 limits->no_turbo = clamp_t(int, input, 0, 1);
1197 intel_pstate_update_policies();
1199 mutex_unlock(&intel_pstate_limits_lock);
1201 mutex_unlock(&intel_pstate_driver_lock);
1206 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1207 const char *buf, size_t count)
1212 ret = sscanf(buf, "%u", &input);
1216 mutex_lock(&intel_pstate_driver_lock);
1218 if (!driver_registered) {
1219 mutex_unlock(&intel_pstate_driver_lock);
1223 mutex_lock(&intel_pstate_limits_lock);
1225 limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
1226 limits->max_perf_pct = min(limits->max_policy_pct,
1227 limits->max_sysfs_pct);
1228 limits->max_perf_pct = max(limits->min_policy_pct,
1229 limits->max_perf_pct);
1230 limits->max_perf_pct = max(limits->min_perf_pct,
1231 limits->max_perf_pct);
1232 limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
1234 intel_pstate_update_policies();
1236 mutex_unlock(&intel_pstate_limits_lock);
1238 mutex_unlock(&intel_pstate_driver_lock);
1243 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1244 const char *buf, size_t count)
1249 ret = sscanf(buf, "%u", &input);
1253 mutex_lock(&intel_pstate_driver_lock);
1255 if (!driver_registered) {
1256 mutex_unlock(&intel_pstate_driver_lock);
1260 mutex_lock(&intel_pstate_limits_lock);
1262 limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
1263 limits->min_perf_pct = max(limits->min_policy_pct,
1264 limits->min_sysfs_pct);
1265 limits->min_perf_pct = min(limits->max_policy_pct,
1266 limits->min_perf_pct);
1267 limits->min_perf_pct = min(limits->max_perf_pct,
1268 limits->min_perf_pct);
1269 limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
1271 intel_pstate_update_policies();
1273 mutex_unlock(&intel_pstate_limits_lock);
1275 mutex_unlock(&intel_pstate_driver_lock);
1280 show_one(max_perf_pct, max_perf_pct);
1281 show_one(min_perf_pct, min_perf_pct);
1283 define_one_global_rw(status);
1284 define_one_global_rw(no_turbo);
1285 define_one_global_rw(max_perf_pct);
1286 define_one_global_rw(min_perf_pct);
1287 define_one_global_ro(turbo_pct);
1288 define_one_global_ro(num_pstates);
1290 static struct attribute *intel_pstate_attributes[] = {
1298 static struct attribute_group intel_pstate_attr_group = {
1299 .attrs = intel_pstate_attributes,
1302 static void __init intel_pstate_sysfs_expose_params(void)
1304 struct kobject *intel_pstate_kobject;
1307 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1308 &cpu_subsys.dev_root->kobj);
1309 if (WARN_ON(!intel_pstate_kobject))
1312 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1317 * If per cpu limits are enforced there are no global limits, so
1318 * return without creating max/min_perf_pct attributes
1323 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1326 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1330 /************************** sysfs end ************************/
1332 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1334 /* First disable HWP notification interrupt as we don't process them */
1335 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1336 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1338 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1339 cpudata->epp_policy = 0;
1340 if (cpudata->epp_default == -EINVAL)
1341 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1344 #define MSR_IA32_POWER_CTL_BIT_EE 19
1346 /* Disable energy efficiency optimization */
1347 static void intel_pstate_disable_ee(int cpu)
1352 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1356 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1357 pr_info("Disabling energy efficiency optimization\n");
1358 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1359 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1363 static int atom_get_min_pstate(void)
1367 rdmsrl(ATOM_RATIOS, value);
1368 return (value >> 8) & 0x7F;
1371 static int atom_get_max_pstate(void)
1375 rdmsrl(ATOM_RATIOS, value);
1376 return (value >> 16) & 0x7F;
1379 static int atom_get_turbo_pstate(void)
1383 rdmsrl(ATOM_TURBO_RATIOS, value);
1384 return value & 0x7F;
1387 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1393 val = (u64)pstate << 8;
1394 if (limits->no_turbo && !limits->turbo_disabled)
1395 val |= (u64)1 << 32;
1397 vid_fp = cpudata->vid.min + mul_fp(
1398 int_tofp(pstate - cpudata->pstate.min_pstate),
1399 cpudata->vid.ratio);
1401 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1402 vid = ceiling_fp(vid_fp);
1404 if (pstate > cpudata->pstate.max_pstate)
1405 vid = cpudata->vid.turbo;
1410 static int silvermont_get_scaling(void)
1414 /* Defined in Table 35-6 from SDM (Sept 2015) */
1415 static int silvermont_freq_table[] = {
1416 83300, 100000, 133300, 116700, 80000};
1418 rdmsrl(MSR_FSB_FREQ, value);
1422 return silvermont_freq_table[i];
1425 static int airmont_get_scaling(void)
1429 /* Defined in Table 35-10 from SDM (Sept 2015) */
1430 static int airmont_freq_table[] = {
1431 83300, 100000, 133300, 116700, 80000,
1432 93300, 90000, 88900, 87500};
1434 rdmsrl(MSR_FSB_FREQ, value);
1438 return airmont_freq_table[i];
1441 static void atom_get_vid(struct cpudata *cpudata)
1445 rdmsrl(ATOM_VIDS, value);
1446 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1447 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1448 cpudata->vid.ratio = div_fp(
1449 cpudata->vid.max - cpudata->vid.min,
1450 int_tofp(cpudata->pstate.max_pstate -
1451 cpudata->pstate.min_pstate));
1453 rdmsrl(ATOM_TURBO_VIDS, value);
1454 cpudata->vid.turbo = value & 0x7f;
1457 static int core_get_min_pstate(void)
1461 rdmsrl(MSR_PLATFORM_INFO, value);
1462 return (value >> 40) & 0xFF;
1465 static int core_get_max_pstate_physical(void)
1469 rdmsrl(MSR_PLATFORM_INFO, value);
1470 return (value >> 8) & 0xFF;
1473 static int core_get_tdp_ratio(u64 plat_info)
1475 /* Check how many TDP levels present */
1476 if (plat_info & 0x600000000) {
1482 /* Get the TDP level (0, 1, 2) to get ratios */
1483 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1487 /* TDP MSR are continuous starting at 0x648 */
1488 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1489 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1493 /* For level 1 and 2, bits[23:16] contain the ratio */
1494 if (tdp_ctrl & 0x03)
1497 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1498 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1500 return (int)tdp_ratio;
1506 static int core_get_max_pstate(void)
1514 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1515 max_pstate = (plat_info >> 8) & 0xFF;
1517 tdp_ratio = core_get_tdp_ratio(plat_info);
1522 /* Turbo activation ratio is not used on HWP platforms */
1526 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1530 /* Do some sanity checking for safety */
1531 tar_levels = tar & 0xff;
1532 if (tdp_ratio - 1 == tar_levels) {
1533 max_pstate = tar_levels;
1534 pr_debug("max_pstate=TAC %x\n", max_pstate);
1541 static int core_get_turbo_pstate(void)
1546 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1547 nont = core_get_max_pstate();
1548 ret = (value) & 255;
1554 static inline int core_get_scaling(void)
1559 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1563 val = (u64)pstate << 8;
1564 if (limits->no_turbo && !limits->turbo_disabled)
1565 val |= (u64)1 << 32;
1570 static int knl_get_turbo_pstate(void)
1575 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1576 nont = core_get_max_pstate();
1577 ret = (((value) >> 8) & 0xFF);
1583 static struct cpu_defaults core_params = {
1585 .sample_rate_ms = 10,
1593 .get_max = core_get_max_pstate,
1594 .get_max_physical = core_get_max_pstate_physical,
1595 .get_min = core_get_min_pstate,
1596 .get_turbo = core_get_turbo_pstate,
1597 .get_scaling = core_get_scaling,
1598 .get_val = core_get_val,
1599 .get_target_pstate = get_target_pstate_use_performance,
1603 static const struct cpu_defaults silvermont_params = {
1605 .sample_rate_ms = 10,
1613 .get_max = atom_get_max_pstate,
1614 .get_max_physical = atom_get_max_pstate,
1615 .get_min = atom_get_min_pstate,
1616 .get_turbo = atom_get_turbo_pstate,
1617 .get_val = atom_get_val,
1618 .get_scaling = silvermont_get_scaling,
1619 .get_vid = atom_get_vid,
1620 .get_target_pstate = get_target_pstate_use_cpu_load,
1624 static const struct cpu_defaults airmont_params = {
1626 .sample_rate_ms = 10,
1634 .get_max = atom_get_max_pstate,
1635 .get_max_physical = atom_get_max_pstate,
1636 .get_min = atom_get_min_pstate,
1637 .get_turbo = atom_get_turbo_pstate,
1638 .get_val = atom_get_val,
1639 .get_scaling = airmont_get_scaling,
1640 .get_vid = atom_get_vid,
1641 .get_target_pstate = get_target_pstate_use_cpu_load,
1645 static const struct cpu_defaults knl_params = {
1647 .sample_rate_ms = 10,
1655 .get_max = core_get_max_pstate,
1656 .get_max_physical = core_get_max_pstate_physical,
1657 .get_min = core_get_min_pstate,
1658 .get_turbo = knl_get_turbo_pstate,
1659 .get_scaling = core_get_scaling,
1660 .get_val = core_get_val,
1661 .get_target_pstate = get_target_pstate_use_performance,
1665 static const struct cpu_defaults bxt_params = {
1667 .sample_rate_ms = 10,
1675 .get_max = core_get_max_pstate,
1676 .get_max_physical = core_get_max_pstate_physical,
1677 .get_min = core_get_min_pstate,
1678 .get_turbo = core_get_turbo_pstate,
1679 .get_scaling = core_get_scaling,
1680 .get_val = core_get_val,
1681 .get_target_pstate = get_target_pstate_use_cpu_load,
1685 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1687 int max_perf = cpu->pstate.turbo_pstate;
1690 struct perf_limits *perf_limits = limits;
1692 if (limits->no_turbo || limits->turbo_disabled)
1693 max_perf = cpu->pstate.max_pstate;
1696 perf_limits = cpu->perf_limits;
1699 * performance can be limited by user through sysfs, by cpufreq
1700 * policy, or by cpu specific default values determined through
1703 max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf);
1704 *max = clamp_t(int, max_perf_adj,
1705 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
1707 min_perf = fp_ext_toint(max_perf * perf_limits->min_perf);
1708 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
1711 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1713 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1714 cpu->pstate.current_pstate = pstate;
1716 * Generally, there is no guarantee that this code will always run on
1717 * the CPU being updated, so force the register update to run on the
1720 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1721 pstate_funcs.get_val(cpu, pstate));
1724 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1726 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1729 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1731 int min_pstate, max_pstate;
1733 update_turbo_state();
1734 intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1735 intel_pstate_set_pstate(cpu, max_pstate);
1738 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1740 cpu->pstate.min_pstate = pstate_funcs.get_min();
1741 cpu->pstate.max_pstate = pstate_funcs.get_max();
1742 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1743 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1744 cpu->pstate.scaling = pstate_funcs.get_scaling();
1745 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1746 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1748 if (pstate_funcs.get_vid)
1749 pstate_funcs.get_vid(cpu);
1751 intel_pstate_set_min_pstate(cpu);
1754 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1756 struct sample *sample = &cpu->sample;
1758 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1761 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1764 unsigned long flags;
1767 local_irq_save(flags);
1768 rdmsrl(MSR_IA32_APERF, aperf);
1769 rdmsrl(MSR_IA32_MPERF, mperf);
1771 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1772 local_irq_restore(flags);
1775 local_irq_restore(flags);
1777 cpu->last_sample_time = cpu->sample.time;
1778 cpu->sample.time = time;
1779 cpu->sample.aperf = aperf;
1780 cpu->sample.mperf = mperf;
1781 cpu->sample.tsc = tsc;
1782 cpu->sample.aperf -= cpu->prev_aperf;
1783 cpu->sample.mperf -= cpu->prev_mperf;
1784 cpu->sample.tsc -= cpu->prev_tsc;
1786 cpu->prev_aperf = aperf;
1787 cpu->prev_mperf = mperf;
1788 cpu->prev_tsc = tsc;
1790 * First time this function is invoked in a given cycle, all of the
1791 * previous sample data fields are equal to zero or stale and they must
1792 * be populated with meaningful numbers for things to work, so assume
1793 * that sample.time will always be reset before setting the utilization
1794 * update hook and make the caller skip the sample then.
1796 return !!cpu->last_sample_time;
1799 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1801 return mul_ext_fp(cpu->sample.core_avg_perf,
1802 cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1805 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1807 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1808 cpu->sample.core_avg_perf);
1811 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1813 struct sample *sample = &cpu->sample;
1814 int32_t busy_frac, boost;
1815 int target, avg_pstate;
1817 busy_frac = div_fp(sample->mperf, sample->tsc);
1819 boost = cpu->iowait_boost;
1820 cpu->iowait_boost >>= 1;
1822 if (busy_frac < boost)
1825 sample->busy_scaled = busy_frac * 100;
1827 target = limits->no_turbo || limits->turbo_disabled ?
1828 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1829 target += target >> 2;
1830 target = mul_fp(target, busy_frac);
1831 if (target < cpu->pstate.min_pstate)
1832 target = cpu->pstate.min_pstate;
1835 * If the average P-state during the previous cycle was higher than the
1836 * current target, add 50% of the difference to the target to reduce
1837 * possible performance oscillations and offset possible performance
1838 * loss related to moving the workload from one CPU to another within
1841 avg_pstate = get_avg_pstate(cpu);
1842 if (avg_pstate > target)
1843 target += (avg_pstate - target) >> 1;
1848 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1850 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1854 * perf_scaled is the ratio of the average P-state during the last
1855 * sampling period to the P-state requested last time (in percent).
1857 * That measures the system's response to the previous P-state
1860 max_pstate = cpu->pstate.max_pstate_physical;
1861 current_pstate = cpu->pstate.current_pstate;
1862 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1863 div_fp(100 * max_pstate, current_pstate));
1866 * Since our utilization update callback will not run unless we are
1867 * in C0, check if the actual elapsed time is significantly greater (3x)
1868 * than our sample interval. If it is, then we were idle for a long
1869 * enough period of time to adjust our performance metric.
1871 duration_ns = cpu->sample.time - cpu->last_sample_time;
1872 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1873 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1874 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1876 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1877 if (sample_ratio < int_tofp(1))
1881 cpu->sample.busy_scaled = perf_scaled;
1882 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1885 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1887 int max_perf, min_perf;
1889 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1890 pstate = clamp_t(int, pstate, min_perf, max_perf);
1894 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1896 if (pstate == cpu->pstate.current_pstate)
1899 cpu->pstate.current_pstate = pstate;
1900 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1903 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1905 int from, target_pstate;
1906 struct sample *sample;
1908 from = cpu->pstate.current_pstate;
1910 target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1911 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
1913 update_turbo_state();
1915 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1916 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1917 intel_pstate_update_pstate(cpu, target_pstate);
1919 sample = &cpu->sample;
1920 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1921 fp_toint(sample->busy_scaled),
1923 cpu->pstate.current_pstate,
1927 get_avg_frequency(cpu),
1928 fp_toint(cpu->iowait_boost * 100));
1931 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1934 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1937 if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
1938 if (flags & SCHED_CPUFREQ_IOWAIT) {
1939 cpu->iowait_boost = int_tofp(1);
1940 } else if (cpu->iowait_boost) {
1941 /* Clear iowait_boost if the CPU may have been idle. */
1942 delta_ns = time - cpu->last_update;
1943 if (delta_ns > TICK_NSEC)
1944 cpu->iowait_boost = 0;
1946 cpu->last_update = time;
1949 delta_ns = time - cpu->sample.time;
1950 if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1951 bool sample_taken = intel_pstate_sample(cpu, time);
1954 intel_pstate_calc_avg_perf(cpu);
1956 intel_pstate_adjust_busy_pstate(cpu);
1961 #define ICPU(model, policy) \
1962 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1963 (unsigned long)&policy }
1965 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1966 ICPU(INTEL_FAM6_SANDYBRIDGE, core_params),
1967 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params),
1968 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params),
1969 ICPU(INTEL_FAM6_IVYBRIDGE, core_params),
1970 ICPU(INTEL_FAM6_HASWELL_CORE, core_params),
1971 ICPU(INTEL_FAM6_BROADWELL_CORE, core_params),
1972 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params),
1973 ICPU(INTEL_FAM6_HASWELL_X, core_params),
1974 ICPU(INTEL_FAM6_HASWELL_ULT, core_params),
1975 ICPU(INTEL_FAM6_HASWELL_GT3E, core_params),
1976 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params),
1977 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params),
1978 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params),
1979 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1980 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params),
1981 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1982 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params),
1983 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_params),
1984 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params),
1987 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1989 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1990 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1991 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1992 ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
1996 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1997 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_params),
2001 static int intel_pstate_init_cpu(unsigned int cpunum)
2003 struct cpudata *cpu;
2005 cpu = all_cpu_data[cpunum];
2008 unsigned int size = sizeof(struct cpudata);
2011 size += sizeof(struct perf_limits);
2013 cpu = kzalloc(size, GFP_KERNEL);
2017 all_cpu_data[cpunum] = cpu;
2019 cpu->perf_limits = (struct perf_limits *)(cpu + 1);
2021 cpu->epp_default = -EINVAL;
2022 cpu->epp_powersave = -EINVAL;
2023 cpu->epp_saved = -EINVAL;
2026 cpu = all_cpu_data[cpunum];
2031 const struct x86_cpu_id *id;
2033 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
2035 intel_pstate_disable_ee(cpunum);
2037 intel_pstate_hwp_enable(cpu);
2038 pid_params.sample_rate_ms = 50;
2039 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
2042 intel_pstate_get_cpu_pstates(cpu);
2044 intel_pstate_busy_pid_reset(cpu);
2046 pr_debug("controlling: cpu %d\n", cpunum);
2051 static unsigned int intel_pstate_get(unsigned int cpu_num)
2053 struct cpudata *cpu = all_cpu_data[cpu_num];
2055 return cpu ? get_avg_frequency(cpu) : 0;
2058 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2060 struct cpudata *cpu = all_cpu_data[cpu_num];
2062 if (cpu->update_util_set)
2065 /* Prevent intel_pstate_update_util() from using stale data. */
2066 cpu->sample.time = 0;
2067 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2068 intel_pstate_update_util);
2069 cpu->update_util_set = true;
2072 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2074 struct cpudata *cpu_data = all_cpu_data[cpu];
2076 if (!cpu_data->update_util_set)
2079 cpufreq_remove_update_util_hook(cpu);
2080 cpu_data->update_util_set = false;
2081 synchronize_sched();
2084 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
2085 struct perf_limits *limits)
2088 limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
2089 policy->cpuinfo.max_freq);
2090 limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100);
2091 if (policy->max == policy->min) {
2092 limits->min_policy_pct = limits->max_policy_pct;
2094 limits->min_policy_pct = DIV_ROUND_UP(policy->min * 100,
2095 policy->cpuinfo.max_freq);
2096 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct,
2100 /* Normalize user input to [min_policy_pct, max_policy_pct] */
2101 limits->min_perf_pct = max(limits->min_policy_pct,
2102 limits->min_sysfs_pct);
2103 limits->min_perf_pct = min(limits->max_policy_pct,
2104 limits->min_perf_pct);
2105 limits->max_perf_pct = min(limits->max_policy_pct,
2106 limits->max_sysfs_pct);
2107 limits->max_perf_pct = max(limits->min_policy_pct,
2108 limits->max_perf_pct);
2110 /* Make sure min_perf_pct <= max_perf_pct */
2111 limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
2113 limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
2114 limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
2115 limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS);
2116 limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS);
2118 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
2119 limits->max_perf_pct, limits->min_perf_pct);
2122 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2124 struct cpudata *cpu;
2125 struct perf_limits *perf_limits = NULL;
2127 if (!policy->cpuinfo.max_freq)
2130 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2131 policy->cpuinfo.max_freq, policy->max);
2133 cpu = all_cpu_data[policy->cpu];
2134 cpu->policy = policy->policy;
2136 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2137 policy->max < policy->cpuinfo.max_freq &&
2138 policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
2139 pr_debug("policy->max > max non turbo frequency\n");
2140 policy->max = policy->cpuinfo.max_freq;
2144 perf_limits = cpu->perf_limits;
2146 mutex_lock(&intel_pstate_limits_lock);
2148 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
2150 limits = &performance_limits;
2151 perf_limits = limits;
2153 if (policy->max >= policy->cpuinfo.max_freq &&
2154 !limits->no_turbo) {
2155 pr_debug("set performance\n");
2156 intel_pstate_set_performance_limits(perf_limits);
2160 pr_debug("set powersave\n");
2162 limits = &powersave_limits;
2163 perf_limits = limits;
2168 intel_pstate_update_perf_limits(policy, perf_limits);
2170 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2172 * NOHZ_FULL CPUs need this as the governor callback may not
2173 * be invoked on them.
2175 intel_pstate_clear_update_util_hook(policy->cpu);
2176 intel_pstate_max_within_limits(cpu);
2179 intel_pstate_set_update_util_hook(policy->cpu);
2181 intel_pstate_hwp_set_policy(policy);
2183 mutex_unlock(&intel_pstate_limits_lock);
2188 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2190 struct cpudata *cpu = all_cpu_data[policy->cpu];
2191 struct perf_limits *perf_limits;
2193 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE)
2194 perf_limits = &performance_limits;
2196 perf_limits = &powersave_limits;
2198 update_turbo_state();
2199 policy->cpuinfo.max_freq = perf_limits->turbo_disabled ||
2200 perf_limits->no_turbo ?
2201 cpu->pstate.max_freq :
2202 cpu->pstate.turbo_freq;
2204 cpufreq_verify_within_cpu_limits(policy);
2206 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2207 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2210 /* When per-CPU limits are used, sysfs limits are not used */
2211 if (!per_cpu_limits) {
2212 unsigned int max_freq, min_freq;
2214 max_freq = policy->cpuinfo.max_freq *
2215 perf_limits->max_sysfs_pct / 100;
2216 min_freq = policy->cpuinfo.max_freq *
2217 perf_limits->min_sysfs_pct / 100;
2218 cpufreq_verify_within_limits(policy, min_freq, max_freq);
2224 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2226 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2229 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2231 pr_debug("CPU %d exiting\n", policy->cpu);
2233 intel_pstate_clear_update_util_hook(policy->cpu);
2235 intel_pstate_hwp_save_state(policy);
2237 intel_cpufreq_stop_cpu(policy);
2240 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2242 intel_pstate_exit_perf_limits(policy);
2244 policy->fast_switch_possible = false;
2249 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2251 struct cpudata *cpu;
2254 rc = intel_pstate_init_cpu(policy->cpu);
2258 cpu = all_cpu_data[policy->cpu];
2261 * We need sane value in the cpu->perf_limits, so inherit from global
2262 * perf_limits limits, which are seeded with values based on the
2263 * CONFIG_CPU_FREQ_DEFAULT_GOV_*, during boot up.
2266 memcpy(cpu->perf_limits, limits, sizeof(struct perf_limits));
2268 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2269 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2271 /* cpuinfo and default policy values */
2272 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2273 update_turbo_state();
2274 policy->cpuinfo.max_freq = limits->turbo_disabled ?
2275 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2276 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2278 intel_pstate_init_acpi_perf_limits(policy);
2279 cpumask_set_cpu(policy->cpu, policy->cpus);
2281 policy->fast_switch_possible = true;
2286 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2288 int ret = __intel_pstate_cpu_init(policy);
2293 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2294 if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
2295 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2297 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2302 static struct cpufreq_driver intel_pstate = {
2303 .flags = CPUFREQ_CONST_LOOPS,
2304 .verify = intel_pstate_verify_policy,
2305 .setpolicy = intel_pstate_set_policy,
2306 .suspend = intel_pstate_hwp_save_state,
2307 .resume = intel_pstate_resume,
2308 .get = intel_pstate_get,
2309 .init = intel_pstate_cpu_init,
2310 .exit = intel_pstate_cpu_exit,
2311 .stop_cpu = intel_pstate_stop_cpu,
2312 .name = "intel_pstate",
2315 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2317 struct cpudata *cpu = all_cpu_data[policy->cpu];
2319 update_turbo_state();
2320 policy->cpuinfo.max_freq = limits->turbo_disabled ?
2321 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2323 cpufreq_verify_within_cpu_limits(policy);
2328 static unsigned int intel_cpufreq_turbo_update(struct cpudata *cpu,
2329 struct cpufreq_policy *policy,
2330 unsigned int target_freq)
2332 unsigned int max_freq;
2334 update_turbo_state();
2336 max_freq = limits->no_turbo || limits->turbo_disabled ?
2337 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2338 policy->cpuinfo.max_freq = max_freq;
2339 if (policy->max > max_freq)
2340 policy->max = max_freq;
2342 if (target_freq > max_freq)
2343 target_freq = max_freq;
2348 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2349 unsigned int target_freq,
2350 unsigned int relation)
2352 struct cpudata *cpu = all_cpu_data[policy->cpu];
2353 struct cpufreq_freqs freqs;
2356 freqs.old = policy->cur;
2357 freqs.new = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2359 cpufreq_freq_transition_begin(policy, &freqs);
2361 case CPUFREQ_RELATION_L:
2362 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2364 case CPUFREQ_RELATION_H:
2365 target_pstate = freqs.new / cpu->pstate.scaling;
2368 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2371 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2372 if (target_pstate != cpu->pstate.current_pstate) {
2373 cpu->pstate.current_pstate = target_pstate;
2374 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2375 pstate_funcs.get_val(cpu, target_pstate));
2377 freqs.new = target_pstate * cpu->pstate.scaling;
2378 cpufreq_freq_transition_end(policy, &freqs, false);
2383 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2384 unsigned int target_freq)
2386 struct cpudata *cpu = all_cpu_data[policy->cpu];
2389 target_freq = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2390 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2391 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2392 intel_pstate_update_pstate(cpu, target_pstate);
2393 return target_pstate * cpu->pstate.scaling;
2396 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2398 int ret = __intel_pstate_cpu_init(policy);
2403 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2404 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2405 policy->cur = policy->cpuinfo.min_freq;
2410 static struct cpufreq_driver intel_cpufreq = {
2411 .flags = CPUFREQ_CONST_LOOPS,
2412 .verify = intel_cpufreq_verify_policy,
2413 .target = intel_cpufreq_target,
2414 .fast_switch = intel_cpufreq_fast_switch,
2415 .init = intel_cpufreq_cpu_init,
2416 .exit = intel_pstate_cpu_exit,
2417 .stop_cpu = intel_cpufreq_stop_cpu,
2418 .name = "intel_cpufreq",
2421 static struct cpufreq_driver *intel_pstate_driver = &intel_pstate;
2423 static void intel_pstate_driver_cleanup(void)
2428 for_each_online_cpu(cpu) {
2429 if (all_cpu_data[cpu]) {
2430 if (intel_pstate_driver == &intel_pstate)
2431 intel_pstate_clear_update_util_hook(cpu);
2433 kfree(all_cpu_data[cpu]);
2434 all_cpu_data[cpu] = NULL;
2440 static int intel_pstate_register_driver(void)
2444 intel_pstate_init_limits(&powersave_limits);
2445 intel_pstate_set_performance_limits(&performance_limits);
2446 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE) &&
2447 intel_pstate_driver == &intel_pstate)
2448 limits = &performance_limits;
2450 limits = &powersave_limits;
2452 ret = cpufreq_register_driver(intel_pstate_driver);
2454 intel_pstate_driver_cleanup();
2458 mutex_lock(&intel_pstate_limits_lock);
2459 driver_registered = true;
2460 mutex_unlock(&intel_pstate_limits_lock);
2462 if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2463 pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2464 intel_pstate_debug_expose_params();
2469 static int intel_pstate_unregister_driver(void)
2474 if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2475 pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2476 intel_pstate_debug_hide_params();
2478 mutex_lock(&intel_pstate_limits_lock);
2479 driver_registered = false;
2480 mutex_unlock(&intel_pstate_limits_lock);
2482 cpufreq_unregister_driver(intel_pstate_driver);
2483 intel_pstate_driver_cleanup();
2488 static ssize_t intel_pstate_show_status(char *buf)
2490 if (!driver_registered)
2491 return sprintf(buf, "off\n");
2493 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2494 "active" : "passive");
2497 static int intel_pstate_update_status(const char *buf, size_t size)
2501 if (size == 3 && !strncmp(buf, "off", size))
2502 return driver_registered ?
2503 intel_pstate_unregister_driver() : -EINVAL;
2505 if (size == 6 && !strncmp(buf, "active", size)) {
2506 if (driver_registered) {
2507 if (intel_pstate_driver == &intel_pstate)
2510 ret = intel_pstate_unregister_driver();
2515 intel_pstate_driver = &intel_pstate;
2516 return intel_pstate_register_driver();
2519 if (size == 7 && !strncmp(buf, "passive", size)) {
2520 if (driver_registered) {
2521 if (intel_pstate_driver != &intel_pstate)
2524 ret = intel_pstate_unregister_driver();
2529 intel_pstate_driver = &intel_cpufreq;
2530 return intel_pstate_register_driver();
2536 static int no_load __initdata;
2537 static int no_hwp __initdata;
2538 static int hwp_only __initdata;
2539 static unsigned int force_load __initdata;
2541 static int __init intel_pstate_msrs_not_valid(void)
2543 if (!pstate_funcs.get_max() ||
2544 !pstate_funcs.get_min() ||
2545 !pstate_funcs.get_turbo())
2551 static void __init copy_pid_params(struct pstate_adjust_policy *policy)
2553 pid_params.sample_rate_ms = policy->sample_rate_ms;
2554 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
2555 pid_params.p_gain_pct = policy->p_gain_pct;
2556 pid_params.i_gain_pct = policy->i_gain_pct;
2557 pid_params.d_gain_pct = policy->d_gain_pct;
2558 pid_params.deadband = policy->deadband;
2559 pid_params.setpoint = policy->setpoint;
2563 static void intel_pstate_use_acpi_profile(void)
2565 if (acpi_gbl_FADT.preferred_profile == PM_MOBILE)
2566 pstate_funcs.get_target_pstate =
2567 get_target_pstate_use_cpu_load;
2570 static void intel_pstate_use_acpi_profile(void)
2575 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2577 pstate_funcs.get_max = funcs->get_max;
2578 pstate_funcs.get_max_physical = funcs->get_max_physical;
2579 pstate_funcs.get_min = funcs->get_min;
2580 pstate_funcs.get_turbo = funcs->get_turbo;
2581 pstate_funcs.get_scaling = funcs->get_scaling;
2582 pstate_funcs.get_val = funcs->get_val;
2583 pstate_funcs.get_vid = funcs->get_vid;
2584 pstate_funcs.get_target_pstate = funcs->get_target_pstate;
2586 intel_pstate_use_acpi_profile();
2591 static bool __init intel_pstate_no_acpi_pss(void)
2595 for_each_possible_cpu(i) {
2597 union acpi_object *pss;
2598 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2599 struct acpi_processor *pr = per_cpu(processors, i);
2604 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2605 if (ACPI_FAILURE(status))
2608 pss = buffer.pointer;
2609 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2620 static bool __init intel_pstate_has_acpi_ppc(void)
2624 for_each_possible_cpu(i) {
2625 struct acpi_processor *pr = per_cpu(processors, i);
2629 if (acpi_has_method(pr->handle, "_PPC"))
2640 struct hw_vendor_info {
2642 char oem_id[ACPI_OEM_ID_SIZE];
2643 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2647 /* Hardware vendor-specific info that has its own power management modes */
2648 static struct hw_vendor_info vendor_info[] __initdata = {
2649 {1, "HP ", "ProLiant", PSS},
2650 {1, "ORACLE", "X4-2 ", PPC},
2651 {1, "ORACLE", "X4-2L ", PPC},
2652 {1, "ORACLE", "X4-2B ", PPC},
2653 {1, "ORACLE", "X3-2 ", PPC},
2654 {1, "ORACLE", "X3-2L ", PPC},
2655 {1, "ORACLE", "X3-2B ", PPC},
2656 {1, "ORACLE", "X4470M2 ", PPC},
2657 {1, "ORACLE", "X4270M3 ", PPC},
2658 {1, "ORACLE", "X4270M2 ", PPC},
2659 {1, "ORACLE", "X4170M2 ", PPC},
2660 {1, "ORACLE", "X4170 M3", PPC},
2661 {1, "ORACLE", "X4275 M3", PPC},
2662 {1, "ORACLE", "X6-2 ", PPC},
2663 {1, "ORACLE", "Sudbury ", PPC},
2667 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2669 struct acpi_table_header hdr;
2670 struct hw_vendor_info *v_info;
2671 const struct x86_cpu_id *id;
2674 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2676 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2677 if ( misc_pwr & (1 << 8))
2681 if (acpi_disabled ||
2682 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2685 for (v_info = vendor_info; v_info->valid; v_info++) {
2686 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2687 !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2688 ACPI_OEM_TABLE_ID_SIZE))
2689 switch (v_info->oem_pwr_table) {
2691 return intel_pstate_no_acpi_pss();
2693 return intel_pstate_has_acpi_ppc() &&
2701 static void intel_pstate_request_control_from_smm(void)
2704 * It may be unsafe to request P-states control from SMM if _PPC support
2705 * has not been enabled.
2708 acpi_processor_pstate_control();
2710 #else /* CONFIG_ACPI not enabled */
2711 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2712 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2713 static inline void intel_pstate_request_control_from_smm(void) {}
2714 #endif /* CONFIG_ACPI */
2716 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2717 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2721 static int __init intel_pstate_init(void)
2723 const struct x86_cpu_id *id;
2724 struct cpu_defaults *cpu_def;
2730 if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
2731 copy_cpu_funcs(&core_params.funcs);
2733 intel_pstate.attr = hwp_cpufreq_attrs;
2734 goto hwp_cpu_matched;
2737 id = x86_match_cpu(intel_pstate_cpu_ids);
2741 cpu_def = (struct cpu_defaults *)id->driver_data;
2743 copy_pid_params(&cpu_def->pid_policy);
2744 copy_cpu_funcs(&cpu_def->funcs);
2746 if (intel_pstate_msrs_not_valid())
2751 * The Intel pstate driver will be ignored if the platform
2752 * firmware has its own power management modes.
2754 if (intel_pstate_platform_pwr_mgmt_exists())
2757 if (!hwp_active && hwp_only)
2760 pr_info("Intel P-state driver initializing\n");
2762 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2766 intel_pstate_request_control_from_smm();
2768 intel_pstate_sysfs_expose_params();
2770 mutex_lock(&intel_pstate_driver_lock);
2771 rc = intel_pstate_register_driver();
2772 mutex_unlock(&intel_pstate_driver_lock);
2777 pr_info("HWP enabled\n");
2781 device_initcall(intel_pstate_init);
2783 static int __init intel_pstate_setup(char *str)
2788 if (!strcmp(str, "disable")) {
2790 } else if (!strcmp(str, "passive")) {
2791 pr_info("Passive mode enabled\n");
2792 intel_pstate_driver = &intel_cpufreq;
2795 if (!strcmp(str, "no_hwp")) {
2796 pr_info("HWP disabled\n");
2799 if (!strcmp(str, "force"))
2801 if (!strcmp(str, "hwp_only"))
2803 if (!strcmp(str, "per_cpu_perf_limits"))
2804 per_cpu_limits = true;
2807 if (!strcmp(str, "support_acpi_ppc"))
2813 early_param("intel_pstate", intel_pstate_setup);
2815 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2816 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2817 MODULE_LICENSE("GPL");