drivers/cpufreq/intel_pstate.c

   1 /*
   2  * intel_pstate.c: Native P state management for Intel processors
   3  *
   4  * (C) Copyright 2012 Intel Corporation
   5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; version 2
  10  * of the License.
  11  */
  12
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/kernel_stat.h>
  17 #include <linux/module.h>
  18 #include <linux/ktime.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/tick.h>
  21 #include <linux/slab.h>
  22 #include <linux/sched.h>
  23 #include <linux/list.h>
  24 #include <linux/cpu.h>
  25 #include <linux/cpufreq.h>
  26 #include <linux/sysfs.h>
  27 #include <linux/types.h>
  28 #include <linux/fs.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/acpi.h>
  31 #include <linux/vmalloc.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/div64.h>
  35 #include <asm/msr.h>
  36 #include <asm/cpu_device_id.h>
  37 #include <asm/cpufeature.h>
  38 #include <asm/intel-family.h>
  39
  40 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
  41
  42 #define ATOM_RATIOS             0x66a
  43 #define ATOM_VIDS               0x66b
  44 #define ATOM_TURBO_RATIOS       0x66c
  45 #define ATOM_TURBO_VIDS         0x66d
  46
  47 #ifdef CONFIG_ACPI
  48 #include <acpi/processor.h>
  49 #include <acpi/cppc_acpi.h>
  50 #endif
  51
  52 #define FRAC_BITS 8
  53 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  54 #define fp_toint(X) ((X) >> FRAC_BITS)
  55
  56 #define EXT_BITS 6
  57 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  58 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
  59 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
  60
  61 static inline int32_t mul_fp(int32_t x, int32_t y)
  62 {
  63         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  64 }
  65
  66 static inline int32_t div_fp(s64 x, s64 y)
  67 {
  68         return div64_s64((int64_t)x << FRAC_BITS, y);
  69 }
  70
  71 static inline int ceiling_fp(int32_t x)
  72 {
  73         int mask, ret;
  74
  75         ret = fp_toint(x);
  76         mask = (1 << FRAC_BITS) - 1;
  77         if (x & mask)
  78                 ret += 1;
  79         return ret;
  80 }
  81
  82 static inline u64 mul_ext_fp(u64 x, u64 y)
  83 {
  84         return (x * y) >> EXT_FRAC_BITS;
  85 }
  86
  87 static inline u64 div_ext_fp(u64 x, u64 y)
  88 {
  89         return div64_u64(x << EXT_FRAC_BITS, y);
  90 }
  91
  92 /**
  93  * struct sample -      Store performance sample
  94  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
  95  *                      performance during last sample period
  96  * @busy_scaled:        Scaled busy value which is used to calculate next
  97  *                      P state. This can be different than core_avg_perf
  98  *                      to account for cpu idle period
  99  * @aperf:              Difference of actual performance frequency clock count
 100  *                      read from APERF MSR between last and current sample
 101  * @mperf:              Difference of maximum performance frequency clock count
 102  *                      read from MPERF MSR between last and current sample
 103  * @tsc:                Difference of time stamp counter between last and
 104  *                      current sample
 105  * @time:               Current time from scheduler
 106  *
 107  * This structure is used in the cpudata structure to store performance sample
 108  * data for choosing next P State.
 109  */
 110 struct sample {
 111         int32_t core_avg_perf;
 112         int32_t busy_scaled;
 113         u64 aperf;
 114         u64 mperf;
 115         u64 tsc;
 116         u64 time;
 117 };
 118
 119 /**
 120  * struct pstate_data - Store P state data
 121  * @current_pstate:     Current requested P state
 122  * @min_pstate:         Min P state possible for this platform
 123  * @max_pstate:         Max P state possible for this platform
 124  * @max_pstate_physical:This is physical Max P state for a processor
 125  *                      This can be higher than the max_pstate which can
 126  *                      be limited by platform thermal design power limits
 127  * @scaling:            Scaling factor to  convert frequency to cpufreq
 128  *                      frequency units
 129  * @turbo_pstate:       Max Turbo P state possible for this platform
 130  * @max_freq:           @max_pstate frequency in cpufreq units
 131  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
 132  *
 133  * Stores the per cpu model P state limits and current P state.
 134  */
 135 struct pstate_data {
 136         int     current_pstate;
 137         int     min_pstate;
 138         int     max_pstate;
 139         int     max_pstate_physical;
 140         int     scaling;
 141         int     turbo_pstate;
 142         unsigned int max_freq;
 143         unsigned int turbo_freq;
 144 };
 145
 146 /**
 147  * struct vid_data -    Stores voltage information data
 148  * @min:                VID data for this platform corresponding to
 149  *                      the lowest P state
 150  * @max:                VID data corresponding to the highest P State.
 151  * @turbo:              VID data for turbo P state
 152  * @ratio:              Ratio of (vid max - vid min) /
 153  *                      (max P state - Min P State)
 154  *
 155  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 156  * This data is used in Atom platforms, where in addition to target P state,
 157  * the voltage data needs to be specified to select next P State.
 158  */
 159 struct vid_data {
 160         int min;
 161         int max;
 162         int turbo;
 163         int32_t ratio;
 164 };
 165
 166 /**
 167  * struct _pid -        Stores PID data
 168  * @setpoint:           Target set point for busyness or performance
 169  * @integral:           Storage for accumulated error values
 170  * @p_gain:             PID proportional gain
 171  * @i_gain:             PID integral gain
 172  * @d_gain:             PID derivative gain
 173  * @deadband:           PID deadband
 174  * @last_err:           Last error storage for integral part of PID calculation
 175  *
 176  * Stores PID coefficients and last error for PID controller.
 177  */
 178 struct _pid {
 179         int setpoint;
 180         int32_t integral;
 181         int32_t p_gain;
 182         int32_t i_gain;
 183         int32_t d_gain;
 184         int deadband;
 185         int32_t last_err;
 186 };
 187
 188 /**
 189  * struct perf_limits - Store user and policy limits
 190  * @no_turbo:           User requested turbo state from intel_pstate sysfs
 191  * @turbo_disabled:     Platform turbo status either from msr
 192  *                      MSR_IA32_MISC_ENABLE or when maximum available pstate
 193  *                      matches the maximum turbo pstate
 194  * @max_perf_pct:       Effective maximum performance limit in percentage, this
 195  *                      is minimum of either limits enforced by cpufreq policy
 196  *                      or limits from user set limits via intel_pstate sysfs
 197  * @min_perf_pct:       Effective minimum performance limit in percentage, this
 198  *                      is maximum of either limits enforced by cpufreq policy
 199  *                      or limits from user set limits via intel_pstate sysfs
 200  * @max_perf:           This is a scaled value between 0 to 255 for max_perf_pct
 201  *                      This value is used to limit max pstate
 202  * @min_perf:           This is a scaled value between 0 to 255 for min_perf_pct
 203  *                      This value is used to limit min pstate
 204  * @max_policy_pct:     The maximum performance in percentage enforced by
 205  *                      cpufreq setpolicy interface
 206  * @max_sysfs_pct:      The maximum performance in percentage enforced by
 207  *                      intel pstate sysfs interface, unused when per cpu
 208  *                      controls are enforced
 209  * @min_policy_pct:     The minimum performance in percentage enforced by
 210  *                      cpufreq setpolicy interface
 211  * @min_sysfs_pct:      The minimum performance in percentage enforced by
 212  *                      intel pstate sysfs interface, unused when per cpu
 213  *                      controls are enforced
 214  *
 215  * Storage for user and policy defined limits.
 216  */
 217 struct perf_limits {
 218         int no_turbo;
 219         int turbo_disabled;
 220         int max_perf_pct;
 221         int min_perf_pct;
 222         int32_t max_perf;
 223         int32_t min_perf;
 224         int max_policy_pct;
 225         int max_sysfs_pct;
 226         int min_policy_pct;
 227         int min_sysfs_pct;
 228 };
 229
 230 /**
 231  * struct cpudata -     Per CPU instance data storage
 232  * @cpu:                CPU number for this instance data
 233  * @policy:             CPUFreq policy value
 234  * @update_util:        CPUFreq utility callback information
 235  * @update_util_set:    CPUFreq utility callback is set
 236  * @iowait_boost:       iowait-related boost fraction
 237  * @last_update:        Time of the last update.
 238  * @pstate:             Stores P state limits for this CPU
 239  * @vid:                Stores VID limits for this CPU
 240  * @pid:                Stores PID parameters for this CPU
 241  * @last_sample_time:   Last Sample time
 242  * @prev_aperf:         Last APERF value read from APERF MSR
 243  * @prev_mperf:         Last MPERF value read from MPERF MSR
 244  * @prev_tsc:           Last timestamp counter (TSC) value
 245  * @prev_cummulative_iowait: IO Wait time difference from last and
 246  *                      current sample
 247  * @sample:             Storage for storing last Sample data
 248  * @perf_limits:        Pointer to perf_limit unique to this CPU
 249  *                      Not all field in the structure are applicable
 250  *                      when per cpu controls are enforced
 251  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 252  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 253  * @epp_powersave:      Last saved HWP energy performance preference
 254  *                      (EPP) or energy performance bias (EPB),
 255  *                      when policy switched to performance
 256  * @epp_policy:         Last saved policy used to set EPP/EPB
 257  * @epp_default:        Power on default HWP energy performance
 258  *                      preference/bias
 259  * @epp_saved:          Saved EPP/EPB during system suspend or CPU offline
 260  *                      operation
 261  *
 262  * This structure stores per CPU instance data for all CPUs.
 263  */
 264 struct cpudata {
 265         int cpu;
 266
 267         unsigned int policy;
 268         struct update_util_data update_util;
 269         bool   update_util_set;
 270
 271         struct pstate_data pstate;
 272         struct vid_data vid;
 273         struct _pid pid;
 274
 275         u64     last_update;
 276         u64     last_sample_time;
 277         u64     prev_aperf;
 278         u64     prev_mperf;
 279         u64     prev_tsc;
 280         u64     prev_cummulative_iowait;
 281         struct sample sample;
 282         struct perf_limits *perf_limits;
 283 #ifdef CONFIG_ACPI
 284         struct acpi_processor_performance acpi_perf_data;
 285         bool valid_pss_table;
 286 #endif
 287         unsigned int iowait_boost;
 288         s16 epp_powersave;
 289         s16 epp_policy;
 290         s16 epp_default;
 291         s16 epp_saved;
 292 };
 293
 294 static struct cpudata **all_cpu_data;
 295
 296 /**
 297  * struct pstate_adjust_policy - Stores static PID configuration data
 298  * @sample_rate_ms:     PID calculation sample rate in ms
 299  * @sample_rate_ns:     Sample rate calculation in ns
 300  * @deadband:           PID deadband
 301  * @setpoint:           PID Setpoint
 302  * @p_gain_pct:         PID proportional gain
 303  * @i_gain_pct:         PID integral gain
 304  * @d_gain_pct:         PID derivative gain
 305  *
 306  * Stores per CPU model static PID configuration data.
 307  */
 308 struct pstate_adjust_policy {
 309         int sample_rate_ms;
 310         s64 sample_rate_ns;
 311         int deadband;
 312         int setpoint;
 313         int p_gain_pct;
 314         int d_gain_pct;
 315         int i_gain_pct;
 316 };
 317
 318 /**
 319  * struct pstate_funcs - Per CPU model specific callbacks
 320  * @get_max:            Callback to get maximum non turbo effective P state
 321  * @get_max_physical:   Callback to get maximum non turbo physical P state
 322  * @get_min:            Callback to get minimum P state
 323  * @get_turbo:          Callback to get turbo P state
 324  * @get_scaling:        Callback to get frequency scaling factor
 325  * @get_val:            Callback to convert P state to actual MSR write value
 326  * @get_vid:            Callback to get VID data for Atom platforms
 327  * @get_target_pstate:  Callback to a function to calculate next P state to use
 328  *
 329  * Core and Atom CPU models have different way to get P State limits. This
 330  * structure is used to store those callbacks.
 331  */
 332 struct pstate_funcs {
 333         int (*get_max)(void);
 334         int (*get_max_physical)(void);
 335         int (*get_min)(void);
 336         int (*get_turbo)(void);
 337         int (*get_scaling)(void);
 338         u64 (*get_val)(struct cpudata*, int pstate);
 339         void (*get_vid)(struct cpudata *);
 340         int32_t (*get_target_pstate)(struct cpudata *);
 341 };
 342
 343 /**
 344  * struct cpu_defaults- Per CPU model default config data
 345  * @pid_policy: PID config data
 346  * @funcs:              Callback function data
 347  */
 348 struct cpu_defaults {
 349         struct pstate_adjust_policy pid_policy;
 350         struct pstate_funcs funcs;
 351 };
 352
 353 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
 354 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
 355
 356 static struct pstate_adjust_policy pid_params __read_mostly;
 357 static struct pstate_funcs pstate_funcs __read_mostly;
 358 static int hwp_active __read_mostly;
 359 static bool per_cpu_limits __read_mostly;
 360
 361 static bool driver_registered __read_mostly;
 362
 363 #ifdef CONFIG_ACPI
 364 static bool acpi_ppc;
 365 #endif
 366
 367 static struct perf_limits performance_limits;
 368 static struct perf_limits powersave_limits;
 369 static struct perf_limits *limits;
 370
 371 static void intel_pstate_init_limits(struct perf_limits *limits)
 372 {
 373         memset(limits, 0, sizeof(*limits));
 374         limits->max_perf_pct = 100;
 375         limits->max_perf = int_ext_tofp(1);
 376         limits->max_policy_pct = 100;
 377         limits->max_sysfs_pct = 100;
 378 }
 379
 380 static void intel_pstate_set_performance_limits(struct perf_limits *limits)
 381 {
 382         intel_pstate_init_limits(limits);
 383         limits->min_perf_pct = 100;
 384         limits->min_perf = int_ext_tofp(1);
 385 }
 386
 387 static DEFINE_MUTEX(intel_pstate_driver_lock);
 388 static DEFINE_MUTEX(intel_pstate_limits_lock);
 389
 390 #ifdef CONFIG_ACPI
 391
 392 static bool intel_pstate_get_ppc_enable_status(void)
 393 {
 394         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 395             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 396                 return true;
 397
 398         return acpi_ppc;
 399 }
 400
 401 #ifdef CONFIG_ACPI_CPPC_LIB
 402
 403 /* The work item is needed to avoid CPU hotplug locking issues */
 404 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
 405 {
 406         sched_set_itmt_support();
 407 }
 408
 409 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 410
 411 static void intel_pstate_set_itmt_prio(int cpu)
 412 {
 413         struct cppc_perf_caps cppc_perf;
 414         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
 415         int ret;
 416
 417         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 418         if (ret)
 419                 return;
 420
 421         /*
 422          * The priorities can be set regardless of whether or not
 423          * sched_set_itmt_support(true) has been called and it is valid to
 424          * update them at any time after it has been called.
 425          */
 426         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
 427
 428         if (max_highest_perf <= min_highest_perf) {
 429                 if (cppc_perf.highest_perf > max_highest_perf)
 430                         max_highest_perf = cppc_perf.highest_perf;
 431
 432                 if (cppc_perf.highest_perf < min_highest_perf)
 433                         min_highest_perf = cppc_perf.highest_perf;
 434
 435                 if (max_highest_perf > min_highest_perf) {
 436                         /*
 437                          * This code can be run during CPU online under the
 438                          * CPU hotplug locks, so sched_set_itmt_support()
 439                          * cannot be called from here.  Queue up a work item
 440                          * to invoke it.
 441                          */
 442                         schedule_work(&sched_itmt_work);
 443                 }
 444         }
 445 }
 446 #else
 447 static void intel_pstate_set_itmt_prio(int cpu)
 448 {
 449 }
 450 #endif
 451
 452 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 453 {
 454         struct cpudata *cpu;
 455         int ret;
 456         int i;
 457
 458         if (hwp_active) {
 459                 intel_pstate_set_itmt_prio(policy->cpu);
 460                 return;
 461         }
 462
 463         if (!intel_pstate_get_ppc_enable_status())
 464                 return;
 465
 466         cpu = all_cpu_data[policy->cpu];
 467
 468         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 469                                                   policy->cpu);
 470         if (ret)
 471                 return;
 472
 473         /*
 474          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 475          * guarantee that the states returned by it map to the states in our
 476          * list directly.
 477          */
 478         if (cpu->acpi_perf_data.control_register.space_id !=
 479                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 480                 goto err;
 481
 482         /*
 483          * If there is only one entry _PSS, simply ignore _PSS and continue as
 484          * usual without taking _PSS into account
 485          */
 486         if (cpu->acpi_perf_data.state_count < 2)
 487                 goto err;
 488
 489         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 490         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 491                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 492                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 493                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 494                          (u32) cpu->acpi_perf_data.states[i].power,
 495                          (u32) cpu->acpi_perf_data.states[i].control);
 496         }
 497
 498         /*
 499          * The _PSS table doesn't contain whole turbo frequency range.
 500          * This just contains +1 MHZ above the max non turbo frequency,
 501          * with control value corresponding to max turbo ratio. But
 502          * when cpufreq set policy is called, it will call with this
 503          * max frequency, which will cause a reduced performance as
 504          * this driver uses real max turbo frequency as the max
 505          * frequency. So correct this frequency in _PSS table to
 506          * correct max turbo frequency based on the turbo state.
 507          * Also need to convert to MHz as _PSS freq is in MHz.
 508          */
 509         if (!limits->turbo_disabled)
 510                 cpu->acpi_perf_data.states[0].core_frequency =
 511                                         policy->cpuinfo.max_freq / 1000;
 512         cpu->valid_pss_table = true;
 513         pr_debug("_PPC limits will be enforced\n");
 514
 515         return;
 516
 517  err:
 518         cpu->valid_pss_table = false;
 519         acpi_processor_unregister_performance(policy->cpu);
 520 }
 521
 522 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 523 {
 524         struct cpudata *cpu;
 525
 526         cpu = all_cpu_data[policy->cpu];
 527         if (!cpu->valid_pss_table)
 528                 return;
 529
 530         acpi_processor_unregister_performance(policy->cpu);
 531 }
 532 #else
 533 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 534 {
 535 }
 536
 537 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 538 {
 539 }
 540 #endif
 541
 542 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
 543                              int deadband, int integral) {
 544         pid->setpoint = int_tofp(setpoint);
 545         pid->deadband  = int_tofp(deadband);
 546         pid->integral  = int_tofp(integral);
 547         pid->last_err  = int_tofp(setpoint) - int_tofp(busy);
 548 }
 549
 550 static inline void pid_p_gain_set(struct _pid *pid, int percent)
 551 {
 552         pid->p_gain = div_fp(percent, 100);
 553 }
 554
 555 static inline void pid_i_gain_set(struct _pid *pid, int percent)
 556 {
 557         pid->i_gain = div_fp(percent, 100);
 558 }
 559
 560 static inline void pid_d_gain_set(struct _pid *pid, int percent)
 561 {
 562         pid->d_gain = div_fp(percent, 100);
 563 }
 564
 565 static signed int pid_calc(struct _pid *pid, int32_t busy)
 566 {
 567         signed int result;
 568         int32_t pterm, dterm, fp_error;
 569         int32_t integral_limit;
 570
 571         fp_error = pid->setpoint - busy;
 572
 573         if (abs(fp_error) <= pid->deadband)
 574                 return 0;
 575
 576         pterm = mul_fp(pid->p_gain, fp_error);
 577
 578         pid->integral += fp_error;
 579
 580         /*
 581          * We limit the integral here so that it will never
 582          * get higher than 30.  This prevents it from becoming
 583          * too large an input over long periods of time and allows
 584          * it to get factored out sooner.
 585          *
 586          * The value of 30 was chosen through experimentation.
 587          */
 588         integral_limit = int_tofp(30);
 589         if (pid->integral > integral_limit)
 590                 pid->integral = integral_limit;
 591         if (pid->integral < -integral_limit)
 592                 pid->integral = -integral_limit;
 593
 594         dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
 595         pid->last_err = fp_error;
 596
 597         result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
 598         result = result + (1 << (FRAC_BITS-1));
 599         return (signed int)fp_toint(result);
 600 }
 601
 602 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
 603 {
 604         pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
 605         pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
 606         pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
 607
 608         pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
 609 }
 610
 611 static inline void intel_pstate_reset_all_pid(void)
 612 {
 613         unsigned int cpu;
 614
 615         for_each_online_cpu(cpu) {
 616                 if (all_cpu_data[cpu])
 617                         intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
 618         }
 619 }
 620
 621 static inline void update_turbo_state(void)
 622 {
 623         u64 misc_en;
 624         struct cpudata *cpu;
 625
 626         cpu = all_cpu_data[0];
 627         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 628         limits->turbo_disabled =
 629                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 630                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 631 }
 632
 633 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
 634 {
 635         u64 epb;
 636         int ret;
 637
 638         if (!static_cpu_has(X86_FEATURE_EPB))
 639                 return -ENXIO;
 640
 641         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 642         if (ret)
 643                 return (s16)ret;
 644
 645         return (s16)(epb & 0x0f);
 646 }
 647
 648 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
 649 {
 650         s16 epp;
 651
 652         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 653                 /*
 654                  * When hwp_req_data is 0, means that caller didn't read
 655                  * MSR_HWP_REQUEST, so need to read and get EPP.
 656                  */
 657                 if (!hwp_req_data) {
 658                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
 659                                             &hwp_req_data);
 660                         if (epp)
 661                                 return epp;
 662                 }
 663                 epp = (hwp_req_data >> 24) & 0xff;
 664         } else {
 665                 /* When there is no EPP present, HWP uses EPB settings */
 666                 epp = intel_pstate_get_epb(cpu_data);
 667         }
 668
 669         return epp;
 670 }
 671
 672 static int intel_pstate_set_epb(int cpu, s16 pref)
 673 {
 674         u64 epb;
 675         int ret;
 676
 677         if (!static_cpu_has(X86_FEATURE_EPB))
 678                 return -ENXIO;
 679
 680         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 681         if (ret)
 682                 return ret;
 683
 684         epb = (epb & ~0x0f) | pref;
 685         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
 686
 687         return 0;
 688 }
 689
 690 /*
 691  * EPP/EPB display strings corresponding to EPP index in the
 692  * energy_perf_strings[]
 693  *      index           String
 694  *-------------------------------------
 695  *      0               default
 696  *      1               performance
 697  *      2               balance_performance
 698  *      3               balance_power
 699  *      4               power
 700  */
 701 static const char * const energy_perf_strings[] = {
 702         "default",
 703         "performance",
 704         "balance_performance",
 705         "balance_power",
 706         "power",
 707         NULL
 708 };
 709
 710 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
 711 {
 712         s16 epp;
 713         int index = -EINVAL;
 714
 715         epp = intel_pstate_get_epp(cpu_data, 0);
 716         if (epp < 0)
 717                 return epp;
 718
 719         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 720                 /*
 721                  * Range:
 722                  *      0x00-0x3F       :       Performance
 723                  *      0x40-0x7F       :       Balance performance
 724                  *      0x80-0xBF       :       Balance power
 725                  *      0xC0-0xFF       :       Power
 726                  * The EPP is a 8 bit value, but our ranges restrict the
 727                  * value which can be set. Here only using top two bits
 728                  * effectively.
 729                  */
 730                 index = (epp >> 6) + 1;
 731         } else if (static_cpu_has(X86_FEATURE_EPB)) {
 732                 /*
 733                  * Range:
 734                  *      0x00-0x03       :       Performance
 735                  *      0x04-0x07       :       Balance performance
 736                  *      0x08-0x0B       :       Balance power
 737                  *      0x0C-0x0F       :       Power
 738                  * The EPB is a 4 bit value, but our ranges restrict the
 739                  * value which can be set. Here only using top two bits
 740                  * effectively.
 741                  */
 742                 index = (epp >> 2) + 1;
 743         }
 744
 745         return index;
 746 }
 747
 748 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
 749                                               int pref_index)
 750 {
 751         int epp = -EINVAL;
 752         int ret;
 753
 754         if (!pref_index)
 755                 epp = cpu_data->epp_default;
 756
 757         mutex_lock(&intel_pstate_limits_lock);
 758
 759         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 760                 u64 value;
 761
 762                 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
 763                 if (ret)
 764                         goto return_pref;
 765
 766                 value &= ~GENMASK_ULL(31, 24);
 767
 768                 /*
 769                  * If epp is not default, convert from index into
 770                  * energy_perf_strings to epp value, by shifting 6
 771                  * bits left to use only top two bits in epp.
 772                  * The resultant epp need to shifted by 24 bits to
 773                  * epp position in MSR_HWP_REQUEST.
 774                  */
 775                 if (epp == -EINVAL)
 776                         epp = (pref_index - 1) << 6;
 777
 778                 value |= (u64)epp << 24;
 779                 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
 780         } else {
 781                 if (epp == -EINVAL)
 782                         epp = (pref_index - 1) << 2;
 783                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
 784         }
 785 return_pref:
 786         mutex_unlock(&intel_pstate_limits_lock);
 787
 788         return ret;
 789 }
 790
 791 static ssize_t show_energy_performance_available_preferences(
 792                                 struct cpufreq_policy *policy, char *buf)
 793 {
 794         int i = 0;
 795         int ret = 0;
 796
 797         while (energy_perf_strings[i] != NULL)
 798                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
 799
 800         ret += sprintf(&buf[ret], "\n");
 801
 802         return ret;
 803 }
 804
 805 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 806
 807 static ssize_t store_energy_performance_preference(
 808                 struct cpufreq_policy *policy, const char *buf, size_t count)
 809 {
 810         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 811         char str_preference[21];
 812         int ret, i = 0;
 813
 814         ret = sscanf(buf, "%20s", str_preference);
 815         if (ret != 1)
 816                 return -EINVAL;
 817
 818         while (energy_perf_strings[i] != NULL) {
 819                 if (!strcmp(str_preference, energy_perf_strings[i])) {
 820                         intel_pstate_set_energy_pref_index(cpu_data, i);
 821                         return count;
 822                 }
 823                 ++i;
 824         }
 825
 826         return -EINVAL;
 827 }
 828
 829 static ssize_t show_energy_performance_preference(
 830                                 struct cpufreq_policy *policy, char *buf)
 831 {
 832         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 833         int preference;
 834
 835         preference = intel_pstate_get_energy_pref_index(cpu_data);
 836         if (preference < 0)
 837                 return preference;
 838
 839         return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
 840 }
 841
 842 cpufreq_freq_attr_rw(energy_performance_preference);
 843
 844 static struct freq_attr *hwp_cpufreq_attrs[] = {
 845         &energy_performance_preference,
 846         &energy_performance_available_preferences,
 847         NULL,
 848 };
 849
 850 static void intel_pstate_hwp_set(struct cpufreq_policy *policy)
 851 {
 852         int min, hw_min, max, hw_max, cpu, range, adj_range;
 853         struct perf_limits *perf_limits = limits;
 854         u64 value, cap;
 855
 856         for_each_cpu(cpu, policy->cpus) {
 857                 int max_perf_pct, min_perf_pct;
 858                 struct cpudata *cpu_data = all_cpu_data[cpu];
 859                 s16 epp;
 860
 861                 if (per_cpu_limits)
 862                         perf_limits = all_cpu_data[cpu]->perf_limits;
 863
 864                 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
 865                 hw_min = HWP_LOWEST_PERF(cap);
 866                 if (limits->no_turbo)
 867                         hw_max = HWP_GUARANTEED_PERF(cap);
 868                 else
 869                         hw_max = HWP_HIGHEST_PERF(cap);
 870                 range = hw_max - hw_min;
 871
 872                 max_perf_pct = perf_limits->max_perf_pct;
 873                 min_perf_pct = perf_limits->min_perf_pct;
 874
 875                 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 876                 adj_range = min_perf_pct * range / 100;
 877                 min = hw_min + adj_range;
 878                 value &= ~HWP_MIN_PERF(~0L);
 879                 value |= HWP_MIN_PERF(min);
 880
 881                 adj_range = max_perf_pct * range / 100;
 882                 max = hw_min + adj_range;
 883
 884                 value &= ~HWP_MAX_PERF(~0L);
 885                 value |= HWP_MAX_PERF(max);
 886
 887                 if (cpu_data->epp_policy == cpu_data->policy)
 888                         goto skip_epp;
 889
 890                 cpu_data->epp_policy = cpu_data->policy;
 891
 892                 if (cpu_data->epp_saved >= 0) {
 893                         epp = cpu_data->epp_saved;
 894                         cpu_data->epp_saved = -EINVAL;
 895                         goto update_epp;
 896                 }
 897
 898                 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
 899                         epp = intel_pstate_get_epp(cpu_data, value);
 900                         cpu_data->epp_powersave = epp;
 901                         /* If EPP read was failed, then don't try to write */
 902                         if (epp < 0)
 903                                 goto skip_epp;
 904
 905
 906                         epp = 0;
 907                 } else {
 908                         /* skip setting EPP, when saved value is invalid */
 909                         if (cpu_data->epp_powersave < 0)
 910                                 goto skip_epp;
 911
 912                         /*
 913                          * No need to restore EPP when it is not zero. This
 914                          * means:
 915                          *  - Policy is not changed
 916                          *  - user has manually changed
 917                          *  - Error reading EPB
 918                          */
 919                         epp = intel_pstate_get_epp(cpu_data, value);
 920                         if (epp)
 921                                 goto skip_epp;
 922
 923                         epp = cpu_data->epp_powersave;
 924                 }
 925 update_epp:
 926                 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 927                         value &= ~GENMASK_ULL(31, 24);
 928                         value |= (u64)epp << 24;
 929                 } else {
 930                         intel_pstate_set_epb(cpu, epp);
 931                 }
 932 skip_epp:
 933                 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 934         }
 935 }
 936
 937 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy)
 938 {
 939         if (hwp_active)
 940                 intel_pstate_hwp_set(policy);
 941
 942         return 0;
 943 }
 944
 945 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
 946 {
 947         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 948
 949         if (!hwp_active)
 950                 return 0;
 951
 952         cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
 953
 954         return 0;
 955 }
 956
 957 static int intel_pstate_resume(struct cpufreq_policy *policy)
 958 {
 959         int ret;
 960
 961         if (!hwp_active)
 962                 return 0;
 963
 964         mutex_lock(&intel_pstate_limits_lock);
 965
 966         all_cpu_data[policy->cpu]->epp_policy = 0;
 967
 968         ret = intel_pstate_hwp_set_policy(policy);
 969
 970         mutex_unlock(&intel_pstate_limits_lock);
 971
 972         return ret;
 973 }
 974
 975 static void intel_pstate_update_policies(void)
 976         __releases(&intel_pstate_limits_lock)
 977         __acquires(&intel_pstate_limits_lock)
 978 {
 979         struct perf_limits *saved_limits = limits;
 980         int cpu;
 981
 982         mutex_unlock(&intel_pstate_limits_lock);
 983
 984         for_each_possible_cpu(cpu)
 985                 cpufreq_update_policy(cpu);
 986
 987         mutex_lock(&intel_pstate_limits_lock);
 988
 989         limits = saved_limits;
 990 }
 991
 992 /************************** debugfs begin ************************/
 993 static int pid_param_set(void *data, u64 val)
 994 {
 995         *(u32 *)data = val;
 996         intel_pstate_reset_all_pid();
 997         return 0;
 998 }
 999
1000 static int pid_param_get(void *data, u64 *val)
1001 {
1002         *val = *(u32 *)data;
1003         return 0;
1004 }
1005 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
1006
1007 static struct dentry *debugfs_parent;
1008
1009 struct pid_param {
1010         char *name;
1011         void *value;
1012         struct dentry *dentry;
1013 };
1014
1015 static struct pid_param pid_files[] = {
1016         {"sample_rate_ms", &pid_params.sample_rate_ms, },
1017         {"d_gain_pct", &pid_params.d_gain_pct, },
1018         {"i_gain_pct", &pid_params.i_gain_pct, },
1019         {"deadband", &pid_params.deadband, },
1020         {"setpoint", &pid_params.setpoint, },
1021         {"p_gain_pct", &pid_params.p_gain_pct, },
1022         {NULL, NULL, }
1023 };
1024
1025 static void intel_pstate_debug_expose_params(void)
1026 {
1027         int i;
1028
1029         debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
1030         if (IS_ERR_OR_NULL(debugfs_parent))
1031                 return;
1032
1033         for (i = 0; pid_files[i].name; i++) {
1034                 struct dentry *dentry;
1035
1036                 dentry = debugfs_create_file(pid_files[i].name, 0660,
1037                                              debugfs_parent, pid_files[i].value,
1038                                              &fops_pid_param);
1039                 if (!IS_ERR(dentry))
1040                         pid_files[i].dentry = dentry;
1041         }
1042 }
1043
1044 static void intel_pstate_debug_hide_params(void)
1045 {
1046         int i;
1047
1048         if (IS_ERR_OR_NULL(debugfs_parent))
1049                 return;
1050
1051         for (i = 0; pid_files[i].name; i++) {
1052                 debugfs_remove(pid_files[i].dentry);
1053                 pid_files[i].dentry = NULL;
1054         }
1055
1056         debugfs_remove(debugfs_parent);
1057         debugfs_parent = NULL;
1058 }
1059
1060 /************************** debugfs end ************************/
1061
1062 /************************** sysfs begin ************************/
1063 #define show_one(file_name, object)                                     \
1064         static ssize_t show_##file_name                                 \
1065         (struct kobject *kobj, struct attribute *attr, char *buf)       \
1066         {                                                               \
1067                 return sprintf(buf, "%u\n", limits->object);            \
1068         }
1069
1070 static ssize_t intel_pstate_show_status(char *buf);
1071 static int intel_pstate_update_status(const char *buf, size_t size);
1072
1073 static ssize_t show_status(struct kobject *kobj,
1074                            struct attribute *attr, char *buf)
1075 {
1076         ssize_t ret;
1077
1078         mutex_lock(&intel_pstate_driver_lock);
1079         ret = intel_pstate_show_status(buf);
1080         mutex_unlock(&intel_pstate_driver_lock);
1081
1082         return ret;
1083 }
1084
1085 static ssize_t store_status(struct kobject *a, struct attribute *b,
1086                             const char *buf, size_t count)
1087 {
1088         char *p = memchr(buf, '\n', count);
1089         int ret;
1090
1091         mutex_lock(&intel_pstate_driver_lock);
1092         ret = intel_pstate_update_status(buf, p ? p - buf : count);
1093         mutex_unlock(&intel_pstate_driver_lock);
1094
1095         return ret < 0 ? ret : count;
1096 }
1097
1098 static ssize_t show_turbo_pct(struct kobject *kobj,
1099                                 struct attribute *attr, char *buf)
1100 {
1101         struct cpudata *cpu;
1102         int total, no_turbo, turbo_pct;
1103         uint32_t turbo_fp;
1104
1105         mutex_lock(&intel_pstate_driver_lock);
1106
1107         if (!driver_registered) {
1108                 mutex_unlock(&intel_pstate_driver_lock);
1109                 return -EAGAIN;
1110         }
1111
1112         cpu = all_cpu_data[0];
1113
1114         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1115         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1116         turbo_fp = div_fp(no_turbo, total);
1117         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1118
1119         mutex_unlock(&intel_pstate_driver_lock);
1120
1121         return sprintf(buf, "%u\n", turbo_pct);
1122 }
1123
1124 static ssize_t show_num_pstates(struct kobject *kobj,
1125                                 struct attribute *attr, char *buf)
1126 {
1127         struct cpudata *cpu;
1128         int total;
1129
1130         mutex_lock(&intel_pstate_driver_lock);
1131
1132         if (!driver_registered) {
1133                 mutex_unlock(&intel_pstate_driver_lock);
1134                 return -EAGAIN;
1135         }
1136
1137         cpu = all_cpu_data[0];
1138         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1139
1140         mutex_unlock(&intel_pstate_driver_lock);
1141
1142         return sprintf(buf, "%u\n", total);
1143 }
1144
1145 static ssize_t show_no_turbo(struct kobject *kobj,
1146                              struct attribute *attr, char *buf)
1147 {
1148         ssize_t ret;
1149
1150         mutex_lock(&intel_pstate_driver_lock);
1151
1152         if (!driver_registered) {
1153                 mutex_unlock(&intel_pstate_driver_lock);
1154                 return -EAGAIN;
1155         }
1156
1157         update_turbo_state();
1158         if (limits->turbo_disabled)
1159                 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
1160         else
1161                 ret = sprintf(buf, "%u\n", limits->no_turbo);
1162
1163         mutex_unlock(&intel_pstate_driver_lock);
1164
1165         return ret;
1166 }
1167
1168 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1169                               const char *buf, size_t count)
1170 {
1171         unsigned int input;
1172         int ret;
1173
1174         ret = sscanf(buf, "%u", &input);
1175         if (ret != 1)
1176                 return -EINVAL;
1177
1178         mutex_lock(&intel_pstate_driver_lock);
1179
1180         if (!driver_registered) {
1181                 mutex_unlock(&intel_pstate_driver_lock);
1182                 return -EAGAIN;
1183         }
1184
1185         mutex_lock(&intel_pstate_limits_lock);
1186
1187         update_turbo_state();
1188         if (limits->turbo_disabled) {
1189                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1190                 mutex_unlock(&intel_pstate_limits_lock);
1191                 mutex_unlock(&intel_pstate_driver_lock);
1192                 return -EPERM;
1193         }
1194
1195         limits->no_turbo = clamp_t(int, input, 0, 1);
1196
1197         intel_pstate_update_policies();
1198
1199         mutex_unlock(&intel_pstate_limits_lock);
1200
1201         mutex_unlock(&intel_pstate_driver_lock);
1202
1203         return count;
1204 }
1205
1206 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1207                                   const char *buf, size_t count)
1208 {
1209         unsigned int input;
1210         int ret;
1211
1212         ret = sscanf(buf, "%u", &input);
1213         if (ret != 1)
1214                 return -EINVAL;
1215
1216         mutex_lock(&intel_pstate_driver_lock);
1217
1218         if (!driver_registered) {
1219                 mutex_unlock(&intel_pstate_driver_lock);
1220                 return -EAGAIN;
1221         }
1222
1223         mutex_lock(&intel_pstate_limits_lock);
1224
1225         limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
1226         limits->max_perf_pct = min(limits->max_policy_pct,
1227                                    limits->max_sysfs_pct);
1228         limits->max_perf_pct = max(limits->min_policy_pct,
1229                                    limits->max_perf_pct);
1230         limits->max_perf_pct = max(limits->min_perf_pct,
1231                                    limits->max_perf_pct);
1232         limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
1233
1234         intel_pstate_update_policies();
1235
1236         mutex_unlock(&intel_pstate_limits_lock);
1237
1238         mutex_unlock(&intel_pstate_driver_lock);
1239
1240         return count;
1241 }
1242
1243 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1244                                   const char *buf, size_t count)
1245 {
1246         unsigned int input;
1247         int ret;
1248
1249         ret = sscanf(buf, "%u", &input);
1250         if (ret != 1)
1251                 return -EINVAL;
1252
1253         mutex_lock(&intel_pstate_driver_lock);
1254
1255         if (!driver_registered) {
1256                 mutex_unlock(&intel_pstate_driver_lock);
1257                 return -EAGAIN;
1258         }
1259
1260         mutex_lock(&intel_pstate_limits_lock);
1261
1262         limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
1263         limits->min_perf_pct = max(limits->min_policy_pct,
1264                                    limits->min_sysfs_pct);
1265         limits->min_perf_pct = min(limits->max_policy_pct,
1266                                    limits->min_perf_pct);
1267         limits->min_perf_pct = min(limits->max_perf_pct,
1268                                    limits->min_perf_pct);
1269         limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
1270
1271         intel_pstate_update_policies();
1272
1273         mutex_unlock(&intel_pstate_limits_lock);
1274
1275         mutex_unlock(&intel_pstate_driver_lock);
1276
1277         return count;
1278 }
1279
1280 show_one(max_perf_pct, max_perf_pct);
1281 show_one(min_perf_pct, min_perf_pct);
1282
1283 define_one_global_rw(status);
1284 define_one_global_rw(no_turbo);
1285 define_one_global_rw(max_perf_pct);
1286 define_one_global_rw(min_perf_pct);
1287 define_one_global_ro(turbo_pct);
1288 define_one_global_ro(num_pstates);
1289
1290 static struct attribute *intel_pstate_attributes[] = {
1291         &status.attr,
1292         &no_turbo.attr,
1293         &turbo_pct.attr,
1294         &num_pstates.attr,
1295         NULL
1296 };
1297
1298 static struct attribute_group intel_pstate_attr_group = {
1299         .attrs = intel_pstate_attributes,
1300 };
1301
1302 static void __init intel_pstate_sysfs_expose_params(void)
1303 {
1304         struct kobject *intel_pstate_kobject;
1305         int rc;
1306
1307         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1308                                                 &cpu_subsys.dev_root->kobj);
1309         if (WARN_ON(!intel_pstate_kobject))
1310                 return;
1311
1312         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1313         if (WARN_ON(rc))
1314                 return;
1315
1316         /*
1317          * If per cpu limits are enforced there are no global limits, so
1318          * return without creating max/min_perf_pct attributes
1319          */
1320         if (per_cpu_limits)
1321                 return;
1322
1323         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1324         WARN_ON(rc);
1325
1326         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1327         WARN_ON(rc);
1328
1329 }
1330 /************************** sysfs end ************************/
1331
1332 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1333 {
1334         /* First disable HWP notification interrupt as we don't process them */
1335         if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1336                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1337
1338         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1339         cpudata->epp_policy = 0;
1340         if (cpudata->epp_default == -EINVAL)
1341                 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1342 }
1343
1344 #define MSR_IA32_POWER_CTL_BIT_EE       19
1345
1346 /* Disable energy efficiency optimization */
1347 static void intel_pstate_disable_ee(int cpu)
1348 {
1349         u64 power_ctl;
1350         int ret;
1351
1352         ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1353         if (ret)
1354                 return;
1355
1356         if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1357                 pr_info("Disabling energy efficiency optimization\n");
1358                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1359                 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1360         }
1361 }
1362
1363 static int atom_get_min_pstate(void)
1364 {
1365         u64 value;
1366
1367         rdmsrl(ATOM_RATIOS, value);
1368         return (value >> 8) & 0x7F;
1369 }
1370
1371 static int atom_get_max_pstate(void)
1372 {
1373         u64 value;
1374
1375         rdmsrl(ATOM_RATIOS, value);
1376         return (value >> 16) & 0x7F;
1377 }
1378
1379 static int atom_get_turbo_pstate(void)
1380 {
1381         u64 value;
1382
1383         rdmsrl(ATOM_TURBO_RATIOS, value);
1384         return value & 0x7F;
1385 }
1386
1387 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1388 {
1389         u64 val;
1390         int32_t vid_fp;
1391         u32 vid;
1392
1393         val = (u64)pstate << 8;
1394         if (limits->no_turbo && !limits->turbo_disabled)
1395                 val |= (u64)1 << 32;
1396
1397         vid_fp = cpudata->vid.min + mul_fp(
1398                 int_tofp(pstate - cpudata->pstate.min_pstate),
1399                 cpudata->vid.ratio);
1400
1401         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1402         vid = ceiling_fp(vid_fp);
1403
1404         if (pstate > cpudata->pstate.max_pstate)
1405                 vid = cpudata->vid.turbo;
1406
1407         return val | vid;
1408 }
1409
1410 static int silvermont_get_scaling(void)
1411 {
1412         u64 value;
1413         int i;
1414         /* Defined in Table 35-6 from SDM (Sept 2015) */
1415         static int silvermont_freq_table[] = {
1416                 83300, 100000, 133300, 116700, 80000};
1417
1418         rdmsrl(MSR_FSB_FREQ, value);
1419         i = value & 0x7;
1420         WARN_ON(i > 4);
1421
1422         return silvermont_freq_table[i];
1423 }
1424
1425 static int airmont_get_scaling(void)
1426 {
1427         u64 value;
1428         int i;
1429         /* Defined in Table 35-10 from SDM (Sept 2015) */
1430         static int airmont_freq_table[] = {
1431                 83300, 100000, 133300, 116700, 80000,
1432                 93300, 90000, 88900, 87500};
1433
1434         rdmsrl(MSR_FSB_FREQ, value);
1435         i = value & 0xF;
1436         WARN_ON(i > 8);
1437
1438         return airmont_freq_table[i];
1439 }
1440
1441 static void atom_get_vid(struct cpudata *cpudata)
1442 {
1443         u64 value;
1444
1445         rdmsrl(ATOM_VIDS, value);
1446         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1447         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1448         cpudata->vid.ratio = div_fp(
1449                 cpudata->vid.max - cpudata->vid.min,
1450                 int_tofp(cpudata->pstate.max_pstate -
1451                         cpudata->pstate.min_pstate));
1452
1453         rdmsrl(ATOM_TURBO_VIDS, value);
1454         cpudata->vid.turbo = value & 0x7f;
1455 }
1456
1457 static int core_get_min_pstate(void)
1458 {
1459         u64 value;
1460
1461         rdmsrl(MSR_PLATFORM_INFO, value);
1462         return (value >> 40) & 0xFF;
1463 }
1464
1465 static int core_get_max_pstate_physical(void)
1466 {
1467         u64 value;
1468
1469         rdmsrl(MSR_PLATFORM_INFO, value);
1470         return (value >> 8) & 0xFF;
1471 }
1472
1473 static int core_get_tdp_ratio(u64 plat_info)
1474 {
1475         /* Check how many TDP levels present */
1476         if (plat_info & 0x600000000) {
1477                 u64 tdp_ctrl;
1478                 u64 tdp_ratio;
1479                 int tdp_msr;
1480                 int err;
1481
1482                 /* Get the TDP level (0, 1, 2) to get ratios */
1483                 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1484                 if (err)
1485                         return err;
1486
1487                 /* TDP MSR are continuous starting at 0x648 */
1488                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1489                 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1490                 if (err)
1491                         return err;
1492
1493                 /* For level 1 and 2, bits[23:16] contain the ratio */
1494                 if (tdp_ctrl & 0x03)
1495                         tdp_ratio >>= 16;
1496
1497                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1498                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1499
1500                 return (int)tdp_ratio;
1501         }
1502
1503         return -ENXIO;
1504 }
1505
1506 static int core_get_max_pstate(void)
1507 {
1508         u64 tar;
1509         u64 plat_info;
1510         int max_pstate;
1511         int tdp_ratio;
1512         int err;
1513
1514         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1515         max_pstate = (plat_info >> 8) & 0xFF;
1516
1517         tdp_ratio = core_get_tdp_ratio(plat_info);
1518         if (tdp_ratio <= 0)
1519                 return max_pstate;
1520
1521         if (hwp_active) {
1522                 /* Turbo activation ratio is not used on HWP platforms */
1523                 return tdp_ratio;
1524         }
1525
1526         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1527         if (!err) {
1528                 int tar_levels;
1529
1530                 /* Do some sanity checking for safety */
1531                 tar_levels = tar & 0xff;
1532                 if (tdp_ratio - 1 == tar_levels) {
1533                         max_pstate = tar_levels;
1534                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1535                 }
1536         }
1537
1538         return max_pstate;
1539 }
1540
1541 static int core_get_turbo_pstate(void)
1542 {
1543         u64 value;
1544         int nont, ret;
1545
1546         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1547         nont = core_get_max_pstate();
1548         ret = (value) & 255;
1549         if (ret <= nont)
1550                 ret = nont;
1551         return ret;
1552 }
1553
1554 static inline int core_get_scaling(void)
1555 {
1556         return 100000;
1557 }
1558
1559 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1560 {
1561         u64 val;
1562
1563         val = (u64)pstate << 8;
1564         if (limits->no_turbo && !limits->turbo_disabled)
1565                 val |= (u64)1 << 32;
1566
1567         return val;
1568 }
1569
1570 static int knl_get_turbo_pstate(void)
1571 {
1572         u64 value;
1573         int nont, ret;
1574
1575         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1576         nont = core_get_max_pstate();
1577         ret = (((value) >> 8) & 0xFF);
1578         if (ret <= nont)
1579                 ret = nont;
1580         return ret;
1581 }
1582
1583 static struct cpu_defaults core_params = {
1584         .pid_policy = {
1585                 .sample_rate_ms = 10,
1586                 .deadband = 0,
1587                 .setpoint = 97,
1588                 .p_gain_pct = 20,
1589                 .d_gain_pct = 0,
1590                 .i_gain_pct = 0,
1591         },
1592         .funcs = {
1593                 .get_max = core_get_max_pstate,
1594                 .get_max_physical = core_get_max_pstate_physical,
1595                 .get_min = core_get_min_pstate,
1596                 .get_turbo = core_get_turbo_pstate,
1597                 .get_scaling = core_get_scaling,
1598                 .get_val = core_get_val,
1599                 .get_target_pstate = get_target_pstate_use_performance,
1600         },
1601 };
1602
1603 static const struct cpu_defaults silvermont_params = {
1604         .pid_policy = {
1605                 .sample_rate_ms = 10,
1606                 .deadband = 0,
1607                 .setpoint = 60,
1608                 .p_gain_pct = 14,
1609                 .d_gain_pct = 0,
1610                 .i_gain_pct = 4,
1611         },
1612         .funcs = {
1613                 .get_max = atom_get_max_pstate,
1614                 .get_max_physical = atom_get_max_pstate,
1615                 .get_min = atom_get_min_pstate,
1616                 .get_turbo = atom_get_turbo_pstate,
1617                 .get_val = atom_get_val,
1618                 .get_scaling = silvermont_get_scaling,
1619                 .get_vid = atom_get_vid,
1620                 .get_target_pstate = get_target_pstate_use_cpu_load,
1621         },
1622 };
1623
1624 static const struct cpu_defaults airmont_params = {
1625         .pid_policy = {
1626                 .sample_rate_ms = 10,
1627                 .deadband = 0,
1628                 .setpoint = 60,
1629                 .p_gain_pct = 14,
1630                 .d_gain_pct = 0,
1631                 .i_gain_pct = 4,
1632         },
1633         .funcs = {
1634                 .get_max = atom_get_max_pstate,
1635                 .get_max_physical = atom_get_max_pstate,
1636                 .get_min = atom_get_min_pstate,
1637                 .get_turbo = atom_get_turbo_pstate,
1638                 .get_val = atom_get_val,
1639                 .get_scaling = airmont_get_scaling,
1640                 .get_vid = atom_get_vid,
1641                 .get_target_pstate = get_target_pstate_use_cpu_load,
1642         },
1643 };
1644
1645 static const struct cpu_defaults knl_params = {
1646         .pid_policy = {
1647                 .sample_rate_ms = 10,
1648                 .deadband = 0,
1649                 .setpoint = 97,
1650                 .p_gain_pct = 20,
1651                 .d_gain_pct = 0,
1652                 .i_gain_pct = 0,
1653         },
1654         .funcs = {
1655                 .get_max = core_get_max_pstate,
1656                 .get_max_physical = core_get_max_pstate_physical,
1657                 .get_min = core_get_min_pstate,
1658                 .get_turbo = knl_get_turbo_pstate,
1659                 .get_scaling = core_get_scaling,
1660                 .get_val = core_get_val,
1661                 .get_target_pstate = get_target_pstate_use_performance,
1662         },
1663 };
1664
1665 static const struct cpu_defaults bxt_params = {
1666         .pid_policy = {
1667                 .sample_rate_ms = 10,
1668                 .deadband = 0,
1669                 .setpoint = 60,
1670                 .p_gain_pct = 14,
1671                 .d_gain_pct = 0,
1672                 .i_gain_pct = 4,
1673         },
1674         .funcs = {
1675                 .get_max = core_get_max_pstate,
1676                 .get_max_physical = core_get_max_pstate_physical,
1677                 .get_min = core_get_min_pstate,
1678                 .get_turbo = core_get_turbo_pstate,
1679                 .get_scaling = core_get_scaling,
1680                 .get_val = core_get_val,
1681                 .get_target_pstate = get_target_pstate_use_cpu_load,
1682         },
1683 };
1684
1685 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1686 {
1687         int max_perf = cpu->pstate.turbo_pstate;
1688         int max_perf_adj;
1689         int min_perf;
1690         struct perf_limits *perf_limits = limits;
1691
1692         if (limits->no_turbo || limits->turbo_disabled)
1693                 max_perf = cpu->pstate.max_pstate;
1694
1695         if (per_cpu_limits)
1696                 perf_limits = cpu->perf_limits;
1697
1698         /*
1699          * performance can be limited by user through sysfs, by cpufreq
1700          * policy, or by cpu specific default values determined through
1701          * experimentation.
1702          */
1703         max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf);
1704         *max = clamp_t(int, max_perf_adj,
1705                         cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
1706
1707         min_perf = fp_ext_toint(max_perf * perf_limits->min_perf);
1708         *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
1709 }
1710
1711 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1712 {
1713         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1714         cpu->pstate.current_pstate = pstate;
1715         /*
1716          * Generally, there is no guarantee that this code will always run on
1717          * the CPU being updated, so force the register update to run on the
1718          * right CPU.
1719          */
1720         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1721                       pstate_funcs.get_val(cpu, pstate));
1722 }
1723
1724 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1725 {
1726         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1727 }
1728
1729 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1730 {
1731         int min_pstate, max_pstate;
1732
1733         update_turbo_state();
1734         intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1735         intel_pstate_set_pstate(cpu, max_pstate);
1736 }
1737
1738 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1739 {
1740         cpu->pstate.min_pstate = pstate_funcs.get_min();
1741         cpu->pstate.max_pstate = pstate_funcs.get_max();
1742         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1743         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1744         cpu->pstate.scaling = pstate_funcs.get_scaling();
1745         cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1746         cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1747
1748         if (pstate_funcs.get_vid)
1749                 pstate_funcs.get_vid(cpu);
1750
1751         intel_pstate_set_min_pstate(cpu);
1752 }
1753
1754 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1755 {
1756         struct sample *sample = &cpu->sample;
1757
1758         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1759 }
1760
1761 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1762 {
1763         u64 aperf, mperf;
1764         unsigned long flags;
1765         u64 tsc;
1766
1767         local_irq_save(flags);
1768         rdmsrl(MSR_IA32_APERF, aperf);
1769         rdmsrl(MSR_IA32_MPERF, mperf);
1770         tsc = rdtsc();
1771         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1772                 local_irq_restore(flags);
1773                 return false;
1774         }
1775         local_irq_restore(flags);
1776
1777         cpu->last_sample_time = cpu->sample.time;
1778         cpu->sample.time = time;
1779         cpu->sample.aperf = aperf;
1780         cpu->sample.mperf = mperf;
1781         cpu->sample.tsc =  tsc;
1782         cpu->sample.aperf -= cpu->prev_aperf;
1783         cpu->sample.mperf -= cpu->prev_mperf;
1784         cpu->sample.tsc -= cpu->prev_tsc;
1785
1786         cpu->prev_aperf = aperf;
1787         cpu->prev_mperf = mperf;
1788         cpu->prev_tsc = tsc;
1789         /*
1790          * First time this function is invoked in a given cycle, all of the
1791          * previous sample data fields are equal to zero or stale and they must
1792          * be populated with meaningful numbers for things to work, so assume
1793          * that sample.time will always be reset before setting the utilization
1794          * update hook and make the caller skip the sample then.
1795          */
1796         return !!cpu->last_sample_time;
1797 }
1798
1799 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1800 {
1801         return mul_ext_fp(cpu->sample.core_avg_perf,
1802                           cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1803 }
1804
1805 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1806 {
1807         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1808                           cpu->sample.core_avg_perf);
1809 }
1810
1811 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1812 {
1813         struct sample *sample = &cpu->sample;
1814         int32_t busy_frac, boost;
1815         int target, avg_pstate;
1816
1817         busy_frac = div_fp(sample->mperf, sample->tsc);
1818
1819         boost = cpu->iowait_boost;
1820         cpu->iowait_boost >>= 1;
1821
1822         if (busy_frac < boost)
1823                 busy_frac = boost;
1824
1825         sample->busy_scaled = busy_frac * 100;
1826
1827         target = limits->no_turbo || limits->turbo_disabled ?
1828                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1829         target += target >> 2;
1830         target = mul_fp(target, busy_frac);
1831         if (target < cpu->pstate.min_pstate)
1832                 target = cpu->pstate.min_pstate;
1833
1834         /*
1835          * If the average P-state during the previous cycle was higher than the
1836          * current target, add 50% of the difference to the target to reduce
1837          * possible performance oscillations and offset possible performance
1838          * loss related to moving the workload from one CPU to another within
1839          * a package/module.
1840          */
1841         avg_pstate = get_avg_pstate(cpu);
1842         if (avg_pstate > target)
1843                 target += (avg_pstate - target) >> 1;
1844
1845         return target;
1846 }
1847
1848 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1849 {
1850         int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1851         u64 duration_ns;
1852
1853         /*
1854          * perf_scaled is the ratio of the average P-state during the last
1855          * sampling period to the P-state requested last time (in percent).
1856          *
1857          * That measures the system's response to the previous P-state
1858          * selection.
1859          */
1860         max_pstate = cpu->pstate.max_pstate_physical;
1861         current_pstate = cpu->pstate.current_pstate;
1862         perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1863                                div_fp(100 * max_pstate, current_pstate));
1864
1865         /*
1866          * Since our utilization update callback will not run unless we are
1867          * in C0, check if the actual elapsed time is significantly greater (3x)
1868          * than our sample interval.  If it is, then we were idle for a long
1869          * enough period of time to adjust our performance metric.
1870          */
1871         duration_ns = cpu->sample.time - cpu->last_sample_time;
1872         if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1873                 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1874                 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1875         } else {
1876                 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1877                 if (sample_ratio < int_tofp(1))
1878                         perf_scaled = 0;
1879         }
1880
1881         cpu->sample.busy_scaled = perf_scaled;
1882         return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1883 }
1884
1885 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1886 {
1887         int max_perf, min_perf;
1888
1889         intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1890         pstate = clamp_t(int, pstate, min_perf, max_perf);
1891         return pstate;
1892 }
1893
1894 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1895 {
1896         if (pstate == cpu->pstate.current_pstate)
1897                 return;
1898
1899         cpu->pstate.current_pstate = pstate;
1900         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1901 }
1902
1903 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1904 {
1905         int from, target_pstate;
1906         struct sample *sample;
1907
1908         from = cpu->pstate.current_pstate;
1909
1910         target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1911                 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
1912
1913         update_turbo_state();
1914
1915         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1916         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1917         intel_pstate_update_pstate(cpu, target_pstate);
1918
1919         sample = &cpu->sample;
1920         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1921                 fp_toint(sample->busy_scaled),
1922                 from,
1923                 cpu->pstate.current_pstate,
1924                 sample->mperf,
1925                 sample->aperf,
1926                 sample->tsc,
1927                 get_avg_frequency(cpu),
1928                 fp_toint(cpu->iowait_boost * 100));
1929 }
1930
1931 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1932                                      unsigned int flags)
1933 {
1934         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1935         u64 delta_ns;
1936
1937         if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
1938                 if (flags & SCHED_CPUFREQ_IOWAIT) {
1939                         cpu->iowait_boost = int_tofp(1);
1940                 } else if (cpu->iowait_boost) {
1941                         /* Clear iowait_boost if the CPU may have been idle. */
1942                         delta_ns = time - cpu->last_update;
1943                         if (delta_ns > TICK_NSEC)
1944                                 cpu->iowait_boost = 0;
1945                 }
1946                 cpu->last_update = time;
1947         }
1948
1949         delta_ns = time - cpu->sample.time;
1950         if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1951                 bool sample_taken = intel_pstate_sample(cpu, time);
1952
1953                 if (sample_taken) {
1954                         intel_pstate_calc_avg_perf(cpu);
1955                         if (!hwp_active)
1956                                 intel_pstate_adjust_busy_pstate(cpu);
1957                 }
1958         }
1959 }
1960
1961 #define ICPU(model, policy) \
1962         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1963                         (unsigned long)&policy }
1964
1965 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1966         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_params),
1967         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_params),
1968         ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       silvermont_params),
1969         ICPU(INTEL_FAM6_IVYBRIDGE,              core_params),
1970         ICPU(INTEL_FAM6_HASWELL_CORE,           core_params),
1971         ICPU(INTEL_FAM6_BROADWELL_CORE,         core_params),
1972         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_params),
1973         ICPU(INTEL_FAM6_HASWELL_X,              core_params),
1974         ICPU(INTEL_FAM6_HASWELL_ULT,            core_params),
1975         ICPU(INTEL_FAM6_HASWELL_GT3E,           core_params),
1976         ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_params),
1977         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_params),
1978         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_params),
1979         ICPU(INTEL_FAM6_BROADWELL_X,            core_params),
1980         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_params),
1981         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_params),
1982         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_params),
1983         ICPU(INTEL_FAM6_XEON_PHI_KNM,           knl_params),
1984         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          bxt_params),
1985         {}
1986 };
1987 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1988
1989 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1990         ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1991         ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1992         ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
1993         {}
1994 };
1995
1996 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1997         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_params),
1998         {}
1999 };
2000
2001 static int intel_pstate_init_cpu(unsigned int cpunum)
2002 {
2003         struct cpudata *cpu;
2004
2005         cpu = all_cpu_data[cpunum];
2006
2007         if (!cpu) {
2008                 unsigned int size = sizeof(struct cpudata);
2009
2010                 if (per_cpu_limits)
2011                         size += sizeof(struct perf_limits);
2012
2013                 cpu = kzalloc(size, GFP_KERNEL);
2014                 if (!cpu)
2015                         return -ENOMEM;
2016
2017                 all_cpu_data[cpunum] = cpu;
2018                 if (per_cpu_limits)
2019                         cpu->perf_limits = (struct perf_limits *)(cpu + 1);
2020
2021                 cpu->epp_default = -EINVAL;
2022                 cpu->epp_powersave = -EINVAL;
2023                 cpu->epp_saved = -EINVAL;
2024         }
2025
2026         cpu = all_cpu_data[cpunum];
2027
2028         cpu->cpu = cpunum;
2029
2030         if (hwp_active) {
2031                 const struct x86_cpu_id *id;
2032
2033                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
2034                 if (id)
2035                         intel_pstate_disable_ee(cpunum);
2036
2037                 intel_pstate_hwp_enable(cpu);
2038                 pid_params.sample_rate_ms = 50;
2039                 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
2040         }
2041
2042         intel_pstate_get_cpu_pstates(cpu);
2043
2044         intel_pstate_busy_pid_reset(cpu);
2045
2046         pr_debug("controlling: cpu %d\n", cpunum);
2047
2048         return 0;
2049 }
2050
2051 static unsigned int intel_pstate_get(unsigned int cpu_num)
2052 {
2053         struct cpudata *cpu = all_cpu_data[cpu_num];
2054
2055         return cpu ? get_avg_frequency(cpu) : 0;
2056 }
2057
2058 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2059 {
2060         struct cpudata *cpu = all_cpu_data[cpu_num];
2061
2062         if (cpu->update_util_set)
2063                 return;
2064
2065         /* Prevent intel_pstate_update_util() from using stale data. */
2066         cpu->sample.time = 0;
2067         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2068                                      intel_pstate_update_util);
2069         cpu->update_util_set = true;
2070 }
2071
2072 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2073 {
2074         struct cpudata *cpu_data = all_cpu_data[cpu];
2075
2076         if (!cpu_data->update_util_set)
2077                 return;
2078
2079         cpufreq_remove_update_util_hook(cpu);
2080         cpu_data->update_util_set = false;
2081         synchronize_sched();
2082 }
2083
2084 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
2085                                             struct perf_limits *limits)
2086 {
2087
2088         limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
2089                                               policy->cpuinfo.max_freq);
2090         limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100);
2091         if (policy->max == policy->min) {
2092                 limits->min_policy_pct = limits->max_policy_pct;
2093         } else {
2094                 limits->min_policy_pct = DIV_ROUND_UP(policy->min * 100,
2095                                                       policy->cpuinfo.max_freq);
2096                 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct,
2097                                                  0, 100);
2098         }
2099
2100         /* Normalize user input to [min_policy_pct, max_policy_pct] */
2101         limits->min_perf_pct = max(limits->min_policy_pct,
2102                                    limits->min_sysfs_pct);
2103         limits->min_perf_pct = min(limits->max_policy_pct,
2104                                    limits->min_perf_pct);
2105         limits->max_perf_pct = min(limits->max_policy_pct,
2106                                    limits->max_sysfs_pct);
2107         limits->max_perf_pct = max(limits->min_policy_pct,
2108                                    limits->max_perf_pct);
2109
2110         /* Make sure min_perf_pct <= max_perf_pct */
2111         limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
2112
2113         limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
2114         limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
2115         limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS);
2116         limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS);
2117
2118         pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
2119                  limits->max_perf_pct, limits->min_perf_pct);
2120 }
2121
2122 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2123 {
2124         struct cpudata *cpu;
2125         struct perf_limits *perf_limits = NULL;
2126
2127         if (!policy->cpuinfo.max_freq)
2128                 return -ENODEV;
2129
2130         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2131                  policy->cpuinfo.max_freq, policy->max);
2132
2133         cpu = all_cpu_data[policy->cpu];
2134         cpu->policy = policy->policy;
2135
2136         if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2137             policy->max < policy->cpuinfo.max_freq &&
2138             policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
2139                 pr_debug("policy->max > max non turbo frequency\n");
2140                 policy->max = policy->cpuinfo.max_freq;
2141         }
2142
2143         if (per_cpu_limits)
2144                 perf_limits = cpu->perf_limits;
2145
2146         mutex_lock(&intel_pstate_limits_lock);
2147
2148         if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
2149                 if (!perf_limits) {
2150                         limits = &performance_limits;
2151                         perf_limits = limits;
2152                 }
2153                 if (policy->max >= policy->cpuinfo.max_freq &&
2154                     !limits->no_turbo) {
2155                         pr_debug("set performance\n");
2156                         intel_pstate_set_performance_limits(perf_limits);
2157                         goto out;
2158                 }
2159         } else {
2160                 pr_debug("set powersave\n");
2161                 if (!perf_limits) {
2162                         limits = &powersave_limits;
2163                         perf_limits = limits;
2164                 }
2165
2166         }
2167
2168         intel_pstate_update_perf_limits(policy, perf_limits);
2169  out:
2170         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2171                 /*
2172                  * NOHZ_FULL CPUs need this as the governor callback may not
2173                  * be invoked on them.
2174                  */
2175                 intel_pstate_clear_update_util_hook(policy->cpu);
2176                 intel_pstate_max_within_limits(cpu);
2177         }
2178
2179         intel_pstate_set_update_util_hook(policy->cpu);
2180
2181         intel_pstate_hwp_set_policy(policy);
2182
2183         mutex_unlock(&intel_pstate_limits_lock);
2184
2185         return 0;
2186 }
2187
2188 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2189 {
2190         struct cpudata *cpu = all_cpu_data[policy->cpu];
2191         struct perf_limits *perf_limits;
2192
2193         if (policy->policy == CPUFREQ_POLICY_PERFORMANCE)
2194                 perf_limits = &performance_limits;
2195         else
2196                 perf_limits = &powersave_limits;
2197
2198         update_turbo_state();
2199         policy->cpuinfo.max_freq = perf_limits->turbo_disabled ||
2200                                         perf_limits->no_turbo ?
2201                                         cpu->pstate.max_freq :
2202                                         cpu->pstate.turbo_freq;
2203
2204         cpufreq_verify_within_cpu_limits(policy);
2205
2206         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2207             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2208                 return -EINVAL;
2209
2210         /* When per-CPU limits are used, sysfs limits are not used */
2211         if (!per_cpu_limits) {
2212                 unsigned int max_freq, min_freq;
2213
2214                 max_freq = policy->cpuinfo.max_freq *
2215                                         perf_limits->max_sysfs_pct / 100;
2216                 min_freq = policy->cpuinfo.max_freq *
2217                                         perf_limits->min_sysfs_pct / 100;
2218                 cpufreq_verify_within_limits(policy, min_freq, max_freq);
2219         }
2220
2221         return 0;
2222 }
2223
2224 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2225 {
2226         intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2227 }
2228
2229 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2230 {
2231         pr_debug("CPU %d exiting\n", policy->cpu);
2232
2233         intel_pstate_clear_update_util_hook(policy->cpu);
2234         if (hwp_active)
2235                 intel_pstate_hwp_save_state(policy);
2236         else
2237                 intel_cpufreq_stop_cpu(policy);
2238 }
2239
2240 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2241 {
2242         intel_pstate_exit_perf_limits(policy);
2243
2244         policy->fast_switch_possible = false;
2245
2246         return 0;
2247 }
2248
2249 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2250 {
2251         struct cpudata *cpu;
2252         int rc;
2253
2254         rc = intel_pstate_init_cpu(policy->cpu);
2255         if (rc)
2256                 return rc;
2257
2258         cpu = all_cpu_data[policy->cpu];
2259
2260         /*
2261          * We need sane value in the cpu->perf_limits, so inherit from global
2262          * perf_limits limits, which are seeded with values based on the
2263          * CONFIG_CPU_FREQ_DEFAULT_GOV_*, during boot up.
2264          */
2265         if (per_cpu_limits)
2266                 memcpy(cpu->perf_limits, limits, sizeof(struct perf_limits));
2267
2268         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2269         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2270
2271         /* cpuinfo and default policy values */
2272         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2273         update_turbo_state();
2274         policy->cpuinfo.max_freq = limits->turbo_disabled ?
2275                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2276         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2277
2278         intel_pstate_init_acpi_perf_limits(policy);
2279         cpumask_set_cpu(policy->cpu, policy->cpus);
2280
2281         policy->fast_switch_possible = true;
2282
2283         return 0;
2284 }
2285
2286 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2287 {
2288         int ret = __intel_pstate_cpu_init(policy);
2289
2290         if (ret)
2291                 return ret;
2292
2293         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2294         if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
2295                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2296         else
2297                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2298
2299         return 0;
2300 }
2301
2302 static struct cpufreq_driver intel_pstate = {
2303         .flags          = CPUFREQ_CONST_LOOPS,
2304         .verify         = intel_pstate_verify_policy,
2305         .setpolicy      = intel_pstate_set_policy,
2306         .suspend        = intel_pstate_hwp_save_state,
2307         .resume         = intel_pstate_resume,
2308         .get            = intel_pstate_get,
2309         .init           = intel_pstate_cpu_init,
2310         .exit           = intel_pstate_cpu_exit,
2311         .stop_cpu       = intel_pstate_stop_cpu,
2312         .name           = "intel_pstate",
2313 };
2314
2315 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2316 {
2317         struct cpudata *cpu = all_cpu_data[policy->cpu];
2318
2319         update_turbo_state();
2320         policy->cpuinfo.max_freq = limits->turbo_disabled ?
2321                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2322
2323         cpufreq_verify_within_cpu_limits(policy);
2324
2325         return 0;
2326 }
2327
2328 static unsigned int intel_cpufreq_turbo_update(struct cpudata *cpu,
2329                                                struct cpufreq_policy *policy,
2330                                                unsigned int target_freq)
2331 {
2332         unsigned int max_freq;
2333
2334         update_turbo_state();
2335
2336         max_freq = limits->no_turbo || limits->turbo_disabled ?
2337                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2338         policy->cpuinfo.max_freq = max_freq;
2339         if (policy->max > max_freq)
2340                 policy->max = max_freq;
2341
2342         if (target_freq > max_freq)
2343                 target_freq = max_freq;
2344
2345         return target_freq;
2346 }
2347
2348 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2349                                 unsigned int target_freq,
2350                                 unsigned int relation)
2351 {
2352         struct cpudata *cpu = all_cpu_data[policy->cpu];
2353         struct cpufreq_freqs freqs;
2354         int target_pstate;
2355
2356         freqs.old = policy->cur;
2357         freqs.new = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2358
2359         cpufreq_freq_transition_begin(policy, &freqs);
2360         switch (relation) {
2361         case CPUFREQ_RELATION_L:
2362                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2363                 break;
2364         case CPUFREQ_RELATION_H:
2365                 target_pstate = freqs.new / cpu->pstate.scaling;
2366                 break;
2367         default:
2368                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2369                 break;
2370         }
2371         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2372         if (target_pstate != cpu->pstate.current_pstate) {
2373                 cpu->pstate.current_pstate = target_pstate;
2374                 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2375                               pstate_funcs.get_val(cpu, target_pstate));
2376         }
2377         freqs.new = target_pstate * cpu->pstate.scaling;
2378         cpufreq_freq_transition_end(policy, &freqs, false);
2379
2380         return 0;
2381 }
2382
2383 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2384                                               unsigned int target_freq)
2385 {
2386         struct cpudata *cpu = all_cpu_data[policy->cpu];
2387         int target_pstate;
2388
2389         target_freq = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2390         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2391         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2392         intel_pstate_update_pstate(cpu, target_pstate);
2393         return target_pstate * cpu->pstate.scaling;
2394 }
2395
2396 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2397 {
2398         int ret = __intel_pstate_cpu_init(policy);
2399
2400         if (ret)
2401                 return ret;
2402
2403         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2404         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2405         policy->cur = policy->cpuinfo.min_freq;
2406
2407         return 0;
2408 }
2409
2410 static struct cpufreq_driver intel_cpufreq = {
2411         .flags          = CPUFREQ_CONST_LOOPS,
2412         .verify         = intel_cpufreq_verify_policy,
2413         .target         = intel_cpufreq_target,
2414         .fast_switch    = intel_cpufreq_fast_switch,
2415         .init           = intel_cpufreq_cpu_init,
2416         .exit           = intel_pstate_cpu_exit,
2417         .stop_cpu       = intel_cpufreq_stop_cpu,
2418         .name           = "intel_cpufreq",
2419 };
2420
2421 static struct cpufreq_driver *intel_pstate_driver = &intel_pstate;
2422
2423 static void intel_pstate_driver_cleanup(void)
2424 {
2425         unsigned int cpu;
2426
2427         get_online_cpus();
2428         for_each_online_cpu(cpu) {
2429                 if (all_cpu_data[cpu]) {
2430                         if (intel_pstate_driver == &intel_pstate)
2431                                 intel_pstate_clear_update_util_hook(cpu);
2432
2433                         kfree(all_cpu_data[cpu]);
2434                         all_cpu_data[cpu] = NULL;
2435                 }
2436         }
2437         put_online_cpus();
2438 }
2439
2440 static int intel_pstate_register_driver(void)
2441 {
2442         int ret;
2443
2444         intel_pstate_init_limits(&powersave_limits);
2445         intel_pstate_set_performance_limits(&performance_limits);
2446         if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE) &&
2447             intel_pstate_driver == &intel_pstate)
2448                 limits = &performance_limits;
2449         else
2450                 limits = &powersave_limits;
2451
2452         ret = cpufreq_register_driver(intel_pstate_driver);
2453         if (ret) {
2454                 intel_pstate_driver_cleanup();
2455                 return ret;
2456         }
2457
2458         mutex_lock(&intel_pstate_limits_lock);
2459         driver_registered = true;
2460         mutex_unlock(&intel_pstate_limits_lock);
2461
2462         if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2463             pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2464                 intel_pstate_debug_expose_params();
2465
2466         return 0;
2467 }
2468
2469 static int intel_pstate_unregister_driver(void)
2470 {
2471         if (hwp_active)
2472                 return -EBUSY;
2473
2474         if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2475             pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2476                 intel_pstate_debug_hide_params();
2477
2478         mutex_lock(&intel_pstate_limits_lock);
2479         driver_registered = false;
2480         mutex_unlock(&intel_pstate_limits_lock);
2481
2482         cpufreq_unregister_driver(intel_pstate_driver);
2483         intel_pstate_driver_cleanup();
2484
2485         return 0;
2486 }
2487
2488 static ssize_t intel_pstate_show_status(char *buf)
2489 {
2490         if (!driver_registered)
2491                 return sprintf(buf, "off\n");
2492
2493         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2494                                         "active" : "passive");
2495 }
2496
2497 static int intel_pstate_update_status(const char *buf, size_t size)
2498 {
2499         int ret;
2500
2501         if (size == 3 && !strncmp(buf, "off", size))
2502                 return driver_registered ?
2503                         intel_pstate_unregister_driver() : -EINVAL;
2504
2505         if (size == 6 && !strncmp(buf, "active", size)) {
2506                 if (driver_registered) {
2507                         if (intel_pstate_driver == &intel_pstate)
2508                                 return 0;
2509
2510                         ret = intel_pstate_unregister_driver();
2511                         if (ret)
2512                                 return ret;
2513                 }
2514
2515                 intel_pstate_driver = &intel_pstate;
2516                 return intel_pstate_register_driver();
2517         }
2518
2519         if (size == 7 && !strncmp(buf, "passive", size)) {
2520                 if (driver_registered) {
2521                         if (intel_pstate_driver != &intel_pstate)
2522                                 return 0;
2523
2524                         ret = intel_pstate_unregister_driver();
2525                         if (ret)
2526                                 return ret;
2527                 }
2528
2529                 intel_pstate_driver = &intel_cpufreq;
2530                 return intel_pstate_register_driver();
2531         }
2532
2533         return -EINVAL;
2534 }
2535
2536 static int no_load __initdata;
2537 static int no_hwp __initdata;
2538 static int hwp_only __initdata;
2539 static unsigned int force_load __initdata;
2540
2541 static int __init intel_pstate_msrs_not_valid(void)
2542 {
2543         if (!pstate_funcs.get_max() ||
2544             !pstate_funcs.get_min() ||
2545             !pstate_funcs.get_turbo())
2546                 return -ENODEV;
2547
2548         return 0;
2549 }
2550
2551 static void __init copy_pid_params(struct pstate_adjust_policy *policy)
2552 {
2553         pid_params.sample_rate_ms = policy->sample_rate_ms;
2554         pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
2555         pid_params.p_gain_pct = policy->p_gain_pct;
2556         pid_params.i_gain_pct = policy->i_gain_pct;
2557         pid_params.d_gain_pct = policy->d_gain_pct;
2558         pid_params.deadband = policy->deadband;
2559         pid_params.setpoint = policy->setpoint;
2560 }
2561
2562 #ifdef CONFIG_ACPI
2563 static void intel_pstate_use_acpi_profile(void)
2564 {
2565         if (acpi_gbl_FADT.preferred_profile == PM_MOBILE)
2566                 pstate_funcs.get_target_pstate =
2567                                 get_target_pstate_use_cpu_load;
2568 }
2569 #else
2570 static void intel_pstate_use_acpi_profile(void)
2571 {
2572 }
2573 #endif
2574
2575 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2576 {
2577         pstate_funcs.get_max   = funcs->get_max;
2578         pstate_funcs.get_max_physical = funcs->get_max_physical;
2579         pstate_funcs.get_min   = funcs->get_min;
2580         pstate_funcs.get_turbo = funcs->get_turbo;
2581         pstate_funcs.get_scaling = funcs->get_scaling;
2582         pstate_funcs.get_val   = funcs->get_val;
2583         pstate_funcs.get_vid   = funcs->get_vid;
2584         pstate_funcs.get_target_pstate = funcs->get_target_pstate;
2585
2586         intel_pstate_use_acpi_profile();
2587 }
2588
2589 #ifdef CONFIG_ACPI
2590
2591 static bool __init intel_pstate_no_acpi_pss(void)
2592 {
2593         int i;
2594
2595         for_each_possible_cpu(i) {
2596                 acpi_status status;
2597                 union acpi_object *pss;
2598                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2599                 struct acpi_processor *pr = per_cpu(processors, i);
2600
2601                 if (!pr)
2602                         continue;
2603
2604                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2605                 if (ACPI_FAILURE(status))
2606                         continue;
2607
2608                 pss = buffer.pointer;
2609                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2610                         kfree(pss);
2611                         return false;
2612                 }
2613
2614                 kfree(pss);
2615         }
2616
2617         return true;
2618 }
2619
2620 static bool __init intel_pstate_has_acpi_ppc(void)
2621 {
2622         int i;
2623
2624         for_each_possible_cpu(i) {
2625                 struct acpi_processor *pr = per_cpu(processors, i);
2626
2627                 if (!pr)
2628                         continue;
2629                 if (acpi_has_method(pr->handle, "_PPC"))
2630                         return true;
2631         }
2632         return false;
2633 }
2634
2635 enum {
2636         PSS,
2637         PPC,
2638 };
2639
2640 struct hw_vendor_info {
2641         u16  valid;
2642         char oem_id[ACPI_OEM_ID_SIZE];
2643         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2644         int  oem_pwr_table;
2645 };
2646
2647 /* Hardware vendor-specific info that has its own power management modes */
2648 static struct hw_vendor_info vendor_info[] __initdata = {
2649         {1, "HP    ", "ProLiant", PSS},
2650         {1, "ORACLE", "X4-2    ", PPC},
2651         {1, "ORACLE", "X4-2L   ", PPC},
2652         {1, "ORACLE", "X4-2B   ", PPC},
2653         {1, "ORACLE", "X3-2    ", PPC},
2654         {1, "ORACLE", "X3-2L   ", PPC},
2655         {1, "ORACLE", "X3-2B   ", PPC},
2656         {1, "ORACLE", "X4470M2 ", PPC},
2657         {1, "ORACLE", "X4270M3 ", PPC},
2658         {1, "ORACLE", "X4270M2 ", PPC},
2659         {1, "ORACLE", "X4170M2 ", PPC},
2660         {1, "ORACLE", "X4170 M3", PPC},
2661         {1, "ORACLE", "X4275 M3", PPC},
2662         {1, "ORACLE", "X6-2    ", PPC},
2663         {1, "ORACLE", "Sudbury ", PPC},
2664         {0, "", ""},
2665 };
2666
2667 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2668 {
2669         struct acpi_table_header hdr;
2670         struct hw_vendor_info *v_info;
2671         const struct x86_cpu_id *id;
2672         u64 misc_pwr;
2673
2674         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2675         if (id) {
2676                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2677                 if ( misc_pwr & (1 << 8))
2678                         return true;
2679         }
2680
2681         if (acpi_disabled ||
2682             ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2683                 return false;
2684
2685         for (v_info = vendor_info; v_info->valid; v_info++) {
2686                 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2687                         !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2688                                                 ACPI_OEM_TABLE_ID_SIZE))
2689                         switch (v_info->oem_pwr_table) {
2690                         case PSS:
2691                                 return intel_pstate_no_acpi_pss();
2692                         case PPC:
2693                                 return intel_pstate_has_acpi_ppc() &&
2694                                         (!force_load);
2695                         }
2696         }
2697
2698         return false;
2699 }
2700
2701 static void intel_pstate_request_control_from_smm(void)
2702 {
2703         /*
2704          * It may be unsafe to request P-states control from SMM if _PPC support
2705          * has not been enabled.
2706          */
2707         if (acpi_ppc)
2708                 acpi_processor_pstate_control();
2709 }
2710 #else /* CONFIG_ACPI not enabled */
2711 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2712 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2713 static inline void intel_pstate_request_control_from_smm(void) {}
2714 #endif /* CONFIG_ACPI */
2715
2716 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2717         { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2718         {}
2719 };
2720
2721 static int __init intel_pstate_init(void)
2722 {
2723         const struct x86_cpu_id *id;
2724         struct cpu_defaults *cpu_def;
2725         int rc = 0;
2726
2727         if (no_load)
2728                 return -ENODEV;
2729
2730         if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
2731                 copy_cpu_funcs(&core_params.funcs);
2732                 hwp_active++;
2733                 intel_pstate.attr = hwp_cpufreq_attrs;
2734                 goto hwp_cpu_matched;
2735         }
2736
2737         id = x86_match_cpu(intel_pstate_cpu_ids);
2738         if (!id)
2739                 return -ENODEV;
2740
2741         cpu_def = (struct cpu_defaults *)id->driver_data;
2742
2743         copy_pid_params(&cpu_def->pid_policy);
2744         copy_cpu_funcs(&cpu_def->funcs);
2745
2746         if (intel_pstate_msrs_not_valid())
2747                 return -ENODEV;
2748
2749 hwp_cpu_matched:
2750         /*
2751          * The Intel pstate driver will be ignored if the platform
2752          * firmware has its own power management modes.
2753          */
2754         if (intel_pstate_platform_pwr_mgmt_exists())
2755                 return -ENODEV;
2756
2757         if (!hwp_active && hwp_only)
2758                 return -ENOTSUPP;
2759
2760         pr_info("Intel P-state driver initializing\n");
2761
2762         all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2763         if (!all_cpu_data)
2764                 return -ENOMEM;
2765
2766         intel_pstate_request_control_from_smm();
2767
2768         intel_pstate_sysfs_expose_params();
2769
2770         mutex_lock(&intel_pstate_driver_lock);
2771         rc = intel_pstate_register_driver();
2772         mutex_unlock(&intel_pstate_driver_lock);
2773         if (rc)
2774                 return rc;
2775
2776         if (hwp_active)
2777                 pr_info("HWP enabled\n");
2778
2779         return 0;
2780 }
2781 device_initcall(intel_pstate_init);
2782
2783 static int __init intel_pstate_setup(char *str)
2784 {
2785         if (!str)
2786                 return -EINVAL;
2787
2788         if (!strcmp(str, "disable")) {
2789                 no_load = 1;
2790         } else if (!strcmp(str, "passive")) {
2791                 pr_info("Passive mode enabled\n");
2792                 intel_pstate_driver = &intel_cpufreq;
2793                 no_hwp = 1;
2794         }
2795         if (!strcmp(str, "no_hwp")) {
2796                 pr_info("HWP disabled\n");
2797                 no_hwp = 1;
2798         }
2799         if (!strcmp(str, "force"))
2800                 force_load = 1;
2801         if (!strcmp(str, "hwp_only"))
2802                 hwp_only = 1;
2803         if (!strcmp(str, "per_cpu_perf_limits"))
2804                 per_cpu_limits = true;
2805
2806 #ifdef CONFIG_ACPI
2807         if (!strcmp(str, "support_acpi_ppc"))
2808                 acpi_ppc = true;
2809 #endif
2810
2811         return 0;
2812 }
2813 early_param("intel_pstate", intel_pstate_setup);
2814
2815 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2816 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2817 MODULE_LICENSE("GPL");