1 // SPDX-License-Identifier: GPL-2.0+
3 * CPU frequency scaling support for Armada 37xx platform.
5 * Copyright (C) 2017 Marvell
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 #include <linux/clk.h>
11 #include <linux/cpu.h>
12 #include <linux/cpufreq.h>
13 #include <linux/err.h>
14 #include <linux/interrupt.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/of_irq.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_opp.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
26 #include "cpufreq-dt.h"
28 /* Clk register set */
29 #define ARMADA_37XX_CLK_TBG_SEL 0
30 #define ARMADA_37XX_CLK_TBG_SEL_CPU_OFF 22
32 /* Power management in North Bridge register set */
33 #define ARMADA_37XX_NB_L0L1 0x18
34 #define ARMADA_37XX_NB_L2L3 0x1C
35 #define ARMADA_37XX_NB_TBG_DIV_OFF 13
36 #define ARMADA_37XX_NB_TBG_DIV_MASK 0x7
37 #define ARMADA_37XX_NB_CLK_SEL_OFF 11
38 #define ARMADA_37XX_NB_CLK_SEL_MASK 0x1
39 #define ARMADA_37XX_NB_CLK_SEL_TBG 0x1
40 #define ARMADA_37XX_NB_TBG_SEL_OFF 9
41 #define ARMADA_37XX_NB_TBG_SEL_MASK 0x3
42 #define ARMADA_37XX_NB_VDD_SEL_OFF 6
43 #define ARMADA_37XX_NB_VDD_SEL_MASK 0x3
44 #define ARMADA_37XX_NB_CONFIG_SHIFT 16
45 #define ARMADA_37XX_NB_DYN_MOD 0x24
46 #define ARMADA_37XX_NB_CLK_SEL_EN BIT(26)
47 #define ARMADA_37XX_NB_TBG_EN BIT(28)
48 #define ARMADA_37XX_NB_DIV_EN BIT(29)
49 #define ARMADA_37XX_NB_VDD_EN BIT(30)
50 #define ARMADA_37XX_NB_DFS_EN BIT(31)
51 #define ARMADA_37XX_NB_CPU_LOAD 0x30
52 #define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3
53 #define ARMADA_37XX_DVFS_LOAD_0 0
54 #define ARMADA_37XX_DVFS_LOAD_1 1
55 #define ARMADA_37XX_DVFS_LOAD_2 2
56 #define ARMADA_37XX_DVFS_LOAD_3 3
58 /* AVS register set */
59 #define ARMADA_37XX_AVS_CTL0 0x0
60 #define ARMADA_37XX_AVS_ENABLE BIT(30)
61 #define ARMADA_37XX_AVS_HIGH_VDD_LIMIT 16
62 #define ARMADA_37XX_AVS_LOW_VDD_LIMIT 22
63 #define ARMADA_37XX_AVS_VDD_MASK 0x3F
64 #define ARMADA_37XX_AVS_CTL2 0x8
65 #define ARMADA_37XX_AVS_LOW_VDD_EN BIT(6)
66 #define ARMADA_37XX_AVS_VSET(x) (0x1C + 4 * (x))
69 * On Armada 37xx the Power management manages 4 level of CPU load,
70 * each level can be associated with a CPU clock source, a CPU
71 * divider, a VDD level, etc...
73 #define LOAD_LEVEL_NR 4
75 #define MIN_VOLT_MV 1000
76 #define MIN_VOLT_MV_FOR_L1_1000MHZ 1108
77 #define MIN_VOLT_MV_FOR_L1_1200MHZ 1155
79 /* AVS value for the corresponding voltage (in mV) */
80 static int avs_map[] = {
81 747, 758, 770, 782, 793, 805, 817, 828, 840, 852, 863, 875, 887, 898,
82 910, 922, 933, 945, 957, 968, 980, 992, 1003, 1015, 1027, 1038, 1050,
83 1062, 1073, 1085, 1097, 1108, 1120, 1132, 1143, 1155, 1167, 1178, 1190,
84 1202, 1213, 1225, 1237, 1248, 1260, 1272, 1283, 1295, 1307, 1318, 1330,
88 struct armada37xx_cpufreq_state {
89 struct platform_device *pdev;
90 struct device *cpu_dev;
91 struct regmap *regmap;
98 static struct armada37xx_cpufreq_state *armada37xx_cpufreq_state;
100 struct armada_37xx_dvfs {
102 u8 divider[LOAD_LEVEL_NR];
103 u32 avs[LOAD_LEVEL_NR];
106 static struct armada_37xx_dvfs armada_37xx_dvfs[] = {
107 {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} },
108 {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
109 {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
110 {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
113 static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq)
117 for (i = 0; i < ARRAY_SIZE(armada_37xx_dvfs); i++) {
118 if (freq == armada_37xx_dvfs[i].cpu_freq_max)
119 return &armada_37xx_dvfs[i];
122 pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000);
127 * Setup the four level managed by the hardware. Once the four level
128 * will be configured then the DVFS will be enabled.
130 static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
131 struct regmap *clk_base, u8 *divider)
136 /* Determine to which TBG clock is CPU connected */
137 regmap_read(clk_base, ARMADA_37XX_CLK_TBG_SEL, &cpu_tbg_sel);
138 cpu_tbg_sel >>= ARMADA_37XX_CLK_TBG_SEL_CPU_OFF;
139 cpu_tbg_sel &= ARMADA_37XX_NB_TBG_SEL_MASK;
141 for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
142 unsigned int reg, mask, val, offset = 0;
144 if (load_lvl <= ARMADA_37XX_DVFS_LOAD_1)
145 reg = ARMADA_37XX_NB_L0L1;
147 reg = ARMADA_37XX_NB_L2L3;
149 if (load_lvl == ARMADA_37XX_DVFS_LOAD_0 ||
150 load_lvl == ARMADA_37XX_DVFS_LOAD_2)
151 offset += ARMADA_37XX_NB_CONFIG_SHIFT;
153 /* Set cpu clock source, for all the level we use TBG */
154 val = ARMADA_37XX_NB_CLK_SEL_TBG << ARMADA_37XX_NB_CLK_SEL_OFF;
155 mask = (ARMADA_37XX_NB_CLK_SEL_MASK
156 << ARMADA_37XX_NB_CLK_SEL_OFF);
158 /* Set TBG index, for all levels we use the same TBG */
159 val = cpu_tbg_sel << ARMADA_37XX_NB_TBG_SEL_OFF;
160 mask = (ARMADA_37XX_NB_TBG_SEL_MASK
161 << ARMADA_37XX_NB_TBG_SEL_OFF);
164 * Set cpu divider based on the pre-computed array in
165 * order to have balanced step.
167 val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF;
168 mask |= (ARMADA_37XX_NB_TBG_DIV_MASK
169 << ARMADA_37XX_NB_TBG_DIV_OFF);
171 /* Set VDD divider which is actually the load level. */
172 val |= load_lvl << ARMADA_37XX_NB_VDD_SEL_OFF;
173 mask |= (ARMADA_37XX_NB_VDD_SEL_MASK
174 << ARMADA_37XX_NB_VDD_SEL_OFF);
179 regmap_update_bits(base, reg, mask, val);
184 * Find out the armada 37x supported AVS value whose voltage value is
185 * the round-up closest to the target voltage value.
187 static u32 armada_37xx_avs_val_match(int target_vm)
191 /* Find out the round-up closest supported voltage value */
192 for (avs = 0; avs < ARRAY_SIZE(avs_map); avs++)
193 if (avs_map[avs] >= target_vm)
197 * If all supported voltages are smaller than target one,
198 * choose the largest supported voltage
200 if (avs == ARRAY_SIZE(avs_map))
201 avs = ARRAY_SIZE(avs_map) - 1;
207 * For Armada 37xx soc, L0(VSET0) VDD AVS value is set to SVC revision
208 * value or a default value when SVC is not supported.
209 * - L0 can be read out from the register of AVS_CTRL_0 and L0 voltage
210 * can be got from the mapping table of avs_map.
211 * - L1 voltage should be about 100mv smaller than L0 voltage
212 * - L2 & L3 voltage should be about 150mv smaller than L0 voltage.
213 * This function calculates L1 & L2 & L3 AVS values dynamically based
214 * on L0 voltage and fill all AVS values to the AVS value table.
215 * When base CPU frequency is 1000 or 1200 MHz then there is additional
216 * minimal avs value for load L1.
218 static void __init armada37xx_cpufreq_avs_configure(struct regmap *base,
219 struct armada_37xx_dvfs *dvfs)
221 unsigned int target_vm;
228 /* Get L0 VDD min value */
229 regmap_read(base, ARMADA_37XX_AVS_CTL0, &l0_vdd_min);
230 l0_vdd_min = (l0_vdd_min >> ARMADA_37XX_AVS_LOW_VDD_LIMIT) &
231 ARMADA_37XX_AVS_VDD_MASK;
232 if (l0_vdd_min >= ARRAY_SIZE(avs_map)) {
233 pr_err("L0 VDD MIN %d is not correct.\n", l0_vdd_min);
236 dvfs->avs[0] = l0_vdd_min;
238 if (avs_map[l0_vdd_min] <= MIN_VOLT_MV) {
240 * If L0 voltage is smaller than 1000mv, then all VDD sets
243 u32 avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV);
245 for (load_level = 1; load_level < LOAD_LEVEL_NR; load_level++)
246 dvfs->avs[load_level] = avs_min;
249 * Set the avs values for load L0 and L1 when base CPU frequency
250 * is 1000/1200 MHz to its typical initial values according to
251 * the Armada 3700 Hardware Specifications.
253 if (dvfs->cpu_freq_max >= 1000*1000*1000) {
254 if (dvfs->cpu_freq_max >= 1200*1000*1000)
255 avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1200MHZ);
257 avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1000MHZ);
258 dvfs->avs[0] = dvfs->avs[1] = avs_min;
265 * L1 voltage is equal to L0 voltage - 100mv and it must be
269 target_vm = avs_map[l0_vdd_min] - 100;
270 target_vm = target_vm > MIN_VOLT_MV ? target_vm : MIN_VOLT_MV;
271 dvfs->avs[1] = armada_37xx_avs_val_match(target_vm);
274 * L2 & L3 voltage is equal to L0 voltage - 150mv and it must
275 * be larger than 1000mv
277 target_vm = avs_map[l0_vdd_min] - 150;
278 target_vm = target_vm > MIN_VOLT_MV ? target_vm : MIN_VOLT_MV;
279 dvfs->avs[2] = dvfs->avs[3] = armada_37xx_avs_val_match(target_vm);
282 * Fix the avs value for load L1 when base CPU frequency is 1000/1200 MHz,
283 * otherwise the CPU gets stuck when switching from load L1 to load L0.
284 * Also ensure that avs value for load L1 is not higher than for L0.
286 if (dvfs->cpu_freq_max >= 1000*1000*1000) {
289 if (dvfs->cpu_freq_max >= 1200*1000*1000)
290 avs_min_l1 = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1200MHZ);
292 avs_min_l1 = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1000MHZ);
294 if (avs_min_l1 > dvfs->avs[0])
295 avs_min_l1 = dvfs->avs[0];
297 if (dvfs->avs[1] < avs_min_l1)
298 dvfs->avs[1] = avs_min_l1;
302 static void __init armada37xx_cpufreq_avs_setup(struct regmap *base,
303 struct armada_37xx_dvfs *dvfs)
305 unsigned int avs_val = 0;
311 /* Disable AVS before the configuration */
312 regmap_update_bits(base, ARMADA_37XX_AVS_CTL0,
313 ARMADA_37XX_AVS_ENABLE, 0);
316 /* Enable low voltage mode */
317 regmap_update_bits(base, ARMADA_37XX_AVS_CTL2,
318 ARMADA_37XX_AVS_LOW_VDD_EN,
319 ARMADA_37XX_AVS_LOW_VDD_EN);
322 for (load_level = 1; load_level < LOAD_LEVEL_NR; load_level++) {
323 avs_val = dvfs->avs[load_level];
324 regmap_update_bits(base, ARMADA_37XX_AVS_VSET(load_level-1),
325 ARMADA_37XX_AVS_VDD_MASK << ARMADA_37XX_AVS_HIGH_VDD_LIMIT |
326 ARMADA_37XX_AVS_VDD_MASK << ARMADA_37XX_AVS_LOW_VDD_LIMIT,
327 avs_val << ARMADA_37XX_AVS_HIGH_VDD_LIMIT |
328 avs_val << ARMADA_37XX_AVS_LOW_VDD_LIMIT);
331 /* Enable AVS after the configuration */
332 regmap_update_bits(base, ARMADA_37XX_AVS_CTL0,
333 ARMADA_37XX_AVS_ENABLE,
334 ARMADA_37XX_AVS_ENABLE);
338 static void armada37xx_cpufreq_disable_dvfs(struct regmap *base)
340 unsigned int reg = ARMADA_37XX_NB_DYN_MOD,
341 mask = ARMADA_37XX_NB_DFS_EN;
343 regmap_update_bits(base, reg, mask, 0);
346 static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base)
348 unsigned int val, reg = ARMADA_37XX_NB_CPU_LOAD,
349 mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
351 /* Start with the highest load (0) */
352 val = ARMADA_37XX_DVFS_LOAD_0;
353 regmap_update_bits(base, reg, mask, val);
355 /* Now enable DVFS for the CPUs */
356 reg = ARMADA_37XX_NB_DYN_MOD;
357 mask = ARMADA_37XX_NB_CLK_SEL_EN | ARMADA_37XX_NB_TBG_EN |
358 ARMADA_37XX_NB_DIV_EN | ARMADA_37XX_NB_VDD_EN |
359 ARMADA_37XX_NB_DFS_EN;
361 regmap_update_bits(base, reg, mask, mask);
364 static int armada37xx_cpufreq_suspend(struct cpufreq_policy *policy)
366 struct armada37xx_cpufreq_state *state = armada37xx_cpufreq_state;
368 regmap_read(state->regmap, ARMADA_37XX_NB_L0L1, &state->nb_l0l1);
369 regmap_read(state->regmap, ARMADA_37XX_NB_L2L3, &state->nb_l2l3);
370 regmap_read(state->regmap, ARMADA_37XX_NB_CPU_LOAD,
371 &state->nb_cpu_load);
372 regmap_read(state->regmap, ARMADA_37XX_NB_DYN_MOD, &state->nb_dyn_mod);
377 static int armada37xx_cpufreq_resume(struct cpufreq_policy *policy)
379 struct armada37xx_cpufreq_state *state = armada37xx_cpufreq_state;
381 /* Ensure DVFS is disabled otherwise the following registers are RO */
382 armada37xx_cpufreq_disable_dvfs(state->regmap);
384 regmap_write(state->regmap, ARMADA_37XX_NB_L0L1, state->nb_l0l1);
385 regmap_write(state->regmap, ARMADA_37XX_NB_L2L3, state->nb_l2l3);
386 regmap_write(state->regmap, ARMADA_37XX_NB_CPU_LOAD,
390 * NB_DYN_MOD register is the one that actually enable back DVFS if it
391 * was enabled before the suspend operation. This must be done last
392 * otherwise other registers are not writable.
394 regmap_write(state->regmap, ARMADA_37XX_NB_DYN_MOD, state->nb_dyn_mod);
399 static int __init armada37xx_cpufreq_driver_init(void)
401 struct cpufreq_dt_platform_data pdata;
402 struct armada_37xx_dvfs *dvfs;
403 struct platform_device *pdev;
405 unsigned int base_frequency;
406 struct regmap *nb_clk_base, *nb_pm_base, *avs_base;
407 struct device *cpu_dev;
409 struct clk *clk, *parent;
412 syscon_regmap_lookup_by_compatible("marvell,armada-3700-periph-clock-nb");
413 if (IS_ERR(nb_clk_base))
417 syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
419 if (IS_ERR(nb_pm_base))
423 syscon_regmap_lookup_by_compatible("marvell,armada-3700-avs");
425 /* if AVS is not present don't use it but still try to setup dvfs */
426 if (IS_ERR(avs_base)) {
427 pr_info("Syscon failed for Adapting Voltage Scaling: skip it\n");
430 /* Before doing any configuration on the DVFS first, disable it */
431 armada37xx_cpufreq_disable_dvfs(nb_pm_base);
434 * On CPU 0 register the operating points supported (which are
435 * the nominal CPU frequency and full integer divisions of
438 cpu_dev = get_cpu_device(0);
440 dev_err(cpu_dev, "Cannot get CPU\n");
444 clk = clk_get(cpu_dev, 0);
446 dev_err(cpu_dev, "Cannot get clock for CPU0\n");
450 parent = clk_get_parent(clk);
451 if (IS_ERR(parent)) {
452 dev_err(cpu_dev, "Cannot get parent clock for CPU0\n");
454 return PTR_ERR(parent);
457 /* Get parent CPU frequency */
458 base_frequency = clk_get_rate(parent);
460 if (!base_frequency) {
461 dev_err(cpu_dev, "Failed to get parent clock rate for CPU\n");
466 dvfs = armada_37xx_cpu_freq_info_get(base_frequency);
472 armada37xx_cpufreq_state = kmalloc(sizeof(*armada37xx_cpufreq_state),
474 if (!armada37xx_cpufreq_state) {
479 armada37xx_cpufreq_state->regmap = nb_pm_base;
481 armada37xx_cpufreq_avs_configure(avs_base, dvfs);
482 armada37xx_cpufreq_avs_setup(avs_base, dvfs);
484 armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider);
487 for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
489 unsigned long u_volt = avs_map[dvfs->avs[load_lvl]] * 1000;
490 freq = base_frequency / dvfs->divider[load_lvl];
491 ret = dev_pm_opp_add(cpu_dev, freq, u_volt);
498 /* Now that everything is setup, enable the DVFS at hardware level */
499 armada37xx_cpufreq_enable_dvfs(nb_pm_base);
501 memset(&pdata, 0, sizeof(pdata));
502 pdata.suspend = armada37xx_cpufreq_suspend;
503 pdata.resume = armada37xx_cpufreq_resume;
505 pdev = platform_device_register_data(NULL, "cpufreq-dt", -1, &pdata,
507 ret = PTR_ERR_OR_ZERO(pdev);
511 armada37xx_cpufreq_state->cpu_dev = cpu_dev;
512 armada37xx_cpufreq_state->pdev = pdev;
513 platform_set_drvdata(pdev, dvfs);
517 armada37xx_cpufreq_disable_dvfs(nb_pm_base);
519 /* clean-up the already added opp before leaving */
520 while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {
521 freq = base_frequency / dvfs->divider[load_lvl];
522 dev_pm_opp_remove(cpu_dev, freq);
525 kfree(armada37xx_cpufreq_state);
529 /* late_initcall, to guarantee the driver is loaded after A37xx clock driver */
530 late_initcall(armada37xx_cpufreq_driver_init);
532 static void __exit armada37xx_cpufreq_driver_exit(void)
534 struct platform_device *pdev = armada37xx_cpufreq_state->pdev;
535 struct armada_37xx_dvfs *dvfs = platform_get_drvdata(pdev);
539 platform_device_unregister(pdev);
541 armada37xx_cpufreq_disable_dvfs(armada37xx_cpufreq_state->regmap);
543 for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
544 freq = dvfs->cpu_freq_max / dvfs->divider[load_lvl];
545 dev_pm_opp_remove(armada37xx_cpufreq_state->cpu_dev, freq);
548 kfree(armada37xx_cpufreq_state);
550 module_exit(armada37xx_cpufreq_driver_exit);
552 static const struct of_device_id __maybe_unused armada37xx_cpufreq_of_match[] = {
553 { .compatible = "marvell,armada-3700-nb-pm" },
556 MODULE_DEVICE_TABLE(of, armada37xx_cpufreq_of_match);
558 MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
559 MODULE_DESCRIPTION("Armada 37xx cpufreq driver");
560 MODULE_LICENSE("GPL");