drivers/counter/stm32-timer-cnt.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * STM32 Timer Encoder and Counter driver
   4  *
   5  * Copyright (C) STMicroelectronics 2018
   6  *
   7  * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
   8  *
   9  */
  10 #include <linux/counter.h>
  11 #include <linux/mfd/stm32-timers.h>
  12 #include <linux/mod_devicetable.h>
  13 #include <linux/module.h>
  14 #include <linux/pinctrl/consumer.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/types.h>
  17
  18 #define TIM_CCMR_CCXS   (BIT(8) | BIT(0))
  19 #define TIM_CCMR_MASK   (TIM_CCMR_CC1S | TIM_CCMR_CC2S | \
  20                          TIM_CCMR_IC1F | TIM_CCMR_IC2F)
  21 #define TIM_CCER_MASK   (TIM_CCER_CC1P | TIM_CCER_CC1NP | \
  22                          TIM_CCER_CC2P | TIM_CCER_CC2NP)
  23
  24 struct stm32_timer_regs {
  25         u32 cr1;
  26         u32 cnt;
  27         u32 smcr;
  28         u32 arr;
  29 };
  30
  31 struct stm32_timer_cnt {
  32         struct counter_device counter;
  33         struct regmap *regmap;
  34         struct clk *clk;
  35         u32 max_arr;
  36         bool enabled;
  37         struct stm32_timer_regs bak;
  38 };
  39
  40 static const enum counter_function stm32_count_functions[] = {
  41         COUNTER_FUNCTION_INCREASE,
  42         COUNTER_FUNCTION_QUADRATURE_X2_A,
  43         COUNTER_FUNCTION_QUADRATURE_X2_B,
  44         COUNTER_FUNCTION_QUADRATURE_X4,
  45 };
  46
  47 static int stm32_count_read(struct counter_device *counter,
  48                             struct counter_count *count, u64 *val)
  49 {
  50         struct stm32_timer_cnt *const priv = counter->priv;
  51         u32 cnt;
  52
  53         regmap_read(priv->regmap, TIM_CNT, &cnt);
  54         *val = cnt;
  55
  56         return 0;
  57 }
  58
  59 static int stm32_count_write(struct counter_device *counter,
  60                              struct counter_count *count, const u64 val)
  61 {
  62         struct stm32_timer_cnt *const priv = counter->priv;
  63         u32 ceiling;
  64
  65         regmap_read(priv->regmap, TIM_ARR, &ceiling);
  66         if (val > ceiling)
  67                 return -EINVAL;
  68
  69         return regmap_write(priv->regmap, TIM_CNT, val);
  70 }
  71
  72 static int stm32_count_function_read(struct counter_device *counter,
  73                                      struct counter_count *count,
  74                                      enum counter_function *function)
  75 {
  76         struct stm32_timer_cnt *const priv = counter->priv;
  77         u32 smcr;
  78
  79         regmap_read(priv->regmap, TIM_SMCR, &smcr);
  80
  81         switch (smcr & TIM_SMCR_SMS) {
  82         case TIM_SMCR_SMS_SLAVE_MODE_DISABLED:
  83                 *function = COUNTER_FUNCTION_INCREASE;
  84                 return 0;
  85         case TIM_SMCR_SMS_ENCODER_MODE_1:
  86                 *function = COUNTER_FUNCTION_QUADRATURE_X2_A;
  87                 return 0;
  88         case TIM_SMCR_SMS_ENCODER_MODE_2:
  89                 *function = COUNTER_FUNCTION_QUADRATURE_X2_B;
  90                 return 0;
  91         case TIM_SMCR_SMS_ENCODER_MODE_3:
  92                 *function = COUNTER_FUNCTION_QUADRATURE_X4;
  93                 return 0;
  94         default:
  95                 return -EINVAL;
  96         }
  97 }
  98
  99 static int stm32_count_function_write(struct counter_device *counter,
 100                                       struct counter_count *count,
 101                                       enum counter_function function)
 102 {
 103         struct stm32_timer_cnt *const priv = counter->priv;
 104         u32 cr1, sms;
 105
 106         switch (function) {
 107         case COUNTER_FUNCTION_INCREASE:
 108                 sms = TIM_SMCR_SMS_SLAVE_MODE_DISABLED;
 109                 break;
 110         case COUNTER_FUNCTION_QUADRATURE_X2_A:
 111                 sms = TIM_SMCR_SMS_ENCODER_MODE_1;
 112                 break;
 113         case COUNTER_FUNCTION_QUADRATURE_X2_B:
 114                 sms = TIM_SMCR_SMS_ENCODER_MODE_2;
 115                 break;
 116         case COUNTER_FUNCTION_QUADRATURE_X4:
 117                 sms = TIM_SMCR_SMS_ENCODER_MODE_3;
 118                 break;
 119         default:
 120                 return -EINVAL;
 121         }
 122
 123         /* Store enable status */
 124         regmap_read(priv->regmap, TIM_CR1, &cr1);
 125
 126         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 127
 128         regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
 129
 130         /* Make sure that registers are updated */
 131         regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
 132
 133         /* Restore the enable status */
 134         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);
 135
 136         return 0;
 137 }
 138
 139 static int stm32_count_direction_read(struct counter_device *counter,
 140                                       struct counter_count *count,
 141                                       enum counter_count_direction *direction)
 142 {
 143         struct stm32_timer_cnt *const priv = counter->priv;
 144         u32 cr1;
 145
 146         regmap_read(priv->regmap, TIM_CR1, &cr1);
 147         *direction = (cr1 & TIM_CR1_DIR) ? COUNTER_COUNT_DIRECTION_BACKWARD :
 148                 COUNTER_COUNT_DIRECTION_FORWARD;
 149
 150         return 0;
 151 }
 152
 153 static int stm32_count_ceiling_read(struct counter_device *counter,
 154                                     struct counter_count *count, u64 *ceiling)
 155 {
 156         struct stm32_timer_cnt *const priv = counter->priv;
 157         u32 arr;
 158
 159         regmap_read(priv->regmap, TIM_ARR, &arr);
 160
 161         *ceiling = arr;
 162
 163         return 0;
 164 }
 165
 166 static int stm32_count_ceiling_write(struct counter_device *counter,
 167                                      struct counter_count *count, u64 ceiling)
 168 {
 169         struct stm32_timer_cnt *const priv = counter->priv;
 170
 171         if (ceiling > priv->max_arr)
 172                 return -ERANGE;
 173
 174         /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
 175         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
 176         regmap_write(priv->regmap, TIM_ARR, ceiling);
 177
 178         return 0;
 179 }
 180
 181 static int stm32_count_enable_read(struct counter_device *counter,
 182                                    struct counter_count *count, u8 *enable)
 183 {
 184         struct stm32_timer_cnt *const priv = counter->priv;
 185         u32 cr1;
 186
 187         regmap_read(priv->regmap, TIM_CR1, &cr1);
 188
 189         *enable = cr1 & TIM_CR1_CEN;
 190
 191         return 0;
 192 }
 193
 194 static int stm32_count_enable_write(struct counter_device *counter,
 195                                     struct counter_count *count, u8 enable)
 196 {
 197         struct stm32_timer_cnt *const priv = counter->priv;
 198         u32 cr1;
 199
 200         if (enable) {
 201                 regmap_read(priv->regmap, TIM_CR1, &cr1);
 202                 if (!(cr1 & TIM_CR1_CEN))
 203                         clk_enable(priv->clk);
 204
 205                 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
 206                                    TIM_CR1_CEN);
 207         } else {
 208                 regmap_read(priv->regmap, TIM_CR1, &cr1);
 209                 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 210                 if (cr1 & TIM_CR1_CEN)
 211                         clk_disable(priv->clk);
 212         }
 213
 214         /* Keep enabled state to properly handle low power states */
 215         priv->enabled = enable;
 216
 217         return 0;
 218 }
 219
 220 static struct counter_comp stm32_count_ext[] = {
 221         COUNTER_COMP_DIRECTION(stm32_count_direction_read),
 222         COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write),
 223         COUNTER_COMP_CEILING(stm32_count_ceiling_read,
 224                              stm32_count_ceiling_write),
 225 };
 226
 227 static const enum counter_synapse_action stm32_synapse_actions[] = {
 228         COUNTER_SYNAPSE_ACTION_NONE,
 229         COUNTER_SYNAPSE_ACTION_BOTH_EDGES
 230 };
 231
 232 static int stm32_action_read(struct counter_device *counter,
 233                              struct counter_count *count,
 234                              struct counter_synapse *synapse,
 235                              enum counter_synapse_action *action)
 236 {
 237         enum counter_function function;
 238         int err;
 239
 240         err = stm32_count_function_read(counter, count, &function);
 241         if (err)
 242                 return err;
 243
 244         switch (function) {
 245         case COUNTER_FUNCTION_INCREASE:
 246                 /* counts on internal clock when CEN=1 */
 247                 *action = COUNTER_SYNAPSE_ACTION_NONE;
 248                 return 0;
 249         case COUNTER_FUNCTION_QUADRATURE_X2_A:
 250                 /* counts up/down on TI1FP1 edge depending on TI2FP2 level */
 251                 if (synapse->signal->id == count->synapses[0].signal->id)
 252                         *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
 253                 else
 254                         *action = COUNTER_SYNAPSE_ACTION_NONE;
 255                 return 0;
 256         case COUNTER_FUNCTION_QUADRATURE_X2_B:
 257                 /* counts up/down on TI2FP2 edge depending on TI1FP1 level */
 258                 if (synapse->signal->id == count->synapses[1].signal->id)
 259                         *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
 260                 else
 261                         *action = COUNTER_SYNAPSE_ACTION_NONE;
 262                 return 0;
 263         case COUNTER_FUNCTION_QUADRATURE_X4:
 264                 /* counts up/down on both TI1FP1 and TI2FP2 edges */
 265                 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
 266                 return 0;
 267         default:
 268                 return -EINVAL;
 269         }
 270 }
 271
 272 static const struct counter_ops stm32_timer_cnt_ops = {
 273         .count_read = stm32_count_read,
 274         .count_write = stm32_count_write,
 275         .function_read = stm32_count_function_read,
 276         .function_write = stm32_count_function_write,
 277         .action_read = stm32_action_read,
 278 };
 279
 280 static struct counter_signal stm32_signals[] = {
 281         {
 282                 .id = 0,
 283                 .name = "Channel 1 Quadrature A"
 284         },
 285         {
 286                 .id = 1,
 287                 .name = "Channel 1 Quadrature B"
 288         }
 289 };
 290
 291 static struct counter_synapse stm32_count_synapses[] = {
 292         {
 293                 .actions_list = stm32_synapse_actions,
 294                 .num_actions = ARRAY_SIZE(stm32_synapse_actions),
 295                 .signal = &stm32_signals[0]
 296         },
 297         {
 298                 .actions_list = stm32_synapse_actions,
 299                 .num_actions = ARRAY_SIZE(stm32_synapse_actions),
 300                 .signal = &stm32_signals[1]
 301         }
 302 };
 303
 304 static struct counter_count stm32_counts = {
 305         .id = 0,
 306         .name = "Channel 1 Count",
 307         .functions_list = stm32_count_functions,
 308         .num_functions = ARRAY_SIZE(stm32_count_functions),
 309         .synapses = stm32_count_synapses,
 310         .num_synapses = ARRAY_SIZE(stm32_count_synapses),
 311         .ext = stm32_count_ext,
 312         .num_ext = ARRAY_SIZE(stm32_count_ext)
 313 };
 314
 315 static int stm32_timer_cnt_probe(struct platform_device *pdev)
 316 {
 317         struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
 318         struct device *dev = &pdev->dev;
 319         struct stm32_timer_cnt *priv;
 320
 321         if (IS_ERR_OR_NULL(ddata))
 322                 return -EINVAL;
 323
 324         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 325         if (!priv)
 326                 return -ENOMEM;
 327
 328         priv->regmap = ddata->regmap;
 329         priv->clk = ddata->clk;
 330         priv->max_arr = ddata->max_arr;
 331
 332         priv->counter.name = dev_name(dev);
 333         priv->counter.parent = dev;
 334         priv->counter.ops = &stm32_timer_cnt_ops;
 335         priv->counter.counts = &stm32_counts;
 336         priv->counter.num_counts = 1;
 337         priv->counter.signals = stm32_signals;
 338         priv->counter.num_signals = ARRAY_SIZE(stm32_signals);
 339         priv->counter.priv = priv;
 340
 341         platform_set_drvdata(pdev, priv);
 342
 343         /* Register Counter device */
 344         return devm_counter_register(dev, &priv->counter);
 345 }
 346
 347 static int __maybe_unused stm32_timer_cnt_suspend(struct device *dev)
 348 {
 349         struct stm32_timer_cnt *priv = dev_get_drvdata(dev);
 350
 351         /* Only take care of enabled counter: don't disturb other MFD child */
 352         if (priv->enabled) {
 353                 /* Backup registers that may get lost in low power mode */
 354                 regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);
 355                 regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);
 356                 regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);
 357                 regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);
 358
 359                 /* Disable the counter */
 360                 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 361                 clk_disable(priv->clk);
 362         }
 363
 364         return pinctrl_pm_select_sleep_state(dev);
 365 }
 366
 367 static int __maybe_unused stm32_timer_cnt_resume(struct device *dev)
 368 {
 369         struct stm32_timer_cnt *priv = dev_get_drvdata(dev);
 370         int ret;
 371
 372         ret = pinctrl_pm_select_default_state(dev);
 373         if (ret)
 374                 return ret;
 375
 376         if (priv->enabled) {
 377                 clk_enable(priv->clk);
 378
 379                 /* Restore registers that may have been lost */
 380                 regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);
 381                 regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);
 382                 regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);
 383
 384                 /* Also re-enables the counter */
 385                 regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);
 386         }
 387
 388         return 0;
 389 }
 390
 391 static SIMPLE_DEV_PM_OPS(stm32_timer_cnt_pm_ops, stm32_timer_cnt_suspend,
 392                          stm32_timer_cnt_resume);
 393
 394 static const struct of_device_id stm32_timer_cnt_of_match[] = {
 395         { .compatible = "st,stm32-timer-counter", },
 396         {},
 397 };
 398 MODULE_DEVICE_TABLE(of, stm32_timer_cnt_of_match);
 399
 400 static struct platform_driver stm32_timer_cnt_driver = {
 401         .probe = stm32_timer_cnt_probe,
 402         .driver = {
 403                 .name = "stm32-timer-counter",
 404                 .of_match_table = stm32_timer_cnt_of_match,
 405                 .pm = &stm32_timer_cnt_pm_ops,
 406         },
 407 };
 408 module_platform_driver(stm32_timer_cnt_driver);
 409
 410 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
 411 MODULE_ALIAS("platform:stm32-timer-counter");
 412 MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver");
 413 MODULE_LICENSE("GPL v2");