drivers/counter/104-quad-8.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Counter driver for the ACCES 104-QUAD-8
   4  * Copyright (C) 2016 William Breathitt Gray
   5  *
   6  * This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
   7  */
   8 #include <linux/bitops.h>
   9 #include <linux/counter.h>
  10 #include <linux/device.h>
  11 #include <linux/errno.h>
  12 #include <linux/io.h>
  13 #include <linux/ioport.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/isa.h>
  16 #include <linux/kernel.h>
  17 #include <linux/list.h>
  18 #include <linux/module.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/types.h>
  21 #include <linux/spinlock.h>
  22
  23 #define QUAD8_EXTENT 32
  24
  25 static unsigned int base[max_num_isa_dev(QUAD8_EXTENT)];
  26 static unsigned int num_quad8;
  27 module_param_hw_array(base, uint, ioport, &num_quad8, 0);
  28 MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
  29
  30 static unsigned int irq[max_num_isa_dev(QUAD8_EXTENT)];
  31 static unsigned int num_irq;
  32 module_param_hw_array(irq, uint, irq, &num_irq, 0);
  33 MODULE_PARM_DESC(irq, "ACCES 104-QUAD-8 interrupt line numbers");
  34
  35 #define QUAD8_NUM_COUNTERS 8
  36
  37 /**
  38  * struct channel_reg - channel register structure
  39  * @data:       Count data
  40  * @control:    Channel flags and control
  41  */
  42 struct channel_reg {
  43         u8 data;
  44         u8 control;
  45 };
  46
  47 /**
  48  * struct quad8_reg - device register structure
  49  * @channel:            quadrature counter data and control
  50  * @interrupt_status:   channel interrupt status
  51  * @channel_oper:       enable/reset counters and interrupt functions
  52  * @index_interrupt:    enable channel interrupts
  53  * @reserved:           reserved for Factory Use
  54  * @index_input_levels: index signal logical input level
  55  * @cable_status:       differential encoder cable status
  56  */
  57 struct quad8_reg {
  58         struct channel_reg channel[QUAD8_NUM_COUNTERS];
  59         u8 interrupt_status;
  60         u8 channel_oper;
  61         u8 index_interrupt;
  62         u8 reserved[3];
  63         u8 index_input_levels;
  64         u8 cable_status;
  65 };
  66
  67 /**
  68  * struct quad8 - device private data structure
  69  * @lock:               lock to prevent clobbering device states during R/W ops
  70  * @counter:            instance of the counter_device
  71  * @fck_prescaler:      array of filter clock prescaler configurations
  72  * @preset:             array of preset values
  73  * @count_mode:         array of count mode configurations
  74  * @quadrature_mode:    array of quadrature mode configurations
  75  * @quadrature_scale:   array of quadrature mode scale configurations
  76  * @ab_enable:          array of A and B inputs enable configurations
  77  * @preset_enable:      array of set_to_preset_on_index attribute configurations
  78  * @irq_trigger:        array of current IRQ trigger function configurations
  79  * @synchronous_mode:   array of index function synchronous mode configurations
  80  * @index_polarity:     array of index function polarity configurations
  81  * @cable_fault_enable: differential encoder cable status enable configurations
  82  * @reg:                I/O address offset for the device registers
  83  */
  84 struct quad8 {
  85         spinlock_t lock;
  86         unsigned int fck_prescaler[QUAD8_NUM_COUNTERS];
  87         unsigned int preset[QUAD8_NUM_COUNTERS];
  88         unsigned int count_mode[QUAD8_NUM_COUNTERS];
  89         unsigned int quadrature_mode[QUAD8_NUM_COUNTERS];
  90         unsigned int quadrature_scale[QUAD8_NUM_COUNTERS];
  91         unsigned int ab_enable[QUAD8_NUM_COUNTERS];
  92         unsigned int preset_enable[QUAD8_NUM_COUNTERS];
  93         unsigned int irq_trigger[QUAD8_NUM_COUNTERS];
  94         unsigned int synchronous_mode[QUAD8_NUM_COUNTERS];
  95         unsigned int index_polarity[QUAD8_NUM_COUNTERS];
  96         unsigned int cable_fault_enable;
  97         struct quad8_reg __iomem *reg;
  98 };
  99
 100 /* Error flag */
 101 #define QUAD8_FLAG_E BIT(4)
 102 /* Up/Down flag */
 103 #define QUAD8_FLAG_UD BIT(5)
 104 /* Reset and Load Signal Decoders */
 105 #define QUAD8_CTR_RLD 0x00
 106 /* Counter Mode Register */
 107 #define QUAD8_CTR_CMR 0x20
 108 /* Input / Output Control Register */
 109 #define QUAD8_CTR_IOR 0x40
 110 /* Index Control Register */
 111 #define QUAD8_CTR_IDR 0x60
 112 /* Reset Byte Pointer (three byte data pointer) */
 113 #define QUAD8_RLD_RESET_BP 0x01
 114 /* Reset Counter */
 115 #define QUAD8_RLD_RESET_CNTR 0x02
 116 /* Reset Borrow Toggle, Carry Toggle, Compare Toggle, and Sign flags */
 117 #define QUAD8_RLD_RESET_FLAGS 0x04
 118 /* Reset Error flag */
 119 #define QUAD8_RLD_RESET_E 0x06
 120 /* Preset Register to Counter */
 121 #define QUAD8_RLD_PRESET_CNTR 0x08
 122 /* Transfer Counter to Output Latch */
 123 #define QUAD8_RLD_CNTR_OUT 0x10
 124 /* Transfer Preset Register LSB to FCK Prescaler */
 125 #define QUAD8_RLD_PRESET_PSC 0x18
 126 #define QUAD8_CHAN_OP_RESET_COUNTERS 0x01
 127 #define QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC 0x04
 128 #define QUAD8_CMR_QUADRATURE_X1 0x08
 129 #define QUAD8_CMR_QUADRATURE_X2 0x10
 130 #define QUAD8_CMR_QUADRATURE_X4 0x18
 131
 132 /* Each Counter is 24 bits wide */
 133 #define LS7267_CNTR_MAX GENMASK(23, 0)
 134
 135 static int quad8_signal_read(struct counter_device *counter,
 136                              struct counter_signal *signal,
 137                              enum counter_signal_level *level)
 138 {
 139         const struct quad8 *const priv = counter_priv(counter);
 140         unsigned int state;
 141
 142         /* Only Index signal levels can be read */
 143         if (signal->id < 16)
 144                 return -EINVAL;
 145
 146         state = ioread8(&priv->reg->index_input_levels) & BIT(signal->id - 16);
 147
 148         *level = (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
 149
 150         return 0;
 151 }
 152
 153 static int quad8_count_read(struct counter_device *counter,
 154                             struct counter_count *count, u64 *val)
 155 {
 156         struct quad8 *const priv = counter_priv(counter);
 157         struct channel_reg __iomem *const chan = priv->reg->channel + count->id;
 158         unsigned long irqflags;
 159         int i;
 160
 161         *val = 0;
 162
 163         spin_lock_irqsave(&priv->lock, irqflags);
 164
 165         /* Reset Byte Pointer; transfer Counter to Output Latch */
 166         iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
 167                  &chan->control);
 168
 169         for (i = 0; i < 3; i++)
 170                 *val |= (unsigned long)ioread8(&chan->data) << (8 * i);
 171
 172         spin_unlock_irqrestore(&priv->lock, irqflags);
 173
 174         return 0;
 175 }
 176
 177 static int quad8_count_write(struct counter_device *counter,
 178                              struct counter_count *count, u64 val)
 179 {
 180         struct quad8 *const priv = counter_priv(counter);
 181         struct channel_reg __iomem *const chan = priv->reg->channel + count->id;
 182         unsigned long irqflags;
 183         int i;
 184
 185         if (val > LS7267_CNTR_MAX)
 186                 return -ERANGE;
 187
 188         spin_lock_irqsave(&priv->lock, irqflags);
 189
 190         /* Reset Byte Pointer */
 191         iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
 192
 193         /* Counter can only be set via Preset Register */
 194         for (i = 0; i < 3; i++)
 195                 iowrite8(val >> (8 * i), &chan->data);
 196
 197         /* Transfer Preset Register to Counter */
 198         iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, &chan->control);
 199
 200         /* Reset Byte Pointer */
 201         iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
 202
 203         /* Set Preset Register back to original value */
 204         val = priv->preset[count->id];
 205         for (i = 0; i < 3; i++)
 206                 iowrite8(val >> (8 * i), &chan->data);
 207
 208         /* Reset Borrow, Carry, Compare, and Sign flags */
 209         iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control);
 210         /* Reset Error flag */
 211         iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control);
 212
 213         spin_unlock_irqrestore(&priv->lock, irqflags);
 214
 215         return 0;
 216 }
 217
 218 static const enum counter_function quad8_count_functions_list[] = {
 219         COUNTER_FUNCTION_PULSE_DIRECTION,
 220         COUNTER_FUNCTION_QUADRATURE_X1_A,
 221         COUNTER_FUNCTION_QUADRATURE_X2_A,
 222         COUNTER_FUNCTION_QUADRATURE_X4,
 223 };
 224
 225 static int quad8_function_get(const struct quad8 *const priv, const size_t id,
 226                               enum counter_function *const function)
 227 {
 228         if (!priv->quadrature_mode[id]) {
 229                 *function = COUNTER_FUNCTION_PULSE_DIRECTION;
 230                 return 0;
 231         }
 232
 233         switch (priv->quadrature_scale[id]) {
 234         case 0:
 235                 *function = COUNTER_FUNCTION_QUADRATURE_X1_A;
 236                 return 0;
 237         case 1:
 238                 *function = COUNTER_FUNCTION_QUADRATURE_X2_A;
 239                 return 0;
 240         case 2:
 241                 *function = COUNTER_FUNCTION_QUADRATURE_X4;
 242                 return 0;
 243         default:
 244                 /* should never reach this path */
 245                 return -EINVAL;
 246         }
 247 }
 248
 249 static int quad8_function_read(struct counter_device *counter,
 250                                struct counter_count *count,
 251                                enum counter_function *function)
 252 {
 253         struct quad8 *const priv = counter_priv(counter);
 254         unsigned long irqflags;
 255         int retval;
 256
 257         spin_lock_irqsave(&priv->lock, irqflags);
 258
 259         retval = quad8_function_get(priv, count->id, function);
 260
 261         spin_unlock_irqrestore(&priv->lock, irqflags);
 262
 263         return retval;
 264 }
 265
 266 static int quad8_function_write(struct counter_device *counter,
 267                                 struct counter_count *count,
 268                                 enum counter_function function)
 269 {
 270         struct quad8 *const priv = counter_priv(counter);
 271         const int id = count->id;
 272         unsigned int *const quadrature_mode = priv->quadrature_mode + id;
 273         unsigned int *const scale = priv->quadrature_scale + id;
 274         unsigned int *const synchronous_mode = priv->synchronous_mode + id;
 275         u8 __iomem *const control = &priv->reg->channel[id].control;
 276         unsigned long irqflags;
 277         unsigned int mode_cfg;
 278         unsigned int idr_cfg;
 279
 280         spin_lock_irqsave(&priv->lock, irqflags);
 281
 282         mode_cfg = priv->count_mode[id] << 1;
 283         idr_cfg = priv->index_polarity[id] << 1;
 284
 285         if (function == COUNTER_FUNCTION_PULSE_DIRECTION) {
 286                 *quadrature_mode = 0;
 287
 288                 /* Quadrature scaling only available in quadrature mode */
 289                 *scale = 0;
 290
 291                 /* Synchronous function not supported in non-quadrature mode */
 292                 if (*synchronous_mode) {
 293                         *synchronous_mode = 0;
 294                         /* Disable synchronous function mode */
 295                         iowrite8(QUAD8_CTR_IDR | idr_cfg, control);
 296                 }
 297         } else {
 298                 *quadrature_mode = 1;
 299
 300                 switch (function) {
 301                 case COUNTER_FUNCTION_QUADRATURE_X1_A:
 302                         *scale = 0;
 303                         mode_cfg |= QUAD8_CMR_QUADRATURE_X1;
 304                         break;
 305                 case COUNTER_FUNCTION_QUADRATURE_X2_A:
 306                         *scale = 1;
 307                         mode_cfg |= QUAD8_CMR_QUADRATURE_X2;
 308                         break;
 309                 case COUNTER_FUNCTION_QUADRATURE_X4:
 310                         *scale = 2;
 311                         mode_cfg |= QUAD8_CMR_QUADRATURE_X4;
 312                         break;
 313                 default:
 314                         /* should never reach this path */
 315                         spin_unlock_irqrestore(&priv->lock, irqflags);
 316                         return -EINVAL;
 317                 }
 318         }
 319
 320         /* Load mode configuration to Counter Mode Register */
 321         iowrite8(QUAD8_CTR_CMR | mode_cfg, control);
 322
 323         spin_unlock_irqrestore(&priv->lock, irqflags);
 324
 325         return 0;
 326 }
 327
 328 static int quad8_direction_read(struct counter_device *counter,
 329                                 struct counter_count *count,
 330                                 enum counter_count_direction *direction)
 331 {
 332         const struct quad8 *const priv = counter_priv(counter);
 333         unsigned int ud_flag;
 334         u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control;
 335
 336         /* U/D flag: nonzero = up, zero = down */
 337         ud_flag = ioread8(flag_addr) & QUAD8_FLAG_UD;
 338
 339         *direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD :
 340                 COUNTER_COUNT_DIRECTION_BACKWARD;
 341
 342         return 0;
 343 }
 344
 345 static const enum counter_synapse_action quad8_index_actions_list[] = {
 346         COUNTER_SYNAPSE_ACTION_NONE,
 347         COUNTER_SYNAPSE_ACTION_RISING_EDGE,
 348 };
 349
 350 static const enum counter_synapse_action quad8_synapse_actions_list[] = {
 351         COUNTER_SYNAPSE_ACTION_NONE,
 352         COUNTER_SYNAPSE_ACTION_RISING_EDGE,
 353         COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
 354         COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
 355 };
 356
 357 static int quad8_action_read(struct counter_device *counter,
 358                              struct counter_count *count,
 359                              struct counter_synapse *synapse,
 360                              enum counter_synapse_action *action)
 361 {
 362         struct quad8 *const priv = counter_priv(counter);
 363         unsigned long irqflags;
 364         int err;
 365         enum counter_function function;
 366         const size_t signal_a_id = count->synapses[0].signal->id;
 367         enum counter_count_direction direction;
 368
 369         /* Handle Index signals */
 370         if (synapse->signal->id >= 16) {
 371                 if (!priv->preset_enable[count->id])
 372                         *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
 373                 else
 374                         *action = COUNTER_SYNAPSE_ACTION_NONE;
 375
 376                 return 0;
 377         }
 378
 379         spin_lock_irqsave(&priv->lock, irqflags);
 380
 381         /* Get Count function and direction atomically */
 382         err = quad8_function_get(priv, count->id, &function);
 383         if (err) {
 384                 spin_unlock_irqrestore(&priv->lock, irqflags);
 385                 return err;
 386         }
 387         err = quad8_direction_read(counter, count, &direction);
 388         if (err) {
 389                 spin_unlock_irqrestore(&priv->lock, irqflags);
 390                 return err;
 391         }
 392
 393         spin_unlock_irqrestore(&priv->lock, irqflags);
 394
 395         /* Default action mode */
 396         *action = COUNTER_SYNAPSE_ACTION_NONE;
 397
 398         /* Determine action mode based on current count function mode */
 399         switch (function) {
 400         case COUNTER_FUNCTION_PULSE_DIRECTION:
 401                 if (synapse->signal->id == signal_a_id)
 402                         *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
 403                 return 0;
 404         case COUNTER_FUNCTION_QUADRATURE_X1_A:
 405                 if (synapse->signal->id == signal_a_id) {
 406                         if (direction == COUNTER_COUNT_DIRECTION_FORWARD)
 407                                 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
 408                         else
 409                                 *action = COUNTER_SYNAPSE_ACTION_FALLING_EDGE;
 410                 }
 411                 return 0;
 412         case COUNTER_FUNCTION_QUADRATURE_X2_A:
 413                 if (synapse->signal->id == signal_a_id)
 414                         *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
 415                 return 0;
 416         case COUNTER_FUNCTION_QUADRATURE_X4:
 417                 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
 418                 return 0;
 419         default:
 420                 /* should never reach this path */
 421                 return -EINVAL;
 422         }
 423 }
 424
 425 enum {
 426         QUAD8_EVENT_CARRY = 0,
 427         QUAD8_EVENT_COMPARE = 1,
 428         QUAD8_EVENT_CARRY_BORROW = 2,
 429         QUAD8_EVENT_INDEX = 3,
 430 };
 431
 432 static int quad8_events_configure(struct counter_device *counter)
 433 {
 434         struct quad8 *const priv = counter_priv(counter);
 435         unsigned long irq_enabled = 0;
 436         unsigned long irqflags;
 437         struct counter_event_node *event_node;
 438         unsigned int next_irq_trigger;
 439         unsigned long ior_cfg;
 440
 441         spin_lock_irqsave(&priv->lock, irqflags);
 442
 443         list_for_each_entry(event_node, &counter->events_list, l) {
 444                 switch (event_node->event) {
 445                 case COUNTER_EVENT_OVERFLOW:
 446                         next_irq_trigger = QUAD8_EVENT_CARRY;
 447                         break;
 448                 case COUNTER_EVENT_THRESHOLD:
 449                         next_irq_trigger = QUAD8_EVENT_COMPARE;
 450                         break;
 451                 case COUNTER_EVENT_OVERFLOW_UNDERFLOW:
 452                         next_irq_trigger = QUAD8_EVENT_CARRY_BORROW;
 453                         break;
 454                 case COUNTER_EVENT_INDEX:
 455                         next_irq_trigger = QUAD8_EVENT_INDEX;
 456                         break;
 457                 default:
 458                         /* should never reach this path */
 459                         spin_unlock_irqrestore(&priv->lock, irqflags);
 460                         return -EINVAL;
 461                 }
 462
 463                 /* Enable IRQ line */
 464                 irq_enabled |= BIT(event_node->channel);
 465
 466                 /* Skip configuration if it is the same as previously set */
 467                 if (priv->irq_trigger[event_node->channel] == next_irq_trigger)
 468                         continue;
 469
 470                 /* Save new IRQ function configuration */
 471                 priv->irq_trigger[event_node->channel] = next_irq_trigger;
 472
 473                 /* Load configuration to I/O Control Register */
 474                 ior_cfg = priv->ab_enable[event_node->channel] |
 475                           priv->preset_enable[event_node->channel] << 1 |
 476                           priv->irq_trigger[event_node->channel] << 3;
 477                 iowrite8(QUAD8_CTR_IOR | ior_cfg,
 478                          &priv->reg->channel[event_node->channel].control);
 479         }
 480
 481         iowrite8(irq_enabled, &priv->reg->index_interrupt);
 482
 483         spin_unlock_irqrestore(&priv->lock, irqflags);
 484
 485         return 0;
 486 }
 487
 488 static int quad8_watch_validate(struct counter_device *counter,
 489                                 const struct counter_watch *watch)
 490 {
 491         struct counter_event_node *event_node;
 492
 493         if (watch->channel > QUAD8_NUM_COUNTERS - 1)
 494                 return -EINVAL;
 495
 496         switch (watch->event) {
 497         case COUNTER_EVENT_OVERFLOW:
 498         case COUNTER_EVENT_THRESHOLD:
 499         case COUNTER_EVENT_OVERFLOW_UNDERFLOW:
 500         case COUNTER_EVENT_INDEX:
 501                 list_for_each_entry(event_node, &counter->next_events_list, l)
 502                         if (watch->channel == event_node->channel &&
 503                                 watch->event != event_node->event)
 504                                 return -EINVAL;
 505                 return 0;
 506         default:
 507                 return -EINVAL;
 508         }
 509 }
 510
 511 static const struct counter_ops quad8_ops = {
 512         .signal_read = quad8_signal_read,
 513         .count_read = quad8_count_read,
 514         .count_write = quad8_count_write,
 515         .function_read = quad8_function_read,
 516         .function_write = quad8_function_write,
 517         .action_read = quad8_action_read,
 518         .events_configure = quad8_events_configure,
 519         .watch_validate = quad8_watch_validate,
 520 };
 521
 522 static const char *const quad8_index_polarity_modes[] = {
 523         "negative",
 524         "positive"
 525 };
 526
 527 static int quad8_index_polarity_get(struct counter_device *counter,
 528                                     struct counter_signal *signal,
 529                                     u32 *index_polarity)
 530 {
 531         const struct quad8 *const priv = counter_priv(counter);
 532         const size_t channel_id = signal->id - 16;
 533
 534         *index_polarity = priv->index_polarity[channel_id];
 535
 536         return 0;
 537 }
 538
 539 static int quad8_index_polarity_set(struct counter_device *counter,
 540                                     struct counter_signal *signal,
 541                                     u32 index_polarity)
 542 {
 543         struct quad8 *const priv = counter_priv(counter);
 544         const size_t channel_id = signal->id - 16;
 545         u8 __iomem *const control = &priv->reg->channel[channel_id].control;
 546         unsigned long irqflags;
 547         unsigned int idr_cfg = index_polarity << 1;
 548
 549         spin_lock_irqsave(&priv->lock, irqflags);
 550
 551         idr_cfg |= priv->synchronous_mode[channel_id];
 552
 553         priv->index_polarity[channel_id] = index_polarity;
 554
 555         /* Load Index Control configuration to Index Control Register */
 556         iowrite8(QUAD8_CTR_IDR | idr_cfg, control);
 557
 558         spin_unlock_irqrestore(&priv->lock, irqflags);
 559
 560         return 0;
 561 }
 562
 563 static int quad8_polarity_read(struct counter_device *counter,
 564                                struct counter_signal *signal,
 565                                enum counter_signal_polarity *polarity)
 566 {
 567         int err;
 568         u32 index_polarity;
 569
 570         err = quad8_index_polarity_get(counter, signal, &index_polarity);
 571         if (err)
 572                 return err;
 573
 574         *polarity = (index_polarity) ? COUNTER_SIGNAL_POLARITY_POSITIVE :
 575                 COUNTER_SIGNAL_POLARITY_NEGATIVE;
 576
 577         return 0;
 578 }
 579
 580 static int quad8_polarity_write(struct counter_device *counter,
 581                                 struct counter_signal *signal,
 582                                 enum counter_signal_polarity polarity)
 583 {
 584         const u32 pol = (polarity == COUNTER_SIGNAL_POLARITY_POSITIVE) ? 1 : 0;
 585
 586         return quad8_index_polarity_set(counter, signal, pol);
 587 }
 588
 589 static const char *const quad8_synchronous_modes[] = {
 590         "non-synchronous",
 591         "synchronous"
 592 };
 593
 594 static int quad8_synchronous_mode_get(struct counter_device *counter,
 595                                       struct counter_signal *signal,
 596                                       u32 *synchronous_mode)
 597 {
 598         const struct quad8 *const priv = counter_priv(counter);
 599         const size_t channel_id = signal->id - 16;
 600
 601         *synchronous_mode = priv->synchronous_mode[channel_id];
 602
 603         return 0;
 604 }
 605
 606 static int quad8_synchronous_mode_set(struct counter_device *counter,
 607                                       struct counter_signal *signal,
 608                                       u32 synchronous_mode)
 609 {
 610         struct quad8 *const priv = counter_priv(counter);
 611         const size_t channel_id = signal->id - 16;
 612         u8 __iomem *const control = &priv->reg->channel[channel_id].control;
 613         unsigned long irqflags;
 614         unsigned int idr_cfg = synchronous_mode;
 615
 616         spin_lock_irqsave(&priv->lock, irqflags);
 617
 618         idr_cfg |= priv->index_polarity[channel_id] << 1;
 619
 620         /* Index function must be non-synchronous in non-quadrature mode */
 621         if (synchronous_mode && !priv->quadrature_mode[channel_id]) {
 622                 spin_unlock_irqrestore(&priv->lock, irqflags);
 623                 return -EINVAL;
 624         }
 625
 626         priv->synchronous_mode[channel_id] = synchronous_mode;
 627
 628         /* Load Index Control configuration to Index Control Register */
 629         iowrite8(QUAD8_CTR_IDR | idr_cfg, control);
 630
 631         spin_unlock_irqrestore(&priv->lock, irqflags);
 632
 633         return 0;
 634 }
 635
 636 static int quad8_count_floor_read(struct counter_device *counter,
 637                                   struct counter_count *count, u64 *floor)
 638 {
 639         /* Only a floor of 0 is supported */
 640         *floor = 0;
 641
 642         return 0;
 643 }
 644
 645 static int quad8_count_mode_read(struct counter_device *counter,
 646                                  struct counter_count *count,
 647                                  enum counter_count_mode *cnt_mode)
 648 {
 649         const struct quad8 *const priv = counter_priv(counter);
 650
 651         /* Map 104-QUAD-8 count mode to Generic Counter count mode */
 652         switch (priv->count_mode[count->id]) {
 653         case 0:
 654                 *cnt_mode = COUNTER_COUNT_MODE_NORMAL;
 655                 break;
 656         case 1:
 657                 *cnt_mode = COUNTER_COUNT_MODE_RANGE_LIMIT;
 658                 break;
 659         case 2:
 660                 *cnt_mode = COUNTER_COUNT_MODE_NON_RECYCLE;
 661                 break;
 662         case 3:
 663                 *cnt_mode = COUNTER_COUNT_MODE_MODULO_N;
 664                 break;
 665         }
 666
 667         return 0;
 668 }
 669
 670 static int quad8_count_mode_write(struct counter_device *counter,
 671                                   struct counter_count *count,
 672                                   enum counter_count_mode cnt_mode)
 673 {
 674         struct quad8 *const priv = counter_priv(counter);
 675         unsigned int count_mode;
 676         unsigned int mode_cfg;
 677         u8 __iomem *const control = &priv->reg->channel[count->id].control;
 678         unsigned long irqflags;
 679
 680         /* Map Generic Counter count mode to 104-QUAD-8 count mode */
 681         switch (cnt_mode) {
 682         case COUNTER_COUNT_MODE_NORMAL:
 683                 count_mode = 0;
 684                 break;
 685         case COUNTER_COUNT_MODE_RANGE_LIMIT:
 686                 count_mode = 1;
 687                 break;
 688         case COUNTER_COUNT_MODE_NON_RECYCLE:
 689                 count_mode = 2;
 690                 break;
 691         case COUNTER_COUNT_MODE_MODULO_N:
 692                 count_mode = 3;
 693                 break;
 694         default:
 695                 /* should never reach this path */
 696                 return -EINVAL;
 697         }
 698
 699         spin_lock_irqsave(&priv->lock, irqflags);
 700
 701         priv->count_mode[count->id] = count_mode;
 702
 703         /* Set count mode configuration value */
 704         mode_cfg = count_mode << 1;
 705
 706         /* Add quadrature mode configuration */
 707         if (priv->quadrature_mode[count->id])
 708                 mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3;
 709
 710         /* Load mode configuration to Counter Mode Register */
 711         iowrite8(QUAD8_CTR_CMR | mode_cfg, control);
 712
 713         spin_unlock_irqrestore(&priv->lock, irqflags);
 714
 715         return 0;
 716 }
 717
 718 static int quad8_count_enable_read(struct counter_device *counter,
 719                                    struct counter_count *count, u8 *enable)
 720 {
 721         const struct quad8 *const priv = counter_priv(counter);
 722
 723         *enable = priv->ab_enable[count->id];
 724
 725         return 0;
 726 }
 727
 728 static int quad8_count_enable_write(struct counter_device *counter,
 729                                     struct counter_count *count, u8 enable)
 730 {
 731         struct quad8 *const priv = counter_priv(counter);
 732         u8 __iomem *const control = &priv->reg->channel[count->id].control;
 733         unsigned long irqflags;
 734         unsigned int ior_cfg;
 735
 736         spin_lock_irqsave(&priv->lock, irqflags);
 737
 738         priv->ab_enable[count->id] = enable;
 739
 740         ior_cfg = enable | priv->preset_enable[count->id] << 1 |
 741                   priv->irq_trigger[count->id] << 3;
 742
 743         /* Load I/O control configuration */
 744         iowrite8(QUAD8_CTR_IOR | ior_cfg, control);
 745
 746         spin_unlock_irqrestore(&priv->lock, irqflags);
 747
 748         return 0;
 749 }
 750
 751 static const char *const quad8_noise_error_states[] = {
 752         "No excessive noise is present at the count inputs",
 753         "Excessive noise is present at the count inputs"
 754 };
 755
 756 static int quad8_error_noise_get(struct counter_device *counter,
 757                                  struct counter_count *count, u32 *noise_error)
 758 {
 759         const struct quad8 *const priv = counter_priv(counter);
 760         u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control;
 761
 762         *noise_error = !!(ioread8(flag_addr) & QUAD8_FLAG_E);
 763
 764         return 0;
 765 }
 766
 767 static int quad8_count_preset_read(struct counter_device *counter,
 768                                    struct counter_count *count, u64 *preset)
 769 {
 770         const struct quad8 *const priv = counter_priv(counter);
 771
 772         *preset = priv->preset[count->id];
 773
 774         return 0;
 775 }
 776
 777 static void quad8_preset_register_set(struct quad8 *const priv, const int id,
 778                                       const unsigned int preset)
 779 {
 780         struct channel_reg __iomem *const chan = priv->reg->channel + id;
 781         int i;
 782
 783         priv->preset[id] = preset;
 784
 785         /* Reset Byte Pointer */
 786         iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
 787
 788         /* Set Preset Register */
 789         for (i = 0; i < 3; i++)
 790                 iowrite8(preset >> (8 * i), &chan->data);
 791 }
 792
 793 static int quad8_count_preset_write(struct counter_device *counter,
 794                                     struct counter_count *count, u64 preset)
 795 {
 796         struct quad8 *const priv = counter_priv(counter);
 797         unsigned long irqflags;
 798
 799         if (preset > LS7267_CNTR_MAX)
 800                 return -ERANGE;
 801
 802         spin_lock_irqsave(&priv->lock, irqflags);
 803
 804         quad8_preset_register_set(priv, count->id, preset);
 805
 806         spin_unlock_irqrestore(&priv->lock, irqflags);
 807
 808         return 0;
 809 }
 810
 811 static int quad8_count_ceiling_read(struct counter_device *counter,
 812                                     struct counter_count *count, u64 *ceiling)
 813 {
 814         struct quad8 *const priv = counter_priv(counter);
 815         unsigned long irqflags;
 816
 817         spin_lock_irqsave(&priv->lock, irqflags);
 818
 819         /* Range Limit and Modulo-N count modes use preset value as ceiling */
 820         switch (priv->count_mode[count->id]) {
 821         case 1:
 822         case 3:
 823                 *ceiling = priv->preset[count->id];
 824                 break;
 825         default:
 826                 *ceiling = LS7267_CNTR_MAX;
 827                 break;
 828         }
 829
 830         spin_unlock_irqrestore(&priv->lock, irqflags);
 831
 832         return 0;
 833 }
 834
 835 static int quad8_count_ceiling_write(struct counter_device *counter,
 836                                      struct counter_count *count, u64 ceiling)
 837 {
 838         struct quad8 *const priv = counter_priv(counter);
 839         unsigned long irqflags;
 840
 841         if (ceiling > LS7267_CNTR_MAX)
 842                 return -ERANGE;
 843
 844         spin_lock_irqsave(&priv->lock, irqflags);
 845
 846         /* Range Limit and Modulo-N count modes use preset value as ceiling */
 847         switch (priv->count_mode[count->id]) {
 848         case 1:
 849         case 3:
 850                 quad8_preset_register_set(priv, count->id, ceiling);
 851                 spin_unlock_irqrestore(&priv->lock, irqflags);
 852                 return 0;
 853         }
 854
 855         spin_unlock_irqrestore(&priv->lock, irqflags);
 856
 857         return -EINVAL;
 858 }
 859
 860 static int quad8_count_preset_enable_read(struct counter_device *counter,
 861                                           struct counter_count *count,
 862                                           u8 *preset_enable)
 863 {
 864         const struct quad8 *const priv = counter_priv(counter);
 865
 866         *preset_enable = !priv->preset_enable[count->id];
 867
 868         return 0;
 869 }
 870
 871 static int quad8_count_preset_enable_write(struct counter_device *counter,
 872                                            struct counter_count *count,
 873                                            u8 preset_enable)
 874 {
 875         struct quad8 *const priv = counter_priv(counter);
 876         u8 __iomem *const control = &priv->reg->channel[count->id].control;
 877         unsigned long irqflags;
 878         unsigned int ior_cfg;
 879
 880         /* Preset enable is active low in Input/Output Control register */
 881         preset_enable = !preset_enable;
 882
 883         spin_lock_irqsave(&priv->lock, irqflags);
 884
 885         priv->preset_enable[count->id] = preset_enable;
 886
 887         ior_cfg = priv->ab_enable[count->id] | preset_enable << 1 |
 888                   priv->irq_trigger[count->id] << 3;
 889
 890         /* Load I/O control configuration to Input / Output Control Register */
 891         iowrite8(QUAD8_CTR_IOR | ior_cfg, control);
 892
 893         spin_unlock_irqrestore(&priv->lock, irqflags);
 894
 895         return 0;
 896 }
 897
 898 static int quad8_signal_cable_fault_read(struct counter_device *counter,
 899                                          struct counter_signal *signal,
 900                                          u8 *cable_fault)
 901 {
 902         struct quad8 *const priv = counter_priv(counter);
 903         const size_t channel_id = signal->id / 2;
 904         unsigned long irqflags;
 905         bool disabled;
 906         unsigned int status;
 907
 908         spin_lock_irqsave(&priv->lock, irqflags);
 909
 910         disabled = !(priv->cable_fault_enable & BIT(channel_id));
 911
 912         if (disabled) {
 913                 spin_unlock_irqrestore(&priv->lock, irqflags);
 914                 return -EINVAL;
 915         }
 916
 917         /* Logic 0 = cable fault */
 918         status = ioread8(&priv->reg->cable_status);
 919
 920         spin_unlock_irqrestore(&priv->lock, irqflags);
 921
 922         /* Mask respective channel and invert logic */
 923         *cable_fault = !(status & BIT(channel_id));
 924
 925         return 0;
 926 }
 927
 928 static int quad8_signal_cable_fault_enable_read(struct counter_device *counter,
 929                                                 struct counter_signal *signal,
 930                                                 u8 *enable)
 931 {
 932         const struct quad8 *const priv = counter_priv(counter);
 933         const size_t channel_id = signal->id / 2;
 934
 935         *enable = !!(priv->cable_fault_enable & BIT(channel_id));
 936
 937         return 0;
 938 }
 939
 940 static int quad8_signal_cable_fault_enable_write(struct counter_device *counter,
 941                                                  struct counter_signal *signal,
 942                                                  u8 enable)
 943 {
 944         struct quad8 *const priv = counter_priv(counter);
 945         const size_t channel_id = signal->id / 2;
 946         unsigned long irqflags;
 947         unsigned int cable_fault_enable;
 948
 949         spin_lock_irqsave(&priv->lock, irqflags);
 950
 951         if (enable)
 952                 priv->cable_fault_enable |= BIT(channel_id);
 953         else
 954                 priv->cable_fault_enable &= ~BIT(channel_id);
 955
 956         /* Enable is active low in Differential Encoder Cable Status register */
 957         cable_fault_enable = ~priv->cable_fault_enable;
 958
 959         iowrite8(cable_fault_enable, &priv->reg->cable_status);
 960
 961         spin_unlock_irqrestore(&priv->lock, irqflags);
 962
 963         return 0;
 964 }
 965
 966 static int quad8_signal_fck_prescaler_read(struct counter_device *counter,
 967                                            struct counter_signal *signal,
 968                                            u8 *prescaler)
 969 {
 970         const struct quad8 *const priv = counter_priv(counter);
 971
 972         *prescaler = priv->fck_prescaler[signal->id / 2];
 973
 974         return 0;
 975 }
 976
 977 static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
 978                                             struct counter_signal *signal,
 979                                             u8 prescaler)
 980 {
 981         struct quad8 *const priv = counter_priv(counter);
 982         const size_t channel_id = signal->id / 2;
 983         struct channel_reg __iomem *const chan = priv->reg->channel + channel_id;
 984         unsigned long irqflags;
 985
 986         spin_lock_irqsave(&priv->lock, irqflags);
 987
 988         priv->fck_prescaler[channel_id] = prescaler;
 989
 990         /* Reset Byte Pointer */
 991         iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
 992
 993         /* Set filter clock factor */
 994         iowrite8(prescaler, &chan->data);
 995         iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
 996                  &chan->control);
 997
 998         spin_unlock_irqrestore(&priv->lock, irqflags);
 999
1000         return 0;
1001 }
1002
1003 static struct counter_comp quad8_signal_ext[] = {
1004         COUNTER_COMP_SIGNAL_BOOL("cable_fault", quad8_signal_cable_fault_read,
1005                                  NULL),
1006         COUNTER_COMP_SIGNAL_BOOL("cable_fault_enable",
1007                                  quad8_signal_cable_fault_enable_read,
1008                                  quad8_signal_cable_fault_enable_write),
1009         COUNTER_COMP_SIGNAL_U8("filter_clock_prescaler",
1010                                quad8_signal_fck_prescaler_read,
1011                                quad8_signal_fck_prescaler_write)
1012 };
1013
1014 static const enum counter_signal_polarity quad8_polarities[] = {
1015         COUNTER_SIGNAL_POLARITY_POSITIVE,
1016         COUNTER_SIGNAL_POLARITY_NEGATIVE,
1017 };
1018
1019 static DEFINE_COUNTER_AVAILABLE(quad8_polarity_available, quad8_polarities);
1020
1021 static DEFINE_COUNTER_ENUM(quad8_index_pol_enum, quad8_index_polarity_modes);
1022 static DEFINE_COUNTER_ENUM(quad8_synch_mode_enum, quad8_synchronous_modes);
1023
1024 static struct counter_comp quad8_index_ext[] = {
1025         COUNTER_COMP_SIGNAL_ENUM("index_polarity", quad8_index_polarity_get,
1026                                  quad8_index_polarity_set,
1027                                  quad8_index_pol_enum),
1028         COUNTER_COMP_POLARITY(quad8_polarity_read, quad8_polarity_write,
1029                               quad8_polarity_available),
1030         COUNTER_COMP_SIGNAL_ENUM("synchronous_mode", quad8_synchronous_mode_get,
1031                                  quad8_synchronous_mode_set,
1032                                  quad8_synch_mode_enum),
1033 };
1034
1035 #define QUAD8_QUAD_SIGNAL(_id, _name) {         \
1036         .id = (_id),                            \
1037         .name = (_name),                        \
1038         .ext = quad8_signal_ext,                \
1039         .num_ext = ARRAY_SIZE(quad8_signal_ext) \
1040 }
1041
1042 #define QUAD8_INDEX_SIGNAL(_id, _name) {        \
1043         .id = (_id),                            \
1044         .name = (_name),                        \
1045         .ext = quad8_index_ext,                 \
1046         .num_ext = ARRAY_SIZE(quad8_index_ext)  \
1047 }
1048
1049 static struct counter_signal quad8_signals[] = {
1050         QUAD8_QUAD_SIGNAL(0, "Channel 1 Quadrature A"),
1051         QUAD8_QUAD_SIGNAL(1, "Channel 1 Quadrature B"),
1052         QUAD8_QUAD_SIGNAL(2, "Channel 2 Quadrature A"),
1053         QUAD8_QUAD_SIGNAL(3, "Channel 2 Quadrature B"),
1054         QUAD8_QUAD_SIGNAL(4, "Channel 3 Quadrature A"),
1055         QUAD8_QUAD_SIGNAL(5, "Channel 3 Quadrature B"),
1056         QUAD8_QUAD_SIGNAL(6, "Channel 4 Quadrature A"),
1057         QUAD8_QUAD_SIGNAL(7, "Channel 4 Quadrature B"),
1058         QUAD8_QUAD_SIGNAL(8, "Channel 5 Quadrature A"),
1059         QUAD8_QUAD_SIGNAL(9, "Channel 5 Quadrature B"),
1060         QUAD8_QUAD_SIGNAL(10, "Channel 6 Quadrature A"),
1061         QUAD8_QUAD_SIGNAL(11, "Channel 6 Quadrature B"),
1062         QUAD8_QUAD_SIGNAL(12, "Channel 7 Quadrature A"),
1063         QUAD8_QUAD_SIGNAL(13, "Channel 7 Quadrature B"),
1064         QUAD8_QUAD_SIGNAL(14, "Channel 8 Quadrature A"),
1065         QUAD8_QUAD_SIGNAL(15, "Channel 8 Quadrature B"),
1066         QUAD8_INDEX_SIGNAL(16, "Channel 1 Index"),
1067         QUAD8_INDEX_SIGNAL(17, "Channel 2 Index"),
1068         QUAD8_INDEX_SIGNAL(18, "Channel 3 Index"),
1069         QUAD8_INDEX_SIGNAL(19, "Channel 4 Index"),
1070         QUAD8_INDEX_SIGNAL(20, "Channel 5 Index"),
1071         QUAD8_INDEX_SIGNAL(21, "Channel 6 Index"),
1072         QUAD8_INDEX_SIGNAL(22, "Channel 7 Index"),
1073         QUAD8_INDEX_SIGNAL(23, "Channel 8 Index")
1074 };
1075
1076 #define QUAD8_COUNT_SYNAPSES(_id) {                                     \
1077         {                                                               \
1078                 .actions_list = quad8_synapse_actions_list,             \
1079                 .num_actions = ARRAY_SIZE(quad8_synapse_actions_list),  \
1080                 .signal = quad8_signals + 2 * (_id)                     \
1081         },                                                              \
1082         {                                                               \
1083                 .actions_list = quad8_synapse_actions_list,             \
1084                 .num_actions = ARRAY_SIZE(quad8_synapse_actions_list),  \
1085                 .signal = quad8_signals + 2 * (_id) + 1                 \
1086         },                                                              \
1087         {                                                               \
1088                 .actions_list = quad8_index_actions_list,               \
1089                 .num_actions = ARRAY_SIZE(quad8_index_actions_list),    \
1090                 .signal = quad8_signals + 2 * (_id) + 16                \
1091         }                                                               \
1092 }
1093
1094 static struct counter_synapse quad8_count_synapses[][3] = {
1095         QUAD8_COUNT_SYNAPSES(0), QUAD8_COUNT_SYNAPSES(1),
1096         QUAD8_COUNT_SYNAPSES(2), QUAD8_COUNT_SYNAPSES(3),
1097         QUAD8_COUNT_SYNAPSES(4), QUAD8_COUNT_SYNAPSES(5),
1098         QUAD8_COUNT_SYNAPSES(6), QUAD8_COUNT_SYNAPSES(7)
1099 };
1100
1101 static const enum counter_count_mode quad8_cnt_modes[] = {
1102         COUNTER_COUNT_MODE_NORMAL,
1103         COUNTER_COUNT_MODE_RANGE_LIMIT,
1104         COUNTER_COUNT_MODE_NON_RECYCLE,
1105         COUNTER_COUNT_MODE_MODULO_N,
1106 };
1107
1108 static DEFINE_COUNTER_AVAILABLE(quad8_count_mode_available, quad8_cnt_modes);
1109
1110 static DEFINE_COUNTER_ENUM(quad8_error_noise_enum, quad8_noise_error_states);
1111
1112 static struct counter_comp quad8_count_ext[] = {
1113         COUNTER_COMP_CEILING(quad8_count_ceiling_read,
1114                              quad8_count_ceiling_write),
1115         COUNTER_COMP_FLOOR(quad8_count_floor_read, NULL),
1116         COUNTER_COMP_COUNT_MODE(quad8_count_mode_read, quad8_count_mode_write,
1117                                 quad8_count_mode_available),
1118         COUNTER_COMP_DIRECTION(quad8_direction_read),
1119         COUNTER_COMP_ENABLE(quad8_count_enable_read, quad8_count_enable_write),
1120         COUNTER_COMP_COUNT_ENUM("error_noise", quad8_error_noise_get, NULL,
1121                                 quad8_error_noise_enum),
1122         COUNTER_COMP_PRESET(quad8_count_preset_read, quad8_count_preset_write),
1123         COUNTER_COMP_PRESET_ENABLE(quad8_count_preset_enable_read,
1124                                    quad8_count_preset_enable_write),
1125 };
1126
1127 #define QUAD8_COUNT(_id, _cntname) {                                    \
1128         .id = (_id),                                                    \
1129         .name = (_cntname),                                             \
1130         .functions_list = quad8_count_functions_list,                   \
1131         .num_functions = ARRAY_SIZE(quad8_count_functions_list),        \
1132         .synapses = quad8_count_synapses[(_id)],                        \
1133         .num_synapses = 2,                                              \
1134         .ext = quad8_count_ext,                                         \
1135         .num_ext = ARRAY_SIZE(quad8_count_ext)                          \
1136 }
1137
1138 static struct counter_count quad8_counts[] = {
1139         QUAD8_COUNT(0, "Channel 1 Count"),
1140         QUAD8_COUNT(1, "Channel 2 Count"),
1141         QUAD8_COUNT(2, "Channel 3 Count"),
1142         QUAD8_COUNT(3, "Channel 4 Count"),
1143         QUAD8_COUNT(4, "Channel 5 Count"),
1144         QUAD8_COUNT(5, "Channel 6 Count"),
1145         QUAD8_COUNT(6, "Channel 7 Count"),
1146         QUAD8_COUNT(7, "Channel 8 Count")
1147 };
1148
1149 static irqreturn_t quad8_irq_handler(int irq, void *private)
1150 {
1151         struct counter_device *counter = private;
1152         struct quad8 *const priv = counter_priv(counter);
1153         unsigned long irq_status;
1154         unsigned long channel;
1155         u8 event;
1156
1157         irq_status = ioread8(&priv->reg->interrupt_status);
1158         if (!irq_status)
1159                 return IRQ_NONE;
1160
1161         for_each_set_bit(channel, &irq_status, QUAD8_NUM_COUNTERS) {
1162                 switch (priv->irq_trigger[channel]) {
1163                 case QUAD8_EVENT_CARRY:
1164                         event = COUNTER_EVENT_OVERFLOW;
1165                                 break;
1166                 case QUAD8_EVENT_COMPARE:
1167                         event = COUNTER_EVENT_THRESHOLD;
1168                                 break;
1169                 case QUAD8_EVENT_CARRY_BORROW:
1170                         event = COUNTER_EVENT_OVERFLOW_UNDERFLOW;
1171                                 break;
1172                 case QUAD8_EVENT_INDEX:
1173                         event = COUNTER_EVENT_INDEX;
1174                                 break;
1175                 default:
1176                         /* should never reach this path */
1177                         WARN_ONCE(true, "invalid interrupt trigger function %u configured for channel %lu\n",
1178                                   priv->irq_trigger[channel], channel);
1179                         continue;
1180                 }
1181
1182                 counter_push_event(counter, event, channel);
1183         }
1184
1185         /* Clear pending interrupts on device */
1186         iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper);
1187
1188         return IRQ_HANDLED;
1189 }
1190
1191 static void quad8_init_counter(struct channel_reg __iomem *const chan)
1192 {
1193         unsigned long i;
1194
1195         /* Reset Byte Pointer */
1196         iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
1197         /* Reset filter clock factor */
1198         iowrite8(0, &chan->data);
1199         iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
1200                  &chan->control);
1201         /* Reset Byte Pointer */
1202         iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
1203         /* Reset Preset Register */
1204         for (i = 0; i < 3; i++)
1205                 iowrite8(0x00, &chan->data);
1206         /* Reset Borrow, Carry, Compare, and Sign flags */
1207         iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control);
1208         /* Reset Error flag */
1209         iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control);
1210         /* Binary encoding; Normal count; non-quadrature mode */
1211         iowrite8(QUAD8_CTR_CMR, &chan->control);
1212         /* Disable A and B inputs; preset on index; FLG1 as Carry */
1213         iowrite8(QUAD8_CTR_IOR, &chan->control);
1214         /* Disable index function; negative index polarity */
1215         iowrite8(QUAD8_CTR_IDR, &chan->control);
1216 }
1217
1218 static int quad8_probe(struct device *dev, unsigned int id)
1219 {
1220         struct counter_device *counter;
1221         struct quad8 *priv;
1222         unsigned long i;
1223         int err;
1224
1225         if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) {
1226                 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
1227                         base[id], base[id] + QUAD8_EXTENT);
1228                 return -EBUSY;
1229         }
1230
1231         counter = devm_counter_alloc(dev, sizeof(*priv));
1232         if (!counter)
1233                 return -ENOMEM;
1234         priv = counter_priv(counter);
1235
1236         priv->reg = devm_ioport_map(dev, base[id], QUAD8_EXTENT);
1237         if (!priv->reg)
1238                 return -ENOMEM;
1239
1240         /* Initialize Counter device and driver data */
1241         counter->name = dev_name(dev);
1242         counter->parent = dev;
1243         counter->ops = &quad8_ops;
1244         counter->counts = quad8_counts;
1245         counter->num_counts = ARRAY_SIZE(quad8_counts);
1246         counter->signals = quad8_signals;
1247         counter->num_signals = ARRAY_SIZE(quad8_signals);
1248
1249         spin_lock_init(&priv->lock);
1250
1251         /* Reset Index/Interrupt Register */
1252         iowrite8(0x00, &priv->reg->index_interrupt);
1253         /* Reset all counters and disable interrupt function */
1254         iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, &priv->reg->channel_oper);
1255         /* Set initial configuration for all counters */
1256         for (i = 0; i < QUAD8_NUM_COUNTERS; i++)
1257                 quad8_init_counter(priv->reg->channel + i);
1258         /* Disable Differential Encoder Cable Status for all channels */
1259         iowrite8(0xFF, &priv->reg->cable_status);
1260         /* Enable all counters and enable interrupt function */
1261         iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper);
1262
1263         err = devm_request_irq(&counter->dev, irq[id], quad8_irq_handler,
1264                                IRQF_SHARED, counter->name, counter);
1265         if (err)
1266                 return err;
1267
1268         err = devm_counter_add(dev, counter);
1269         if (err < 0)
1270                 return dev_err_probe(dev, err, "Failed to add counter\n");
1271
1272         return 0;
1273 }
1274
1275 static struct isa_driver quad8_driver = {
1276         .probe = quad8_probe,
1277         .driver = {
1278                 .name = "104-quad-8"
1279         }
1280 };
1281
1282 module_isa_driver_with_irq(quad8_driver, num_quad8, num_irq);
1283
1284 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
1285 MODULE_DESCRIPTION("ACCES 104-QUAD-8 driver");
1286 MODULE_LICENSE("GPL v2");
1287 MODULE_IMPORT_NS(COUNTER);