1 // SPDX-License-Identifier: GPL-2.0
4 * Quatech DAQP PCMCIA data capture cards COMEDI client driver
5 * Copyright (C) 2000, 2003 Brent Baccala <baccala@freesoft.org>
6 * The DAQP interface code in this file is released into the public domain.
8 * COMEDI - Linux Control and Measurement Device Interface
9 * Copyright (C) 1998 David A. Schleef <ds@schleef.org>
10 * https://www.comedi.org/
12 * Documentation for the DAQP PCMCIA cards can be found on Quatech's site:
13 * ftp://ftp.quatech.com/Manuals/daqp-208.pdf
15 * This manual is for both the DAQP-208 and the DAQP-308.
21 * - ground ref or differential
22 * - single-shot and timed both supported
23 * - D/A conversion, single-shot
27 * - any kind of triggering - external or D/A channel 1
28 * - the card's optional expansion board
29 * - the card's timer (for anything other than A/D conversion)
30 * - D/A update modes other than immediate (i.e, timed)
31 * - fancier timing modes
32 * - setting card's FIFO buffer thresholds to anything but default
36 * Driver: quatech_daqp_cs
37 * Description: Quatech DAQP PCMCIA data capture cards
38 * Devices: [Quatech] DAQP-208 (daqp), DAQP-308
39 * Author: Brent Baccala <baccala@freesoft.org>
43 #include <linux/module.h>
45 #include "../comedi_pcmcia.h"
50 * The D/A and timer registers can be accessed with 16-bit or 8-bit I/O
51 * instructions. All other registers can only use 8-bit instructions.
53 * The FIFO and scanlist registers require two 8-bit instructions to
54 * access the 16-bit data. Data is transferred LSB then MSB.
56 #define DAQP_AI_FIFO_REG 0x00
58 #define DAQP_SCANLIST_REG 0x01
59 #define DAQP_SCANLIST_DIFFERENTIAL BIT(14)
60 #define DAQP_SCANLIST_GAIN(x) (((x) & 0x3) << 12)
61 #define DAQP_SCANLIST_CHANNEL(x) (((x) & 0xf) << 8)
62 #define DAQP_SCANLIST_START BIT(7)
63 #define DAQP_SCANLIST_EXT_GAIN(x) (((x) & 0x3) << 4)
64 #define DAQP_SCANLIST_EXT_CHANNEL(x) (((x) & 0xf) << 0)
66 #define DAQP_CTRL_REG 0x02
67 #define DAQP_CTRL_PACER_CLK(x) (((x) & 0x3) << 6)
68 #define DAQP_CTRL_PACER_CLK_EXT DAQP_CTRL_PACER_CLK(0)
69 #define DAQP_CTRL_PACER_CLK_5MHZ DAQP_CTRL_PACER_CLK(1)
70 #define DAQP_CTRL_PACER_CLK_1MHZ DAQP_CTRL_PACER_CLK(2)
71 #define DAQP_CTRL_PACER_CLK_100KHZ DAQP_CTRL_PACER_CLK(3)
72 #define DAQP_CTRL_EXPANSION BIT(5)
73 #define DAQP_CTRL_EOS_INT_ENA BIT(4)
74 #define DAQP_CTRL_FIFO_INT_ENA BIT(3)
75 #define DAQP_CTRL_TRIG_MODE BIT(2) /* 0=one-shot; 1=continuous */
76 #define DAQP_CTRL_TRIG_SRC BIT(1) /* 0=internal; 1=external */
77 #define DAQP_CTRL_TRIG_EDGE BIT(0) /* 0=rising; 1=falling */
79 #define DAQP_STATUS_REG 0x02
80 #define DAQP_STATUS_IDLE BIT(7)
81 #define DAQP_STATUS_RUNNING BIT(6)
82 #define DAQP_STATUS_DATA_LOST BIT(5)
83 #define DAQP_STATUS_END_OF_SCAN BIT(4)
84 #define DAQP_STATUS_FIFO_THRESHOLD BIT(3)
85 #define DAQP_STATUS_FIFO_FULL BIT(2)
86 #define DAQP_STATUS_FIFO_NEARFULL BIT(1)
87 #define DAQP_STATUS_FIFO_EMPTY BIT(0)
88 /* these bits clear when the status register is read */
89 #define DAQP_STATUS_EVENTS (DAQP_STATUS_DATA_LOST | \
90 DAQP_STATUS_END_OF_SCAN | \
91 DAQP_STATUS_FIFO_THRESHOLD)
93 #define DAQP_DI_REG 0x03
94 #define DAQP_DO_REG 0x03
96 #define DAQP_PACER_LOW_REG 0x04
97 #define DAQP_PACER_MID_REG 0x05
98 #define DAQP_PACER_HIGH_REG 0x06
100 #define DAQP_CMD_REG 0x07
101 /* the monostable bits are self-clearing after the function is complete */
102 #define DAQP_CMD_ARM BIT(7) /* monostable */
103 #define DAQP_CMD_RSTF BIT(6) /* monostable */
104 #define DAQP_CMD_RSTQ BIT(5) /* monostable */
105 #define DAQP_CMD_STOP BIT(4) /* monostable */
106 #define DAQP_CMD_LATCH BIT(3) /* monostable */
107 #define DAQP_CMD_SCANRATE(x) (((x) & 0x3) << 1)
108 #define DAQP_CMD_SCANRATE_100KHZ DAQP_CMD_SCANRATE(0)
109 #define DAQP_CMD_SCANRATE_50KHZ DAQP_CMD_SCANRATE(1)
110 #define DAQP_CMD_SCANRATE_25KHZ DAQP_CMD_SCANRATE(2)
111 #define DAQP_CMD_FIFO_DATA BIT(0)
113 #define DAQP_AO_REG 0x08 /* and 0x09 (16-bit) */
115 #define DAQP_TIMER_REG 0x0a /* and 0x0b (16-bit) */
117 #define DAQP_AUX_REG 0x0f
118 /* Auxiliary Control register bits (write) */
119 #define DAQP_AUX_EXT_ANALOG_TRIG BIT(7)
120 #define DAQP_AUX_PRETRIG BIT(6)
121 #define DAQP_AUX_TIMER_INT_ENA BIT(5)
122 #define DAQP_AUX_TIMER_MODE(x) (((x) & 0x3) << 3)
123 #define DAQP_AUX_TIMER_MODE_RELOAD DAQP_AUX_TIMER_MODE(0)
124 #define DAQP_AUX_TIMER_MODE_PAUSE DAQP_AUX_TIMER_MODE(1)
125 #define DAQP_AUX_TIMER_MODE_GO DAQP_AUX_TIMER_MODE(2)
126 #define DAQP_AUX_TIMER_MODE_EXT DAQP_AUX_TIMER_MODE(3)
127 #define DAQP_AUX_TIMER_CLK_SRC_EXT BIT(2)
128 #define DAQP_AUX_DA_UPDATE(x) (((x) & 0x3) << 0)
129 #define DAQP_AUX_DA_UPDATE_DIRECT DAQP_AUX_DA_UPDATE(0)
130 #define DAQP_AUX_DA_UPDATE_OVERFLOW DAQP_AUX_DA_UPDATE(1)
131 #define DAQP_AUX_DA_UPDATE_EXTERNAL DAQP_AUX_DA_UPDATE(2)
132 #define DAQP_AUX_DA_UPDATE_PACER DAQP_AUX_DA_UPDATE(3)
133 /* Auxiliary Status register bits (read) */
134 #define DAQP_AUX_RUNNING BIT(7)
135 #define DAQP_AUX_TRIGGERED BIT(6)
136 #define DAQP_AUX_DA_BUFFER BIT(5)
137 #define DAQP_AUX_TIMER_OVERFLOW BIT(4)
138 #define DAQP_AUX_CONVERSION BIT(3)
139 #define DAQP_AUX_DATA_LOST BIT(2)
140 #define DAQP_AUX_FIFO_NEARFULL BIT(1)
141 #define DAQP_AUX_FIFO_EMPTY BIT(0)
143 #define DAQP_FIFO_SIZE 4096
145 #define DAQP_MAX_TIMER_SPEED 10000 /* 100 kHz in nanoseconds */
147 struct daqp_private {
148 unsigned int pacer_div;
152 static const struct comedi_lrange range_daqp_ai = {
161 static int daqp_clear_events(struct comedi_device *dev, int loops)
166 * Reset any pending interrupts (my card has a tendency to require
167 * multiple reads on the status register to achieve this).
170 status = inb(dev->iobase + DAQP_STATUS_REG);
171 if ((status & DAQP_STATUS_EVENTS) == 0)
174 dev_err(dev->class_dev, "couldn't clear events in status register\n");
178 static int daqp_ai_cancel(struct comedi_device *dev,
179 struct comedi_subdevice *s)
181 struct daqp_private *devpriv = dev->private;
187 * Stop any conversions, disable interrupts, and clear
188 * the status event flags.
190 outb(DAQP_CMD_STOP, dev->iobase + DAQP_CMD_REG);
191 outb(0, dev->iobase + DAQP_CTRL_REG);
192 inb(dev->iobase + DAQP_STATUS_REG);
197 static unsigned int daqp_ai_get_sample(struct comedi_device *dev,
198 struct comedi_subdevice *s)
203 * Get a two's complement sample from the FIFO and
204 * return the munged offset binary value.
206 val = inb(dev->iobase + DAQP_AI_FIFO_REG);
207 val |= inb(dev->iobase + DAQP_AI_FIFO_REG) << 8;
208 return comedi_offset_munge(s, val);
211 static irqreturn_t daqp_interrupt(int irq, void *dev_id)
213 struct comedi_device *dev = dev_id;
214 struct comedi_subdevice *s = dev->read_subdev;
215 struct comedi_cmd *cmd = &s->async->cmd;
216 int loop_limit = 10000;
222 status = inb(dev->iobase + DAQP_STATUS_REG);
223 if (!(status & DAQP_STATUS_EVENTS))
226 while (!(status & DAQP_STATUS_FIFO_EMPTY)) {
229 if (status & DAQP_STATUS_DATA_LOST) {
230 s->async->events |= COMEDI_CB_OVERFLOW;
231 dev_warn(dev->class_dev, "data lost\n");
235 data = daqp_ai_get_sample(dev, s);
236 comedi_buf_write_samples(s, &data, 1);
238 if (cmd->stop_src == TRIG_COUNT &&
239 s->async->scans_done >= cmd->stop_arg) {
240 s->async->events |= COMEDI_CB_EOA;
244 if ((loop_limit--) <= 0)
247 status = inb(dev->iobase + DAQP_STATUS_REG);
250 if (loop_limit <= 0) {
251 dev_warn(dev->class_dev,
252 "loop_limit reached in %s()\n", __func__);
253 s->async->events |= COMEDI_CB_ERROR;
256 comedi_handle_events(dev, s);
261 static void daqp_ai_set_one_scanlist_entry(struct comedi_device *dev,
262 unsigned int chanspec,
265 unsigned int chan = CR_CHAN(chanspec);
266 unsigned int range = CR_RANGE(chanspec);
267 unsigned int aref = CR_AREF(chanspec);
270 val = DAQP_SCANLIST_CHANNEL(chan) | DAQP_SCANLIST_GAIN(range);
272 if (aref == AREF_DIFF)
273 val |= DAQP_SCANLIST_DIFFERENTIAL;
276 val |= DAQP_SCANLIST_START;
278 outb(val & 0xff, dev->iobase + DAQP_SCANLIST_REG);
279 outb((val >> 8) & 0xff, dev->iobase + DAQP_SCANLIST_REG);
282 static int daqp_ai_eos(struct comedi_device *dev,
283 struct comedi_subdevice *s,
284 struct comedi_insn *insn,
285 unsigned long context)
289 status = inb(dev->iobase + DAQP_AUX_REG);
290 if (status & DAQP_AUX_CONVERSION)
295 static int daqp_ai_insn_read(struct comedi_device *dev,
296 struct comedi_subdevice *s,
297 struct comedi_insn *insn,
300 struct daqp_private *devpriv = dev->private;
307 outb(0, dev->iobase + DAQP_AUX_REG);
309 /* Reset scan list queue */
310 outb(DAQP_CMD_RSTQ, dev->iobase + DAQP_CMD_REG);
312 /* Program one scan list entry */
313 daqp_ai_set_one_scanlist_entry(dev, insn->chanspec, 1);
315 /* Reset data FIFO (see page 28 of DAQP User's Manual) */
316 outb(DAQP_CMD_RSTF, dev->iobase + DAQP_CMD_REG);
318 /* Set trigger - one-shot, internal, no interrupts */
319 outb(DAQP_CTRL_PACER_CLK_100KHZ, dev->iobase + DAQP_CTRL_REG);
321 ret = daqp_clear_events(dev, 10000);
325 for (i = 0; i < insn->n; i++) {
326 /* Start conversion */
327 outb(DAQP_CMD_ARM | DAQP_CMD_FIFO_DATA,
328 dev->iobase + DAQP_CMD_REG);
330 ret = comedi_timeout(dev, s, insn, daqp_ai_eos, 0);
334 /* clear the status event flags */
335 inb(dev->iobase + DAQP_STATUS_REG);
337 data[i] = daqp_ai_get_sample(dev, s);
340 /* stop any conversions and clear the status event flags */
341 outb(DAQP_CMD_STOP, dev->iobase + DAQP_CMD_REG);
342 inb(dev->iobase + DAQP_STATUS_REG);
344 return ret ? ret : insn->n;
347 /* This function converts ns nanoseconds to a counter value suitable
348 * for programming the device. We always use the DAQP's 5 MHz clock,
349 * which with its 24-bit counter, allows values up to 84 seconds.
350 * Also, the function adjusts ns so that it cooresponds to the actual
351 * time that the device will use.
354 static int daqp_ns_to_timer(unsigned int *ns, unsigned int flags)
364 static void daqp_set_pacer(struct comedi_device *dev, unsigned int val)
366 outb(val & 0xff, dev->iobase + DAQP_PACER_LOW_REG);
367 outb((val >> 8) & 0xff, dev->iobase + DAQP_PACER_MID_REG);
368 outb((val >> 16) & 0xff, dev->iobase + DAQP_PACER_HIGH_REG);
371 static int daqp_ai_cmdtest(struct comedi_device *dev,
372 struct comedi_subdevice *s,
373 struct comedi_cmd *cmd)
375 struct daqp_private *devpriv = dev->private;
379 /* Step 1 : check if triggers are trivially valid */
381 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
382 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
383 TRIG_TIMER | TRIG_FOLLOW);
384 err |= comedi_check_trigger_src(&cmd->convert_src,
385 TRIG_TIMER | TRIG_NOW);
386 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
387 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
392 /* Step 2a : make sure trigger sources are unique */
394 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
395 err |= comedi_check_trigger_is_unique(cmd->convert_src);
396 err |= comedi_check_trigger_is_unique(cmd->stop_src);
398 /* Step 2b : and mutually compatible */
400 /* the async command requires a pacer */
401 if (cmd->scan_begin_src != TRIG_TIMER && cmd->convert_src != TRIG_TIMER)
407 /* Step 3: check if arguments are trivially valid */
409 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
411 err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1);
412 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
415 if (cmd->scan_begin_src == TRIG_TIMER)
416 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
417 DAQP_MAX_TIMER_SPEED);
419 if (cmd->convert_src == TRIG_TIMER) {
420 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
421 DAQP_MAX_TIMER_SPEED);
423 if (cmd->scan_begin_src == TRIG_TIMER) {
425 * If both scan_begin and convert are both timer
426 * values, the only way that can make sense is if
427 * the scan time is the number of conversions times
430 arg = cmd->convert_arg * cmd->scan_end_arg;
431 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg,
436 if (cmd->stop_src == TRIG_COUNT)
437 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
439 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
444 /* step 4: fix up any arguments */
446 if (cmd->convert_src == TRIG_TIMER) {
447 arg = cmd->convert_arg;
448 devpriv->pacer_div = daqp_ns_to_timer(&arg, cmd->flags);
449 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, arg);
450 } else if (cmd->scan_begin_src == TRIG_TIMER) {
451 arg = cmd->scan_begin_arg;
452 devpriv->pacer_div = daqp_ns_to_timer(&arg, cmd->flags);
453 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
462 static int daqp_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
464 struct daqp_private *devpriv = dev->private;
465 struct comedi_cmd *cmd = &s->async->cmd;
466 int scanlist_start_on_every_entry;
474 outb(0, dev->iobase + DAQP_AUX_REG);
476 /* Reset scan list queue */
477 outb(DAQP_CMD_RSTQ, dev->iobase + DAQP_CMD_REG);
479 /* Program pacer clock
481 * There's two modes we can operate in. If convert_src is
482 * TRIG_TIMER, then convert_arg specifies the time between
483 * each conversion, so we program the pacer clock to that
484 * frequency and set the SCANLIST_START bit on every scanlist
485 * entry. Otherwise, convert_src is TRIG_NOW, which means
486 * we want the fastest possible conversions, scan_begin_src
487 * is TRIG_TIMER, and scan_begin_arg specifies the time between
488 * each scan, so we program the pacer clock to this frequency
489 * and only set the SCANLIST_START bit on the first entry.
491 daqp_set_pacer(dev, devpriv->pacer_div);
493 if (cmd->convert_src == TRIG_TIMER)
494 scanlist_start_on_every_entry = 1;
496 scanlist_start_on_every_entry = 0;
498 /* Program scan list */
499 for (i = 0; i < cmd->chanlist_len; i++) {
500 int start = (i == 0 || scanlist_start_on_every_entry);
502 daqp_ai_set_one_scanlist_entry(dev, cmd->chanlist[i], start);
505 /* Now it's time to program the FIFO threshold, basically the
506 * number of samples the card will buffer before it interrupts
509 * If we don't have a stop count, then use half the size of
510 * the FIFO (the manufacturer's recommendation). Consider
511 * that the FIFO can hold 2K samples (4K bytes). With the
512 * threshold set at half the FIFO size, we have a margin of
513 * error of 1024 samples. At the chip's maximum sample rate
514 * of 100,000 Hz, the CPU would have to delay interrupt
515 * service for a full 10 milliseconds in order to lose data
516 * here (as opposed to higher up in the kernel). I've never
517 * seen it happen. However, for slow sample rates it may
518 * buffer too much data and introduce too much delay for the
521 * If we have a stop count, then things get more interesting.
522 * If the stop count is less than the FIFO size (actually
523 * three-quarters of the FIFO size - see below), we just use
524 * the stop count itself as the threshold, the card interrupts
525 * us when that many samples have been taken, and we kill the
526 * acquisition at that point and are done. If the stop count
527 * is larger than that, then we divide it by 2 until it's less
528 * than three quarters of the FIFO size (we always leave the
529 * top quarter of the FIFO as protection against sluggish CPU
530 * interrupt response) and use that as the threshold. So, if
531 * the stop count is 4000 samples, we divide by two twice to
532 * get 1000 samples, use that as the threshold, take four
533 * interrupts to get our 4000 samples and are done.
535 * The algorithm could be more clever. For example, if 81000
536 * samples are requested, we could set the threshold to 1500
537 * samples and take 54 interrupts to get 81000. But 54 isn't
538 * a power of two, so this algorithm won't find that option.
539 * Instead, it'll set the threshold at 1266 and take 64
540 * interrupts to get 81024 samples, of which the last 24 will
541 * be discarded... but we won't get the last interrupt until
542 * they've been collected. To find the first option, the
543 * computer could look at the prime decomposition of the
544 * sample count (81000 = 3^4 * 5^3 * 2^3) and factor it into a
545 * threshold (1500 = 3 * 5^3 * 2^2) and an interrupt count (54
546 * = 3^3 * 2). Hmmm... a one-line while loop or prime
547 * decomposition of integers... I'll leave it the way it is.
549 * I'll also note a mini-race condition before ignoring it in
550 * the code. Let's say we're taking 4000 samples, as before.
551 * After 1000 samples, we get an interrupt. But before that
552 * interrupt is completely serviced, another sample is taken
553 * and loaded into the FIFO. Since the interrupt handler
554 * empties the FIFO before returning, it will read 1001 samples.
555 * If that happens four times, we'll end up taking 4004 samples,
556 * not 4000. The interrupt handler will discard the extra four
557 * samples (by halting the acquisition with four samples still
558 * in the FIFO), but we will have to wait for them.
560 * In short, this code works pretty well, but for either of
561 * the two reasons noted, might end up waiting for a few more
562 * samples than actually requested. Shouldn't make too much
566 /* Save away the number of conversions we should perform, and
567 * compute the FIFO threshold (in bytes, not samples - that's
568 * why we multiple devpriv->count by 2 = sizeof(sample))
571 if (cmd->stop_src == TRIG_COUNT) {
572 unsigned long long nsamples;
573 unsigned long long nbytes;
575 nsamples = (unsigned long long)cmd->stop_arg *
577 nbytes = nsamples * comedi_bytes_per_sample(s);
578 while (nbytes > DAQP_FIFO_SIZE * 3 / 4)
582 threshold = DAQP_FIFO_SIZE / 2;
585 /* Reset data FIFO (see page 28 of DAQP User's Manual) */
587 outb(DAQP_CMD_RSTF, dev->iobase + DAQP_CMD_REG);
589 /* Set FIFO threshold. First two bytes are near-empty
590 * threshold, which is unused; next two bytes are near-full
591 * threshold. We computed the number of bytes we want in the
592 * FIFO when the interrupt is generated, what the card wants
593 * is actually the number of available bytes left in the FIFO
594 * when the interrupt is to happen.
597 outb(0x00, dev->iobase + DAQP_AI_FIFO_REG);
598 outb(0x00, dev->iobase + DAQP_AI_FIFO_REG);
600 outb((DAQP_FIFO_SIZE - threshold) & 0xff,
601 dev->iobase + DAQP_AI_FIFO_REG);
602 outb((DAQP_FIFO_SIZE - threshold) >> 8, dev->iobase + DAQP_AI_FIFO_REG);
604 /* Set trigger - continuous, internal */
605 outb(DAQP_CTRL_TRIG_MODE | DAQP_CTRL_PACER_CLK_5MHZ |
606 DAQP_CTRL_FIFO_INT_ENA, dev->iobase + DAQP_CTRL_REG);
608 ret = daqp_clear_events(dev, 100);
612 /* Start conversion */
613 outb(DAQP_CMD_ARM | DAQP_CMD_FIFO_DATA, dev->iobase + DAQP_CMD_REG);
618 static int daqp_ao_empty(struct comedi_device *dev,
619 struct comedi_subdevice *s,
620 struct comedi_insn *insn,
621 unsigned long context)
625 status = inb(dev->iobase + DAQP_AUX_REG);
626 if ((status & DAQP_AUX_DA_BUFFER) == 0)
631 static int daqp_ao_insn_write(struct comedi_device *dev,
632 struct comedi_subdevice *s,
633 struct comedi_insn *insn,
636 struct daqp_private *devpriv = dev->private;
637 unsigned int chan = CR_CHAN(insn->chanspec);
643 /* Make sure D/A update mode is direct update */
644 outb(0, dev->iobase + DAQP_AUX_REG);
646 for (i = 0; i < insn->n; i++) {
647 unsigned int val = data[i];
650 /* D/A transfer rate is about 8ms */
651 ret = comedi_timeout(dev, s, insn, daqp_ao_empty, 0);
655 /* write the two's complement value to the channel */
656 outw((chan << 12) | comedi_offset_munge(s, val),
657 dev->iobase + DAQP_AO_REG);
659 s->readback[chan] = val;
665 static int daqp_di_insn_bits(struct comedi_device *dev,
666 struct comedi_subdevice *s,
667 struct comedi_insn *insn,
670 struct daqp_private *devpriv = dev->private;
675 data[0] = inb(dev->iobase + DAQP_DI_REG);
680 static int daqp_do_insn_bits(struct comedi_device *dev,
681 struct comedi_subdevice *s,
682 struct comedi_insn *insn,
685 struct daqp_private *devpriv = dev->private;
690 if (comedi_dio_update_state(s, data))
691 outb(s->state, dev->iobase + DAQP_DO_REG);
698 static int daqp_auto_attach(struct comedi_device *dev,
699 unsigned long context)
701 struct pcmcia_device *link = comedi_to_pcmcia_dev(dev);
702 struct daqp_private *devpriv;
703 struct comedi_subdevice *s;
706 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
710 link->config_flags |= CONF_AUTO_SET_IO | CONF_ENABLE_IRQ;
711 ret = comedi_pcmcia_enable(dev, NULL);
714 dev->iobase = link->resource[0]->start;
717 ret = pcmcia_request_irq(link, daqp_interrupt);
719 dev->irq = link->irq;
721 ret = comedi_alloc_subdevices(dev, 4);
725 s = &dev->subdevices[0];
726 s->type = COMEDI_SUBD_AI;
727 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF;
730 s->range_table = &range_daqp_ai;
731 s->insn_read = daqp_ai_insn_read;
733 dev->read_subdev = s;
734 s->subdev_flags |= SDF_CMD_READ;
735 s->len_chanlist = 2048;
736 s->do_cmdtest = daqp_ai_cmdtest;
737 s->do_cmd = daqp_ai_cmd;
738 s->cancel = daqp_ai_cancel;
741 s = &dev->subdevices[1];
742 s->type = COMEDI_SUBD_AO;
743 s->subdev_flags = SDF_WRITABLE;
746 s->range_table = &range_bipolar5;
747 s->insn_write = daqp_ao_insn_write;
749 ret = comedi_alloc_subdev_readback(s);
754 * Digital Input subdevice
755 * NOTE: The digital input lines are shared:
757 * Chan Normal Mode Expansion Mode
758 * ---- ----------------- ----------------------------
759 * 0 DI0, ext. trigger Same as normal mode
760 * 1 DI1 External gain select, lo bit
761 * 2 DI2, ext. clock Same as normal mode
762 * 3 DI3 External gain select, hi bit
764 s = &dev->subdevices[2];
765 s->type = COMEDI_SUBD_DI;
766 s->subdev_flags = SDF_READABLE;
769 s->insn_bits = daqp_di_insn_bits;
772 * Digital Output subdevice
773 * NOTE: The digital output lines share the same pins on the
774 * interface connector as the four external channel selection
775 * bits. If expansion mode is used the digital outputs do not
778 s = &dev->subdevices[3];
779 s->type = COMEDI_SUBD_DO;
780 s->subdev_flags = SDF_WRITABLE;
783 s->insn_bits = daqp_do_insn_bits;
788 static struct comedi_driver driver_daqp = {
789 .driver_name = "quatech_daqp_cs",
790 .module = THIS_MODULE,
791 .auto_attach = daqp_auto_attach,
792 .detach = comedi_pcmcia_disable,
795 static int daqp_cs_suspend(struct pcmcia_device *link)
797 struct comedi_device *dev = link->priv;
798 struct daqp_private *devpriv = dev ? dev->private : NULL;
800 /* Mark the device as stopped, to block IO until later */
807 static int daqp_cs_resume(struct pcmcia_device *link)
809 struct comedi_device *dev = link->priv;
810 struct daqp_private *devpriv = dev ? dev->private : NULL;
818 static int daqp_cs_attach(struct pcmcia_device *link)
820 return comedi_pcmcia_auto_config(link, &driver_daqp);
823 static const struct pcmcia_device_id daqp_cs_id_table[] = {
824 PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0027),
827 MODULE_DEVICE_TABLE(pcmcia, daqp_cs_id_table);
829 static struct pcmcia_driver daqp_cs_driver = {
830 .name = "quatech_daqp_cs",
831 .owner = THIS_MODULE,
832 .id_table = daqp_cs_id_table,
833 .probe = daqp_cs_attach,
834 .remove = comedi_pcmcia_auto_unconfig,
835 .suspend = daqp_cs_suspend,
836 .resume = daqp_cs_resume,
838 module_comedi_pcmcia_driver(driver_daqp, daqp_cs_driver);
840 MODULE_DESCRIPTION("Comedi driver for Quatech DAQP PCMCIA data capture cards");
841 MODULE_AUTHOR("Brent Baccala <baccala@freesoft.org>");
842 MODULE_LICENSE("GPL");