1 // SPDX-License-Identifier: GPL-2.0+
3 * Comedi driver for NI PCI-MIO E series cards
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
11 * Description: National Instruments PCI-MIO-E series and M series (all boards)
12 * Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
13 * Herman Bruyninckx, Terry Barnaby
15 * Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
16 * PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014,
17 * PCI-6040E, PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E,
18 * PCI-6071E, PCI-6023E, PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E,
19 * PCI-6035E, PCI-6052E, PCI-6110, PCI-6111, PCI-6220, PXI-6220,
20 * PCI-6221, PXI-6221, PCI-6224, PXI-6224, PCI-6225, PXI-6225,
21 * PCI-6229, PXI-6229, PCI-6250, PXI-6250, PCI-6251, PXI-6251,
22 * PCIe-6251, PXIe-6251, PCI-6254, PXI-6254, PCI-6259, PXI-6259,
23 * PCIe-6259, PXIe-6259, PCI-6280, PXI-6280, PCI-6281, PXI-6281,
24 * PCI-6284, PXI-6284, PCI-6289, PXI-6289, PCI-6711, PXI-6711,
25 * PCI-6713, PXI-6713, PXI-6071E, PCI-6070E, PXI-6070E,
26 * PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
28 * Updated: Mon, 16 Jan 2017 12:56:04 +0000
30 * These boards are almost identical to the AT-MIO E series, except that
31 * they use the PCI bus instead of ISA (i.e., AT). See the notes for the
32 * ni_atmio.o driver for additional information about these boards.
34 * Autocalibration is supported on many of the devices, using the
35 * comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
36 * M-Series boards do analog input and analog output calibration entirely
37 * in software. The software calibration corrects the analog input for
38 * offset, gain and nonlinearity. The analog outputs are corrected for
39 * offset and gain. See the comedilib documentation on
40 * comedi_get_softcal_converter() for more information.
42 * By default, the driver uses DMA to transfer analog input data to
43 * memory. When DMA is enabled, not all triggering features are
46 * Digital I/O may not work on 673x.
48 * Note that the PCI-6143 is a simultaineous sampling device with 8
49 * convertors. With this board all of the convertors perform one
50 * simultaineous sample during a scan interval. The period for a scan
51 * is used for the convert time in a Comedi cmd. The convert trigger
52 * source is normally set to TRIG_NOW by default.
54 * The RTSI trigger bus is supported on these cards on subdevice 10.
55 * See the comedilib documentation for details.
57 * Information (number of channels, bits, etc.) for some devices may be
58 * incorrect. Please check this and submit a bug if there are problems
61 * SCXI is probably broken for m-series boards.
64 * - When DMA is enabled, COMEDI_EV_CONVERT does not work correctly.
68 * The PCI-MIO E series driver was originally written by
69 * Tomasz Motylewski <...>, and ported to comedi by ds.
72 * 341079b.pdf PCI E Series Register-Level Programmer Manual
73 * 340934b.pdf DAQ-STC reference manual
75 * 322080b.pdf 6711/6713/6715 User Manual
77 * 320945c.pdf PCI E Series User Manual
78 * 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
81 * - need to deal with external reference for DAC, and other DAC
82 * properties in board properties
83 * - deal with at-mio-16de-10 revision D to N changes, etc.
84 * - need to add other CALDAC type
85 * - need to slow down DAC loading. I don't trust NI's claim that
86 * two writes to the PCI bus slows IO enough. I would prefer to
88 * Timing specs: (clock)
95 #include <linux/module.h>
96 #include <linux/delay.h>
98 #include "../comedi_pci.h"
100 #include <asm/byteorder.h>
108 * These are not all the possible ao ranges for 628x boards.
109 * They can do OFFSET +- REFERENCE where OFFSET can be
110 * 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
111 * be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
112 * 63 different possibilities. An AO channel
113 * can not act as it's own OFFSET or REFERENCE.
115 static const struct comedi_lrange range_ni_M_628x_ao = {
129 static const struct comedi_lrange range_ni_M_625x_ao = {
137 enum ni_pcimio_boardid {
138 BOARD_PCIMIO_16XE_50,
139 BOARD_PCIMIO_16XE_10,
208 static const struct ni_board_struct ni_boards[] = {
209 [BOARD_PCIMIO_16XE_50] = {
210 .name = "pci-mio-16xe-50",
212 .ai_maxdata = 0xffff,
213 .ai_fifo_depth = 2048,
215 .gainlkup = ai_gain_8,
218 .ao_maxdata = 0x0fff,
219 .ao_range_table = &range_bipolar10,
221 .caldac = { dac8800, dac8043 },
223 [BOARD_PCIMIO_16XE_10] = {
224 .name = "pci-mio-16xe-10", /* aka pci-6030E */
226 .ai_maxdata = 0xffff,
227 .ai_fifo_depth = 512,
229 .gainlkup = ai_gain_14,
232 .ao_maxdata = 0xffff,
233 .ao_fifo_depth = 2048,
234 .ao_range_table = &range_ni_E_ao_ext,
236 .caldac = { dac8800, dac8043, ad8522 },
241 .ai_maxdata = 0xffff,
242 .ai_fifo_depth = 512,
244 .gainlkup = ai_gain_4,
247 .ao_maxdata = 0xffff,
248 .ao_range_table = &range_bipolar10,
250 .caldac = { ad8804_debug },
255 .ai_maxdata = 0xffff,
256 .ai_fifo_depth = 512,
258 .gainlkup = ai_gain_14,
261 .ao_maxdata = 0xffff,
262 .ao_fifo_depth = 2048,
263 .ao_range_table = &range_ni_E_ao_ext,
265 .caldac = { dac8800, dac8043, ad8522 },
267 [BOARD_PCIMIO_16E_1] = {
268 .name = "pci-mio-16e-1", /* aka pci-6070e */
270 .ai_maxdata = 0x0fff,
271 .ai_fifo_depth = 512,
272 .gainlkup = ai_gain_16,
275 .ao_maxdata = 0x0fff,
276 .ao_fifo_depth = 2048,
277 .ao_range_table = &range_ni_E_ao_ext,
279 .caldac = { mb88341 },
281 [BOARD_PCIMIO_16E_4] = {
282 .name = "pci-mio-16e-4", /* aka pci-6040e */
284 .ai_maxdata = 0x0fff,
285 .ai_fifo_depth = 512,
286 .gainlkup = ai_gain_16,
288 * there have been reported problems with
289 * full speed on this board
293 .ao_maxdata = 0x0fff,
294 .ao_fifo_depth = 512,
295 .ao_range_table = &range_ni_E_ao_ext,
297 .caldac = { ad8804_debug }, /* doc says mb88341 */
302 .ai_maxdata = 0x0fff,
303 .ai_fifo_depth = 512,
304 .gainlkup = ai_gain_16,
307 .ao_maxdata = 0x0fff,
308 .ao_fifo_depth = 512,
309 .ao_range_table = &range_ni_E_ao_ext,
311 .caldac = { mb88341 },
316 .ai_maxdata = 0xffff,
317 .ai_fifo_depth = 512,
319 .gainlkup = ai_gain_14,
322 .ao_maxdata = 0xffff,
323 .ao_fifo_depth = 2048,
324 .ao_range_table = &range_ni_E_ao_ext,
326 .caldac = { dac8800, dac8043, ad8522 },
331 .ai_maxdata = 0xffff,
332 .ai_fifo_depth = 512,
334 .gainlkup = ai_gain_14,
336 .caldac = { dac8800, dac8043, ad8522 },
341 .ai_maxdata = 0xffff,
342 .ai_fifo_depth = 512,
344 .gainlkup = ai_gain_14,
346 .caldac = { dac8800, dac8043, ad8522 },
351 .ai_maxdata = 0x0fff,
352 .ai_fifo_depth = 512,
354 .gainlkup = ai_gain_16,
357 .ao_maxdata = 0x0fff,
358 .ao_fifo_depth = 2048,
359 .ao_range_table = &range_ni_E_ao_ext,
361 .caldac = { ad8804_debug },
366 .ai_maxdata = 0x0fff,
367 .ai_fifo_depth = 512,
368 .gainlkup = ai_gain_4,
370 .caldac = { ad8804_debug }, /* manual is wrong */
375 .ai_maxdata = 0x0fff,
376 .ai_fifo_depth = 512,
377 .gainlkup = ai_gain_4,
380 .ao_maxdata = 0x0fff,
381 .ao_range_table = &range_bipolar10,
383 .caldac = { ad8804_debug }, /* manual is wrong */
388 .ai_maxdata = 0x0fff,
389 .ai_fifo_depth = 512,
390 .gainlkup = ai_gain_4,
393 .ao_maxdata = 0x0fff,
394 .ao_range_table = &range_bipolar10,
396 .caldac = { ad8804_debug }, /* manual is wrong */
402 .ai_maxdata = 0x0fff,
403 .ai_fifo_depth = 512,
404 .gainlkup = ai_gain_4,
407 .ao_maxdata = 0x0fff,
408 .ao_range_table = &range_ni_E_ao_ext,
410 .caldac = { ad8804_debug }, /* manual is wrong */
416 .ai_maxdata = 0xffff,
417 .ai_fifo_depth = 512,
419 .gainlkup = ai_gain_4,
421 .caldac = { ad8804_debug },
426 .ai_maxdata = 0xffff,
427 .ai_fifo_depth = 512,
429 .gainlkup = ai_gain_4,
432 .ao_maxdata = 0x0fff,
433 .ao_range_table = &range_bipolar10,
435 .caldac = { ad8804_debug },
440 .ai_maxdata = 0xffff,
441 .ai_fifo_depth = 512,
443 .gainlkup = ai_gain_16,
446 .ao_maxdata = 0xffff,
447 .ao_fifo_depth = 2048,
448 .ao_range_table = &range_ni_E_ao_ext,
450 /* manual is wrong */
451 .caldac = { ad8804_debug, ad8804_debug, ad8522 },
456 .ai_maxdata = 0x0fff,
457 .ai_fifo_depth = 8192,
459 .gainlkup = ai_gain_611x,
462 .ao_maxdata = 0xffff,
463 .reg_type = ni_reg_611x,
464 .ao_range_table = &range_bipolar10,
465 .ao_fifo_depth = 2048,
467 .caldac = { ad8804, ad8804 },
472 .ai_maxdata = 0x0fff,
473 .ai_fifo_depth = 8192,
474 .gainlkup = ai_gain_611x,
477 .ao_maxdata = 0xffff,
478 .reg_type = ni_reg_611x,
479 .ao_range_table = &range_bipolar10,
480 .ao_fifo_depth = 2048,
482 .caldac = { ad8804, ad8804 },
485 /* The 6115 boards probably need their own driver */
486 [BOARD_PCI6115] = { /* .device_id = 0x2ed0, */
489 .ai_maxdata = 0x0fff,
490 .ai_fifo_depth = 8192,
491 .gainlkup = ai_gain_611x,
494 .ao_maxdata = 0xffff,
496 .ao_fifo_depth = 2048,
500 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
504 [BOARD_PXI6115] = { /* .device_id = ????, */
507 .ai_maxdata = 0x0fff,
508 .ai_fifo_depth = 8192,
509 .gainlkup = ai_gain_611x,
512 .ao_maxdata = 0xffff,
514 .ao_fifo_depth = 2048,
518 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
524 .ao_maxdata = 0x0fff,
525 /* data sheet says 8192, but fifo really holds 16384 samples */
526 .ao_fifo_depth = 16384,
527 .ao_range_table = &range_bipolar10,
529 .reg_type = ni_reg_6711,
530 .caldac = { ad8804_debug },
535 .ao_maxdata = 0x0fff,
536 .ao_fifo_depth = 16384,
537 .ao_range_table = &range_bipolar10,
539 .reg_type = ni_reg_6711,
540 .caldac = { ad8804_debug },
545 .ao_maxdata = 0x0fff,
546 .ao_fifo_depth = 16384,
547 .ao_range_table = &range_bipolar10,
549 .reg_type = ni_reg_6713,
550 .caldac = { ad8804_debug, ad8804_debug },
555 .ao_maxdata = 0x0fff,
556 .ao_fifo_depth = 16384,
557 .ao_range_table = &range_bipolar10,
559 .reg_type = ni_reg_6713,
560 .caldac = { ad8804_debug, ad8804_debug },
565 .ao_maxdata = 0xffff,
566 .ao_fifo_depth = 8192,
567 .ao_range_table = &range_bipolar10,
569 .reg_type = ni_reg_6711,
570 .caldac = { ad8804_debug },
573 [BOARD_PXI6731] = { /* .device_id = ????, */
576 .ao_maxdata = 0xffff,
577 .ao_fifo_depth = 8192,
578 .ao_range_table = &range_bipolar10,
579 .reg_type = ni_reg_6711,
580 .caldac = { ad8804_debug },
586 .ao_maxdata = 0xffff,
587 .ao_fifo_depth = 16384,
588 .ao_range_table = &range_bipolar10,
590 .reg_type = ni_reg_6713,
591 .caldac = { ad8804_debug, ad8804_debug },
596 .ao_maxdata = 0xffff,
597 .ao_fifo_depth = 16384,
598 .ao_range_table = &range_bipolar10,
600 .reg_type = ni_reg_6713,
601 .caldac = { ad8804_debug, ad8804_debug },
606 .ai_maxdata = 0x0fff,
607 .ai_fifo_depth = 512,
609 .gainlkup = ai_gain_16,
612 .ao_maxdata = 0x0fff,
613 .ao_fifo_depth = 2048,
614 .ao_range_table = &range_ni_E_ao_ext,
616 .caldac = { ad8804_debug },
621 .ai_maxdata = 0x0fff,
622 .ai_fifo_depth = 512,
624 .gainlkup = ai_gain_16,
627 .ao_maxdata = 0x0fff,
628 .ao_fifo_depth = 2048,
629 .ao_range_table = &range_ni_E_ao_ext,
631 .caldac = { ad8804_debug },
636 .ai_maxdata = 0xffff,
637 .ai_fifo_depth = 512,
639 .gainlkup = ai_gain_16,
642 .ao_maxdata = 0xffff,
643 .ao_fifo_depth = 2048,
644 .ao_range_table = &range_ni_E_ao_ext,
646 .caldac = { mb88341, mb88341, ad8522 },
651 .ai_maxdata = 0xffff,
652 .ai_fifo_depth = 512,
654 .gainlkup = ai_gain_14,
657 .ao_maxdata = 0xffff,
658 .ao_fifo_depth = 2048,
659 .ao_range_table = &range_ni_E_ao_ext,
661 .caldac = { dac8800, dac8043, ad8522 },
666 .ai_maxdata = 0xffff,
667 .ai_fifo_depth = 512,
669 .gainlkup = ai_gain_4,
672 .ao_maxdata = 0xffff,
673 .ao_range_table = &range_bipolar10,
675 .caldac = { ad8804_debug },
680 .ai_maxdata = 0xffff,
681 .ai_fifo_depth = 512, /* FIXME: guess */
682 .gainlkup = ai_gain_622x,
684 .reg_type = ni_reg_622x,
685 .caldac = { caldac_none },
690 .ai_maxdata = 0xffff,
691 .ai_fifo_depth = 512, /* FIXME: guess */
692 .gainlkup = ai_gain_622x,
694 .reg_type = ni_reg_622x,
695 .caldac = { caldac_none },
701 .ai_maxdata = 0xffff,
702 .ai_fifo_depth = 4095,
703 .gainlkup = ai_gain_622x,
706 .ao_maxdata = 0xffff,
707 .ao_fifo_depth = 8191,
708 .ao_range_table = &range_bipolar10,
709 .reg_type = ni_reg_622x,
711 .caldac = { caldac_none },
714 [BOARD_PCI6221_37PIN] = {
715 .name = "pci-6221_37pin",
717 .ai_maxdata = 0xffff,
718 .ai_fifo_depth = 4095,
719 .gainlkup = ai_gain_622x,
722 .ao_maxdata = 0xffff,
723 .ao_fifo_depth = 8191,
724 .ao_range_table = &range_bipolar10,
725 .reg_type = ni_reg_622x,
727 .caldac = { caldac_none },
732 .ai_maxdata = 0xffff,
733 .ai_fifo_depth = 4095,
734 .gainlkup = ai_gain_622x,
737 .ao_maxdata = 0xffff,
738 .ao_fifo_depth = 8191,
739 .ao_range_table = &range_bipolar10,
740 .reg_type = ni_reg_622x,
742 .caldac = { caldac_none },
748 .ai_maxdata = 0xffff,
749 .ai_fifo_depth = 4095,
750 .gainlkup = ai_gain_622x,
752 .reg_type = ni_reg_622x,
754 .caldac = { caldac_none },
760 .ai_maxdata = 0xffff,
761 .ai_fifo_depth = 4095,
762 .gainlkup = ai_gain_622x,
764 .reg_type = ni_reg_622x,
766 .caldac = { caldac_none },
772 .ai_maxdata = 0xffff,
773 .ai_fifo_depth = 4095,
774 .gainlkup = ai_gain_622x,
777 .ao_maxdata = 0xffff,
778 .ao_fifo_depth = 8191,
779 .ao_range_table = &range_bipolar10,
780 .reg_type = ni_reg_622x,
783 .caldac = { caldac_none },
789 .ai_maxdata = 0xffff,
790 .ai_fifo_depth = 4095,
791 .gainlkup = ai_gain_622x,
794 .ao_maxdata = 0xffff,
795 .ao_fifo_depth = 8191,
796 .ao_range_table = &range_bipolar10,
797 .reg_type = ni_reg_622x,
800 .caldac = { caldac_none },
806 .ai_maxdata = 0xffff,
807 .ai_fifo_depth = 4095,
808 .gainlkup = ai_gain_622x,
811 .ao_maxdata = 0xffff,
812 .ao_fifo_depth = 8191,
813 .ao_range_table = &range_bipolar10,
814 .reg_type = ni_reg_622x,
817 .caldac = { caldac_none },
822 .ai_maxdata = 0xffff,
823 .ai_fifo_depth = 4095,
824 .gainlkup = ai_gain_622x,
827 .ao_maxdata = 0xffff,
828 .ao_fifo_depth = 8191,
829 .ao_range_table = &range_bipolar10,
830 .reg_type = ni_reg_622x,
833 .caldac = { caldac_none },
839 .ai_maxdata = 0xffff,
840 .ai_fifo_depth = 4095,
841 .gainlkup = ai_gain_628x,
843 .reg_type = ni_reg_625x,
844 .caldac = { caldac_none },
849 .ai_maxdata = 0xffff,
850 .ai_fifo_depth = 4095,
851 .gainlkup = ai_gain_628x,
853 .reg_type = ni_reg_625x,
854 .caldac = { caldac_none },
860 .ai_maxdata = 0xffff,
861 .ai_fifo_depth = 4095,
862 .gainlkup = ai_gain_628x,
865 .ao_maxdata = 0xffff,
866 .ao_fifo_depth = 8191,
867 .ao_range_table = &range_ni_M_625x_ao,
868 .reg_type = ni_reg_625x,
870 .caldac = { caldac_none },
876 .ai_maxdata = 0xffff,
877 .ai_fifo_depth = 4095,
878 .gainlkup = ai_gain_628x,
881 .ao_maxdata = 0xffff,
882 .ao_fifo_depth = 8191,
883 .ao_range_table = &range_ni_M_625x_ao,
884 .reg_type = ni_reg_625x,
886 .caldac = { caldac_none },
891 .alt_route_name = "pci-6251",
893 .ai_maxdata = 0xffff,
894 .ai_fifo_depth = 4095,
895 .gainlkup = ai_gain_628x,
898 .ao_maxdata = 0xffff,
899 .ao_fifo_depth = 8191,
900 .ao_range_table = &range_ni_M_625x_ao,
901 .reg_type = ni_reg_625x,
903 .caldac = { caldac_none },
909 .ai_maxdata = 0xffff,
910 .ai_fifo_depth = 4095,
911 .gainlkup = ai_gain_628x,
914 .ao_maxdata = 0xffff,
915 .ao_fifo_depth = 8191,
916 .ao_range_table = &range_ni_M_625x_ao,
917 .reg_type = ni_reg_625x,
919 .caldac = { caldac_none },
925 .ai_maxdata = 0xffff,
926 .ai_fifo_depth = 4095,
927 .gainlkup = ai_gain_628x,
929 .reg_type = ni_reg_625x,
931 .caldac = { caldac_none },
936 .ai_maxdata = 0xffff,
937 .ai_fifo_depth = 4095,
938 .gainlkup = ai_gain_628x,
940 .reg_type = ni_reg_625x,
942 .caldac = { caldac_none },
948 .ai_maxdata = 0xffff,
949 .ai_fifo_depth = 4095,
950 .gainlkup = ai_gain_628x,
953 .ao_maxdata = 0xffff,
954 .ao_fifo_depth = 8191,
955 .ao_range_table = &range_ni_M_625x_ao,
956 .reg_type = ni_reg_625x,
959 .caldac = { caldac_none },
964 .ai_maxdata = 0xffff,
965 .ai_fifo_depth = 4095,
966 .gainlkup = ai_gain_628x,
969 .ao_maxdata = 0xffff,
970 .ao_fifo_depth = 8191,
971 .ao_range_table = &range_ni_M_625x_ao,
972 .reg_type = ni_reg_625x,
975 .caldac = { caldac_none },
980 .alt_route_name = "pci-6259",
982 .ai_maxdata = 0xffff,
983 .ai_fifo_depth = 4095,
984 .gainlkup = ai_gain_628x,
987 .ao_maxdata = 0xffff,
988 .ao_fifo_depth = 8191,
989 .ao_range_table = &range_ni_M_625x_ao,
990 .reg_type = ni_reg_625x,
993 .caldac = { caldac_none },
998 .ai_maxdata = 0xffff,
999 .ai_fifo_depth = 4095,
1000 .gainlkup = ai_gain_628x,
1003 .ao_maxdata = 0xffff,
1004 .ao_fifo_depth = 8191,
1005 .ao_range_table = &range_ni_M_625x_ao,
1006 .reg_type = ni_reg_625x,
1008 .has_32dio_chan = 1,
1009 .caldac = { caldac_none },
1015 .ai_maxdata = 0x3ffff,
1016 .ai_fifo_depth = 2047,
1017 .gainlkup = ai_gain_628x,
1019 .ao_fifo_depth = 8191,
1020 .reg_type = ni_reg_628x,
1021 .caldac = { caldac_none },
1026 .ai_maxdata = 0x3ffff,
1027 .ai_fifo_depth = 2047,
1028 .gainlkup = ai_gain_628x,
1030 .ao_fifo_depth = 8191,
1031 .reg_type = ni_reg_628x,
1032 .caldac = { caldac_none },
1038 .ai_maxdata = 0x3ffff,
1039 .ai_fifo_depth = 2047,
1040 .gainlkup = ai_gain_628x,
1043 .ao_maxdata = 0xffff,
1044 .ao_fifo_depth = 8191,
1045 .ao_range_table = &range_ni_M_628x_ao,
1046 .reg_type = ni_reg_628x,
1048 .caldac = { caldac_none },
1054 .ai_maxdata = 0x3ffff,
1055 .ai_fifo_depth = 2047,
1056 .gainlkup = ai_gain_628x,
1059 .ao_maxdata = 0xffff,
1060 .ao_fifo_depth = 8191,
1061 .ao_range_table = &range_ni_M_628x_ao,
1062 .reg_type = ni_reg_628x,
1064 .caldac = { caldac_none },
1070 .ai_maxdata = 0x3ffff,
1071 .ai_fifo_depth = 2047,
1072 .gainlkup = ai_gain_628x,
1074 .reg_type = ni_reg_628x,
1075 .has_32dio_chan = 1,
1076 .caldac = { caldac_none },
1081 .ai_maxdata = 0x3ffff,
1082 .ai_fifo_depth = 2047,
1083 .gainlkup = ai_gain_628x,
1085 .reg_type = ni_reg_628x,
1086 .has_32dio_chan = 1,
1087 .caldac = { caldac_none },
1093 .ai_maxdata = 0x3ffff,
1094 .ai_fifo_depth = 2047,
1095 .gainlkup = ai_gain_628x,
1098 .ao_maxdata = 0xffff,
1099 .ao_fifo_depth = 8191,
1100 .ao_range_table = &range_ni_M_628x_ao,
1101 .reg_type = ni_reg_628x,
1103 .has_32dio_chan = 1,
1104 .caldac = { caldac_none },
1109 .ai_maxdata = 0x3ffff,
1110 .ai_fifo_depth = 2047,
1111 .gainlkup = ai_gain_628x,
1114 .ao_maxdata = 0xffff,
1115 .ao_fifo_depth = 8191,
1116 .ao_range_table = &range_ni_M_628x_ao,
1117 .reg_type = ni_reg_628x,
1119 .has_32dio_chan = 1,
1120 .caldac = { caldac_none },
1126 .ai_maxdata = 0xffff,
1127 .ai_fifo_depth = 1024,
1128 .gainlkup = ai_gain_6143,
1130 .reg_type = ni_reg_6143,
1131 .caldac = { ad8804_debug, ad8804_debug },
1136 .ai_maxdata = 0xffff,
1137 .ai_fifo_depth = 1024,
1138 .gainlkup = ai_gain_6143,
1140 .reg_type = ni_reg_6143,
1141 .caldac = { ad8804_debug, ad8804_debug },
1145 #include "ni_mio_common.c"
1147 static int pcimio_ai_change(struct comedi_device *dev,
1148 struct comedi_subdevice *s)
1150 struct ni_private *devpriv = dev->private;
1153 ret = mite_buf_change(devpriv->ai_mite_ring, s);
1160 static int pcimio_ao_change(struct comedi_device *dev,
1161 struct comedi_subdevice *s)
1163 struct ni_private *devpriv = dev->private;
1166 ret = mite_buf_change(devpriv->ao_mite_ring, s);
1173 static int pcimio_gpct0_change(struct comedi_device *dev,
1174 struct comedi_subdevice *s)
1176 struct ni_private *devpriv = dev->private;
1179 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s);
1186 static int pcimio_gpct1_change(struct comedi_device *dev,
1187 struct comedi_subdevice *s)
1189 struct ni_private *devpriv = dev->private;
1192 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s);
1199 static int pcimio_dio_change(struct comedi_device *dev,
1200 struct comedi_subdevice *s)
1202 struct ni_private *devpriv = dev->private;
1205 ret = mite_buf_change(devpriv->cdo_mite_ring, s);
1212 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1214 struct ni_private *devpriv = dev->private;
1215 struct mite *mite = devpriv->mite;
1216 resource_size_t daq_phys_addr;
1217 static const int start_cal_eeprom = 0x400;
1218 static const unsigned int window_size = 10;
1219 unsigned int old_iodwbsr_bits;
1220 unsigned int old_iodwbsr1_bits;
1221 unsigned int old_iodwcr1_bits;
1224 /* IO Window 1 needs to be temporarily mapped to read the eeprom */
1225 daq_phys_addr = pci_resource_start(mite->pcidev, 1);
1227 old_iodwbsr_bits = readl(mite->mmio + MITE_IODWBSR);
1228 old_iodwbsr1_bits = readl(mite->mmio + MITE_IODWBSR_1);
1229 old_iodwcr1_bits = readl(mite->mmio + MITE_IODWCR_1);
1230 writel(0x0, mite->mmio + MITE_IODWBSR);
1231 writel(((0x80 | window_size) | daq_phys_addr),
1232 mite->mmio + MITE_IODWBSR_1);
1233 writel(0x1 | old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1234 writel(0xf, mite->mmio + 0x30);
1236 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1237 devpriv->eeprom_buffer[i] = ni_readb(dev, start_cal_eeprom + i);
1239 writel(old_iodwbsr1_bits, mite->mmio + MITE_IODWBSR_1);
1240 writel(old_iodwbsr_bits, mite->mmio + MITE_IODWBSR);
1241 writel(old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1242 writel(0x0, mite->mmio + 0x30);
1245 static void init_6143(struct comedi_device *dev)
1247 const struct ni_board_struct *board = dev->board_ptr;
1248 struct ni_private *devpriv = dev->private;
1250 /* Disable interrupts */
1251 ni_stc_writew(dev, 0, NISTC_INT_CTRL_REG);
1253 /* Initialise 6143 AI specific bits */
1255 /* Set G0,G1 DMA mode to E series version */
1256 ni_writeb(dev, 0x00, NI6143_MAGIC_REG);
1257 /* Set EOCMode, ADCMode and pipelinedelay */
1258 ni_writeb(dev, 0x80, NI6143_PIPELINE_DELAY_REG);
1260 ni_writeb(dev, 0x00, NI6143_EOC_SET_REG);
1262 /* Set the FIFO half full level */
1263 ni_writel(dev, board->ai_fifo_depth / 2, NI6143_AI_FIFO_FLAG_REG);
1265 /* Strobe Relay disable bit */
1266 devpriv->ai_calib_source_enabled = 0;
1267 ni_writew(dev, devpriv->ai_calib_source | NI6143_CALIB_CHAN_RELAY_OFF,
1268 NI6143_CALIB_CHAN_REG);
1269 ni_writew(dev, devpriv->ai_calib_source, NI6143_CALIB_CHAN_REG);
1272 static void pcimio_detach(struct comedi_device *dev)
1274 struct ni_private *devpriv = dev->private;
1276 mio_common_detach(dev);
1278 free_irq(dev->irq, dev);
1280 mite_free_ring(devpriv->ai_mite_ring);
1281 mite_free_ring(devpriv->ao_mite_ring);
1282 mite_free_ring(devpriv->cdo_mite_ring);
1283 mite_free_ring(devpriv->gpct_mite_ring[0]);
1284 mite_free_ring(devpriv->gpct_mite_ring[1]);
1285 mite_detach(devpriv->mite);
1289 comedi_pci_disable(dev);
1292 static int pcimio_auto_attach(struct comedi_device *dev,
1293 unsigned long context)
1295 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1296 const struct ni_board_struct *board = NULL;
1297 struct ni_private *devpriv;
1301 if (context < ARRAY_SIZE(ni_boards))
1302 board = &ni_boards[context];
1305 dev->board_ptr = board;
1306 dev->board_name = board->name;
1308 ret = comedi_pci_enable(dev);
1312 ret = ni_alloc_private(dev);
1315 devpriv = dev->private;
1317 devpriv->mite = mite_attach(dev, false); /* use win0 */
1321 if (board->reg_type & ni_reg_m_series_mask)
1322 devpriv->is_m_series = 1;
1323 if (board->reg_type & ni_reg_6xxx_mask)
1324 devpriv->is_6xxx = 1;
1325 if (board->reg_type == ni_reg_611x)
1326 devpriv->is_611x = 1;
1327 if (board->reg_type == ni_reg_6143)
1328 devpriv->is_6143 = 1;
1329 if (board->reg_type == ni_reg_622x)
1330 devpriv->is_622x = 1;
1331 if (board->reg_type == ni_reg_625x)
1332 devpriv->is_625x = 1;
1333 if (board->reg_type == ni_reg_628x)
1334 devpriv->is_628x = 1;
1335 if (board->reg_type & ni_reg_67xx_mask)
1336 devpriv->is_67xx = 1;
1337 if (board->reg_type == ni_reg_6711)
1338 devpriv->is_6711 = 1;
1339 if (board->reg_type == ni_reg_6713)
1340 devpriv->is_6713 = 1;
1342 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1343 if (!devpriv->ai_mite_ring)
1345 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1346 if (!devpriv->ao_mite_ring)
1348 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1349 if (!devpriv->cdo_mite_ring)
1351 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1352 if (!devpriv->gpct_mite_ring[0])
1354 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1355 if (!devpriv->gpct_mite_ring[1])
1358 if (devpriv->is_m_series)
1359 m_series_init_eeprom_buffer(dev);
1360 if (devpriv->is_6143)
1365 ret = request_irq(irq, ni_E_interrupt, IRQF_SHARED,
1366 dev->board_name, dev);
1371 ret = ni_E_init(dev, 0, 1);
1375 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1376 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1377 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1378 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1379 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1384 static struct comedi_driver ni_pcimio_driver = {
1385 .driver_name = "ni_pcimio",
1386 .module = THIS_MODULE,
1387 .auto_attach = pcimio_auto_attach,
1388 .detach = pcimio_detach,
1391 static int ni_pcimio_pci_probe(struct pci_dev *dev,
1392 const struct pci_device_id *id)
1394 return comedi_pci_auto_config(dev, &ni_pcimio_driver, id->driver_data);
1397 static const struct pci_device_id ni_pcimio_pci_table[] = {
1398 { PCI_VDEVICE(NI, 0x0162), BOARD_PCIMIO_16XE_50 }, /* 0x1620? */
1399 { PCI_VDEVICE(NI, 0x1170), BOARD_PCIMIO_16XE_10 },
1400 { PCI_VDEVICE(NI, 0x1180), BOARD_PCIMIO_16E_1 },
1401 { PCI_VDEVICE(NI, 0x1190), BOARD_PCIMIO_16E_4 },
1402 { PCI_VDEVICE(NI, 0x11b0), BOARD_PXI6070E },
1403 { PCI_VDEVICE(NI, 0x11c0), BOARD_PXI6040E },
1404 { PCI_VDEVICE(NI, 0x11d0), BOARD_PXI6030E },
1405 { PCI_VDEVICE(NI, 0x1270), BOARD_PCI6032E },
1406 { PCI_VDEVICE(NI, 0x1330), BOARD_PCI6031E },
1407 { PCI_VDEVICE(NI, 0x1340), BOARD_PCI6033E },
1408 { PCI_VDEVICE(NI, 0x1350), BOARD_PCI6071E },
1409 { PCI_VDEVICE(NI, 0x14e0), BOARD_PCI6110 },
1410 { PCI_VDEVICE(NI, 0x14f0), BOARD_PCI6111 },
1411 { PCI_VDEVICE(NI, 0x1580), BOARD_PXI6031E },
1412 { PCI_VDEVICE(NI, 0x15b0), BOARD_PXI6071E },
1413 { PCI_VDEVICE(NI, 0x1880), BOARD_PCI6711 },
1414 { PCI_VDEVICE(NI, 0x1870), BOARD_PCI6713 },
1415 { PCI_VDEVICE(NI, 0x18b0), BOARD_PCI6052E },
1416 { PCI_VDEVICE(NI, 0x18c0), BOARD_PXI6052E },
1417 { PCI_VDEVICE(NI, 0x2410), BOARD_PCI6733 },
1418 { PCI_VDEVICE(NI, 0x2420), BOARD_PXI6733 },
1419 { PCI_VDEVICE(NI, 0x2430), BOARD_PCI6731 },
1420 { PCI_VDEVICE(NI, 0x2890), BOARD_PCI6036E },
1421 { PCI_VDEVICE(NI, 0x28c0), BOARD_PCI6014 },
1422 { PCI_VDEVICE(NI, 0x2a60), BOARD_PCI6023E },
1423 { PCI_VDEVICE(NI, 0x2a70), BOARD_PCI6024E },
1424 { PCI_VDEVICE(NI, 0x2a80), BOARD_PCI6025E },
1425 { PCI_VDEVICE(NI, 0x2ab0), BOARD_PXI6025E },
1426 { PCI_VDEVICE(NI, 0x2b80), BOARD_PXI6713 },
1427 { PCI_VDEVICE(NI, 0x2b90), BOARD_PXI6711 },
1428 { PCI_VDEVICE(NI, 0x2c80), BOARD_PCI6035E },
1429 { PCI_VDEVICE(NI, 0x2ca0), BOARD_PCI6034E },
1430 { PCI_VDEVICE(NI, 0x70aa), BOARD_PCI6229 },
1431 { PCI_VDEVICE(NI, 0x70ab), BOARD_PCI6259 },
1432 { PCI_VDEVICE(NI, 0x70ac), BOARD_PCI6289 },
1433 { PCI_VDEVICE(NI, 0x70ad), BOARD_PXI6251 },
1434 { PCI_VDEVICE(NI, 0x70ae), BOARD_PXI6220 },
1435 { PCI_VDEVICE(NI, 0x70af), BOARD_PCI6221 },
1436 { PCI_VDEVICE(NI, 0x70b0), BOARD_PCI6220 },
1437 { PCI_VDEVICE(NI, 0x70b1), BOARD_PXI6229 },
1438 { PCI_VDEVICE(NI, 0x70b2), BOARD_PXI6259 },
1439 { PCI_VDEVICE(NI, 0x70b3), BOARD_PXI6289 },
1440 { PCI_VDEVICE(NI, 0x70b4), BOARD_PCI6250 },
1441 { PCI_VDEVICE(NI, 0x70b5), BOARD_PXI6221 },
1442 { PCI_VDEVICE(NI, 0x70b6), BOARD_PCI6280 },
1443 { PCI_VDEVICE(NI, 0x70b7), BOARD_PCI6254 },
1444 { PCI_VDEVICE(NI, 0x70b8), BOARD_PCI6251 },
1445 { PCI_VDEVICE(NI, 0x70b9), BOARD_PXI6250 },
1446 { PCI_VDEVICE(NI, 0x70ba), BOARD_PXI6254 },
1447 { PCI_VDEVICE(NI, 0x70bb), BOARD_PXI6280 },
1448 { PCI_VDEVICE(NI, 0x70bc), BOARD_PCI6284 },
1449 { PCI_VDEVICE(NI, 0x70bd), BOARD_PCI6281 },
1450 { PCI_VDEVICE(NI, 0x70be), BOARD_PXI6284 },
1451 { PCI_VDEVICE(NI, 0x70bf), BOARD_PXI6281 },
1452 { PCI_VDEVICE(NI, 0x70c0), BOARD_PCI6143 },
1453 { PCI_VDEVICE(NI, 0x70f2), BOARD_PCI6224 },
1454 { PCI_VDEVICE(NI, 0x70f3), BOARD_PXI6224 },
1455 { PCI_VDEVICE(NI, 0x710d), BOARD_PXI6143 },
1456 { PCI_VDEVICE(NI, 0x716c), BOARD_PCI6225 },
1457 { PCI_VDEVICE(NI, 0x716d), BOARD_PXI6225 },
1458 { PCI_VDEVICE(NI, 0x717d), BOARD_PCIE6251 },
1459 { PCI_VDEVICE(NI, 0x717f), BOARD_PCIE6259 },
1460 { PCI_VDEVICE(NI, 0x71bc), BOARD_PCI6221_37PIN },
1461 { PCI_VDEVICE(NI, 0x72e8), BOARD_PXIE6251 },
1462 { PCI_VDEVICE(NI, 0x72e9), BOARD_PXIE6259 },
1465 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1467 static struct pci_driver ni_pcimio_pci_driver = {
1468 .name = "ni_pcimio",
1469 .id_table = ni_pcimio_pci_table,
1470 .probe = ni_pcimio_pci_probe,
1471 .remove = comedi_pci_auto_unconfig,
1473 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1475 MODULE_AUTHOR("Comedi https://www.comedi.org");
1476 MODULE_DESCRIPTION("Comedi low-level driver");
1477 MODULE_LICENSE("GPL");