drivers/comedi/drivers/ni_mio_common.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Hardware driver for DAQ-STC based boards
   4  *
   5  * COMEDI - Linux Control and Measurement Device Interface
   6  * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
   7  * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   8  */
   9
  10 /*
  11  * This file is meant to be included by another file, e.g.,
  12  * ni_atmio.c or ni_pcimio.c.
  13  *
  14  * Interrupt support originally added by Truxton Fulton <trux@truxton.com>
  15  *
  16  * References (ftp://ftp.natinst.com/support/manuals):
  17  *   340747b.pdf  AT-MIO E series Register Level Programmer Manual
  18  *   341079b.pdf  PCI E Series RLPM
  19  *   340934b.pdf  DAQ-STC reference manual
  20  *
  21  * 67xx and 611x registers (ftp://ftp.ni.com/support/daq/mhddk/documentation/)
  22  *   release_ni611x.pdf
  23  *   release_ni67xx.pdf
  24  *
  25  * Other possibly relevant info:
  26  *   320517c.pdf  User manual (obsolete)
  27  *   320517f.pdf  User manual (new)
  28  *   320889a.pdf  delete
  29  *   320906c.pdf  maximum signal ratings
  30  *   321066a.pdf  about 16x
  31  *   321791a.pdf  discontinuation of at-mio-16e-10 rev. c
  32  *   321808a.pdf  about at-mio-16e-10 rev P
  33  *   321837a.pdf  discontinuation of at-mio-16de-10 rev d
  34  *   321838a.pdf  about at-mio-16de-10 rev N
  35  *
  36  * ISSUES:
  37  *   - the interrupt routine needs to be cleaned up
  38  *
  39  * 2006-02-07: S-Series PCI-6143: Support has been added but is not
  40  * fully tested as yet. Terry Barnaby, BEAM Ltd.
  41  */
  42
  43 #include <linux/interrupt.h>
  44 #include <linux/sched.h>
  45 #include <linux/delay.h>
  46 #include "8255.h"
  47 #include "mite.h"
  48
  49 /* A timeout count */
  50 #define NI_TIMEOUT 1000
  51
  52 /* Note: this table must match the ai_gain_* definitions */
  53 static const short ni_gainlkup[][16] = {
  54         [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
  55                         0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  56         [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
  57         [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
  58                         0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
  59         [ai_gain_4] = {0, 1, 4, 7},
  60         [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
  61                           0x003, 0x004, 0x005, 0x006},
  62         [ai_gain_622x] = {0, 1, 4, 5},
  63         [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
  64         [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  65 };
  66
  67 static const struct comedi_lrange range_ni_E_ai = {
  68         16, {
  69                 BIP_RANGE(10),
  70                 BIP_RANGE(5),
  71                 BIP_RANGE(2.5),
  72                 BIP_RANGE(1),
  73                 BIP_RANGE(0.5),
  74                 BIP_RANGE(0.25),
  75                 BIP_RANGE(0.1),
  76                 BIP_RANGE(0.05),
  77                 UNI_RANGE(20),
  78                 UNI_RANGE(10),
  79                 UNI_RANGE(5),
  80                 UNI_RANGE(2),
  81                 UNI_RANGE(1),
  82                 UNI_RANGE(0.5),
  83                 UNI_RANGE(0.2),
  84                 UNI_RANGE(0.1)
  85         }
  86 };
  87
  88 static const struct comedi_lrange range_ni_E_ai_limited = {
  89         8, {
  90                 BIP_RANGE(10),
  91                 BIP_RANGE(5),
  92                 BIP_RANGE(1),
  93                 BIP_RANGE(0.1),
  94                 UNI_RANGE(10),
  95                 UNI_RANGE(5),
  96                 UNI_RANGE(1),
  97                 UNI_RANGE(0.1)
  98         }
  99 };
 100
 101 static const struct comedi_lrange range_ni_E_ai_limited14 = {
 102         14, {
 103                 BIP_RANGE(10),
 104                 BIP_RANGE(5),
 105                 BIP_RANGE(2),
 106                 BIP_RANGE(1),
 107                 BIP_RANGE(0.5),
 108                 BIP_RANGE(0.2),
 109                 BIP_RANGE(0.1),
 110                 UNI_RANGE(10),
 111                 UNI_RANGE(5),
 112                 UNI_RANGE(2),
 113                 UNI_RANGE(1),
 114                 UNI_RANGE(0.5),
 115                 UNI_RANGE(0.2),
 116                 UNI_RANGE(0.1)
 117         }
 118 };
 119
 120 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
 121         4, {
 122                 BIP_RANGE(10),
 123                 BIP_RANGE(5),
 124                 BIP_RANGE(0.5),
 125                 BIP_RANGE(0.05)
 126         }
 127 };
 128
 129 static const struct comedi_lrange range_ni_E_ai_611x = {
 130         8, {
 131                 BIP_RANGE(50),
 132                 BIP_RANGE(20),
 133                 BIP_RANGE(10),
 134                 BIP_RANGE(5),
 135                 BIP_RANGE(2),
 136                 BIP_RANGE(1),
 137                 BIP_RANGE(0.5),
 138                 BIP_RANGE(0.2)
 139         }
 140 };
 141
 142 static const struct comedi_lrange range_ni_M_ai_622x = {
 143         4, {
 144                 BIP_RANGE(10),
 145                 BIP_RANGE(5),
 146                 BIP_RANGE(1),
 147                 BIP_RANGE(0.2)
 148         }
 149 };
 150
 151 static const struct comedi_lrange range_ni_M_ai_628x = {
 152         7, {
 153                 BIP_RANGE(10),
 154                 BIP_RANGE(5),
 155                 BIP_RANGE(2),
 156                 BIP_RANGE(1),
 157                 BIP_RANGE(0.5),
 158                 BIP_RANGE(0.2),
 159                 BIP_RANGE(0.1)
 160         }
 161 };
 162
 163 static const struct comedi_lrange range_ni_E_ao_ext = {
 164         4, {
 165                 BIP_RANGE(10),
 166                 UNI_RANGE(10),
 167                 RANGE_ext(-1, 1),
 168                 RANGE_ext(0, 1)
 169         }
 170 };
 171
 172 static const struct comedi_lrange *const ni_range_lkup[] = {
 173         [ai_gain_16] = &range_ni_E_ai,
 174         [ai_gain_8] = &range_ni_E_ai_limited,
 175         [ai_gain_14] = &range_ni_E_ai_limited14,
 176         [ai_gain_4] = &range_ni_E_ai_bipolar4,
 177         [ai_gain_611x] = &range_ni_E_ai_611x,
 178         [ai_gain_622x] = &range_ni_M_ai_622x,
 179         [ai_gain_628x] = &range_ni_M_ai_628x,
 180         [ai_gain_6143] = &range_bipolar5
 181 };
 182
 183 enum aimodes {
 184         AIMODE_NONE = 0,
 185         AIMODE_HALF_FULL = 1,
 186         AIMODE_SCAN = 2,
 187         AIMODE_SAMPLE = 3,
 188 };
 189
 190 enum ni_common_subdevices {
 191         NI_AI_SUBDEV,
 192         NI_AO_SUBDEV,
 193         NI_DIO_SUBDEV,
 194         NI_8255_DIO_SUBDEV,
 195         NI_UNUSED_SUBDEV,
 196         NI_CALIBRATION_SUBDEV,
 197         NI_EEPROM_SUBDEV,
 198         NI_PFI_DIO_SUBDEV,
 199         NI_CS5529_CALIBRATION_SUBDEV,
 200         NI_SERIAL_SUBDEV,
 201         NI_RTSI_SUBDEV,
 202         NI_GPCT0_SUBDEV,
 203         NI_GPCT1_SUBDEV,
 204         NI_FREQ_OUT_SUBDEV,
 205         NI_NUM_SUBDEVICES
 206 };
 207
 208 #define NI_GPCT_SUBDEV(x)       (NI_GPCT0_SUBDEV + (x))
 209
 210 enum timebase_nanoseconds {
 211         TIMEBASE_1_NS = 50,
 212         TIMEBASE_2_NS = 10000
 213 };
 214
 215 #define SERIAL_DISABLED         0
 216 #define SERIAL_600NS            600
 217 #define SERIAL_1_2US            1200
 218 #define SERIAL_10US                     10000
 219
 220 static const int num_adc_stages_611x = 3;
 221
 222 static void ni_writel(struct comedi_device *dev, unsigned int data, int reg)
 223 {
 224         if (dev->mmio)
 225                 writel(data, dev->mmio + reg);
 226         else
 227                 outl(data, dev->iobase + reg);
 228 }
 229
 230 static void ni_writew(struct comedi_device *dev, unsigned int data, int reg)
 231 {
 232         if (dev->mmio)
 233                 writew(data, dev->mmio + reg);
 234         else
 235                 outw(data, dev->iobase + reg);
 236 }
 237
 238 static void ni_writeb(struct comedi_device *dev, unsigned int data, int reg)
 239 {
 240         if (dev->mmio)
 241                 writeb(data, dev->mmio + reg);
 242         else
 243                 outb(data, dev->iobase + reg);
 244 }
 245
 246 static unsigned int ni_readl(struct comedi_device *dev, int reg)
 247 {
 248         if (dev->mmio)
 249                 return readl(dev->mmio + reg);
 250
 251         return inl(dev->iobase + reg);
 252 }
 253
 254 static unsigned int ni_readw(struct comedi_device *dev, int reg)
 255 {
 256         if (dev->mmio)
 257                 return readw(dev->mmio + reg);
 258
 259         return inw(dev->iobase + reg);
 260 }
 261
 262 static unsigned int ni_readb(struct comedi_device *dev, int reg)
 263 {
 264         if (dev->mmio)
 265                 return readb(dev->mmio + reg);
 266
 267         return inb(dev->iobase + reg);
 268 }
 269
 270 /*
 271  * We automatically take advantage of STC registers that can be
 272  * read/written directly in the I/O space of the board.
 273  *
 274  * The AT-MIO and DAQCard devices map the low 8 STC registers to
 275  * iobase+reg*2.
 276  *
 277  * Most PCIMIO devices also map the low 8 STC registers but the
 278  * 611x devices map the read registers to iobase+(addr-1)*2.
 279  * For now non-windowed STC access is disabled if a PCIMIO device
 280  * is detected (devpriv->mite has been initialized).
 281  *
 282  * The M series devices do not used windowed registers for the
 283  * STC registers. The functions below handle the mapping of the
 284  * windowed STC registers to the m series register offsets.
 285  */
 286
 287 struct mio_regmap {
 288         unsigned int mio_reg;
 289         int size;
 290 };
 291
 292 static const struct mio_regmap m_series_stc_write_regmap[] = {
 293         [NISTC_INTA_ACK_REG]            = { 0x104, 2 },
 294         [NISTC_INTB_ACK_REG]            = { 0x106, 2 },
 295         [NISTC_AI_CMD2_REG]             = { 0x108, 2 },
 296         [NISTC_AO_CMD2_REG]             = { 0x10a, 2 },
 297         [NISTC_G0_CMD_REG]              = { 0x10c, 2 },
 298         [NISTC_G1_CMD_REG]              = { 0x10e, 2 },
 299         [NISTC_AI_CMD1_REG]             = { 0x110, 2 },
 300         [NISTC_AO_CMD1_REG]             = { 0x112, 2 },
 301         /*
 302          * NISTC_DIO_OUT_REG maps to:
 303          * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
 304          */
 305         [NISTC_DIO_OUT_REG]             = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 306         [NISTC_DIO_CTRL_REG]            = { 0, 0 }, /* DOES NOT MAP CLEANLY */
 307         [NISTC_AI_MODE1_REG]            = { 0x118, 2 },
 308         [NISTC_AI_MODE2_REG]            = { 0x11a, 2 },
 309         [NISTC_AI_SI_LOADA_REG]         = { 0x11c, 4 },
 310         [NISTC_AI_SI_LOADB_REG]         = { 0x120, 4 },
 311         [NISTC_AI_SC_LOADA_REG]         = { 0x124, 4 },
 312         [NISTC_AI_SC_LOADB_REG]         = { 0x128, 4 },
 313         [NISTC_AI_SI2_LOADA_REG]        = { 0x12c, 4 },
 314         [NISTC_AI_SI2_LOADB_REG]        = { 0x130, 4 },
 315         [NISTC_G0_MODE_REG]             = { 0x134, 2 },
 316         [NISTC_G1_MODE_REG]             = { 0x136, 2 },
 317         [NISTC_G0_LOADA_REG]            = { 0x138, 4 },
 318         [NISTC_G0_LOADB_REG]            = { 0x13c, 4 },
 319         [NISTC_G1_LOADA_REG]            = { 0x140, 4 },
 320         [NISTC_G1_LOADB_REG]            = { 0x144, 4 },
 321         [NISTC_G0_INPUT_SEL_REG]        = { 0x148, 2 },
 322         [NISTC_G1_INPUT_SEL_REG]        = { 0x14a, 2 },
 323         [NISTC_AO_MODE1_REG]            = { 0x14c, 2 },
 324         [NISTC_AO_MODE2_REG]            = { 0x14e, 2 },
 325         [NISTC_AO_UI_LOADA_REG]         = { 0x150, 4 },
 326         [NISTC_AO_UI_LOADB_REG]         = { 0x154, 4 },
 327         [NISTC_AO_BC_LOADA_REG]         = { 0x158, 4 },
 328         [NISTC_AO_BC_LOADB_REG]         = { 0x15c, 4 },
 329         [NISTC_AO_UC_LOADA_REG]         = { 0x160, 4 },
 330         [NISTC_AO_UC_LOADB_REG]         = { 0x164, 4 },
 331         [NISTC_CLK_FOUT_REG]            = { 0x170, 2 },
 332         [NISTC_IO_BIDIR_PIN_REG]        = { 0x172, 2 },
 333         [NISTC_RTSI_TRIG_DIR_REG]       = { 0x174, 2 },
 334         [NISTC_INT_CTRL_REG]            = { 0x176, 2 },
 335         [NISTC_AI_OUT_CTRL_REG]         = { 0x178, 2 },
 336         [NISTC_ATRIG_ETC_REG]           = { 0x17a, 2 },
 337         [NISTC_AI_START_STOP_REG]       = { 0x17c, 2 },
 338         [NISTC_AI_TRIG_SEL_REG]         = { 0x17e, 2 },
 339         [NISTC_AI_DIV_LOADA_REG]        = { 0x180, 4 },
 340         [NISTC_AO_START_SEL_REG]        = { 0x184, 2 },
 341         [NISTC_AO_TRIG_SEL_REG]         = { 0x186, 2 },
 342         [NISTC_G0_AUTOINC_REG]          = { 0x188, 2 },
 343         [NISTC_G1_AUTOINC_REG]          = { 0x18a, 2 },
 344         [NISTC_AO_MODE3_REG]            = { 0x18c, 2 },
 345         [NISTC_RESET_REG]               = { 0x190, 2 },
 346         [NISTC_INTA_ENA_REG]            = { 0x192, 2 },
 347         [NISTC_INTA2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 348         [NISTC_INTB_ENA_REG]            = { 0x196, 2 },
 349         [NISTC_INTB2_ENA_REG]           = { 0, 0 }, /* E-Series only */
 350         [NISTC_AI_PERSONAL_REG]         = { 0x19a, 2 },
 351         [NISTC_AO_PERSONAL_REG]         = { 0x19c, 2 },
 352         [NISTC_RTSI_TRIGA_OUT_REG]      = { 0x19e, 2 },
 353         [NISTC_RTSI_TRIGB_OUT_REG]      = { 0x1a0, 2 },
 354         /* doc for following line: mhddk/nimseries/ChipObjects/tMSeries.h */
 355         [NISTC_RTSI_BOARD_REG]          = { 0x1a2, 2 },
 356         [NISTC_CFG_MEM_CLR_REG]         = { 0x1a4, 2 },
 357         [NISTC_ADC_FIFO_CLR_REG]        = { 0x1a6, 2 },
 358         [NISTC_DAC_FIFO_CLR_REG]        = { 0x1a8, 2 },
 359         [NISTC_AO_OUT_CTRL_REG]         = { 0x1ac, 2 },
 360         [NISTC_AI_MODE3_REG]            = { 0x1ae, 2 },
 361 };
 362
 363 static void m_series_stc_write(struct comedi_device *dev,
 364                                unsigned int data, unsigned int reg)
 365 {
 366         const struct mio_regmap *regmap;
 367
 368         if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
 369                 regmap = &m_series_stc_write_regmap[reg];
 370         } else {
 371                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 372                          __func__, reg);
 373                 return;
 374         }
 375
 376         switch (regmap->size) {
 377         case 4:
 378                 ni_writel(dev, data, regmap->mio_reg);
 379                 break;
 380         case 2:
 381                 ni_writew(dev, data, regmap->mio_reg);
 382                 break;
 383         default:
 384                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 385                          __func__, reg);
 386                 break;
 387         }
 388 }
 389
 390 static const struct mio_regmap m_series_stc_read_regmap[] = {
 391         [NISTC_AI_STATUS1_REG]          = { 0x104, 2 },
 392         [NISTC_AO_STATUS1_REG]          = { 0x106, 2 },
 393         [NISTC_G01_STATUS_REG]          = { 0x108, 2 },
 394         [NISTC_AI_STATUS2_REG]          = { 0, 0 }, /* Unknown */
 395         [NISTC_AO_STATUS2_REG]          = { 0x10c, 2 },
 396         [NISTC_DIO_IN_REG]              = { 0, 0 }, /* Unknown */
 397         [NISTC_G0_HW_SAVE_REG]          = { 0x110, 4 },
 398         [NISTC_G1_HW_SAVE_REG]          = { 0x114, 4 },
 399         [NISTC_G0_SAVE_REG]             = { 0x118, 4 },
 400         [NISTC_G1_SAVE_REG]             = { 0x11c, 4 },
 401         [NISTC_AO_UI_SAVE_REG]          = { 0x120, 4 },
 402         [NISTC_AO_BC_SAVE_REG]          = { 0x124, 4 },
 403         [NISTC_AO_UC_SAVE_REG]          = { 0x128, 4 },
 404         [NISTC_STATUS1_REG]             = { 0x136, 2 },
 405         [NISTC_DIO_SERIAL_IN_REG]       = { 0x009, 1 },
 406         [NISTC_STATUS2_REG]             = { 0x13a, 2 },
 407         [NISTC_AI_SI_SAVE_REG]          = { 0x180, 4 },
 408         [NISTC_AI_SC_SAVE_REG]          = { 0x184, 4 },
 409 };
 410
 411 static unsigned int m_series_stc_read(struct comedi_device *dev,
 412                                       unsigned int reg)
 413 {
 414         const struct mio_regmap *regmap;
 415
 416         if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
 417                 regmap = &m_series_stc_read_regmap[reg];
 418         } else {
 419                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
 420                          __func__, reg);
 421                 return 0;
 422         }
 423
 424         switch (regmap->size) {
 425         case 4:
 426                 return ni_readl(dev, regmap->mio_reg);
 427         case 2:
 428                 return ni_readw(dev, regmap->mio_reg);
 429         case 1:
 430                 return ni_readb(dev, regmap->mio_reg);
 431         default:
 432                 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
 433                          __func__, reg);
 434                 return 0;
 435         }
 436 }
 437
 438 static void ni_stc_writew(struct comedi_device *dev,
 439                           unsigned int data, int reg)
 440 {
 441         struct ni_private *devpriv = dev->private;
 442         unsigned long flags;
 443
 444         if (devpriv->is_m_series) {
 445                 m_series_stc_write(dev, data, reg);
 446         } else {
 447                 spin_lock_irqsave(&devpriv->window_lock, flags);
 448                 if (!devpriv->mite && reg < 8) {
 449                         ni_writew(dev, data, reg * 2);
 450                 } else {
 451                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 452                         ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
 453                 }
 454                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 455         }
 456 }
 457
 458 static void ni_stc_writel(struct comedi_device *dev,
 459                           unsigned int data, int reg)
 460 {
 461         struct ni_private *devpriv = dev->private;
 462
 463         if (devpriv->is_m_series) {
 464                 m_series_stc_write(dev, data, reg);
 465         } else {
 466                 ni_stc_writew(dev, data >> 16, reg);
 467                 ni_stc_writew(dev, data & 0xffff, reg + 1);
 468         }
 469 }
 470
 471 static unsigned int ni_stc_readw(struct comedi_device *dev, int reg)
 472 {
 473         struct ni_private *devpriv = dev->private;
 474         unsigned long flags;
 475         unsigned int val;
 476
 477         if (devpriv->is_m_series) {
 478                 val = m_series_stc_read(dev, reg);
 479         } else {
 480                 spin_lock_irqsave(&devpriv->window_lock, flags);
 481                 if (!devpriv->mite && reg < 8) {
 482                         val = ni_readw(dev, reg * 2);
 483                 } else {
 484                         ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
 485                         val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
 486                 }
 487                 spin_unlock_irqrestore(&devpriv->window_lock, flags);
 488         }
 489         return val;
 490 }
 491
 492 static unsigned int ni_stc_readl(struct comedi_device *dev, int reg)
 493 {
 494         struct ni_private *devpriv = dev->private;
 495         unsigned int val;
 496
 497         if (devpriv->is_m_series) {
 498                 val = m_series_stc_read(dev, reg);
 499         } else {
 500                 val = ni_stc_readw(dev, reg) << 16;
 501                 val |= ni_stc_readw(dev, reg + 1);
 502         }
 503         return val;
 504 }
 505
 506 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
 507                                    unsigned int bit_mask,
 508                                    unsigned int bit_values)
 509 {
 510         struct ni_private *devpriv = dev->private;
 511         unsigned long flags;
 512
 513         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 514         switch (reg) {
 515         case NISTC_INTA_ENA_REG:
 516                 devpriv->int_a_enable_reg &= ~bit_mask;
 517                 devpriv->int_a_enable_reg |= bit_values & bit_mask;
 518                 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
 519                 break;
 520         case NISTC_INTB_ENA_REG:
 521                 devpriv->int_b_enable_reg &= ~bit_mask;
 522                 devpriv->int_b_enable_reg |= bit_values & bit_mask;
 523                 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
 524                 break;
 525         case NISTC_IO_BIDIR_PIN_REG:
 526                 devpriv->io_bidirection_pin_reg &= ~bit_mask;
 527                 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
 528                 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
 529                 break;
 530         case NI_E_DMA_AI_AO_SEL_REG:
 531                 devpriv->ai_ao_select_reg &= ~bit_mask;
 532                 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
 533                 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
 534                 break;
 535         case NI_E_DMA_G0_G1_SEL_REG:
 536                 devpriv->g0_g1_select_reg &= ~bit_mask;
 537                 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
 538                 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
 539                 break;
 540         case NI_M_CDIO_DMA_SEL_REG:
 541                 devpriv->cdio_dma_select_reg &= ~bit_mask;
 542                 devpriv->cdio_dma_select_reg |= bit_values & bit_mask;
 543                 ni_writeb(dev, devpriv->cdio_dma_select_reg, reg);
 544                 break;
 545         default:
 546                 dev_err(dev->class_dev, "called with invalid register %d\n",
 547                         reg);
 548                 break;
 549         }
 550         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 551 }
 552
 553 #ifdef PCIDMA
 554
 555 /* selects the MITE channel to use for DMA */
 556 #define NI_STC_DMA_CHAN_SEL(x)  (((x) < 4) ? BIT(x) :   \
 557                                  ((x) == 4) ? 0x3 :     \
 558                                  ((x) == 5) ? 0x5 : 0x0)
 559
 560 /* DMA channel setup */
 561 static int ni_request_ai_mite_channel(struct comedi_device *dev)
 562 {
 563         struct ni_private *devpriv = dev->private;
 564         struct mite_channel *mite_chan;
 565         unsigned long flags;
 566         unsigned int bits;
 567
 568         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 569         mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
 570         if (!mite_chan) {
 571                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 572                 dev_err(dev->class_dev,
 573                         "failed to reserve mite dma channel for analog input\n");
 574                 return -EBUSY;
 575         }
 576         mite_chan->dir = COMEDI_INPUT;
 577         devpriv->ai_mite_chan = mite_chan;
 578
 579         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 580         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 581                         NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
 582
 583         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 584         return 0;
 585 }
 586
 587 static int ni_request_ao_mite_channel(struct comedi_device *dev)
 588 {
 589         struct ni_private *devpriv = dev->private;
 590         struct mite_channel *mite_chan;
 591         unsigned long flags;
 592         unsigned int bits;
 593
 594         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 595         mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
 596         if (!mite_chan) {
 597                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 598                 dev_err(dev->class_dev,
 599                         "failed to reserve mite dma channel for analog output\n");
 600                 return -EBUSY;
 601         }
 602         mite_chan->dir = COMEDI_OUTPUT;
 603         devpriv->ao_mite_chan = mite_chan;
 604
 605         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 606         ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 607                         NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
 608
 609         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 610         return 0;
 611 }
 612
 613 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
 614                                         unsigned int gpct_index,
 615                                         enum comedi_io_direction direction)
 616 {
 617         struct ni_private *devpriv = dev->private;
 618         struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index];
 619         struct mite_channel *mite_chan;
 620         unsigned long flags;
 621         unsigned int bits;
 622
 623         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 624         mite_chan = mite_request_channel(devpriv->mite,
 625                                          devpriv->gpct_mite_ring[gpct_index]);
 626         if (!mite_chan) {
 627                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 628                 dev_err(dev->class_dev,
 629                         "failed to reserve mite dma channel for counter\n");
 630                 return -EBUSY;
 631         }
 632         mite_chan->dir = direction;
 633         ni_tio_set_mite_channel(counter, mite_chan);
 634
 635         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 636         ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 637                         NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
 638                         NI_E_DMA_G0_G1_SEL(gpct_index, bits));
 639
 640         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 641         return 0;
 642 }
 643
 644 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
 645 {
 646         struct ni_private *devpriv = dev->private;
 647         struct mite_channel *mite_chan;
 648         unsigned long flags;
 649         unsigned int bits;
 650
 651         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 652         mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
 653         if (!mite_chan) {
 654                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 655                 dev_err(dev->class_dev,
 656                         "failed to reserve mite dma channel for correlated digital output\n");
 657                 return -EBUSY;
 658         }
 659         mite_chan->dir = COMEDI_OUTPUT;
 660         devpriv->cdo_mite_chan = mite_chan;
 661
 662         /*
 663          * XXX just guessing NI_STC_DMA_CHAN_SEL()
 664          * returns the right bits, under the assumption the cdio dma
 665          * selection works just like ai/ao/gpct.
 666          * Definitely works for dma channels 0 and 1.
 667          */
 668         bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel);
 669         ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
 670                         NI_M_CDIO_DMA_SEL_CDO_MASK,
 671                         NI_M_CDIO_DMA_SEL_CDO(bits));
 672
 673         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 674         return 0;
 675 }
 676 #endif /*  PCIDMA */
 677
 678 static void ni_release_ai_mite_channel(struct comedi_device *dev)
 679 {
 680 #ifdef PCIDMA
 681         struct ni_private *devpriv = dev->private;
 682         unsigned long flags;
 683
 684         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 685         if (devpriv->ai_mite_chan) {
 686                 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 687                                 NI_E_DMA_AI_SEL_MASK, 0);
 688                 mite_release_channel(devpriv->ai_mite_chan);
 689                 devpriv->ai_mite_chan = NULL;
 690         }
 691         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 692 #endif /*  PCIDMA */
 693 }
 694
 695 static void ni_release_ao_mite_channel(struct comedi_device *dev)
 696 {
 697 #ifdef PCIDMA
 698         struct ni_private *devpriv = dev->private;
 699         unsigned long flags;
 700
 701         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 702         if (devpriv->ao_mite_chan) {
 703                 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
 704                                 NI_E_DMA_AO_SEL_MASK, 0);
 705                 mite_release_channel(devpriv->ao_mite_chan);
 706                 devpriv->ao_mite_chan = NULL;
 707         }
 708         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 709 #endif /*  PCIDMA */
 710 }
 711
 712 #ifdef PCIDMA
 713 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
 714                                          unsigned int gpct_index)
 715 {
 716         struct ni_private *devpriv = dev->private;
 717         unsigned long flags;
 718
 719         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 720         if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
 721                 struct mite_channel *mite_chan =
 722                     devpriv->counter_dev->counters[gpct_index].mite_chan;
 723
 724                 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
 725                                 NI_E_DMA_G0_G1_SEL_MASK(gpct_index), 0);
 726                 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
 727                                         NULL);
 728                 mite_release_channel(mite_chan);
 729         }
 730         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 731 }
 732
 733 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
 734 {
 735         struct ni_private *devpriv = dev->private;
 736         unsigned long flags;
 737
 738         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 739         if (devpriv->cdo_mite_chan) {
 740                 ni_set_bitfield(dev, NI_M_CDIO_DMA_SEL_REG,
 741                                 NI_M_CDIO_DMA_SEL_CDO_MASK, 0);
 742                 mite_release_channel(devpriv->cdo_mite_chan);
 743                 devpriv->cdo_mite_chan = NULL;
 744         }
 745         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 746 }
 747
 748 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
 749                                           unsigned int gpct_index, short enable)
 750 {
 751         struct ni_private *devpriv = dev->private;
 752         unsigned int val = 0;
 753         int reg;
 754
 755         if (devpriv->is_m_series || gpct_index > 1)
 756                 return;
 757
 758         /*
 759          * e-series boards use the second irq signals to generate
 760          * dma requests for their counters
 761          */
 762         if (gpct_index == 0) {
 763                 reg = NISTC_INTA2_ENA_REG;
 764                 if (enable)
 765                         val = NISTC_INTA_ENA_G0_GATE;
 766         } else {
 767                 reg = NISTC_INTB2_ENA_REG;
 768                 if (enable)
 769                         val = NISTC_INTB_ENA_G1_GATE;
 770         }
 771         ni_stc_writew(dev, val, reg);
 772 }
 773 #endif /*  PCIDMA */
 774
 775 static void ni_clear_ai_fifo(struct comedi_device *dev)
 776 {
 777         struct ni_private *devpriv = dev->private;
 778         static const int timeout = 10000;
 779         int i;
 780
 781         if (devpriv->is_6143) {
 782                 /*  Flush the 6143 data FIFO */
 783                 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
 784                 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
 785                 /*  Wait for complete */
 786                 for (i = 0; i < timeout; i++) {
 787                         if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
 788                                 break;
 789                         udelay(1);
 790                 }
 791                 if (i == timeout)
 792                         dev_err(dev->class_dev, "FIFO flush timeout\n");
 793         } else {
 794                 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
 795                 if (devpriv->is_625x) {
 796                         ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
 797                         ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
 798 #if 0
 799                         /*
 800                          * The NI example code does 3 convert pulses for 625x
 801                          * boards, But that appears to be wrong in practice.
 802                          */
 803                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 804                                       NISTC_AI_CMD1_REG);
 805                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 806                                       NISTC_AI_CMD1_REG);
 807                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
 808                                       NISTC_AI_CMD1_REG);
 809 #endif
 810                 }
 811         }
 812 }
 813
 814 static inline void ni_ao_win_outw(struct comedi_device *dev,
 815                                   unsigned int data, int addr)
 816 {
 817         struct ni_private *devpriv = dev->private;
 818         unsigned long flags;
 819
 820         spin_lock_irqsave(&devpriv->window_lock, flags);
 821         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 822         ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
 823         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 824 }
 825
 826 static inline void ni_ao_win_outl(struct comedi_device *dev,
 827                                   unsigned int data, int addr)
 828 {
 829         struct ni_private *devpriv = dev->private;
 830         unsigned long flags;
 831
 832         spin_lock_irqsave(&devpriv->window_lock, flags);
 833         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 834         ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
 835         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 836 }
 837
 838 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
 839 {
 840         struct ni_private *devpriv = dev->private;
 841         unsigned long flags;
 842         unsigned short data;
 843
 844         spin_lock_irqsave(&devpriv->window_lock, flags);
 845         ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
 846         data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
 847         spin_unlock_irqrestore(&devpriv->window_lock, flags);
 848         return data;
 849 }
 850
 851 /*
 852  * ni_set_bits( ) allows different parts of the ni_mio_common driver to
 853  * share registers (such as Interrupt_A_Register) without interfering with
 854  * each other.
 855  *
 856  * NOTE: the switch/case statements are optimized out for a constant argument
 857  * so this is actually quite fast---  If you must wrap another function around
 858  * this make it inline to avoid a large speed penalty.
 859  *
 860  * value should only be 1 or 0.
 861  */
 862 static inline void ni_set_bits(struct comedi_device *dev, int reg,
 863                                unsigned int bits, unsigned int value)
 864 {
 865         unsigned int bit_values;
 866
 867         if (value)
 868                 bit_values = bits;
 869         else
 870                 bit_values = 0;
 871         ni_set_bitfield(dev, reg, bits, bit_values);
 872 }
 873
 874 #ifdef PCIDMA
 875 static void ni_sync_ai_dma(struct comedi_device *dev)
 876 {
 877         struct ni_private *devpriv = dev->private;
 878         struct comedi_subdevice *s = dev->read_subdev;
 879         unsigned long flags;
 880
 881         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 882         if (devpriv->ai_mite_chan)
 883                 mite_sync_dma(devpriv->ai_mite_chan, s);
 884         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 885 }
 886
 887 static int ni_ai_drain_dma(struct comedi_device *dev)
 888 {
 889         struct ni_private *devpriv = dev->private;
 890         int i;
 891         static const int timeout = 10000;
 892         unsigned long flags;
 893         int retval = 0;
 894
 895         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 896         if (devpriv->ai_mite_chan) {
 897                 for (i = 0; i < timeout; i++) {
 898                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
 899                              NISTC_AI_STATUS1_FIFO_E) &&
 900                             mite_bytes_in_transit(devpriv->ai_mite_chan) == 0)
 901                                 break;
 902                         udelay(5);
 903                 }
 904                 if (i == timeout) {
 905                         dev_err(dev->class_dev, "timed out\n");
 906                         dev_err(dev->class_dev,
 907                                 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
 908                                 mite_bytes_in_transit(devpriv->ai_mite_chan),
 909                                 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
 910                         retval = -1;
 911                 }
 912         }
 913         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 914
 915         ni_sync_ai_dma(dev);
 916
 917         return retval;
 918 }
 919
 920 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
 921 {
 922         static const int timeout = 10000;
 923         int i;
 924
 925         for (i = 0; i < timeout; i++) {
 926                 unsigned short b_status;
 927
 928                 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
 929                 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
 930                         break;
 931                 /*
 932                  * If we poll too often, the pci bus activity seems
 933                  * to slow the dma transfer down.
 934                  */
 935                 usleep_range(10, 100);
 936         }
 937         if (i == timeout) {
 938                 dev_err(dev->class_dev, "timed out waiting for dma load\n");
 939                 return -EPIPE;
 940         }
 941         return 0;
 942 }
 943 #endif /* PCIDMA */
 944
 945 #ifndef PCIDMA
 946
 947 static void ni_ao_fifo_load(struct comedi_device *dev,
 948                             struct comedi_subdevice *s, int n)
 949 {
 950         struct ni_private *devpriv = dev->private;
 951         int i;
 952         unsigned short d;
 953         unsigned int packed_data;
 954
 955         for (i = 0; i < n; i++) {
 956                 comedi_buf_read_samples(s, &d, 1);
 957
 958                 if (devpriv->is_6xxx) {
 959                         packed_data = d & 0xffff;
 960                         /* 6711 only has 16 bit wide ao fifo */
 961                         if (!devpriv->is_6711) {
 962                                 comedi_buf_read_samples(s, &d, 1);
 963                                 i++;
 964                                 packed_data |= (d << 16) & 0xffff0000;
 965                         }
 966                         ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
 967                 } else {
 968                         ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
 969                 }
 970         }
 971 }
 972
 973 /*
 974  *  There's a small problem if the FIFO gets really low and we
 975  *  don't have the data to fill it.  Basically, if after we fill
 976  *  the FIFO with all the data available, the FIFO is _still_
 977  *  less than half full, we never clear the interrupt.  If the
 978  *  IRQ is in edge mode, we never get another interrupt, because
 979  *  this one wasn't cleared.  If in level mode, we get flooded
 980  *  with interrupts that we can't fulfill, because nothing ever
 981  *  gets put into the buffer.
 982  *
 983  *  This kind of situation is recoverable, but it is easier to
 984  *  just pretend we had a FIFO underrun, since there is a good
 985  *  chance it will happen anyway.  This is _not_ the case for
 986  *  RT code, as RT code might purposely be running close to the
 987  *  metal.  Needs to be fixed eventually.
 988  */
 989 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
 990                                  struct comedi_subdevice *s)
 991 {
 992         const struct ni_board_struct *board = dev->board_ptr;
 993         unsigned int nbytes;
 994         unsigned int nsamples;
 995
 996         nbytes = comedi_buf_read_n_available(s);
 997         if (nbytes == 0) {
 998                 s->async->events |= COMEDI_CB_OVERFLOW;
 999                 return 0;
1000         }
1001
1002         nsamples = comedi_bytes_to_samples(s, nbytes);
1003         if (nsamples > board->ao_fifo_depth / 2)
1004                 nsamples = board->ao_fifo_depth / 2;
1005
1006         ni_ao_fifo_load(dev, s, nsamples);
1007
1008         return 1;
1009 }
1010
1011 static int ni_ao_prep_fifo(struct comedi_device *dev,
1012                            struct comedi_subdevice *s)
1013 {
1014         const struct ni_board_struct *board = dev->board_ptr;
1015         struct ni_private *devpriv = dev->private;
1016         unsigned int nbytes;
1017         unsigned int nsamples;
1018
1019         /* reset fifo */
1020         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1021         if (devpriv->is_6xxx)
1022                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1023
1024         /* load some data */
1025         nbytes = comedi_buf_read_n_available(s);
1026         if (nbytes == 0)
1027                 return 0;
1028
1029         nsamples = comedi_bytes_to_samples(s, nbytes);
1030         if (nsamples > board->ao_fifo_depth)
1031                 nsamples = board->ao_fifo_depth;
1032
1033         ni_ao_fifo_load(dev, s, nsamples);
1034
1035         return nsamples;
1036 }
1037
1038 static void ni_ai_fifo_read(struct comedi_device *dev,
1039                             struct comedi_subdevice *s, int n)
1040 {
1041         struct ni_private *devpriv = dev->private;
1042         struct comedi_async *async = s->async;
1043         unsigned int dl;
1044         unsigned short data;
1045         int i;
1046
1047         if (devpriv->is_611x) {
1048                 for (i = 0; i < n / 2; i++) {
1049                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1050                         /* This may get the hi/lo data in the wrong order */
1051                         data = (dl >> 16) & 0xffff;
1052                         comedi_buf_write_samples(s, &data, 1);
1053                         data = dl & 0xffff;
1054                         comedi_buf_write_samples(s, &data, 1);
1055                 }
1056                 /* Check if there's a single sample stuck in the FIFO */
1057                 if (n % 2) {
1058                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1059                         data = dl & 0xffff;
1060                         comedi_buf_write_samples(s, &data, 1);
1061                 }
1062         } else if (devpriv->is_6143) {
1063                 /*
1064                  * This just reads the FIFO assuming the data is present,
1065                  * no checks on the FIFO status are performed.
1066                  */
1067                 for (i = 0; i < n / 2; i++) {
1068                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1069
1070                         data = (dl >> 16) & 0xffff;
1071                         comedi_buf_write_samples(s, &data, 1);
1072                         data = dl & 0xffff;
1073                         comedi_buf_write_samples(s, &data, 1);
1074                 }
1075                 if (n % 2) {
1076                         /* Assume there is a single sample stuck in the FIFO */
1077                         /* Get stranded sample into FIFO */
1078                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1079                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1080                         data = (dl >> 16) & 0xffff;
1081                         comedi_buf_write_samples(s, &data, 1);
1082                 }
1083         } else {
1084                 if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) {
1085                         dev_err(dev->class_dev,
1086                                 "bug! ai_fifo_buffer too small\n");
1087                         async->events |= COMEDI_CB_ERROR;
1088                         return;
1089                 }
1090                 for (i = 0; i < n; i++) {
1091                         devpriv->ai_fifo_buffer[i] =
1092                             ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1093                 }
1094                 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1095         }
1096 }
1097
1098 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1099 {
1100         const struct ni_board_struct *board = dev->board_ptr;
1101         struct comedi_subdevice *s = dev->read_subdev;
1102         int n;
1103
1104         n = board->ai_fifo_depth / 2;
1105
1106         ni_ai_fifo_read(dev, s, n);
1107 }
1108 #endif
1109
1110 /* Empties the AI fifo */
1111 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1112 {
1113         struct ni_private *devpriv = dev->private;
1114         struct comedi_subdevice *s = dev->read_subdev;
1115         unsigned int dl;
1116         unsigned short data;
1117         int i;
1118
1119         if (devpriv->is_611x) {
1120                 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1121                         NISTC_AI_STATUS1_FIFO_E) == 0) {
1122                         dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1123
1124                         /* This may get the hi/lo data in the wrong order */
1125                         data = dl >> 16;
1126                         comedi_buf_write_samples(s, &data, 1);
1127                         data = dl & 0xffff;
1128                         comedi_buf_write_samples(s, &data, 1);
1129                 }
1130         } else if (devpriv->is_6143) {
1131                 i = 0;
1132                 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1133                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1134
1135                         /* This may get the hi/lo data in the wrong order */
1136                         data = dl >> 16;
1137                         comedi_buf_write_samples(s, &data, 1);
1138                         data = dl & 0xffff;
1139                         comedi_buf_write_samples(s, &data, 1);
1140                         i += 2;
1141                 }
1142                 /*  Check if stranded sample is present */
1143                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1144                         /* Get stranded sample into FIFO */
1145                         ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1146                         dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1147                         data = (dl >> 16) & 0xffff;
1148                         comedi_buf_write_samples(s, &data, 1);
1149                 }
1150
1151         } else {
1152                 unsigned short fe;      /* fifo empty */
1153
1154                 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1155                      NISTC_AI_STATUS1_FIFO_E;
1156                 while (fe == 0) {
1157                         for (i = 0;
1158                              i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) {
1159                                 fe = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1160                                      NISTC_AI_STATUS1_FIFO_E;
1161                                 if (fe)
1162                                         break;
1163                                 devpriv->ai_fifo_buffer[i] =
1164                                     ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1165                         }
1166                         comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1167                 }
1168         }
1169 }
1170
1171 static void get_last_sample_611x(struct comedi_device *dev)
1172 {
1173         struct ni_private *devpriv = dev->private;
1174         struct comedi_subdevice *s = dev->read_subdev;
1175         unsigned short data;
1176         unsigned int dl;
1177
1178         if (!devpriv->is_611x)
1179                 return;
1180
1181         /* Check if there's a single sample stuck in the FIFO */
1182         if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1183                 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1184                 data = dl & 0xffff;
1185                 comedi_buf_write_samples(s, &data, 1);
1186         }
1187 }
1188
1189 static void get_last_sample_6143(struct comedi_device *dev)
1190 {
1191         struct ni_private *devpriv = dev->private;
1192         struct comedi_subdevice *s = dev->read_subdev;
1193         unsigned short data;
1194         unsigned int dl;
1195
1196         if (!devpriv->is_6143)
1197                 return;
1198
1199         /* Check if there's a single sample stuck in the FIFO */
1200         if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1201                 /* Get stranded sample into FIFO */
1202                 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1203                 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1204
1205                 /* This may get the hi/lo data in the wrong order */
1206                 data = (dl >> 16) & 0xffff;
1207                 comedi_buf_write_samples(s, &data, 1);
1208         }
1209 }
1210
1211 static void shutdown_ai_command(struct comedi_device *dev)
1212 {
1213         struct comedi_subdevice *s = dev->read_subdev;
1214
1215 #ifdef PCIDMA
1216         ni_ai_drain_dma(dev);
1217 #endif
1218         ni_handle_fifo_dregs(dev);
1219         get_last_sample_611x(dev);
1220         get_last_sample_6143(dev);
1221
1222         s->async->events |= COMEDI_CB_EOA;
1223 }
1224
1225 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1226 {
1227         struct ni_private *devpriv = dev->private;
1228
1229         if (devpriv->aimode == AIMODE_SCAN) {
1230 #ifdef PCIDMA
1231                 static const int timeout = 10;
1232                 int i;
1233
1234                 for (i = 0; i < timeout; i++) {
1235                         ni_sync_ai_dma(dev);
1236                         if ((s->async->events & COMEDI_CB_EOS))
1237                                 break;
1238                         udelay(1);
1239                 }
1240 #else
1241                 ni_handle_fifo_dregs(dev);
1242                 s->async->events |= COMEDI_CB_EOS;
1243 #endif
1244         }
1245         /* handle special case of single scan */
1246         if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1247                 shutdown_ai_command(dev);
1248 }
1249
1250 static void handle_gpct_interrupt(struct comedi_device *dev,
1251                                   unsigned short counter_index)
1252 {
1253 #ifdef PCIDMA
1254         struct ni_private *devpriv = dev->private;
1255         struct comedi_subdevice *s;
1256
1257         s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1258
1259         ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1260                                 s);
1261         comedi_handle_events(dev, s);
1262 #endif
1263 }
1264
1265 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1266 {
1267         unsigned short ack = 0;
1268
1269         if (a_status & NISTC_AI_STATUS1_SC_TC)
1270                 ack |= NISTC_INTA_ACK_AI_SC_TC;
1271         if (a_status & NISTC_AI_STATUS1_START1)
1272                 ack |= NISTC_INTA_ACK_AI_START1;
1273         if (a_status & NISTC_AI_STATUS1_START)
1274                 ack |= NISTC_INTA_ACK_AI_START;
1275         if (a_status & NISTC_AI_STATUS1_STOP)
1276                 ack |= NISTC_INTA_ACK_AI_STOP;
1277         if (a_status & NISTC_AI_STATUS1_OVER)
1278                 ack |= NISTC_INTA_ACK_AI_ERR;
1279         if (ack)
1280                 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1281 }
1282
1283 static void handle_a_interrupt(struct comedi_device *dev,
1284                                struct comedi_subdevice *s,
1285                                unsigned short status)
1286 {
1287         struct comedi_cmd *cmd = &s->async->cmd;
1288
1289         /* test for all uncommon interrupt events at the same time */
1290         if (status & (NISTC_AI_STATUS1_ERR |
1291                       NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1292                 if (status == 0xffff) {
1293                         dev_err(dev->class_dev, "Card removed?\n");
1294                         /*
1295                          * We probably aren't even running a command now,
1296                          * so it's a good idea to be careful.
1297                          */
1298                         if (comedi_is_subdevice_running(s))
1299                                 s->async->events |= COMEDI_CB_ERROR;
1300                         return;
1301                 }
1302                 if (status & NISTC_AI_STATUS1_ERR) {
1303                         dev_err(dev->class_dev, "ai error a_status=%04x\n",
1304                                 status);
1305
1306                         shutdown_ai_command(dev);
1307
1308                         s->async->events |= COMEDI_CB_ERROR;
1309                         if (status & NISTC_AI_STATUS1_OVER)
1310                                 s->async->events |= COMEDI_CB_OVERFLOW;
1311                         return;
1312                 }
1313                 if (status & NISTC_AI_STATUS1_SC_TC) {
1314                         if (cmd->stop_src == TRIG_COUNT)
1315                                 shutdown_ai_command(dev);
1316                 }
1317         }
1318 #ifndef PCIDMA
1319         if (status & NISTC_AI_STATUS1_FIFO_HF) {
1320                 int i;
1321                 static const int timeout = 10;
1322                 /*
1323                  * PCMCIA cards (at least 6036) seem to stop producing
1324                  * interrupts if we fail to get the fifo less than half
1325                  * full, so loop to be sure.
1326                  */
1327                 for (i = 0; i < timeout; ++i) {
1328                         ni_handle_fifo_half_full(dev);
1329                         if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1330                              NISTC_AI_STATUS1_FIFO_HF) == 0)
1331                                 break;
1332                 }
1333         }
1334 #endif /*  !PCIDMA */
1335
1336         if (status & NISTC_AI_STATUS1_STOP)
1337                 ni_handle_eos(dev, s);
1338 }
1339
1340 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1341 {
1342         unsigned short ack = 0;
1343
1344         if (b_status & NISTC_AO_STATUS1_BC_TC)
1345                 ack |= NISTC_INTB_ACK_AO_BC_TC;
1346         if (b_status & NISTC_AO_STATUS1_OVERRUN)
1347                 ack |= NISTC_INTB_ACK_AO_ERR;
1348         if (b_status & NISTC_AO_STATUS1_START)
1349                 ack |= NISTC_INTB_ACK_AO_START;
1350         if (b_status & NISTC_AO_STATUS1_START1)
1351                 ack |= NISTC_INTB_ACK_AO_START1;
1352         if (b_status & NISTC_AO_STATUS1_UC_TC)
1353                 ack |= NISTC_INTB_ACK_AO_UC_TC;
1354         if (b_status & NISTC_AO_STATUS1_UI2_TC)
1355                 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1356         if (b_status & NISTC_AO_STATUS1_UPDATE)
1357                 ack |= NISTC_INTB_ACK_AO_UPDATE;
1358         if (ack)
1359                 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1360 }
1361
1362 static void handle_b_interrupt(struct comedi_device *dev,
1363                                struct comedi_subdevice *s,
1364                                unsigned short b_status)
1365 {
1366         if (b_status == 0xffff)
1367                 return;
1368         if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1369                 dev_err(dev->class_dev,
1370                         "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1371                         b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1372                 s->async->events |= COMEDI_CB_OVERFLOW;
1373         }
1374
1375         if (s->async->cmd.stop_src != TRIG_NONE &&
1376             b_status & NISTC_AO_STATUS1_BC_TC)
1377                 s->async->events |= COMEDI_CB_EOA;
1378
1379 #ifndef PCIDMA
1380         if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1381                 int ret;
1382
1383                 ret = ni_ao_fifo_half_empty(dev, s);
1384                 if (!ret) {
1385                         dev_err(dev->class_dev, "AO buffer underrun\n");
1386                         ni_set_bits(dev, NISTC_INTB_ENA_REG,
1387                                     NISTC_INTB_ENA_AO_FIFO |
1388                                     NISTC_INTB_ENA_AO_ERR, 0);
1389                         s->async->events |= COMEDI_CB_OVERFLOW;
1390                 }
1391         }
1392 #endif
1393 }
1394
1395 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1396                         void *data, unsigned int num_bytes,
1397                         unsigned int chan_index)
1398 {
1399         struct ni_private *devpriv = dev->private;
1400         struct comedi_async *async = s->async;
1401         struct comedi_cmd *cmd = &async->cmd;
1402         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1403         unsigned short *array = data;
1404         unsigned int *larray = data;
1405         unsigned int i;
1406 #ifdef PCIDMA
1407         __le16 *barray = data;
1408         __le32 *blarray = data;
1409 #endif
1410
1411         for (i = 0; i < nsamples; i++) {
1412 #ifdef PCIDMA
1413                 if (s->subdev_flags & SDF_LSAMPL)
1414                         larray[i] = le32_to_cpu(blarray[i]);
1415                 else
1416                         array[i] = le16_to_cpu(barray[i]);
1417 #endif
1418                 if (s->subdev_flags & SDF_LSAMPL)
1419                         larray[i] += devpriv->ai_offset[chan_index];
1420                 else
1421                         array[i] += devpriv->ai_offset[chan_index];
1422                 chan_index++;
1423                 chan_index %= cmd->chanlist_len;
1424         }
1425 }
1426
1427 #ifdef PCIDMA
1428
1429 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1430 {
1431         struct ni_private *devpriv = dev->private;
1432         struct comedi_subdevice *s = dev->read_subdev;
1433         int retval;
1434         unsigned long flags;
1435
1436         retval = ni_request_ai_mite_channel(dev);
1437         if (retval)
1438                 return retval;
1439
1440         /* write alloc the entire buffer */
1441         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1442
1443         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1444         if (!devpriv->ai_mite_chan) {
1445                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1446                 return -EIO;
1447         }
1448
1449         if (devpriv->is_611x || devpriv->is_6143)
1450                 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1451         else if (devpriv->is_628x)
1452                 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1453         else
1454                 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1455
1456         /*start the MITE */
1457         mite_dma_arm(devpriv->ai_mite_chan);
1458         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1459
1460         return 0;
1461 }
1462
1463 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1464 {
1465         struct ni_private *devpriv = dev->private;
1466         struct comedi_subdevice *s = dev->write_subdev;
1467         int retval;
1468         unsigned long flags;
1469
1470         retval = ni_request_ao_mite_channel(dev);
1471         if (retval)
1472                 return retval;
1473
1474         /* read alloc the entire buffer */
1475         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1476
1477         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1478         if (devpriv->ao_mite_chan) {
1479                 if (devpriv->is_611x || devpriv->is_6713) {
1480                         mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1481                 } else {
1482                         /*
1483                          * Doing 32 instead of 16 bit wide transfers from
1484                          * memory makes the mite do 32 bit pci transfers,
1485                          * doubling pci bandwidth.
1486                          */
1487                         mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1488                 }
1489                 mite_dma_arm(devpriv->ao_mite_chan);
1490         } else {
1491                 retval = -EIO;
1492         }
1493         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1494
1495         return retval;
1496 }
1497
1498 #endif /*  PCIDMA */
1499
1500 /*
1501  * used for both cancel ioctl and board initialization
1502  *
1503  * this is pretty harsh for a cancel, but it works...
1504  */
1505 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1506 {
1507         struct ni_private *devpriv = dev->private;
1508         unsigned int ai_personal;
1509         unsigned int ai_out_ctrl;
1510
1511         ni_release_ai_mite_channel(dev);
1512         /* ai configuration */
1513         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1514                       NISTC_RESET_REG);
1515
1516         ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1517
1518         ni_clear_ai_fifo(dev);
1519
1520         if (!devpriv->is_6143)
1521                 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1522
1523         ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1524         ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1525                            NISTC_AI_MODE1_RSVD
1526                             /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1527                       NISTC_AI_MODE1_REG);
1528         ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1529         /* generate FIFO interrupts on non-empty */
1530         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1531                       NISTC_AI_MODE3_REG);
1532
1533         ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1534                       NISTC_AI_PERSONAL_SOC_POLARITY |
1535                       NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1536         ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1537                       NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1538                       NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1539                       NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1540         if (devpriv->is_611x) {
1541                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1542         } else if (devpriv->is_6143) {
1543                 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1544         } else {
1545                 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1546                 if (devpriv->is_622x)
1547                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1548                 else
1549                         ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1550         }
1551         ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1552         ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1553
1554         /* the following registers should not be changed, because there
1555          * are no backup registers in devpriv.  If you want to change
1556          * any of these, add a backup register and other appropriate code:
1557          *      NISTC_AI_MODE1_REG
1558          *      NISTC_AI_MODE3_REG
1559          *      NISTC_AI_PERSONAL_REG
1560          *      NISTC_AI_OUT_CTRL_REG
1561          */
1562
1563         /* clear interrupts */
1564         ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1565
1566         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1567
1568         return 0;
1569 }
1570
1571 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1572 {
1573         unsigned long flags;
1574         int count;
1575
1576         /*  lock to avoid race with interrupt handler */
1577         spin_lock_irqsave(&dev->spinlock, flags);
1578 #ifndef PCIDMA
1579         ni_handle_fifo_dregs(dev);
1580 #else
1581         ni_sync_ai_dma(dev);
1582 #endif
1583         count = comedi_buf_n_bytes_ready(s);
1584         spin_unlock_irqrestore(&dev->spinlock, flags);
1585
1586         return count;
1587 }
1588
1589 static void ni_prime_channelgain_list(struct comedi_device *dev)
1590 {
1591         int i;
1592
1593         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1594         for (i = 0; i < NI_TIMEOUT; ++i) {
1595                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1596                       NISTC_AI_STATUS1_FIFO_E)) {
1597                         ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1598                         return;
1599                 }
1600                 udelay(1);
1601         }
1602         dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1603 }
1604
1605 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1606                                               unsigned int n_chan,
1607                                               unsigned int *list)
1608 {
1609         const struct ni_board_struct *board = dev->board_ptr;
1610         struct ni_private *devpriv = dev->private;
1611         unsigned int chan, range, aref;
1612         unsigned int i;
1613         unsigned int dither;
1614         unsigned int range_code;
1615
1616         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1617
1618         if ((list[0] & CR_ALT_SOURCE)) {
1619                 unsigned int bypass_bits;
1620
1621                 chan = CR_CHAN(list[0]);
1622                 range = CR_RANGE(list[0]);
1623                 range_code = ni_gainlkup[board->gainlkup][range];
1624                 dither = (list[0] & CR_ALT_FILTER) != 0;
1625                 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1626                               NI_M_CFG_BYPASS_AI_CHAN(chan) |
1627                               NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1628                               devpriv->ai_calib_source;
1629                 if (dither)
1630                         bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1631                 /*  don't use 2's complement encoding */
1632                 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1633                 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1634         } else {
1635                 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1636         }
1637         for (i = 0; i < n_chan; i++) {
1638                 unsigned int config_bits = 0;
1639
1640                 chan = CR_CHAN(list[i]);
1641                 aref = CR_AREF(list[i]);
1642                 range = CR_RANGE(list[i]);
1643                 dither = (list[i] & CR_ALT_FILTER) != 0;
1644
1645                 range_code = ni_gainlkup[board->gainlkup][range];
1646                 devpriv->ai_offset[i] = 0;
1647                 switch (aref) {
1648                 case AREF_DIFF:
1649                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1650                         break;
1651                 case AREF_COMMON:
1652                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1653                         break;
1654                 case AREF_GROUND:
1655                         config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1656                         break;
1657                 case AREF_OTHER:
1658                         break;
1659                 }
1660                 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1661                 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1662                 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1663                 if (i == n_chan - 1)
1664                         config_bits |= NI_M_AI_CFG_LAST_CHAN;
1665                 if (dither)
1666                         config_bits |= NI_M_AI_CFG_DITHER;
1667                 /*  don't use 2's complement encoding */
1668                 config_bits |= NI_M_AI_CFG_POLARITY;
1669                 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1670         }
1671         ni_prime_channelgain_list(dev);
1672 }
1673
1674 /*
1675  * Notes on the 6110 and 6111:
1676  * These boards a slightly different than the rest of the series, since
1677  * they have multiple A/D converters.
1678  * From the driver side, the configuration memory is a
1679  * little different.
1680  * Configuration Memory Low:
1681  *   bits 15-9: same
1682  *   bit 8: unipolar/bipolar (should be 0 for bipolar)
1683  *   bits 0-3: gain.  This is 4 bits instead of 3 for the other boards
1684  *       1001 gain=0.1 (+/- 50)
1685  *       1010 0.2
1686  *       1011 0.1
1687  *       0001 1
1688  *       0010 2
1689  *       0011 5
1690  *       0100 10
1691  *       0101 20
1692  *       0110 50
1693  * Configuration Memory High:
1694  *   bits 12-14: Channel Type
1695  *       001 for differential
1696  *       000 for calibration
1697  *   bit 11: coupling  (this is not currently handled)
1698  *       1 AC coupling
1699  *       0 DC coupling
1700  *   bits 0-2: channel
1701  *       valid channels are 0-3
1702  */
1703 static void ni_load_channelgain_list(struct comedi_device *dev,
1704                                      struct comedi_subdevice *s,
1705                                      unsigned int n_chan, unsigned int *list)
1706 {
1707         const struct ni_board_struct *board = dev->board_ptr;
1708         struct ni_private *devpriv = dev->private;
1709         unsigned int offset = (s->maxdata + 1) >> 1;
1710         unsigned int chan, range, aref;
1711         unsigned int i;
1712         unsigned int hi, lo;
1713         unsigned int dither;
1714
1715         if (devpriv->is_m_series) {
1716                 ni_m_series_load_channelgain_list(dev, n_chan, list);
1717                 return;
1718         }
1719         if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1720                 if (devpriv->changain_state &&
1721                     devpriv->changain_spec == list[0]) {
1722                         /*  ready to go. */
1723                         return;
1724                 }
1725                 devpriv->changain_state = 1;
1726                 devpriv->changain_spec = list[0];
1727         } else {
1728                 devpriv->changain_state = 0;
1729         }
1730
1731         ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1732
1733         /*  Set up Calibration mode if required */
1734         if (devpriv->is_6143) {
1735                 if ((list[0] & CR_ALT_SOURCE) &&
1736                     !devpriv->ai_calib_source_enabled) {
1737                         /*  Strobe Relay enable bit */
1738                         ni_writew(dev, devpriv->ai_calib_source |
1739                                        NI6143_CALIB_CHAN_RELAY_ON,
1740                                   NI6143_CALIB_CHAN_REG);
1741                         ni_writew(dev, devpriv->ai_calib_source,
1742                                   NI6143_CALIB_CHAN_REG);
1743                         devpriv->ai_calib_source_enabled = 1;
1744                         /* Allow relays to change */
1745                         msleep_interruptible(100);
1746                 } else if (!(list[0] & CR_ALT_SOURCE) &&
1747                            devpriv->ai_calib_source_enabled) {
1748                         /*  Strobe Relay disable bit */
1749                         ni_writew(dev, devpriv->ai_calib_source |
1750                                        NI6143_CALIB_CHAN_RELAY_OFF,
1751                                   NI6143_CALIB_CHAN_REG);
1752                         ni_writew(dev, devpriv->ai_calib_source,
1753                                   NI6143_CALIB_CHAN_REG);
1754                         devpriv->ai_calib_source_enabled = 0;
1755                         /* Allow relays to change */
1756                         msleep_interruptible(100);
1757                 }
1758         }
1759
1760         for (i = 0; i < n_chan; i++) {
1761                 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1762                         chan = devpriv->ai_calib_source;
1763                 else
1764                         chan = CR_CHAN(list[i]);
1765                 aref = CR_AREF(list[i]);
1766                 range = CR_RANGE(list[i]);
1767                 dither = (list[i] & CR_ALT_FILTER) != 0;
1768
1769                 /* fix the external/internal range differences */
1770                 range = ni_gainlkup[board->gainlkup][range];
1771                 if (devpriv->is_611x)
1772                         devpriv->ai_offset[i] = offset;
1773                 else
1774                         devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1775
1776                 hi = 0;
1777                 if ((list[i] & CR_ALT_SOURCE)) {
1778                         if (devpriv->is_611x)
1779                                 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1780                                           NI611X_CALIB_CHAN_SEL_REG);
1781                 } else {
1782                         if (devpriv->is_611x)
1783                                 aref = AREF_DIFF;
1784                         else if (devpriv->is_6143)
1785                                 aref = AREF_OTHER;
1786                         switch (aref) {
1787                         case AREF_DIFF:
1788                                 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1789                                 break;
1790                         case AREF_COMMON:
1791                                 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1792                                 break;
1793                         case AREF_GROUND:
1794                                 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1795                                 break;
1796                         case AREF_OTHER:
1797                                 break;
1798                         }
1799                 }
1800                 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1801
1802                 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1803
1804                 if (!devpriv->is_6143) {
1805                         lo = NI_E_AI_CFG_LO_GAIN(range);
1806
1807                         if (i == n_chan - 1)
1808                                 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1809                         if (dither)
1810                                 lo |= NI_E_AI_CFG_LO_DITHER;
1811
1812                         ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1813                 }
1814         }
1815
1816         /* prime the channel/gain list */
1817         if (!devpriv->is_611x && !devpriv->is_6143)
1818                 ni_prime_channelgain_list(dev);
1819 }
1820
1821 static int ni_ai_insn_read(struct comedi_device *dev,
1822                            struct comedi_subdevice *s,
1823                            struct comedi_insn *insn,
1824                            unsigned int *data)
1825 {
1826         struct ni_private *devpriv = dev->private;
1827         unsigned int mask = s->maxdata;
1828         int i, n;
1829         unsigned int signbits;
1830         unsigned int d;
1831
1832         ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1833
1834         ni_clear_ai_fifo(dev);
1835
1836         signbits = devpriv->ai_offset[0];
1837         if (devpriv->is_611x) {
1838                 for (n = 0; n < num_adc_stages_611x; n++) {
1839                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1840                                       NISTC_AI_CMD1_REG);
1841                         udelay(1);
1842                 }
1843                 for (n = 0; n < insn->n; n++) {
1844                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1845                                       NISTC_AI_CMD1_REG);
1846                         /* The 611x has screwy 32-bit FIFOs. */
1847                         d = 0;
1848                         for (i = 0; i < NI_TIMEOUT; i++) {
1849                                 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1850                                         d = ni_readl(dev,
1851                                                      NI611X_AI_FIFO_DATA_REG);
1852                                         d >>= 16;
1853                                         d &= 0xffff;
1854                                         break;
1855                                 }
1856                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1857                                       NISTC_AI_STATUS1_FIFO_E)) {
1858                                         d = ni_readl(dev,
1859                                                      NI611X_AI_FIFO_DATA_REG);
1860                                         d &= 0xffff;
1861                                         break;
1862                                 }
1863                         }
1864                         if (i == NI_TIMEOUT) {
1865                                 dev_err(dev->class_dev, "timeout\n");
1866                                 return -ETIME;
1867                         }
1868                         d += signbits;
1869                         data[n] = d & 0xffff;
1870                 }
1871         } else if (devpriv->is_6143) {
1872                 for (n = 0; n < insn->n; n++) {
1873                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1874                                       NISTC_AI_CMD1_REG);
1875
1876                         /*
1877                          * The 6143 has 32-bit FIFOs. You need to strobe a
1878                          * bit to move a single 16bit stranded sample into
1879                          * the FIFO.
1880                          */
1881                         d = 0;
1882                         for (i = 0; i < NI_TIMEOUT; i++) {
1883                                 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
1884                                     0x01) {
1885                                         /* Get stranded sample into FIFO */
1886                                         ni_writel(dev, 0x01,
1887                                                   NI6143_AI_FIFO_CTRL_REG);
1888                                         d = ni_readl(dev,
1889                                                      NI6143_AI_FIFO_DATA_REG);
1890                                         break;
1891                                 }
1892                         }
1893                         if (i == NI_TIMEOUT) {
1894                                 dev_err(dev->class_dev, "timeout\n");
1895                                 return -ETIME;
1896                         }
1897                         data[n] = (((d >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1898                 }
1899         } else {
1900                 for (n = 0; n < insn->n; n++) {
1901                         ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1902                                       NISTC_AI_CMD1_REG);
1903                         for (i = 0; i < NI_TIMEOUT; i++) {
1904                                 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1905                                       NISTC_AI_STATUS1_FIFO_E))
1906                                         break;
1907                         }
1908                         if (i == NI_TIMEOUT) {
1909                                 dev_err(dev->class_dev, "timeout\n");
1910                                 return -ETIME;
1911                         }
1912                         if (devpriv->is_m_series) {
1913                                 d = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
1914                                 d &= mask;
1915                                 data[n] = d;
1916                         } else {
1917                                 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1918                                 d += signbits;
1919                                 data[n] = d & 0xffff;
1920                         }
1921                 }
1922         }
1923         return insn->n;
1924 }
1925
1926 static int ni_ns_to_timer(const struct comedi_device *dev,
1927                           unsigned int nanosec, unsigned int flags)
1928 {
1929         struct ni_private *devpriv = dev->private;
1930         int divider;
1931
1932         switch (flags & CMDF_ROUND_MASK) {
1933         case CMDF_ROUND_NEAREST:
1934         default:
1935                 divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns);
1936                 break;
1937         case CMDF_ROUND_DOWN:
1938                 divider = (nanosec) / devpriv->clock_ns;
1939                 break;
1940         case CMDF_ROUND_UP:
1941                 divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns);
1942                 break;
1943         }
1944         return divider - 1;
1945 }
1946
1947 static unsigned int ni_timer_to_ns(const struct comedi_device *dev, int timer)
1948 {
1949         struct ni_private *devpriv = dev->private;
1950
1951         return devpriv->clock_ns * (timer + 1);
1952 }
1953
1954 static void ni_cmd_set_mite_transfer(struct mite_ring *ring,
1955                                      struct comedi_subdevice *sdev,
1956                                      const struct comedi_cmd *cmd,
1957                                      unsigned int max_count)
1958 {
1959 #ifdef PCIDMA
1960         unsigned int nbytes = max_count;
1961
1962         if (cmd->stop_arg > 0 && cmd->stop_arg < max_count)
1963                 nbytes = cmd->stop_arg;
1964         nbytes *= comedi_bytes_per_scan(sdev);
1965
1966         if (nbytes > sdev->async->prealloc_bufsz) {
1967                 if (cmd->stop_arg > 0)
1968                         dev_err(sdev->device->class_dev,
1969                                 "%s: tried exact data transfer limits greater than buffer size\n",
1970                                 __func__);
1971
1972                 /*
1973                  * we can only transfer up to the size of the buffer.  In this
1974                  * case, the user is expected to continue to write into the
1975                  * comedi buffer (already implemented as a ring buffer).
1976                  */
1977                 nbytes = sdev->async->prealloc_bufsz;
1978         }
1979
1980         mite_init_ring_descriptors(ring, sdev, nbytes);
1981 #else
1982         dev_err(sdev->device->class_dev,
1983                 "%s: exact data transfer limits not implemented yet without DMA\n",
1984                 __func__);
1985 #endif
1986 }
1987
1988 static unsigned int ni_min_ai_scan_period_ns(struct comedi_device *dev,
1989                                              unsigned int num_channels)
1990 {
1991         const struct ni_board_struct *board = dev->board_ptr;
1992         struct ni_private *devpriv = dev->private;
1993
1994         /* simultaneously-sampled inputs */
1995         if (devpriv->is_611x || devpriv->is_6143)
1996                 return board->ai_speed;
1997
1998         /* multiplexed inputs */
1999         return board->ai_speed * num_channels;
2000 }
2001
2002 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2003                          struct comedi_cmd *cmd)
2004 {
2005         const struct ni_board_struct *board = dev->board_ptr;
2006         struct ni_private *devpriv = dev->private;
2007         int err = 0;
2008         unsigned int sources;
2009
2010         /* Step 1 : check if triggers are trivially valid */
2011
2012         err |= comedi_check_trigger_src(&cmd->start_src,
2013                                         TRIG_NOW | TRIG_INT | TRIG_EXT);
2014         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2015                                         TRIG_TIMER | TRIG_EXT);
2016
2017         sources = TRIG_TIMER | TRIG_EXT;
2018         if (devpriv->is_611x || devpriv->is_6143)
2019                 sources |= TRIG_NOW;
2020         err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2021
2022         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2023         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2024
2025         if (err)
2026                 return 1;
2027
2028         /* Step 2a : make sure trigger sources are unique */
2029
2030         err |= comedi_check_trigger_is_unique(cmd->start_src);
2031         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2032         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2033         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2034
2035         /* Step 2b : and mutually compatible */
2036
2037         if (err)
2038                 return 2;
2039
2040         /* Step 3: check if arguments are trivially valid */
2041
2042         switch (cmd->start_src) {
2043         case TRIG_NOW:
2044         case TRIG_INT:
2045                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2046                 break;
2047         case TRIG_EXT:
2048                 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->start_arg),
2049                                                   NI_AI_StartTrigger,
2050                                                   &devpriv->routing_tables, 1);
2051                 break;
2052         }
2053
2054         if (cmd->scan_begin_src == TRIG_TIMER) {
2055                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2056                         ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2057                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2058                                                     devpriv->clock_ns *
2059                                                     0xffffff);
2060         } else if (cmd->scan_begin_src == TRIG_EXT) {
2061                 /* external trigger */
2062                 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->scan_begin_arg),
2063                                                   NI_AI_SampleClock,
2064                                                   &devpriv->routing_tables, 1);
2065         } else {                /* TRIG_OTHER */
2066                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2067         }
2068
2069         if (cmd->convert_src == TRIG_TIMER) {
2070                 if (devpriv->is_611x || devpriv->is_6143) {
2071                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2072                                                            0);
2073                 } else {
2074                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2075                                                             board->ai_speed);
2076                         err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2077                                                             devpriv->clock_ns *
2078                                                             0xffff);
2079                 }
2080         } else if (cmd->convert_src == TRIG_EXT) {
2081                 /* external trigger */
2082                 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->convert_arg),
2083                                                   NI_AI_ConvertClock,
2084                                                   &devpriv->routing_tables, 1);
2085         } else if (cmd->convert_src == TRIG_NOW) {
2086                 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2087         }
2088
2089         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2090                                            cmd->chanlist_len);
2091
2092         if (cmd->stop_src == TRIG_COUNT) {
2093                 unsigned int max_count = 0x01000000;
2094
2095                 if (devpriv->is_611x)
2096                         max_count -= num_adc_stages_611x;
2097                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2098                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2099         } else {
2100                 /* TRIG_NONE */
2101                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2102         }
2103
2104         if (err)
2105                 return 3;
2106
2107         /* step 4: fix up any arguments */
2108
2109         if (cmd->scan_begin_src == TRIG_TIMER) {
2110                 unsigned int tmp = cmd->scan_begin_arg;
2111
2112                 cmd->scan_begin_arg =
2113                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2114                                                        cmd->scan_begin_arg,
2115                                                        cmd->flags));
2116                 if (tmp != cmd->scan_begin_arg)
2117                         err++;
2118         }
2119         if (cmd->convert_src == TRIG_TIMER) {
2120                 if (!devpriv->is_611x && !devpriv->is_6143) {
2121                         unsigned int tmp = cmd->convert_arg;
2122
2123                         cmd->convert_arg =
2124                             ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2125                                                                cmd->convert_arg,
2126                                                                cmd->flags));
2127                         if (tmp != cmd->convert_arg)
2128                                 err++;
2129                         if (cmd->scan_begin_src == TRIG_TIMER &&
2130                             cmd->scan_begin_arg <
2131                             cmd->convert_arg * cmd->scan_end_arg) {
2132                                 cmd->scan_begin_arg =
2133                                     cmd->convert_arg * cmd->scan_end_arg;
2134                                 err++;
2135                         }
2136                 }
2137         }
2138
2139         if (err)
2140                 return 4;
2141
2142         return 0;
2143 }
2144
2145 static int ni_ai_inttrig(struct comedi_device *dev,
2146                          struct comedi_subdevice *s,
2147                          unsigned int trig_num)
2148 {
2149         struct ni_private *devpriv = dev->private;
2150         struct comedi_cmd *cmd = &s->async->cmd;
2151
2152         if (trig_num != cmd->start_arg)
2153                 return -EINVAL;
2154
2155         ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2156                       NISTC_AI_CMD2_REG);
2157         s->async->inttrig = NULL;
2158
2159         return 1;
2160 }
2161
2162 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2163 {
2164         struct ni_private *devpriv = dev->private;
2165         const struct comedi_cmd *cmd = &s->async->cmd;
2166         int timer;
2167         int mode1 = 0;          /* mode1 is needed for both stop and convert */
2168         int mode2 = 0;
2169         int start_stop_select = 0;
2170         unsigned int stop_count;
2171         int interrupt_a_enable = 0;
2172         unsigned int ai_trig;
2173
2174         if (dev->irq == 0) {
2175                 dev_err(dev->class_dev, "cannot run command without an irq\n");
2176                 return -EIO;
2177         }
2178         ni_clear_ai_fifo(dev);
2179
2180         ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2181
2182         /* start configuration */
2183         ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2184
2185         /*
2186          * Disable analog triggering for now, since it interferes
2187          * with the use of pfi0.
2188          */
2189         devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2190         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2191
2192         ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2193         switch (cmd->start_src) {
2194         case TRIG_INT:
2195         case TRIG_NOW:
2196                 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2197                            NISTC_AI_TRIG_START1_SEL(0);
2198                 break;
2199         case TRIG_EXT:
2200                 ai_trig |= NISTC_AI_TRIG_START1_SEL(
2201                                 ni_get_reg_value_roffs(
2202                                         CR_CHAN(cmd->start_arg),
2203                                         NI_AI_StartTrigger,
2204                                         &devpriv->routing_tables, 1));
2205
2206                 if (cmd->start_arg & CR_INVERT)
2207                         ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2208                 if (cmd->start_arg & CR_EDGE)
2209                         ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2210                 break;
2211         }
2212         ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2213
2214         mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2215         mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2216         mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2217         ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2218
2219         if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2220                 /* logic low */
2221                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2222                                      NISTC_AI_STOP_SEL(31) |
2223                                      NISTC_AI_STOP_SYNC;
2224         } else {
2225                 /*  ai configuration memory */
2226                 start_stop_select |= NISTC_AI_STOP_SEL(19);
2227         }
2228         ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2229
2230         devpriv->ai_cmd2 = 0;
2231         switch (cmd->stop_src) {
2232         case TRIG_COUNT:
2233                 stop_count = cmd->stop_arg - 1;
2234
2235                 if (devpriv->is_611x) {
2236                         /*  have to take 3 stage adc pipeline into account */
2237                         stop_count += num_adc_stages_611x;
2238                 }
2239                 /* stage number of scans */
2240                 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2241
2242                 mode1 |= NISTC_AI_MODE1_START_STOP |
2243                          NISTC_AI_MODE1_RSVD |
2244                          NISTC_AI_MODE1_TRIGGER_ONCE;
2245                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2246                 /* load SC (Scan Count) */
2247                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2248
2249                 if (stop_count == 0) {
2250                         devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2251                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2252                         /*
2253                          * This is required to get the last sample for
2254                          * chanlist_len > 1, not sure why.
2255                          */
2256                         if (cmd->chanlist_len > 1)
2257                                 start_stop_select |= NISTC_AI_STOP_POLARITY |
2258                                                      NISTC_AI_STOP_EDGE;
2259                 }
2260                 break;
2261         case TRIG_NONE:
2262                 /* stage number of scans */
2263                 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2264
2265                 mode1 |= NISTC_AI_MODE1_START_STOP |
2266                          NISTC_AI_MODE1_RSVD |
2267                          NISTC_AI_MODE1_CONTINUOUS;
2268                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2269
2270                 /* load SC (Scan Count) */
2271                 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2272                 break;
2273         }
2274
2275         switch (cmd->scan_begin_src) {
2276         case TRIG_TIMER:
2277                 /*
2278                  * stop bits for non 611x boards
2279                  * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2280                  * NISTC_AI_MODE2_PRE_TRIGGER=0
2281                  * NISTC_AI_START_STOP_REG:
2282                  * NISTC_AI_START_POLARITY=0    (?) rising edge
2283                  * NISTC_AI_START_EDGE=1        edge triggered
2284                  * NISTC_AI_START_SYNC=1        (?)
2285                  * NISTC_AI_START_SEL=0         SI_TC
2286                  * NISTC_AI_STOP_POLARITY=0     rising edge
2287                  * NISTC_AI_STOP_EDGE=0         level
2288                  * NISTC_AI_STOP_SYNC=1
2289                  * NISTC_AI_STOP_SEL=19         external pin (configuration mem)
2290                  */
2291                 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2292                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2293
2294                 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC;      /* A */
2295                 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2296                 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2297                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2298
2299                 /* load SI */
2300                 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2301                                        CMDF_ROUND_NEAREST);
2302                 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2303                 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2304                 break;
2305         case TRIG_EXT:
2306                 if (cmd->scan_begin_arg & CR_EDGE)
2307                         start_stop_select |= NISTC_AI_START_EDGE;
2308                 if (cmd->scan_begin_arg & CR_INVERT)    /* falling edge */
2309                         start_stop_select |= NISTC_AI_START_POLARITY;
2310                 if (cmd->scan_begin_src != cmd->convert_src ||
2311                     (cmd->scan_begin_arg & ~CR_EDGE) !=
2312                     (cmd->convert_arg & ~CR_EDGE))
2313                         start_stop_select |= NISTC_AI_START_SYNC;
2314
2315                 start_stop_select |= NISTC_AI_START_SEL(
2316                                         ni_get_reg_value_roffs(
2317                                                 CR_CHAN(cmd->scan_begin_arg),
2318                                                 NI_AI_SampleClock,
2319                                                 &devpriv->routing_tables, 1));
2320                 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2321                 break;
2322         }
2323
2324         switch (cmd->convert_src) {
2325         case TRIG_TIMER:
2326         case TRIG_NOW:
2327                 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2328                         timer = 1;
2329                 else
2330                         timer = ni_ns_to_timer(dev, cmd->convert_arg,
2331                                                CMDF_ROUND_NEAREST);
2332                 /* 0,0 does not work */
2333                 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2334                 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2335
2336                 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;     /* A */
2337                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2338                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2339
2340                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2341
2342                 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC;      /* B */
2343                 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE;        /* alternate */
2344                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2345                 break;
2346         case TRIG_EXT:
2347                 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(
2348                                 ni_get_reg_value_roffs(
2349                                                 CR_CHAN(cmd->convert_arg),
2350                                                 NI_AI_ConvertClock,
2351                                                 &devpriv->routing_tables, 1));
2352                 if ((cmd->convert_arg & CR_INVERT) == 0)
2353                         mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2354                 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2355
2356                 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2357                          NISTC_AI_MODE2_START_STOP_GATE_ENA;
2358                 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2359
2360                 break;
2361         }
2362
2363         if (dev->irq) {
2364                 /* interrupt on FIFO, errors, SC_TC */
2365                 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2366                                       NISTC_INTA_ENA_AI_SC_TC;
2367
2368 #ifndef PCIDMA
2369                 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2370 #endif
2371
2372                 if ((cmd->flags & CMDF_WAKE_EOS) ||
2373                     (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2374                         /* wake on end-of-scan */
2375                         devpriv->aimode = AIMODE_SCAN;
2376                 } else {
2377                         devpriv->aimode = AIMODE_HALF_FULL;
2378                 }
2379
2380                 switch (devpriv->aimode) {
2381                 case AIMODE_HALF_FULL:
2382                         /* FIFO interrupts and DMA requests on half-full */
2383 #ifdef PCIDMA
2384                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2385                                       NISTC_AI_MODE3_REG);
2386 #else
2387                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2388                                       NISTC_AI_MODE3_REG);
2389 #endif
2390                         break;
2391                 case AIMODE_SAMPLE:
2392                         /* generate FIFO interrupts on non-empty */
2393                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2394                                       NISTC_AI_MODE3_REG);
2395                         break;
2396                 case AIMODE_SCAN:
2397 #ifdef PCIDMA
2398                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2399                                       NISTC_AI_MODE3_REG);
2400 #else
2401                         ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2402                                       NISTC_AI_MODE3_REG);
2403 #endif
2404                         interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2405                         break;
2406                 default:
2407                         break;
2408                 }
2409
2410                 /* clear interrupts */
2411                 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2412
2413                 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2414         } else {
2415                 /* interrupt on nothing */
2416                 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2417
2418                 /* XXX start polling if necessary */
2419         }
2420
2421         /* end configuration */
2422         ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2423
2424         switch (cmd->scan_begin_src) {
2425         case TRIG_TIMER:
2426                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2427                                    NISTC_AI_CMD1_SI_ARM |
2428                                    NISTC_AI_CMD1_DIV_ARM |
2429                                    NISTC_AI_CMD1_SC_ARM,
2430                               NISTC_AI_CMD1_REG);
2431                 break;
2432         case TRIG_EXT:
2433                 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2434                                    NISTC_AI_CMD1_SI_ARM |       /* XXX ? */
2435                                    NISTC_AI_CMD1_DIV_ARM |
2436                                    NISTC_AI_CMD1_SC_ARM,
2437                               NISTC_AI_CMD1_REG);
2438                 break;
2439         }
2440
2441 #ifdef PCIDMA
2442         {
2443                 int retval = ni_ai_setup_MITE_dma(dev);
2444
2445                 if (retval)
2446                         return retval;
2447         }
2448 #endif
2449
2450         if (cmd->start_src == TRIG_NOW) {
2451                 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2452                                    devpriv->ai_cmd2,
2453                               NISTC_AI_CMD2_REG);
2454                 s->async->inttrig = NULL;
2455         } else if (cmd->start_src == TRIG_EXT) {
2456                 s->async->inttrig = NULL;
2457         } else {        /* TRIG_INT */
2458                 s->async->inttrig = ni_ai_inttrig;
2459         }
2460
2461         return 0;
2462 }
2463
2464 static int ni_ai_insn_config(struct comedi_device *dev,
2465                              struct comedi_subdevice *s,
2466                              struct comedi_insn *insn, unsigned int *data)
2467 {
2468         const struct ni_board_struct *board = dev->board_ptr;
2469         struct ni_private *devpriv = dev->private;
2470
2471         if (insn->n < 1)
2472                 return -EINVAL;
2473
2474         switch (data[0]) {
2475         case INSN_CONFIG_ALT_SOURCE:
2476                 if (devpriv->is_m_series) {
2477                         if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2478                                 return -EINVAL;
2479                         devpriv->ai_calib_source = data[1];
2480                 } else if (devpriv->is_6143) {
2481                         unsigned int calib_source;
2482
2483                         calib_source = data[1] & 0xf;
2484
2485                         devpriv->ai_calib_source = calib_source;
2486                         ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2487                 } else {
2488                         unsigned int calib_source;
2489                         unsigned int calib_source_adjust;
2490
2491                         calib_source = data[1] & 0xf;
2492                         calib_source_adjust = (data[1] >> 4) & 0xff;
2493
2494                         if (calib_source >= 8)
2495                                 return -EINVAL;
2496                         devpriv->ai_calib_source = calib_source;
2497                         if (devpriv->is_611x) {
2498                                 ni_writeb(dev, calib_source_adjust,
2499                                           NI611X_CAL_GAIN_SEL_REG);
2500                         }
2501                 }
2502                 return 2;
2503         case INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS:
2504                 /* we don't care about actual channels */
2505                 /* data[3] : chanlist_len */
2506                 data[1] = ni_min_ai_scan_period_ns(dev, data[3]);
2507                 if (devpriv->is_611x || devpriv->is_6143)
2508                         data[2] = 0; /* simultaneous output */
2509                 else
2510                         data[2] = board->ai_speed;
2511                 return 0;
2512         default:
2513                 break;
2514         }
2515
2516         return -EINVAL;
2517 }
2518
2519 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2520                         void *data, unsigned int num_bytes,
2521                         unsigned int chan_index)
2522 {
2523         struct comedi_cmd *cmd = &s->async->cmd;
2524         unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2525         unsigned short *array = data;
2526         unsigned int i;
2527 #ifdef PCIDMA
2528         __le16 buf, *barray = data;
2529 #endif
2530
2531         for (i = 0; i < nsamples; i++) {
2532                 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2533                 unsigned short val = array[i];
2534
2535                 /*
2536                  * Munge data from unsigned to two's complement for
2537                  * bipolar ranges.
2538                  */
2539                 if (comedi_range_is_bipolar(s, range))
2540                         val = comedi_offset_munge(s, val);
2541 #ifdef PCIDMA
2542                 buf = cpu_to_le16(val);
2543                 barray[i] = buf;
2544 #else
2545                 array[i] = val;
2546 #endif
2547                 chan_index++;
2548                 chan_index %= cmd->chanlist_len;
2549         }
2550 }
2551
2552 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2553                                           struct comedi_subdevice *s,
2554                                           unsigned int chanspec[],
2555                                           unsigned int n_chans, int timed)
2556 {
2557         struct ni_private *devpriv = dev->private;
2558         unsigned int range;
2559         unsigned int chan;
2560         unsigned int conf;
2561         int i;
2562         int invert = 0;
2563
2564         if (timed) {
2565                 for (i = 0; i < s->n_chan; ++i) {
2566                         devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2567                         ni_writeb(dev, devpriv->ao_conf[i],
2568                                   NI_M_AO_CFG_BANK_REG(i));
2569                         ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2570                 }
2571         }
2572         for (i = 0; i < n_chans; i++) {
2573                 const struct comedi_krange *krange;
2574
2575                 chan = CR_CHAN(chanspec[i]);
2576                 range = CR_RANGE(chanspec[i]);
2577                 krange = s->range_table->range + range;
2578                 invert = 0;
2579                 conf = 0;
2580                 switch (krange->max - krange->min) {
2581                 case 20000000:
2582                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2583                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2584                         break;
2585                 case 10000000:
2586                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2587                         ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2588                         break;
2589                 case 4000000:
2590                         conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2591                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2592                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2593                         break;
2594                 case 2000000:
2595                         conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2596                         ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2597                                   NI_M_AO_REF_ATTENUATION_REG(chan));
2598                         break;
2599                 default:
2600                         dev_err(dev->class_dev,
2601                                 "bug! unhandled ao reference voltage\n");
2602                         break;
2603                 }
2604                 switch (krange->max + krange->min) {
2605                 case 0:
2606                         conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2607                         break;
2608                 case 10000000:
2609                         conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2610                         break;
2611                 default:
2612                         dev_err(dev->class_dev,
2613                                 "bug! unhandled ao offset voltage\n");
2614                         break;
2615                 }
2616                 if (timed)
2617                         conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2618                 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2619                 devpriv->ao_conf[chan] = conf;
2620                 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2621         }
2622         return invert;
2623 }
2624
2625 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2626                                      struct comedi_subdevice *s,
2627                                      unsigned int chanspec[],
2628                                      unsigned int n_chans)
2629 {
2630         struct ni_private *devpriv = dev->private;
2631         unsigned int range;
2632         unsigned int chan;
2633         unsigned int conf;
2634         int i;
2635         int invert = 0;
2636
2637         for (i = 0; i < n_chans; i++) {
2638                 chan = CR_CHAN(chanspec[i]);
2639                 range = CR_RANGE(chanspec[i]);
2640                 conf = NI_E_AO_DACSEL(chan);
2641
2642                 if (comedi_range_is_bipolar(s, range)) {
2643                         conf |= NI_E_AO_CFG_BIP;
2644                         invert = (s->maxdata + 1) >> 1;
2645                 } else {
2646                         invert = 0;
2647                 }
2648                 if (comedi_range_is_external(s, range))
2649                         conf |= NI_E_AO_EXT_REF;
2650
2651                 /* not all boards can deglitch, but this shouldn't hurt */
2652                 if (chanspec[i] & CR_DEGLITCH)
2653                         conf |= NI_E_AO_DEGLITCH;
2654
2655                 /* analog reference */
2656                 /* AREF_OTHER connects AO ground to AI ground, i think */
2657                 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2658                         conf |= NI_E_AO_GROUND_REF;
2659
2660                 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2661                 devpriv->ao_conf[chan] = conf;
2662         }
2663         return invert;
2664 }
2665
2666 static int ni_ao_config_chanlist(struct comedi_device *dev,
2667                                  struct comedi_subdevice *s,
2668                                  unsigned int chanspec[], unsigned int n_chans,
2669                                  int timed)
2670 {
2671         struct ni_private *devpriv = dev->private;
2672
2673         if (devpriv->is_m_series)
2674                 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2675                                                       timed);
2676         else
2677                 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2678 }
2679
2680 static int ni_ao_insn_write(struct comedi_device *dev,
2681                             struct comedi_subdevice *s,
2682                             struct comedi_insn *insn,
2683                             unsigned int *data)
2684 {
2685         struct ni_private *devpriv = dev->private;
2686         unsigned int chan = CR_CHAN(insn->chanspec);
2687         unsigned int range = CR_RANGE(insn->chanspec);
2688         int reg;
2689         int i;
2690
2691         if (devpriv->is_6xxx) {
2692                 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2693
2694                 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2695         } else if (devpriv->is_m_series) {
2696                 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2697         } else {
2698                 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2699         }
2700
2701         ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2702
2703         for (i = 0; i < insn->n; i++) {
2704                 unsigned int val = data[i];
2705
2706                 s->readback[chan] = val;
2707
2708                 if (devpriv->is_6xxx) {
2709                         /*
2710                          * 6xxx boards have bipolar outputs, munge the
2711                          * unsigned comedi values to 2's complement
2712                          */
2713                         val = comedi_offset_munge(s, val);
2714
2715                         ni_ao_win_outw(dev, val, reg);
2716                 } else if (devpriv->is_m_series) {
2717                         /*
2718                          * M-series boards use offset binary values for
2719                          * bipolar and uinpolar outputs
2720                          */
2721                         ni_writew(dev, val, reg);
2722                 } else {
2723                         /*
2724                          * Non-M series boards need two's complement values
2725                          * for bipolar ranges.
2726                          */
2727                         if (comedi_range_is_bipolar(s, range))
2728                                 val = comedi_offset_munge(s, val);
2729
2730                         ni_writew(dev, val, reg);
2731                 }
2732         }
2733
2734         return insn->n;
2735 }
2736
2737 /*
2738  * Arms the AO device in preparation for a trigger event.
2739  * This function also allocates and prepares a DMA channel (or FIFO if DMA is
2740  * not used).  As a part of this preparation, this function preloads the DAC
2741  * registers with the first values of the output stream.  This ensures that the
2742  * first clock cycle after the trigger can be used for output.
2743  *
2744  * Note that this function _must_ happen after a user has written data to the
2745  * output buffers via either mmap or write(fileno,...).
2746  */
2747 static int ni_ao_arm(struct comedi_device *dev,
2748                      struct comedi_subdevice *s)
2749 {
2750         struct ni_private *devpriv = dev->private;
2751         int ret;
2752         int interrupt_b_bits;
2753         int i;
2754         static const int timeout = 1000;
2755
2756         /*
2757          * Prevent ao from doing things like trying to allocate the ao dma
2758          * channel multiple times.
2759          */
2760         if (!devpriv->ao_needs_arming) {
2761                 dev_dbg(dev->class_dev, "%s: device does not need arming!\n",
2762                         __func__);
2763                 return -EINVAL;
2764         }
2765
2766         devpriv->ao_needs_arming = 0;
2767
2768         ni_set_bits(dev, NISTC_INTB_ENA_REG,
2769                     NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2770         interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2771 #ifdef PCIDMA
2772         ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2773         if (devpriv->is_6xxx)
2774                 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2775         ret = ni_ao_setup_MITE_dma(dev);
2776         if (ret)
2777                 return ret;
2778         ret = ni_ao_wait_for_dma_load(dev);
2779         if (ret < 0)
2780                 return ret;
2781 #else
2782         ret = ni_ao_prep_fifo(dev, s);
2783         if (ret == 0)
2784                 return -EPIPE;
2785
2786         interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2787 #endif
2788
2789         ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2790                       NISTC_AO_MODE3_REG);
2791         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2792         /* wait for DACs to be loaded */
2793         for (i = 0; i < timeout; i++) {
2794                 udelay(1);
2795                 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2796                      NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2797                         break;
2798         }
2799         if (i == timeout) {
2800                 dev_err(dev->class_dev,
2801                         "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2802                 return -EIO;
2803         }
2804         /*
2805          * stc manual says we are need to clear error interrupt after
2806          * AO_TMRDACWRs_In_Progress_St clears
2807          */
2808         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2809
2810         ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2811
2812         ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2813                            NISTC_AO_CMD1_UC_ARM |
2814                            NISTC_AO_CMD1_BC_ARM |
2815                            devpriv->ao_cmd1,
2816                       NISTC_AO_CMD1_REG);
2817
2818         return 0;
2819 }
2820
2821 static int ni_ao_insn_config(struct comedi_device *dev,
2822                              struct comedi_subdevice *s,
2823                              struct comedi_insn *insn, unsigned int *data)
2824 {
2825         const struct ni_board_struct *board = dev->board_ptr;
2826         struct ni_private *devpriv = dev->private;
2827         unsigned int nbytes;
2828
2829         switch (data[0]) {
2830         case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2831                 switch (data[1]) {
2832                 case COMEDI_OUTPUT:
2833                         nbytes = comedi_samples_to_bytes(s,
2834                                                          board->ao_fifo_depth);
2835                         data[2] = 1 + nbytes;
2836                         if (devpriv->mite)
2837                                 data[2] += devpriv->mite->fifo_size;
2838                         break;
2839                 case COMEDI_INPUT:
2840                         data[2] = 0;
2841                         break;
2842                 default:
2843                         return -EINVAL;
2844                 }
2845                 return 0;
2846         case INSN_CONFIG_ARM:
2847                 return ni_ao_arm(dev, s);
2848         case INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS:
2849                 /* we don't care about actual channels */
2850                 /* data[3] : chanlist_len */
2851                 data[1] = board->ao_speed * data[3];
2852                 data[2] = 0;
2853                 return 0;
2854         default:
2855                 break;
2856         }
2857
2858         return -EINVAL;
2859 }
2860
2861 static int ni_ao_inttrig(struct comedi_device *dev,
2862                          struct comedi_subdevice *s,
2863                          unsigned int trig_num)
2864 {
2865         struct ni_private *devpriv = dev->private;
2866         struct comedi_cmd *cmd = &s->async->cmd;
2867         int ret;
2868
2869         /*
2870          * Require trig_num == cmd->start_arg when cmd->start_src == TRIG_INT.
2871          * For backwards compatibility, also allow trig_num == 0 when
2872          * cmd->start_src != TRIG_INT (i.e. when cmd->start_src == TRIG_EXT);
2873          * in that case, the internal trigger is being used as a pre-trigger
2874          * before the external trigger.
2875          */
2876         if (!(trig_num == cmd->start_arg ||
2877               (trig_num == 0 && cmd->start_src != TRIG_INT)))
2878                 return -EINVAL;
2879
2880         /*
2881          * Null trig at beginning prevent ao start trigger from executing more
2882          * than once per command.
2883          */
2884         s->async->inttrig = NULL;
2885
2886         if (devpriv->ao_needs_arming) {
2887                 /* only arm this device if it still needs arming */
2888                 ret = ni_ao_arm(dev, s);
2889                 if (ret)
2890                         return ret;
2891         }
2892
2893         ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2894                       NISTC_AO_CMD2_REG);
2895
2896         return 0;
2897 }
2898
2899 /*
2900  * begin ni_ao_cmd.
2901  * Organized similar to NI-STC and MHDDK examples.
2902  * ni_ao_cmd is broken out into configuration sub-routines for clarity.
2903  */
2904
2905 static void ni_ao_cmd_personalize(struct comedi_device *dev,
2906                                   const struct comedi_cmd *cmd)
2907 {
2908         const struct ni_board_struct *board = dev->board_ptr;
2909         unsigned int bits;
2910
2911         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2912
2913         bits =
2914           /* fast CPU interface--only eseries */
2915           /* ((slow CPU interface) ? 0 : AO_Fast_CPU) | */
2916           NISTC_AO_PERSONAL_BC_SRC_SEL  |
2917           0 /* (use_original_pulse ? 0 : NISTC_AO_PERSONAL_UPDATE_TIMEBASE) */ |
2918           /*
2919            * FIXME:  start setting following bit when appropriate.  Need to
2920            * determine whether board is E4 or E1.
2921            * FROM MHHDK:
2922            * if board is E4 or E1
2923            *   Set bit "NISTC_AO_PERSONAL_UPDATE_PW" to 0
2924            * else
2925            *   set it to 1
2926            */
2927           NISTC_AO_PERSONAL_UPDATE_PW   |
2928           /* FIXME:  when should we set following bit to zero? */
2929           NISTC_AO_PERSONAL_TMRDACWR_PW |
2930           (board->ao_fifo_depth ?
2931             NISTC_AO_PERSONAL_FIFO_ENA : NISTC_AO_PERSONAL_DMA_PIO_CTRL)
2932           ;
2933 #if 0
2934         /*
2935          * FIXME:
2936          * add something like ".has_individual_dacs = 0" to ni_board_struct
2937          * since, as F Hess pointed out, not all in m series have singles.  not
2938          * sure if e-series all have duals...
2939          */
2940
2941         /*
2942          * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit for
2943          * 6281, verified with bus analyzer.
2944          */
2945         if (devpriv->is_m_series)
2946                 bits |= NISTC_AO_PERSONAL_NUM_DAC;
2947 #endif
2948         ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
2949
2950         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2951 }
2952
2953 static void ni_ao_cmd_set_trigger(struct comedi_device *dev,
2954                                   const struct comedi_cmd *cmd)
2955 {
2956         struct ni_private *devpriv = dev->private;
2957         unsigned int trigsel;
2958
2959         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2960
2961         /* sync */
2962         if (cmd->stop_src == TRIG_NONE) {
2963                 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2964                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2965         } else {
2966                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2967                 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2968         }
2969         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2970
2971         if (cmd->start_src == TRIG_INT) {
2972                 trigsel = NISTC_AO_TRIG_START1_EDGE |
2973                           NISTC_AO_TRIG_START1_SYNC;
2974         } else { /* TRIG_EXT */
2975                 trigsel = NISTC_AO_TRIG_START1_SEL(
2976                                 ni_get_reg_value_roffs(
2977                                                 CR_CHAN(cmd->start_arg),
2978                                                 NI_AO_StartTrigger,
2979                                                 &devpriv->routing_tables, 1));
2980
2981                 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2982                 if (cmd->start_arg & CR_INVERT)
2983                         trigsel |= NISTC_AO_TRIG_START1_POLARITY;
2984                 /* 0=edge detection disabled, 1=enabled */
2985                 if (cmd->start_arg & CR_EDGE)
2986                         trigsel |= NISTC_AO_TRIG_START1_EDGE;
2987         }
2988         ni_stc_writew(dev, trigsel, NISTC_AO_TRIG_SEL_REG);
2989
2990         /* AO_Delayed_START1 = 0, we do not support delayed start...yet */
2991
2992         /* sync */
2993         /* select DA_START1 as PFI6/AO_START1 when configured as an output */
2994         devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2995         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2996
2997         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
2998 }
2999
3000 static void ni_ao_cmd_set_counters(struct comedi_device *dev,
3001                                    const struct comedi_cmd *cmd)
3002 {
3003         struct ni_private *devpriv = dev->private;
3004         /* Not supporting 'waveform staging' or 'local buffer with pauses' */
3005
3006         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3007         /*
3008          * This relies on ao_mode1/(Trigger_Once | Continuous) being set in
3009          * set_trigger above.  It is unclear whether we really need to re-write
3010          * this register with these values.  The mhddk examples for e-series
3011          * show writing this in both places, but the examples for m-series show
3012          * a single write in the set_counters function (here).
3013          */
3014         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3015
3016         /* sync (upload number of buffer iterations -1) */
3017         /* indicate that we want to use BC_Load_A_Register as the source */
3018         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
3019         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3020
3021         /*
3022          * if the BC_TC interrupt is still issued in spite of UC, BC, UI
3023          * ignoring BC_TC, then we will need to find a way to ignore that
3024          * interrupt in continuous mode.
3025          */
3026         ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG); /* iter once */
3027
3028         /* sync (issue command to load number of buffer iterations -1) */
3029         ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
3030
3031         /* sync (upload number of updates in buffer) */
3032         /* indicate that we want to use UC_Load_A_Register as the source */
3033         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
3034         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3035
3036         /*
3037          * if a user specifies '0', this automatically assumes the entire 24bit
3038          * address space is available for the (multiple iterations of single
3039          * buffer) MISB.  Otherwise, stop_arg specifies the MISB length that
3040          * will be used, regardless of whether we are in continuous mode or not.
3041          * In continuous mode, the output will just iterate indefinitely over
3042          * the MISB.
3043          */
3044         {
3045                 unsigned int stop_arg = cmd->stop_arg > 0 ?
3046                         (cmd->stop_arg & 0xffffff) : 0xffffff;
3047
3048                 if (devpriv->is_m_series) {
3049                         /*
3050                          * this is how the NI example code does it for m-series
3051                          * boards, verified correct with 6259
3052                          */
3053                         ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3054
3055                         /* sync (issue cmd to load number of updates in MISB) */
3056                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3057                                       NISTC_AO_CMD1_REG);
3058                 } else {
3059                         ni_stc_writel(dev, stop_arg, NISTC_AO_UC_LOADA_REG);
3060
3061                         /* sync (issue cmd to load number of updates in MISB) */
3062                         ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
3063                                       NISTC_AO_CMD1_REG);
3064
3065                         /*
3066                          * sync (upload number of updates-1 in MISB)
3067                          * --eseries only?
3068                          */
3069                         ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG);
3070                 }
3071         }
3072
3073         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3074 }
3075
3076 static void ni_ao_cmd_set_update(struct comedi_device *dev,
3077                                  const struct comedi_cmd *cmd)
3078 {
3079         struct ni_private *devpriv = dev->private;
3080
3081         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3082
3083         /*
3084          * zero out these bit fields to be set below. Does an ao-reset do this
3085          * automatically?
3086          */
3087         devpriv->ao_mode1 &=  ~(NISTC_AO_MODE1_UI_SRC_MASK         |
3088                                 NISTC_AO_MODE1_UI_SRC_POLARITY     |
3089                                 NISTC_AO_MODE1_UPDATE_SRC_MASK     |
3090                                 NISTC_AO_MODE1_UPDATE_SRC_POLARITY);
3091
3092         if (cmd->scan_begin_src == TRIG_TIMER) {
3093                 unsigned int trigvar;
3094
3095                 devpriv->ao_cmd2  &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3096
3097                 /*
3098                  * NOTE: there are several other ways of configuring internal
3099                  * updates, but we'll only support one for now:  using
3100                  * AO_IN_TIMEBASE, w/o waveform staging, w/o a delay between
3101                  * START1 and first update, and also w/o local buffer mode w/
3102                  * pauses.
3103                  */
3104
3105                 /*
3106                  * This is already done above:
3107                  * devpriv->ao_mode1 &= ~(
3108                  *   // set UPDATE_Source to UI_TC:
3109                  *   NISTC_AO_MODE1_UPDATE_SRC_MASK |
3110                  *   // set UPDATE_Source_Polarity to rising (required?)
3111                  *   NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3112                  *   // set UI_Source to AO_IN_TIMEBASE1:
3113                  *   NISTC_AO_MODE1_UI_SRC_MASK     |
3114                  *   // set UI_Source_Polarity to rising (required?)
3115                  *   NISTC_AO_MODE1_UI_SRC_POLARITY
3116                  * );
3117                  */
3118
3119                 /*
3120                  * TODO:  use ao_ui_clock_source to allow all possible signals
3121                  * to be routed to UI_Source_Select.  See tSTC.h for
3122                  * eseries/ni67xx and tMSeries.h for mseries.
3123                  */
3124
3125                 trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg,
3126                                          CMDF_ROUND_NEAREST);
3127
3128                 /*
3129                  * Wait N TB3 ticks after the start trigger before
3130                  * clocking (N must be >=2).
3131                  */
3132                 /* following line: 2-1 per STC */
3133                 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3134                 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3135                 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3136         } else { /* TRIG_EXT */
3137                 /* FIXME:  assert scan_begin_arg != 0, ret failure otherwise */
3138                 devpriv->ao_cmd2  |= NISTC_AO_CMD2_BC_GATE_ENA;
3139                 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC(
3140                                         ni_get_reg_value(
3141                                                 CR_CHAN(cmd->scan_begin_arg),
3142                                                 NI_AO_SampleClock,
3143                                                 &devpriv->routing_tables));
3144                 if (cmd->scan_begin_arg & CR_INVERT)
3145                         devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3146         }
3147
3148         ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3149         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3150         devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3151                                NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3152         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3153
3154         /* Configure DAQ-STC for Timed update mode */
3155         devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3156                             NISTC_AO_CMD1_DAC0_UPDATE_MODE;
3157         /* We are not using UPDATE2-->don't have to set DACx_Source_Select */
3158         ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3159
3160         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3161 }
3162
3163 static void ni_ao_cmd_set_channels(struct comedi_device *dev,
3164                                    struct comedi_subdevice *s)
3165 {
3166         struct ni_private *devpriv = dev->private;
3167         const struct comedi_cmd *cmd = &s->async->cmd;
3168         unsigned int bits = 0;
3169
3170         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3171
3172         if (devpriv->is_6xxx) {
3173                 unsigned int i;
3174
3175                 bits = 0;
3176                 for (i = 0; i < cmd->chanlist_len; ++i) {
3177                         int chan = CR_CHAN(cmd->chanlist[i]);
3178
3179                         bits |= 1 << chan;
3180                         ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
3181                 }
3182                 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
3183         }
3184
3185         ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3186
3187         if (cmd->scan_end_arg > 1) {
3188                 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3189                 bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1)
3190                                  | NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3191
3192         } else {
3193                 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3194                 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3195                 if (devpriv->is_m_series | devpriv->is_6xxx)
3196                         bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3197                 else
3198                         bits |= NISTC_AO_OUT_CTRL_CHANS(
3199                                         CR_CHAN(cmd->chanlist[0]));
3200         }
3201
3202         ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3203         ni_stc_writew(dev, bits,              NISTC_AO_OUT_CTRL_REG);
3204
3205         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3206 }
3207
3208 static void ni_ao_cmd_set_stop_conditions(struct comedi_device *dev,
3209                                           const struct comedi_cmd *cmd)
3210 {
3211         struct ni_private *devpriv = dev->private;
3212
3213         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3214
3215         devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3216         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3217
3218         /*
3219          * Since we are not supporting waveform staging, we ignore these errors:
3220          * NISTC_AO_MODE3_STOP_ON_BC_TC_ERR,
3221          * NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR
3222          */
3223
3224         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3225 }
3226
3227 static void ni_ao_cmd_set_fifo_mode(struct comedi_device *dev)
3228 {
3229         struct ni_private *devpriv = dev->private;
3230
3231         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3232
3233         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3234 #ifdef PCIDMA
3235         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3236 #else
3237         devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3238 #endif
3239         /* NOTE:  this is where use_onboard_memory=True would be implemented */
3240         devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3241         ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3242
3243         /* enable sending of ao fifo requests (dma request) */
3244         ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3245
3246         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3247
3248         /* we are not supporting boards with virtual fifos */
3249 }
3250
3251 static void ni_ao_cmd_set_interrupts(struct comedi_device *dev,
3252                                      struct comedi_subdevice *s)
3253 {
3254         if (s->async->cmd.stop_src == TRIG_COUNT)
3255                 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3256                             NISTC_INTB_ENA_AO_BC_TC, 1);
3257
3258         s->async->inttrig = ni_ao_inttrig;
3259 }
3260
3261 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3262 {
3263         struct ni_private *devpriv = dev->private;
3264         const struct comedi_cmd *cmd = &s->async->cmd;
3265
3266         if (dev->irq == 0) {
3267                 dev_err(dev->class_dev, "cannot run command without an irq");
3268                 return -EIO;
3269         }
3270
3271         /* ni_ao_reset should have already been done */
3272         ni_ao_cmd_personalize(dev, cmd);
3273         /* clearing fifo and preload happens elsewhere */
3274
3275         ni_ao_cmd_set_trigger(dev, cmd);
3276         ni_ao_cmd_set_counters(dev, cmd);
3277         ni_ao_cmd_set_update(dev, cmd);
3278         ni_ao_cmd_set_channels(dev, s);
3279         ni_ao_cmd_set_stop_conditions(dev, cmd);
3280         ni_ao_cmd_set_fifo_mode(dev);
3281         ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff);
3282         ni_ao_cmd_set_interrupts(dev, s);
3283
3284         /*
3285          * arm(ing) must happen later so that DMA can be setup and DACs
3286          * preloaded with the actual output buffer before starting.
3287          *
3288          * start(ing) must happen _after_ arming is completed.  Starting can be
3289          * done either via ni_ao_inttrig, or via an external trigger.
3290          *
3291          * **Currently, ni_ao_inttrig will automatically attempt a call to
3292          * ni_ao_arm if the device still needs arming at that point.  This
3293          * allows backwards compatibility.
3294          */
3295         devpriv->ao_needs_arming = 1;
3296         return 0;
3297 }
3298
3299 /* end ni_ao_cmd */
3300
3301 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3302                          struct comedi_cmd *cmd)
3303 {
3304         const struct ni_board_struct *board = dev->board_ptr;
3305         struct ni_private *devpriv = dev->private;
3306         int err = 0;
3307         unsigned int tmp;
3308
3309         /* Step 1 : check if triggers are trivially valid */
3310
3311         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3312         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3313                                         TRIG_TIMER | TRIG_EXT);
3314         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3315         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3316         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3317
3318         if (err)
3319                 return 1;
3320
3321         /* Step 2a : make sure trigger sources are unique */
3322
3323         err |= comedi_check_trigger_is_unique(cmd->start_src);
3324         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3325         err |= comedi_check_trigger_is_unique(cmd->stop_src);
3326
3327         /* Step 2b : and mutually compatible */
3328
3329         if (err)
3330                 return 2;
3331
3332         /* Step 3: check if arguments are trivially valid */
3333
3334         switch (cmd->start_src) {
3335         case TRIG_INT:
3336                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3337                 break;
3338         case TRIG_EXT:
3339                 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->start_arg),
3340                                                   NI_AO_StartTrigger,
3341                                                   &devpriv->routing_tables, 1);
3342                 break;
3343         }
3344
3345         if (cmd->scan_begin_src == TRIG_TIMER) {
3346                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3347                                                     board->ao_speed);
3348                 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3349                                                     devpriv->clock_ns *
3350                                                     0xffffff);
3351         } else {                /* TRIG_EXT */
3352                 err |= ni_check_trigger_arg(CR_CHAN(cmd->scan_begin_arg),
3353                                             NI_AO_SampleClock,
3354                                             &devpriv->routing_tables);
3355         }
3356
3357         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3358         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3359                                            cmd->chanlist_len);
3360         err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3361
3362         if (err)
3363                 return 3;
3364
3365         /* step 4: fix up any arguments */
3366         if (cmd->scan_begin_src == TRIG_TIMER) {
3367                 tmp = cmd->scan_begin_arg;
3368                 cmd->scan_begin_arg =
3369                     ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3370                                                        cmd->scan_begin_arg,
3371                                                        cmd->flags));
3372                 if (tmp != cmd->scan_begin_arg)
3373                         err++;
3374         }
3375         if (err)
3376                 return 4;
3377
3378         return 0;
3379 }
3380
3381 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3382 {
3383         /* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */
3384
3385         /*
3386          * In the following, the "--sync" comments are meant to denote
3387          * asynchronous boundaries for setting the registers as described in the
3388          * DAQ-STC mostly in the order also described in the DAQ-STC.
3389          */
3390
3391         struct ni_private *devpriv = dev->private;
3392
3393         ni_release_ao_mite_channel(dev);
3394
3395         /* --sync (reset AO) */
3396         if (devpriv->is_m_series)
3397                 /* following example in mhddk for m-series */
3398                 ni_stc_writew(dev, NISTC_RESET_AO, NISTC_RESET_REG);
3399
3400         /*--sync (start config) */
3401         ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3402
3403         /*--sync (Disarm) */
3404         ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3405
3406         /*
3407          * --sync
3408          * (clear bunch of registers--mseries mhddk examples do not include
3409          * this)
3410          */
3411         devpriv->ao_cmd1  = 0;
3412         devpriv->ao_cmd2  = 0;
3413         devpriv->ao_mode1 = 0;
3414         devpriv->ao_mode2 = 0;
3415         if (devpriv->is_m_series)
3416                 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3417         else
3418                 devpriv->ao_mode3 = 0;
3419
3420         ni_stc_writew(dev, 0, NISTC_AO_PERSONAL_REG);
3421         ni_stc_writew(dev, 0, NISTC_AO_CMD1_REG);
3422         ni_stc_writew(dev, 0, NISTC_AO_CMD2_REG);
3423         ni_stc_writew(dev, 0, NISTC_AO_MODE1_REG);
3424         ni_stc_writew(dev, 0, NISTC_AO_MODE2_REG);
3425         ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3426         ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3427         ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3428         ni_stc_writew(dev, 0, NISTC_AO_TRIG_SEL_REG);
3429
3430         /*--sync (disable interrupts) */
3431         ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3432
3433         /*--sync (ack) */
3434         ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3435         ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3436
3437         /*--not in DAQ-STC.  which doc? */
3438         if (devpriv->is_6xxx) {
3439                 ni_ao_win_outw(dev, (1u << s->n_chan) - 1u,
3440                                NI671X_AO_IMMEDIATE_REG);
3441                 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3442                                NI611X_AO_MISC_REG);
3443         }
3444         ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3445         /*--end */
3446
3447         return 0;
3448 }
3449
3450 /* digital io */
3451
3452 static int ni_dio_insn_config(struct comedi_device *dev,
3453                               struct comedi_subdevice *s,
3454                               struct comedi_insn *insn,
3455                               unsigned int *data)
3456 {
3457         struct ni_private *devpriv = dev->private;
3458         int ret;
3459
3460         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3461         if (ret)
3462                 return ret;
3463
3464         devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3465         devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3466         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3467
3468         return insn->n;
3469 }
3470
3471 static int ni_dio_insn_bits(struct comedi_device *dev,
3472                             struct comedi_subdevice *s,
3473                             struct comedi_insn *insn,
3474                             unsigned int *data)
3475 {
3476         struct ni_private *devpriv = dev->private;
3477
3478         /* Make sure we're not using the serial part of the dio */
3479         if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3480             devpriv->serial_interval_ns)
3481                 return -EBUSY;
3482
3483         if (comedi_dio_update_state(s, data)) {
3484                 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3485                 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3486                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3487         }
3488
3489         data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3490
3491         return insn->n;
3492 }
3493
3494 #ifdef PCIDMA
3495 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3496                                        struct comedi_subdevice *s,
3497                                        struct comedi_insn *insn,
3498                                        unsigned int *data)
3499 {
3500         int ret;
3501
3502         if (data[0] == INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS) {
3503                 const struct ni_board_struct *board = dev->board_ptr;
3504
3505                 /* we don't care about actual channels */
3506                 data[1] = board->dio_speed;
3507                 data[2] = 0;
3508                 return 0;
3509         }
3510
3511         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3512         if (ret)
3513                 return ret;
3514
3515         ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3516
3517         return insn->n;
3518 }
3519
3520 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3521                                      struct comedi_subdevice *s,
3522                                      struct comedi_insn *insn,
3523                                      unsigned int *data)
3524 {
3525         if (comedi_dio_update_state(s, data))
3526                 ni_writel(dev, s->state, NI_M_DIO_REG);
3527
3528         data[1] = ni_readl(dev, NI_M_DIO_REG);
3529
3530         return insn->n;
3531 }
3532
3533 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3534                                   struct comedi_subdevice *s,
3535                                   struct comedi_cmd *cmd)
3536 {
3537         int i;
3538
3539         for (i = 0; i < cmd->chanlist_len; ++i) {
3540                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3541
3542                 if (chan != i)
3543                         return -EINVAL;
3544         }
3545
3546         return 0;
3547 }
3548
3549 static int ni_cdio_cmdtest(struct comedi_device *dev,
3550                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
3551 {
3552         struct ni_private *devpriv = dev->private;
3553         unsigned int bytes_per_scan;
3554         int err = 0;
3555
3556         /* Step 1 : check if triggers are trivially valid */
3557
3558         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3559         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3560         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3561         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3562         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3563
3564         if (err)
3565                 return 1;
3566
3567         /* Step 2a : make sure trigger sources are unique */
3568         /* Step 2b : and mutually compatible */
3569
3570         /* Step 3: check if arguments are trivially valid */
3571
3572         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3573
3574         /*
3575          * Although NI_D[IO]_SampleClock are the same, perhaps we should still,
3576          * for completeness, test whether the cmd is output or input?
3577          */
3578         err |= ni_check_trigger_arg(CR_CHAN(cmd->scan_begin_arg),
3579                                     NI_DO_SampleClock,
3580                                     &devpriv->routing_tables);
3581         if (CR_RANGE(cmd->scan_begin_arg) != 0 ||
3582             CR_AREF(cmd->scan_begin_arg) != 0)
3583                 err |= -EINVAL;
3584
3585         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3586         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3587                                            cmd->chanlist_len);
3588         bytes_per_scan = comedi_bytes_per_scan_cmd(s, cmd);
3589         if (bytes_per_scan) {
3590                 err |= comedi_check_trigger_arg_max(&cmd->stop_arg,
3591                                                     s->async->prealloc_bufsz /
3592                                                     bytes_per_scan);
3593         }
3594
3595         if (err)
3596                 return 3;
3597
3598         /* Step 4: fix up any arguments */
3599
3600         /* Step 5: check channel list if it exists */
3601
3602         if (cmd->chanlist && cmd->chanlist_len > 0)
3603                 err |= ni_cdio_check_chanlist(dev, s, cmd);
3604
3605         if (err)
3606                 return 5;
3607
3608         return 0;
3609 }
3610
3611 static int ni_cdo_inttrig(struct comedi_device *dev,
3612                           struct comedi_subdevice *s,
3613                           unsigned int trig_num)
3614 {
3615         struct comedi_cmd *cmd = &s->async->cmd;
3616         const unsigned int timeout = 1000;
3617         int retval = 0;
3618         unsigned int i;
3619         struct ni_private *devpriv = dev->private;
3620         unsigned long flags;
3621
3622         if (trig_num != cmd->start_arg)
3623                 return -EINVAL;
3624
3625         s->async->inttrig = NULL;
3626
3627         /* read alloc the entire buffer */
3628         comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3629
3630         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3631         if (devpriv->cdo_mite_chan) {
3632                 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3633                 mite_dma_arm(devpriv->cdo_mite_chan);
3634         } else {
3635                 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3636                 retval = -EIO;
3637         }
3638         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3639         if (retval < 0)
3640                 return retval;
3641
3642         /*
3643          * XXX not sure what interrupt C group does
3644          * wait for dma to fill output fifo
3645          * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3646          */
3647         for (i = 0; i < timeout; ++i) {
3648                 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3649                     NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3650                         break;
3651                 usleep_range(10, 100);
3652         }
3653         if (i == timeout) {
3654                 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3655                 s->cancel(dev, s);
3656                 return -EIO;
3657         }
3658         ni_writel(dev, NI_M_CDO_CMD_ARM |
3659                        NI_M_CDO_CMD_ERR_INT_ENA_SET |
3660                        NI_M_CDO_CMD_F_E_INT_ENA_SET,
3661                   NI_M_CDIO_CMD_REG);
3662         return retval;
3663 }
3664
3665 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3666 {
3667         struct ni_private *devpriv = dev->private;
3668         const struct comedi_cmd *cmd = &s->async->cmd;
3669         unsigned int cdo_mode_bits;
3670         int retval;
3671
3672         ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3673         /*
3674          * Although NI_D[IO]_SampleClock are the same, perhaps we should still,
3675          * for completeness, test whether the cmd is output or input(?)
3676          */
3677         cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3678                         NI_M_CDO_MODE_HALT_ON_ERROR |
3679                         NI_M_CDO_MODE_SAMPLE_SRC(
3680                                 ni_get_reg_value(
3681                                         CR_CHAN(cmd->scan_begin_arg),
3682                                         NI_DO_SampleClock,
3683                                         &devpriv->routing_tables));
3684         if (cmd->scan_begin_arg & CR_INVERT)
3685                 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3686         ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3687         if (s->io_bits) {
3688                 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3689                 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3690                 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3691         } else {
3692                 dev_err(dev->class_dev,
3693                         "attempted to run digital output command with no lines configured as outputs\n");
3694                 return -EIO;
3695         }
3696         retval = ni_request_cdo_mite_channel(dev);
3697         if (retval < 0)
3698                 return retval;
3699
3700         ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd,
3701                                  s->async->prealloc_bufsz /
3702                                  comedi_bytes_per_scan(s));
3703
3704         s->async->inttrig = ni_cdo_inttrig;
3705
3706         return 0;
3707 }
3708
3709 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3710 {
3711         ni_writel(dev, NI_M_CDO_CMD_DISARM |
3712                        NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3713                        NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3714                        NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3715                   NI_M_CDIO_CMD_REG);
3716         /*
3717          * XXX not sure what interrupt C group does
3718          * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3719          */
3720         ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3721         ni_release_cdo_mite_channel(dev);
3722         return 0;
3723 }
3724
3725 static void handle_cdio_interrupt(struct comedi_device *dev)
3726 {
3727         struct ni_private *devpriv = dev->private;
3728         unsigned int cdio_status;
3729         struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3730         unsigned long flags;
3731
3732         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3733         if (devpriv->cdo_mite_chan)
3734                 mite_ack_linkc(devpriv->cdo_mite_chan, s, true);
3735         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3736
3737         cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3738         if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3739                 /* XXX just guessing this is needed and does something useful */
3740                 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3741                           NI_M_CDIO_CMD_REG);
3742                 s->async->events |= COMEDI_CB_OVERFLOW;
3743         }
3744         if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3745                 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3746                           NI_M_CDIO_CMD_REG);
3747                 /* s->async->events |= COMEDI_CB_EOA; */
3748         }
3749         comedi_handle_events(dev, s);
3750 }
3751 #endif /*  PCIDMA */
3752
3753 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3754                                    struct comedi_subdevice *s,
3755                                    unsigned char data_out,
3756                                    unsigned char *data_in)
3757 {
3758         struct ni_private *devpriv = dev->private;
3759         unsigned int status1;
3760         int err = 0, count = 20;
3761
3762         devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3763         devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3764         ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3765
3766         status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3767         if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3768                 err = -EBUSY;
3769                 goto error;
3770         }
3771
3772         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3773         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3774         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3775
3776         /* Wait until STC says we're done, but don't loop infinitely. */
3777         while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3778                NISTC_STATUS1_SERIO_IN_PROG) {
3779                 /* Delay one bit per loop */
3780                 udelay((devpriv->serial_interval_ns + 999) / 1000);
3781                 if (--count < 0) {
3782                         dev_err(dev->class_dev,
3783                                 "SPI serial I/O didn't finish in time!\n");
3784                         err = -ETIME;
3785                         goto error;
3786                 }
3787         }
3788
3789         /*
3790          * Delay for last bit. This delay is absolutely necessary, because
3791          * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3792          */
3793         udelay((devpriv->serial_interval_ns + 999) / 1000);
3794
3795         if (data_in)
3796                 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3797
3798 error:
3799         ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3800
3801         return err;
3802 }
3803
3804 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3805                                    struct comedi_subdevice *s,
3806                                    unsigned char data_out,
3807                                    unsigned char *data_in)
3808 {
3809         struct ni_private *devpriv = dev->private;
3810         unsigned char mask, input = 0;
3811
3812         /* Wait for one bit before transfer */
3813         udelay((devpriv->serial_interval_ns + 999) / 1000);
3814
3815         for (mask = 0x80; mask; mask >>= 1) {
3816                 /*
3817                  * Output current bit; note that we cannot touch s->state
3818                  * because it is a per-subdevice field, and serial is
3819                  * a separate subdevice from DIO.
3820                  */
3821                 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3822                 if (data_out & mask)
3823                         devpriv->dio_output |= NISTC_DIO_SDOUT;
3824                 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3825
3826                 /*
3827                  * Assert SDCLK (active low, inverted), wait for half of
3828                  * the delay, deassert SDCLK, and wait for the other half.
3829                  */
3830                 devpriv->dio_control |= NISTC_DIO_SDCLK;
3831                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3832
3833                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3834
3835                 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3836                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3837
3838                 udelay((devpriv->serial_interval_ns + 999) / 2000);
3839
3840                 /* Input current bit */
3841                 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3842                         input |= mask;
3843         }
3844
3845         if (data_in)
3846                 *data_in = input;
3847
3848         return 0;
3849 }
3850
3851 static int ni_serial_insn_config(struct comedi_device *dev,
3852                                  struct comedi_subdevice *s,
3853                                  struct comedi_insn *insn,
3854                                  unsigned int *data)
3855 {
3856         struct ni_private *devpriv = dev->private;
3857         unsigned int clk_fout = devpriv->clock_and_fout;
3858         int err = insn->n;
3859         unsigned char byte_out, byte_in = 0;
3860
3861         if (insn->n != 2)
3862                 return -EINVAL;
3863
3864         switch (data[0]) {
3865         case INSN_CONFIG_SERIAL_CLOCK:
3866                 devpriv->serial_hw_mode = 1;
3867                 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3868
3869                 if (data[1] == SERIAL_DISABLED) {
3870                         devpriv->serial_hw_mode = 0;
3871                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3872                                                   NISTC_DIO_SDCLK);
3873                         data[1] = SERIAL_DISABLED;
3874                         devpriv->serial_interval_ns = data[1];
3875                 } else if (data[1] <= SERIAL_600NS) {
3876                         /*
3877                          * Warning: this clock speed is too fast to reliably
3878                          * control SCXI.
3879                          */
3880                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3881                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3882                         clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3883                         data[1] = SERIAL_600NS;
3884                         devpriv->serial_interval_ns = data[1];
3885                 } else if (data[1] <= SERIAL_1_2US) {
3886                         devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3887                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3888                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3889                         data[1] = SERIAL_1_2US;
3890                         devpriv->serial_interval_ns = data[1];
3891                 } else if (data[1] <= SERIAL_10US) {
3892                         devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3893                         clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3894                                     NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3895                         /*
3896                          * Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3897                          * 600ns/1.2us. If you turn divide_by_2 off with the
3898                          * slow clock, you will still get 10us, except then
3899                          * all your delays are wrong.
3900                          */
3901                         data[1] = SERIAL_10US;
3902                         devpriv->serial_interval_ns = data[1];
3903                 } else {
3904                         devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3905                                                   NISTC_DIO_SDCLK);
3906                         devpriv->serial_hw_mode = 0;
3907                         data[1] = (data[1] / 1000) * 1000;
3908                         devpriv->serial_interval_ns = data[1];
3909                 }
3910                 devpriv->clock_and_fout = clk_fout;
3911
3912                 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3913                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3914                 return 1;
3915
3916         case INSN_CONFIG_BIDIRECTIONAL_DATA:
3917
3918                 if (devpriv->serial_interval_ns == 0)
3919                         return -EINVAL;
3920
3921                 byte_out = data[1] & 0xFF;
3922
3923                 if (devpriv->serial_hw_mode) {
3924                         err = ni_serial_hw_readwrite8(dev, s, byte_out,
3925                                                       &byte_in);
3926                 } else if (devpriv->serial_interval_ns > 0) {
3927                         err = ni_serial_sw_readwrite8(dev, s, byte_out,
3928                                                       &byte_in);
3929                 } else {
3930                         dev_err(dev->class_dev, "serial disabled!\n");
3931                         return -EINVAL;
3932                 }
3933                 if (err < 0)
3934                         return err;
3935                 data[1] = byte_in & 0xFF;
3936                 return insn->n;
3937
3938                 break;
3939         default:
3940                 return -EINVAL;
3941         }
3942 }
3943
3944 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3945 {
3946         int i;
3947
3948         for (i = 0; i < s->n_chan; i++) {
3949                 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3950                                NI67XX_AO_CFG2_REG);
3951         }
3952         ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3953 }
3954
3955 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3956         [NITIO_G0_AUTO_INC]     = { NISTC_G0_AUTOINC_REG, 2 },
3957         [NITIO_G1_AUTO_INC]     = { NISTC_G1_AUTOINC_REG, 2 },
3958         [NITIO_G0_CMD]          = { NISTC_G0_CMD_REG, 2 },
3959         [NITIO_G1_CMD]          = { NISTC_G1_CMD_REG, 2 },
3960         [NITIO_G0_HW_SAVE]      = { NISTC_G0_HW_SAVE_REG, 4 },
3961         [NITIO_G1_HW_SAVE]      = { NISTC_G1_HW_SAVE_REG, 4 },
3962         [NITIO_G0_SW_SAVE]      = { NISTC_G0_SAVE_REG, 4 },
3963         [NITIO_G1_SW_SAVE]      = { NISTC_G1_SAVE_REG, 4 },
3964         [NITIO_G0_MODE]         = { NISTC_G0_MODE_REG, 2 },
3965         [NITIO_G1_MODE]         = { NISTC_G1_MODE_REG, 2 },
3966         [NITIO_G0_LOADA]        = { NISTC_G0_LOADA_REG, 4 },
3967         [NITIO_G1_LOADA]        = { NISTC_G1_LOADA_REG, 4 },
3968         [NITIO_G0_LOADB]        = { NISTC_G0_LOADB_REG, 4 },
3969         [NITIO_G1_LOADB]        = { NISTC_G1_LOADB_REG, 4 },
3970         [NITIO_G0_INPUT_SEL]    = { NISTC_G0_INPUT_SEL_REG, 2 },
3971         [NITIO_G1_INPUT_SEL]    = { NISTC_G1_INPUT_SEL_REG, 2 },
3972         [NITIO_G0_CNT_MODE]     = { 0x1b0, 2 }, /* M-Series only */
3973         [NITIO_G1_CNT_MODE]     = { 0x1b2, 2 }, /* M-Series only */
3974         [NITIO_G0_GATE2]        = { 0x1b4, 2 }, /* M-Series only */
3975         [NITIO_G1_GATE2]        = { 0x1b6, 2 }, /* M-Series only */
3976         [NITIO_G01_STATUS]      = { NISTC_G01_STATUS_REG, 2 },
3977         [NITIO_G01_RESET]       = { NISTC_RESET_REG, 2 },
3978         [NITIO_G01_STATUS1]     = { NISTC_STATUS1_REG, 2 },
3979         [NITIO_G01_STATUS2]     = { NISTC_STATUS2_REG, 2 },
3980         [NITIO_G0_DMA_CFG]      = { 0x1b8, 2 }, /* M-Series only */
3981         [NITIO_G1_DMA_CFG]      = { 0x1ba, 2 }, /* M-Series only */
3982         [NITIO_G0_DMA_STATUS]   = { 0x1b8, 2 }, /* M-Series only */
3983         [NITIO_G1_DMA_STATUS]   = { 0x1ba, 2 }, /* M-Series only */
3984         [NITIO_G0_ABZ]          = { 0x1c0, 2 }, /* M-Series only */
3985         [NITIO_G1_ABZ]          = { 0x1c2, 2 }, /* M-Series only */
3986         [NITIO_G0_INT_ACK]      = { NISTC_INTA_ACK_REG, 2 },
3987         [NITIO_G1_INT_ACK]      = { NISTC_INTB_ACK_REG, 2 },
3988         [NITIO_G0_STATUS]       = { NISTC_AI_STATUS1_REG, 2 },
3989         [NITIO_G1_STATUS]       = { NISTC_AO_STATUS1_REG, 2 },
3990         [NITIO_G0_INT_ENA]      = { NISTC_INTA_ENA_REG, 2 },
3991         [NITIO_G1_INT_ENA]      = { NISTC_INTB_ENA_REG, 2 },
3992 };
3993
3994 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3995                                             enum ni_gpct_register reg)
3996 {
3997         const struct mio_regmap *regmap;
3998
3999         if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
4000                 regmap = &ni_gpct_to_stc_regmap[reg];
4001         } else {
4002                 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
4003                          __func__, reg);
4004                 return 0;
4005         }
4006
4007         return regmap->mio_reg;
4008 }
4009
4010 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned int bits,
4011                                    enum ni_gpct_register reg)
4012 {
4013         struct comedi_device *dev = counter->counter_dev->dev;
4014         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4015
4016         if (stc_register == 0)
4017                 return;
4018
4019         switch (reg) {
4020                 /* m-series only registers */
4021         case NITIO_G0_CNT_MODE:
4022         case NITIO_G1_CNT_MODE:
4023         case NITIO_G0_GATE2:
4024         case NITIO_G1_GATE2:
4025         case NITIO_G0_DMA_CFG:
4026         case NITIO_G1_DMA_CFG:
4027         case NITIO_G0_ABZ:
4028         case NITIO_G1_ABZ:
4029                 ni_writew(dev, bits, stc_register);
4030                 break;
4031
4032                 /* 32 bit registers */
4033         case NITIO_G0_LOADA:
4034         case NITIO_G1_LOADA:
4035         case NITIO_G0_LOADB:
4036         case NITIO_G1_LOADB:
4037                 ni_stc_writel(dev, bits, stc_register);
4038                 break;
4039
4040                 /* 16 bit registers */
4041         case NITIO_G0_INT_ENA:
4042                 ni_set_bitfield(dev, stc_register,
4043                                 NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC,
4044                                 bits);
4045                 break;
4046         case NITIO_G1_INT_ENA:
4047                 ni_set_bitfield(dev, stc_register,
4048                                 NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC,
4049                                 bits);
4050                 break;
4051         default:
4052                 ni_stc_writew(dev, bits, stc_register);
4053         }
4054 }
4055
4056 static unsigned int ni_gpct_read_register(struct ni_gpct *counter,
4057                                           enum ni_gpct_register reg)
4058 {
4059         struct comedi_device *dev = counter->counter_dev->dev;
4060         unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
4061
4062         if (stc_register == 0)
4063                 return 0;
4064
4065         switch (reg) {
4066                 /* m-series only registers */
4067         case NITIO_G0_DMA_STATUS:
4068         case NITIO_G1_DMA_STATUS:
4069                 return ni_readw(dev, stc_register);
4070
4071                 /* 32 bit registers */
4072         case NITIO_G0_HW_SAVE:
4073         case NITIO_G1_HW_SAVE:
4074         case NITIO_G0_SW_SAVE:
4075         case NITIO_G1_SW_SAVE:
4076                 return ni_stc_readl(dev, stc_register);
4077
4078                 /* 16 bit registers */
4079         default:
4080                 return ni_stc_readw(dev, stc_register);
4081         }
4082 }
4083
4084 static int ni_freq_out_insn_read(struct comedi_device *dev,
4085                                  struct comedi_subdevice *s,
4086                                  struct comedi_insn *insn,
4087                                  unsigned int *data)
4088 {
4089         struct ni_private *devpriv = dev->private;
4090         unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
4091         int i;
4092
4093         for (i = 0; i < insn->n; i++)
4094                 data[i] = val;
4095
4096         return insn->n;
4097 }
4098
4099 static int ni_freq_out_insn_write(struct comedi_device *dev,
4100                                   struct comedi_subdevice *s,
4101                                   struct comedi_insn *insn,
4102                                   unsigned int *data)
4103 {
4104         struct ni_private *devpriv = dev->private;
4105
4106         if (insn->n) {
4107                 unsigned int val = data[insn->n - 1];
4108
4109                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
4110                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4111                 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
4112
4113                 /* use the last data value to set the fout divider */
4114                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
4115
4116                 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
4117                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4118         }
4119         return insn->n;
4120 }
4121
4122 static int ni_freq_out_insn_config(struct comedi_device *dev,
4123                                    struct comedi_subdevice *s,
4124                                    struct comedi_insn *insn,
4125                                    unsigned int *data)
4126 {
4127         struct ni_private *devpriv = dev->private;
4128
4129         switch (data[0]) {
4130         case INSN_CONFIG_SET_CLOCK_SRC:
4131                 switch (data[1]) {
4132                 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4133                         devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
4134                         break;
4135                 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4136                         devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
4137                         break;
4138                 default:
4139                         return -EINVAL;
4140                 }
4141                 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
4142                 break;
4143         case INSN_CONFIG_GET_CLOCK_SRC:
4144                 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
4145                         data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4146                         data[2] = TIMEBASE_2_NS;
4147                 } else {
4148                         data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4149                         data[2] = TIMEBASE_1_NS * 2;
4150                 }
4151                 break;
4152         default:
4153                 return -EINVAL;
4154         }
4155         return insn->n;
4156 }
4157
4158 static int ni_8255_callback(struct comedi_device *dev,
4159                             int dir, int port, int data, unsigned long iobase)
4160 {
4161         if (dir) {
4162                 ni_writeb(dev, data, iobase + 2 * port);
4163                 return 0;
4164         }
4165
4166         return ni_readb(dev, iobase + 2 * port);
4167 }
4168
4169 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4170 {
4171         struct ni_private *devpriv = dev->private;
4172
4173         data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4174         data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4175         return 3;
4176 }
4177
4178 static int ni_m_series_pwm_config(struct comedi_device *dev,
4179                                   struct comedi_subdevice *s,
4180                                   struct comedi_insn *insn,
4181                                   unsigned int *data)
4182 {
4183         struct ni_private *devpriv = dev->private;
4184         unsigned int up_count, down_count;
4185
4186         switch (data[0]) {
4187         case INSN_CONFIG_PWM_OUTPUT:
4188                 switch (data[1]) {
4189                 case CMDF_ROUND_NEAREST:
4190                         up_count = DIV_ROUND_CLOSEST(data[2],
4191                                                      devpriv->clock_ns);
4192                         break;
4193                 case CMDF_ROUND_DOWN:
4194                         up_count = data[2] / devpriv->clock_ns;
4195                         break;
4196                 case CMDF_ROUND_UP:
4197                         up_count =
4198                             DIV_ROUND_UP(data[2], devpriv->clock_ns);
4199                         break;
4200                 default:
4201                         return -EINVAL;
4202                 }
4203                 switch (data[3]) {
4204                 case CMDF_ROUND_NEAREST:
4205                         down_count = DIV_ROUND_CLOSEST(data[4],
4206                                                        devpriv->clock_ns);
4207                         break;
4208                 case CMDF_ROUND_DOWN:
4209                         down_count = data[4] / devpriv->clock_ns;
4210                         break;
4211                 case CMDF_ROUND_UP:
4212                         down_count =
4213                             DIV_ROUND_UP(data[4], devpriv->clock_ns);
4214                         break;
4215                 default:
4216                         return -EINVAL;
4217                 }
4218                 if (up_count * devpriv->clock_ns != data[2] ||
4219                     down_count * devpriv->clock_ns != data[4]) {
4220                         data[2] = up_count * devpriv->clock_ns;
4221                         data[4] = down_count * devpriv->clock_ns;
4222                         return -EAGAIN;
4223                 }
4224                 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
4225                                NI_M_CAL_PWM_LOW_TIME(down_count),
4226                           NI_M_CAL_PWM_REG);
4227                 devpriv->pwm_up_count = up_count;
4228                 devpriv->pwm_down_count = down_count;
4229                 return 5;
4230         case INSN_CONFIG_GET_PWM_OUTPUT:
4231                 return ni_get_pwm_config(dev, data);
4232         default:
4233                 return -EINVAL;
4234         }
4235         return 0;
4236 }
4237
4238 static int ni_6143_pwm_config(struct comedi_device *dev,
4239                               struct comedi_subdevice *s,
4240                               struct comedi_insn *insn,
4241                               unsigned int *data)
4242 {
4243         struct ni_private *devpriv = dev->private;
4244         unsigned int up_count, down_count;
4245
4246         switch (data[0]) {
4247         case INSN_CONFIG_PWM_OUTPUT:
4248                 switch (data[1]) {
4249                 case CMDF_ROUND_NEAREST:
4250                         up_count = DIV_ROUND_CLOSEST(data[2],
4251                                                      devpriv->clock_ns);
4252                         break;
4253                 case CMDF_ROUND_DOWN:
4254                         up_count = data[2] / devpriv->clock_ns;
4255                         break;
4256                 case CMDF_ROUND_UP:
4257                         up_count =
4258                             DIV_ROUND_UP(data[2], devpriv->clock_ns);
4259                         break;
4260                 default:
4261                         return -EINVAL;
4262                 }
4263                 switch (data[3]) {
4264                 case CMDF_ROUND_NEAREST:
4265                         down_count = DIV_ROUND_CLOSEST(data[4],
4266                                                        devpriv->clock_ns);
4267                         break;
4268                 case CMDF_ROUND_DOWN:
4269                         down_count = data[4] / devpriv->clock_ns;
4270                         break;
4271                 case CMDF_ROUND_UP:
4272                         down_count =
4273                             DIV_ROUND_UP(data[4], devpriv->clock_ns);
4274                         break;
4275                 default:
4276                         return -EINVAL;
4277                 }
4278                 if (up_count * devpriv->clock_ns != data[2] ||
4279                     down_count * devpriv->clock_ns != data[4]) {
4280                         data[2] = up_count * devpriv->clock_ns;
4281                         data[4] = down_count * devpriv->clock_ns;
4282                         return -EAGAIN;
4283                 }
4284                 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4285                 devpriv->pwm_up_count = up_count;
4286                 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4287                 devpriv->pwm_down_count = down_count;
4288                 return 5;
4289         case INSN_CONFIG_GET_PWM_OUTPUT:
4290                 return ni_get_pwm_config(dev, data);
4291         default:
4292                 return -EINVAL;
4293         }
4294         return 0;
4295 }
4296
4297 static int pack_mb88341(int addr, int val, int *bitstring)
4298 {
4299         /*
4300          * Fujitsu MB 88341
4301          * Note that address bits are reversed.  Thanks to
4302          * Ingo Keen for noticing this.
4303          *
4304          * Note also that the 88341 expects address values from
4305          * 1-12, whereas we use channel numbers 0-11.  The NI
4306          * docs use 1-12, also, so be careful here.
4307          */
4308         addr++;
4309         *bitstring = ((addr & 0x1) << 11) |
4310             ((addr & 0x2) << 9) |
4311             ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4312         return 12;
4313 }
4314
4315 static int pack_dac8800(int addr, int val, int *bitstring)
4316 {
4317         *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4318         return 11;
4319 }
4320
4321 static int pack_dac8043(int addr, int val, int *bitstring)
4322 {
4323         *bitstring = val & 0xfff;
4324         return 12;
4325 }
4326
4327 static int pack_ad8522(int addr, int val, int *bitstring)
4328 {
4329         *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4330         return 16;
4331 }
4332
4333 static int pack_ad8804(int addr, int val, int *bitstring)
4334 {
4335         *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4336         return 12;
4337 }
4338
4339 static int pack_ad8842(int addr, int val, int *bitstring)
4340 {
4341         *bitstring = ((addr + 1) << 8) | (val & 0xff);
4342         return 12;
4343 }
4344
4345 struct caldac_struct {
4346         int n_chans;
4347         int n_bits;
4348         int (*packbits)(int address, int value, int *bitstring);
4349 };
4350
4351 static struct caldac_struct caldacs[] = {
4352         [mb88341] = {12, 8, pack_mb88341},
4353         [dac8800] = {8, 8, pack_dac8800},
4354         [dac8043] = {1, 12, pack_dac8043},
4355         [ad8522] = {2, 12, pack_ad8522},
4356         [ad8804] = {12, 8, pack_ad8804},
4357         [ad8842] = {8, 8, pack_ad8842},
4358         [ad8804_debug] = {16, 8, pack_ad8804},
4359 };
4360
4361 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4362 {
4363         const struct ni_board_struct *board = dev->board_ptr;
4364         struct ni_private *devpriv = dev->private;
4365         unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4366         unsigned int cmd;
4367         int i;
4368         int type;
4369
4370         if (devpriv->caldacs[addr] == val)
4371                 return;
4372         devpriv->caldacs[addr] = val;
4373
4374         for (i = 0; i < 3; i++) {
4375                 type = board->caldac[i];
4376                 if (type == caldac_none)
4377                         break;
4378                 if (addr < caldacs[type].n_chans) {
4379                         bits = caldacs[type].packbits(addr, val, &bitstring);
4380                         loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4381                         break;
4382                 }
4383                 addr -= caldacs[type].n_chans;
4384         }
4385
4386         /* bits will be 0 if there is no caldac for the given addr */
4387         if (bits == 0)
4388                 return;
4389
4390         for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4391                 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4392                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4393                 udelay(1);
4394                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4395                 udelay(1);
4396         }
4397         ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4398         udelay(1);
4399         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4400 }
4401
4402 static int ni_calib_insn_write(struct comedi_device *dev,
4403                                struct comedi_subdevice *s,
4404                                struct comedi_insn *insn,
4405                                unsigned int *data)
4406 {
4407         if (insn->n) {
4408                 /* only bother writing the last sample to the channel */
4409                 ni_write_caldac(dev, CR_CHAN(insn->chanspec),
4410                                 data[insn->n - 1]);
4411         }
4412
4413         return insn->n;
4414 }
4415
4416 static int ni_calib_insn_read(struct comedi_device *dev,
4417                               struct comedi_subdevice *s,
4418                               struct comedi_insn *insn,
4419                               unsigned int *data)
4420 {
4421         struct ni_private *devpriv = dev->private;
4422         unsigned int i;
4423
4424         for (i = 0; i < insn->n; i++)
4425                 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4426
4427         return insn->n;
4428 }
4429
4430 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4431 {
4432         const struct ni_board_struct *board = dev->board_ptr;
4433         struct ni_private *devpriv = dev->private;
4434         int i, j;
4435         int n_dacs;
4436         int n_chans = 0;
4437         int n_bits;
4438         int diffbits = 0;
4439         int type;
4440         int chan;
4441
4442         type = board->caldac[0];
4443         if (type == caldac_none)
4444                 return;
4445         n_bits = caldacs[type].n_bits;
4446         for (i = 0; i < 3; i++) {
4447                 type = board->caldac[i];
4448                 if (type == caldac_none)
4449                         break;
4450                 if (caldacs[type].n_bits != n_bits)
4451                         diffbits = 1;
4452                 n_chans += caldacs[type].n_chans;
4453         }
4454         n_dacs = i;
4455         s->n_chan = n_chans;
4456
4457         if (diffbits) {
4458                 unsigned int *maxdata_list = devpriv->caldac_maxdata_list;
4459
4460                 if (n_chans > MAX_N_CALDACS)
4461                         dev_err(dev->class_dev,
4462                                 "BUG! MAX_N_CALDACS too small\n");
4463                 s->maxdata_list = maxdata_list;
4464                 chan = 0;
4465                 for (i = 0; i < n_dacs; i++) {
4466                         type = board->caldac[i];
4467                         for (j = 0; j < caldacs[type].n_chans; j++) {
4468                                 maxdata_list[chan] =
4469                                     (1 << caldacs[type].n_bits) - 1;
4470                                 chan++;
4471                         }
4472                 }
4473
4474                 for (chan = 0; chan < s->n_chan; chan++)
4475                         ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4476         } else {
4477                 type = board->caldac[0];
4478                 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4479
4480                 for (chan = 0; chan < s->n_chan; chan++)
4481                         ni_write_caldac(dev, i, s->maxdata / 2);
4482         }
4483 }
4484
4485 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4486 {
4487         unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4488         int bit;
4489         int bitstring;
4490
4491         bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4492         ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4493         for (bit = 0x8000; bit; bit >>= 1) {
4494                 if (bit & bitstring)
4495                         cmd |= NI_E_SERIAL_CMD_SDATA;
4496                 else
4497                         cmd &= ~NI_E_SERIAL_CMD_SDATA;
4498
4499                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4500                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4501         }
4502         cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4503         bitstring = 0;
4504         for (bit = 0x80; bit; bit >>= 1) {
4505                 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4506                 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4507                 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4508                         bitstring |= bit;
4509         }
4510         ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4511
4512         return bitstring;
4513 }
4514
4515 static int ni_eeprom_insn_read(struct comedi_device *dev,
4516                                struct comedi_subdevice *s,
4517                                struct comedi_insn *insn,
4518                                unsigned int *data)
4519 {
4520         unsigned int val;
4521         unsigned int i;
4522
4523         if (insn->n) {
4524                 val = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4525                 for (i = 0; i < insn->n; i++)
4526                         data[i] = val;
4527         }
4528         return insn->n;
4529 }
4530
4531 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4532                                         struct comedi_subdevice *s,
4533                                         struct comedi_insn *insn,
4534                                         unsigned int *data)
4535 {
4536         struct ni_private *devpriv = dev->private;
4537         unsigned int i;
4538
4539         for (i = 0; i < insn->n; i++)
4540                 data[i] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4541
4542         return insn->n;
4543 }
4544
4545 static unsigned int ni_old_get_pfi_routing(struct comedi_device *dev,
4546                                            unsigned int chan)
4547 {
4548         /*  pre-m-series boards have fixed signals on pfi pins */
4549         switch (chan) {
4550         case 0:
4551                 return NI_PFI_OUTPUT_AI_START1;
4552         case 1:
4553                 return NI_PFI_OUTPUT_AI_START2;
4554         case 2:
4555                 return NI_PFI_OUTPUT_AI_CONVERT;
4556         case 3:
4557                 return NI_PFI_OUTPUT_G_SRC1;
4558         case 4:
4559                 return NI_PFI_OUTPUT_G_GATE1;
4560         case 5:
4561                 return NI_PFI_OUTPUT_AO_UPDATE_N;
4562         case 6:
4563                 return NI_PFI_OUTPUT_AO_START1;
4564         case 7:
4565                 return NI_PFI_OUTPUT_AI_START_PULSE;
4566         case 8:
4567                 return NI_PFI_OUTPUT_G_SRC0;
4568         case 9:
4569                 return NI_PFI_OUTPUT_G_GATE0;
4570         default:
4571                 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4572                 break;
4573         }
4574         return 0;
4575 }
4576
4577 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4578                                   unsigned int chan, unsigned int source)
4579 {
4580         /*  pre-m-series boards have fixed signals on pfi pins */
4581         if (source != ni_old_get_pfi_routing(dev, chan))
4582                 return -EINVAL;
4583         return 2;
4584 }
4585
4586 static unsigned int ni_m_series_get_pfi_routing(struct comedi_device *dev,
4587                                                 unsigned int chan)
4588 {
4589         struct ni_private *devpriv = dev->private;
4590         const unsigned int array_offset = chan / 3;
4591
4592         return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4593                                 devpriv->pfi_output_select_reg[array_offset]);
4594 }
4595
4596 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4597                                        unsigned int chan, unsigned int source)
4598 {
4599         struct ni_private *devpriv = dev->private;
4600         unsigned int index = chan / 3;
4601         unsigned short val = devpriv->pfi_output_select_reg[index];
4602
4603         if ((source & 0x1f) != source)
4604                 return -EINVAL;
4605
4606         val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4607         val |= NI_M_PFI_OUT_SEL(chan, source);
4608         ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4609         devpriv->pfi_output_select_reg[index] = val;
4610
4611         return 2;
4612 }
4613
4614 static unsigned int ni_get_pfi_routing(struct comedi_device *dev,
4615                                        unsigned int chan)
4616 {
4617         struct ni_private *devpriv = dev->private;
4618
4619         if (chan >= NI_PFI(0)) {
4620                 /* allow new and old names of pfi channels to work. */
4621                 chan -= NI_PFI(0);
4622         }
4623         return (devpriv->is_m_series)
4624                         ? ni_m_series_get_pfi_routing(dev, chan)
4625                         : ni_old_get_pfi_routing(dev, chan);
4626 }
4627
4628 /* Sets the output mux for the specified PFI channel. */
4629 static int ni_set_pfi_routing(struct comedi_device *dev,
4630                               unsigned int chan, unsigned int source)
4631 {
4632         struct ni_private *devpriv = dev->private;
4633
4634         if (chan >= NI_PFI(0)) {
4635                 /* allow new and old names of pfi channels to work. */
4636                 chan -= NI_PFI(0);
4637         }
4638         return (devpriv->is_m_series)
4639                         ? ni_m_series_set_pfi_routing(dev, chan, source)
4640                         : ni_old_set_pfi_routing(dev, chan, source);
4641 }
4642
4643 static int ni_config_pfi_filter(struct comedi_device *dev,
4644                                 unsigned int chan,
4645                                 enum ni_pfi_filter_select filter)
4646 {
4647         struct ni_private *devpriv = dev->private;
4648         unsigned int bits;
4649
4650         if (!devpriv->is_m_series)
4651                 return -ENOTSUPP;
4652
4653         if (chan >= NI_PFI(0)) {
4654                 /* allow new and old names of pfi channels to work. */
4655                 chan -= NI_PFI(0);
4656         }
4657
4658         bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4659         bits &= ~NI_M_PFI_FILTER_SEL_MASK(chan);
4660         bits |= NI_M_PFI_FILTER_SEL(chan, filter);
4661         ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4662         return 0;
4663 }
4664
4665 static void ni_set_pfi_direction(struct comedi_device *dev, int chan,
4666                                  unsigned int direction)
4667 {
4668         if (chan >= NI_PFI(0)) {
4669                 /* allow new and old names of pfi channels to work. */
4670                 chan -= NI_PFI(0);
4671         }
4672         direction = (direction == COMEDI_OUTPUT) ? 1u : 0u;
4673         ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, direction);
4674 }
4675
4676 static int ni_get_pfi_direction(struct comedi_device *dev, int chan)
4677 {
4678         struct ni_private *devpriv = dev->private;
4679
4680         if (chan >= NI_PFI(0)) {
4681                 /* allow new and old names of pfi channels to work. */
4682                 chan -= NI_PFI(0);
4683         }
4684         return devpriv->io_bidirection_pin_reg & (1 << chan) ?
4685                COMEDI_OUTPUT : COMEDI_INPUT;
4686 }
4687
4688 static int ni_pfi_insn_config(struct comedi_device *dev,
4689                               struct comedi_subdevice *s,
4690                               struct comedi_insn *insn,
4691                               unsigned int *data)
4692 {
4693         unsigned int chan;
4694
4695         if (insn->n < 1)
4696                 return -EINVAL;
4697
4698         chan = CR_CHAN(insn->chanspec);
4699
4700         switch (data[0]) {
4701         case COMEDI_OUTPUT:
4702         case COMEDI_INPUT:
4703                 ni_set_pfi_direction(dev, chan, data[0]);
4704                 break;
4705         case INSN_CONFIG_DIO_QUERY:
4706                 data[1] = ni_get_pfi_direction(dev, chan);
4707                 break;
4708         case INSN_CONFIG_SET_ROUTING:
4709                 return ni_set_pfi_routing(dev, chan, data[1]);
4710         case INSN_CONFIG_GET_ROUTING:
4711                 data[1] = ni_get_pfi_routing(dev, chan);
4712                 break;
4713         case INSN_CONFIG_FILTER:
4714                 return ni_config_pfi_filter(dev, chan, data[1]);
4715         default:
4716                 return -EINVAL;
4717         }
4718         return 0;
4719 }
4720
4721 static int ni_pfi_insn_bits(struct comedi_device *dev,
4722                             struct comedi_subdevice *s,
4723                             struct comedi_insn *insn,
4724                             unsigned int *data)
4725 {
4726         struct ni_private *devpriv = dev->private;
4727
4728         if (!devpriv->is_m_series)
4729                 return -ENOTSUPP;
4730
4731         if (comedi_dio_update_state(s, data))
4732                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4733
4734         data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4735
4736         return insn->n;
4737 }
4738
4739 static int cs5529_wait_for_idle(struct comedi_device *dev)
4740 {
4741         unsigned short status;
4742         const int timeout = HZ;
4743         int i;
4744
4745         for (i = 0; i < timeout; i++) {
4746                 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4747                 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4748                         break;
4749                 set_current_state(TASK_INTERRUPTIBLE);
4750                 if (schedule_timeout(1))
4751                         return -EIO;
4752         }
4753         if (i == timeout) {
4754                 dev_err(dev->class_dev, "timeout\n");
4755                 return -ETIME;
4756         }
4757         return 0;
4758 }
4759
4760 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4761 {
4762         static const int timeout = 100;
4763         int i;
4764
4765         ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4766         /* give time for command to start being serially clocked into cs5529.
4767          * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4768          * set before we exit this function.
4769          */
4770         for (i = 0; i < timeout; i++) {
4771                 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4772                     NI67XX_CAL_STATUS_BUSY)
4773                         break;
4774                 udelay(1);
4775         }
4776         if (i == timeout)
4777                 dev_err(dev->class_dev,
4778                         "possible problem - never saw adc go busy?\n");
4779 }
4780
4781 static int cs5529_do_conversion(struct comedi_device *dev,
4782                                 unsigned short *data)
4783 {
4784         int retval;
4785         unsigned short status;
4786
4787         cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4788         retval = cs5529_wait_for_idle(dev);
4789         if (retval) {
4790                 dev_err(dev->class_dev,
4791                         "timeout or signal in %s()\n", __func__);
4792                 return -ETIME;
4793         }
4794         status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4795         if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4796                 dev_err(dev->class_dev,
4797                         "cs5529 conversion error, status CSS_OSC_DETECT\n");
4798                 return -EIO;
4799         }
4800         if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4801                 dev_err(dev->class_dev,
4802                         "cs5529 conversion error, overrange (ignoring)\n");
4803         }
4804         if (data) {
4805                 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4806                 /* cs5529 returns 16 bit signed data in bipolar mode */
4807                 *data ^= BIT(15);
4808         }
4809         return 0;
4810 }
4811
4812 static int cs5529_ai_insn_read(struct comedi_device *dev,
4813                                struct comedi_subdevice *s,
4814                                struct comedi_insn *insn,
4815                                unsigned int *data)
4816 {
4817         int n, retval;
4818         unsigned short sample;
4819         unsigned int channel_select;
4820         const unsigned int INTERNAL_REF = 0x1000;
4821
4822         /*
4823          * Set calibration adc source.  Docs lie, reference select bits 8 to 11
4824          * do nothing. bit 12 seems to chooses internal reference voltage, bit
4825          * 13 causes the adc input to go overrange (maybe reads external
4826          * reference?)
4827          */
4828         if (insn->chanspec & CR_ALT_SOURCE)
4829                 channel_select = INTERNAL_REF;
4830         else
4831                 channel_select = CR_CHAN(insn->chanspec);
4832         ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4833
4834         for (n = 0; n < insn->n; n++) {
4835                 retval = cs5529_do_conversion(dev, &sample);
4836                 if (retval < 0)
4837                         return retval;
4838                 data[n] = sample;
4839         }
4840         return insn->n;
4841 }
4842
4843 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4844                                 unsigned int reg_select_bits)
4845 {
4846         ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4847         ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4848         reg_select_bits &= CS5529_CMD_REG_MASK;
4849         cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4850         if (cs5529_wait_for_idle(dev))
4851                 dev_err(dev->class_dev,
4852                         "timeout or signal in %s\n", __func__);
4853 }
4854
4855 static int init_cs5529(struct comedi_device *dev)
4856 {
4857         unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4858                                    CS5529_CFG_WORD_RATE_2180;
4859
4860 #if 1
4861         /* do self-calibration */
4862         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4863                             CS5529_CFG_REG);
4864         /* need to force a conversion for calibration to run */
4865         cs5529_do_conversion(dev, NULL);
4866 #else
4867         /* force gain calibration to 1 */
4868         cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4869         cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4870                             CS5529_CFG_REG);
4871         if (cs5529_wait_for_idle(dev))
4872                 dev_err(dev->class_dev,
4873                         "timeout or signal in %s\n", __func__);
4874 #endif
4875         return 0;
4876 }
4877
4878 /*
4879  * Find best multiplier/divider to try and get the PLL running at 80 MHz
4880  * given an arbitrary frequency input clock.
4881  */
4882 static int ni_mseries_get_pll_parameters(unsigned int reference_period_ns,
4883                                          unsigned int *freq_divider,
4884                                          unsigned int *freq_multiplier,
4885                                          unsigned int *actual_period_ns)
4886 {
4887         unsigned int div;
4888         unsigned int best_div = 1;
4889         unsigned int mult;
4890         unsigned int best_mult = 1;
4891         static const unsigned int pico_per_nano = 1000;
4892         const unsigned int reference_picosec = reference_period_ns *
4893                                                pico_per_nano;
4894         /*
4895          * m-series wants the phased-locked loop to output 80MHz, which is
4896          * divided by 4 to 20 MHz for most timing clocks
4897          */
4898         static const unsigned int target_picosec = 12500;
4899         int best_period_picosec = 0;
4900
4901         for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4902                 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4903                         unsigned int new_period_ps =
4904                             (reference_picosec * div) / mult;
4905                         if (abs(new_period_ps - target_picosec) <
4906                             abs(best_period_picosec - target_picosec)) {
4907                                 best_period_picosec = new_period_ps;
4908                                 best_div = div;
4909                                 best_mult = mult;
4910                         }
4911                 }
4912         }
4913         if (best_period_picosec == 0)
4914                 return -EIO;
4915
4916         *freq_divider = best_div;
4917         *freq_multiplier = best_mult;
4918         /* return the actual period (* fudge factor for 80 to 20 MHz) */
4919         *actual_period_ns = DIV_ROUND_CLOSEST(best_period_picosec * 4,
4920                                               pico_per_nano);
4921         return 0;
4922 }
4923
4924 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4925                                            unsigned int source,
4926                                            unsigned int period_ns)
4927 {
4928         struct ni_private *devpriv = dev->private;
4929         static const unsigned int min_period_ns = 50;
4930         static const unsigned int max_period_ns = 1000;
4931         static const unsigned int timeout = 1000;
4932         unsigned int pll_control_bits;
4933         unsigned int freq_divider;
4934         unsigned int freq_multiplier;
4935         unsigned int rtsi;
4936         unsigned int i;
4937         int retval;
4938
4939         if (source == NI_MIO_PLL_PXI10_CLOCK)
4940                 period_ns = 100;
4941         /*
4942          * These limits are somewhat arbitrary, but NI advertises 1 to 20MHz
4943          * range so we'll use that.
4944          */
4945         if (period_ns < min_period_ns || period_ns > max_period_ns) {
4946                 dev_err(dev->class_dev,
4947                         "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4948                         __func__, min_period_ns, max_period_ns);
4949                 return -EINVAL;
4950         }
4951         devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4952         ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4953                       NISTC_RTSI_TRIG_DIR_REG);
4954         pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4955         devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4956                                     NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4957         devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4958         switch (source) {
4959         case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4960                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4961                 break;
4962         case NI_MIO_PLL_PXI10_CLOCK:
4963                 /* pxi clock is 10MHz */
4964                 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4965                 break;
4966         default:
4967                 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4968                         if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4969                                 devpriv->clock_and_fout2 |=
4970                                         NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4971                                 break;
4972                         }
4973                 }
4974                 if (rtsi > NI_M_MAX_RTSI_CHAN)
4975                         return -EINVAL;
4976                 break;
4977         }
4978         retval = ni_mseries_get_pll_parameters(period_ns,
4979                                                &freq_divider,
4980                                                &freq_multiplier,
4981                                                &devpriv->clock_ns);
4982         if (retval < 0) {
4983                 dev_err(dev->class_dev,
4984                         "bug, failed to find pll parameters\n");
4985                 return retval;
4986         }
4987
4988         ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4989         pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4990                             NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4991
4992         ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4993         devpriv->clock_source = source;
4994         /* it takes a few hundred microseconds for PLL to lock */
4995         for (i = 0; i < timeout; ++i) {
4996                 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4997                         break;
4998                 udelay(1);
4999         }
5000         if (i == timeout) {
5001                 dev_err(dev->class_dev,
5002                         "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
5003                         __func__, source, period_ns);
5004                 return -ETIMEDOUT;
5005         }
5006         return 3;
5007 }
5008
5009 static int ni_set_master_clock(struct comedi_device *dev,
5010                                unsigned int source, unsigned int period_ns)
5011 {
5012         struct ni_private *devpriv = dev->private;
5013
5014         if (source == NI_MIO_INTERNAL_CLOCK) {
5015                 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
5016                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5017                               NISTC_RTSI_TRIG_DIR_REG);
5018                 devpriv->clock_ns = TIMEBASE_1_NS;
5019                 if (devpriv->is_m_series) {
5020                         devpriv->clock_and_fout2 &=
5021                             ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
5022                               NI_M_CLK_FOUT2_TIMEBASE3_PLL);
5023                         ni_writew(dev, devpriv->clock_and_fout2,
5024                                   NI_M_CLK_FOUT2_REG);
5025                         ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
5026                 }
5027                 devpriv->clock_source = source;
5028         } else {
5029                 if (devpriv->is_m_series) {
5030                         return ni_mseries_set_pll_master_clock(dev, source,
5031                                                                period_ns);
5032                 } else {
5033                         if (source == NI_MIO_RTSI_CLOCK) {
5034                                 devpriv->rtsi_trig_direction_reg |=
5035                                     NISTC_RTSI_TRIG_USE_CLK;
5036                                 ni_stc_writew(dev,
5037                                               devpriv->rtsi_trig_direction_reg,
5038                                               NISTC_RTSI_TRIG_DIR_REG);
5039                                 if (period_ns == 0) {
5040                                         dev_err(dev->class_dev,
5041                                                 "we don't handle an unspecified clock period correctly yet, returning error\n");
5042                                         return -EINVAL;
5043                                 }
5044                                 devpriv->clock_ns = period_ns;
5045                                 devpriv->clock_source = source;
5046                         } else {
5047                                 return -EINVAL;
5048                         }
5049                 }
5050         }
5051         return 3;
5052 }
5053
5054 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
5055                                        unsigned int chan, unsigned int source)
5056 {
5057         struct ni_private *devpriv = dev->private;
5058
5059         if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5060                 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5061                         if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5062                                 return 1;
5063
5064                         dev_err(dev->class_dev,
5065                                 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
5066                                 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
5067                         return 0;
5068                 }
5069                 return 0;
5070         }
5071         switch (source) {
5072         case NI_RTSI_OUTPUT_ADR_START1:
5073         case NI_RTSI_OUTPUT_ADR_START2:
5074         case NI_RTSI_OUTPUT_SCLKG:
5075         case NI_RTSI_OUTPUT_DACUPDN:
5076         case NI_RTSI_OUTPUT_DA_START1:
5077         case NI_RTSI_OUTPUT_G_SRC0:
5078         case NI_RTSI_OUTPUT_G_GATE0:
5079         case NI_RTSI_OUTPUT_RGOUT0:
5080         case NI_RTSI_OUTPUT_RTSI_BRD(0):
5081         case NI_RTSI_OUTPUT_RTSI_BRD(1):
5082         case NI_RTSI_OUTPUT_RTSI_BRD(2):
5083         case NI_RTSI_OUTPUT_RTSI_BRD(3):
5084                 return 1;
5085         case NI_RTSI_OUTPUT_RTSI_OSC:
5086                 return (devpriv->is_m_series) ? 1 : 0;
5087         default:
5088                 return 0;
5089         }
5090 }
5091
5092 static int ni_set_rtsi_routing(struct comedi_device *dev,
5093                                unsigned int chan, unsigned int src)
5094 {
5095         struct ni_private *devpriv = dev->private;
5096
5097         if (chan >= TRIGGER_LINE(0))
5098                 /* allow new and old names of rtsi channels to work. */
5099                 chan -= TRIGGER_LINE(0);
5100
5101         if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
5102                 return -EINVAL;
5103         if (chan < 4) {
5104                 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5105                 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
5106                 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5107                               NISTC_RTSI_TRIGA_OUT_REG);
5108         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5109                 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
5110                 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
5111                 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5112                               NISTC_RTSI_TRIGB_OUT_REG);
5113         } else if (chan != NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5114                 /* probably should never reach this, since the
5115                  * ni_valid_rtsi_output_source above errors out if chan is too
5116                  * high
5117                  */
5118                 dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
5119                 return -EINVAL;
5120         }
5121         return 2;
5122 }
5123
5124 static unsigned int ni_get_rtsi_routing(struct comedi_device *dev,
5125                                         unsigned int chan)
5126 {
5127         struct ni_private *devpriv = dev->private;
5128
5129         if (chan >= TRIGGER_LINE(0))
5130                 /* allow new and old names of rtsi channels to work. */
5131                 chan -= TRIGGER_LINE(0);
5132
5133         if (chan < 4) {
5134                 return NISTC_RTSI_TRIG_TO_SRC(chan,
5135                                               devpriv->rtsi_trig_a_output_reg);
5136         } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
5137                 return NISTC_RTSI_TRIG_TO_SRC(chan,
5138                                               devpriv->rtsi_trig_b_output_reg);
5139         } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5140                 return NI_RTSI_OUTPUT_RTSI_OSC;
5141         }
5142
5143         dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__);
5144         return -EINVAL;
5145 }
5146
5147 static void ni_set_rtsi_direction(struct comedi_device *dev, int chan,
5148                                   unsigned int direction)
5149 {
5150         struct ni_private *devpriv = dev->private;
5151         unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5152
5153         if (chan >= TRIGGER_LINE(0))
5154                 /* allow new and old names of rtsi channels to work. */
5155                 chan -= TRIGGER_LINE(0);
5156
5157         if (direction == COMEDI_OUTPUT) {
5158                 if (chan < max_chan) {
5159                         devpriv->rtsi_trig_direction_reg |=
5160                             NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5161                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5162                         devpriv->rtsi_trig_direction_reg |=
5163                             NISTC_RTSI_TRIG_DRV_CLK;
5164                 }
5165         } else {
5166                 if (chan < max_chan) {
5167                         devpriv->rtsi_trig_direction_reg &=
5168                             ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
5169                 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5170                         devpriv->rtsi_trig_direction_reg &=
5171                             ~NISTC_RTSI_TRIG_DRV_CLK;
5172                 }
5173         }
5174         ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5175                       NISTC_RTSI_TRIG_DIR_REG);
5176 }
5177
5178 static int ni_get_rtsi_direction(struct comedi_device *dev, int chan)
5179 {
5180         struct ni_private *devpriv = dev->private;
5181         unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
5182
5183         if (chan >= TRIGGER_LINE(0))
5184                 /* allow new and old names of rtsi channels to work. */
5185                 chan -= TRIGGER_LINE(0);
5186
5187         if (chan < max_chan) {
5188                 return (devpriv->rtsi_trig_direction_reg &
5189                         NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
5190                            ? COMEDI_OUTPUT : COMEDI_INPUT;
5191         } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
5192                 return (devpriv->rtsi_trig_direction_reg &
5193                         NISTC_RTSI_TRIG_DRV_CLK)
5194                            ? COMEDI_OUTPUT : COMEDI_INPUT;
5195         }
5196         return -EINVAL;
5197 }
5198
5199 static int ni_rtsi_insn_config(struct comedi_device *dev,
5200                                struct comedi_subdevice *s,
5201                                struct comedi_insn *insn,
5202                                unsigned int *data)
5203 {
5204         struct ni_private *devpriv = dev->private;
5205         unsigned int chan = CR_CHAN(insn->chanspec);
5206
5207         switch (data[0]) {
5208         case COMEDI_OUTPUT:
5209         case COMEDI_INPUT:
5210                 ni_set_rtsi_direction(dev, chan, data[0]);
5211                 break;
5212         case INSN_CONFIG_DIO_QUERY: {
5213                 int ret = ni_get_rtsi_direction(dev, chan);
5214
5215                 if (ret < 0)
5216                         return ret;
5217                 data[1] = ret;
5218                 return 2;
5219         }
5220         case INSN_CONFIG_SET_CLOCK_SRC:
5221                 return ni_set_master_clock(dev, data[1], data[2]);
5222         case INSN_CONFIG_GET_CLOCK_SRC:
5223                 data[1] = devpriv->clock_source;
5224                 data[2] = devpriv->clock_ns;
5225                 return 3;
5226         case INSN_CONFIG_SET_ROUTING:
5227                 return ni_set_rtsi_routing(dev, chan, data[1]);
5228         case INSN_CONFIG_GET_ROUTING: {
5229                 int ret = ni_get_rtsi_routing(dev, chan);
5230
5231                 if (ret < 0)
5232                         return ret;
5233                 data[1] = ret;
5234                 return 2;
5235         }
5236         default:
5237                 return -EINVAL;
5238         }
5239         return 1;
5240 }
5241
5242 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5243                              struct comedi_subdevice *s,
5244                              struct comedi_insn *insn,
5245                              unsigned int *data)
5246 {
5247         data[1] = 0;
5248
5249         return insn->n;
5250 }
5251
5252 /*
5253  * Default routing for RTSI trigger lines.
5254  *
5255  * These values are used here in the init function, as well as in the
5256  * disconnect_route function, after a RTSI route has been disconnected.
5257  */
5258 static const int default_rtsi_routing[] = {
5259         [0] = NI_RTSI_OUTPUT_ADR_START1,
5260         [1] = NI_RTSI_OUTPUT_ADR_START2,
5261         [2] = NI_RTSI_OUTPUT_SCLKG,
5262         [3] = NI_RTSI_OUTPUT_DACUPDN,
5263         [4] = NI_RTSI_OUTPUT_DA_START1,
5264         [5] = NI_RTSI_OUTPUT_G_SRC0,
5265         [6] = NI_RTSI_OUTPUT_G_GATE0,
5266         [7] = NI_RTSI_OUTPUT_RTSI_OSC,
5267 };
5268
5269 /*
5270  * Route signals through RGOUT0 terminal.
5271  * @reg: raw register value of RGOUT0 bits (only bit0 is important).
5272  * @dev: comedi device handle.
5273  */
5274 static void set_rgout0_reg(int reg, struct comedi_device *dev)
5275 {
5276         struct ni_private *devpriv = dev->private;
5277
5278         if (devpriv->is_m_series) {
5279                 devpriv->rtsi_trig_direction_reg &=
5280                         ~NISTC_RTSI_TRIG_DIR_SUB_SEL1;
5281                 devpriv->rtsi_trig_direction_reg |=
5282                         (reg << NISTC_RTSI_TRIG_DIR_SUB_SEL1_SHIFT) &
5283                         NISTC_RTSI_TRIG_DIR_SUB_SEL1;
5284                 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5285                               NISTC_RTSI_TRIG_DIR_REG);
5286         } else {
5287                 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIGB_SUB_SEL1;
5288                 devpriv->rtsi_trig_b_output_reg |=
5289                         (reg << NISTC_RTSI_TRIGB_SUB_SEL1_SHIFT) &
5290                         NISTC_RTSI_TRIGB_SUB_SEL1;
5291                 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5292                               NISTC_RTSI_TRIGB_OUT_REG);
5293         }
5294 }
5295
5296 static int get_rgout0_reg(struct comedi_device *dev)
5297 {
5298         struct ni_private *devpriv = dev->private;
5299         int reg;
5300
5301         if (devpriv->is_m_series)
5302                 reg = (devpriv->rtsi_trig_direction_reg &
5303                        NISTC_RTSI_TRIG_DIR_SUB_SEL1)
5304                     >> NISTC_RTSI_TRIG_DIR_SUB_SEL1_SHIFT;
5305         else
5306                 reg = (devpriv->rtsi_trig_b_output_reg &
5307                        NISTC_RTSI_TRIGB_SUB_SEL1)
5308                     >> NISTC_RTSI_TRIGB_SUB_SEL1_SHIFT;
5309         return reg;
5310 }
5311
5312 static inline int get_rgout0_src(struct comedi_device *dev)
5313 {
5314         struct ni_private *devpriv = dev->private;
5315         int reg = get_rgout0_reg(dev);
5316
5317         return ni_find_route_source(reg, NI_RGOUT0, &devpriv->routing_tables);
5318 }
5319
5320 /*
5321  * Route signals through RGOUT0 terminal and increment the RGOUT0 use for this
5322  * particular route.
5323  * @src: device-global signal name
5324  * @dev: comedi device handle
5325  *
5326  * Return: -EINVAL if the source is not valid to route to RGOUT0;
5327  *         -EBUSY if the RGOUT0 is already used;
5328  *         0 if successful.
5329  */
5330 static int incr_rgout0_src_use(int src, struct comedi_device *dev)
5331 {
5332         struct ni_private *devpriv = dev->private;
5333         s8 reg = ni_lookup_route_register(CR_CHAN(src), NI_RGOUT0,
5334                                           &devpriv->routing_tables);
5335
5336         if (reg < 0)
5337                 return -EINVAL;
5338
5339         if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) != reg)
5340                 return -EBUSY;
5341
5342         ++devpriv->rgout0_usage;
5343         set_rgout0_reg(reg, dev);
5344         return 0;
5345 }
5346
5347 /*
5348  * Unroute signals through RGOUT0 terminal and deccrement the RGOUT0 use for
5349  * this particular source.  This function does not actually unroute anything
5350  * with respect to RGOUT0.  It does, on the other hand, decrement the usage
5351  * counter for the current src->RGOUT0 mapping.
5352  *
5353  * Return: -EINVAL if the source is not already routed to RGOUT0 (or usage is
5354  *      already at zero); 0 if successful.
5355  */
5356 static int decr_rgout0_src_use(int src, struct comedi_device *dev)
5357 {
5358         struct ni_private *devpriv = dev->private;
5359         s8 reg = ni_lookup_route_register(CR_CHAN(src), NI_RGOUT0,
5360                                           &devpriv->routing_tables);
5361
5362         if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) == reg) {
5363                 --devpriv->rgout0_usage;
5364                 if (!devpriv->rgout0_usage)
5365                         set_rgout0_reg(0, dev); /* ok default? */
5366                 return 0;
5367         }
5368         return -EINVAL;
5369 }
5370
5371 /*
5372  * Route signals through given NI_RTSI_BRD mux.
5373  * @i: index of mux to route
5374  * @reg: raw register value of RTSI_BRD bits
5375  * @dev: comedi device handle
5376  */
5377 static void set_ith_rtsi_brd_reg(int i, int reg, struct comedi_device *dev)
5378 {
5379         struct ni_private *devpriv = dev->private;
5380         int reg_i_sz = 3; /* value for e-series */
5381         int reg_i_mask;
5382         int reg_i_shift;
5383
5384         if (devpriv->is_m_series)
5385                 reg_i_sz = 4;
5386         reg_i_mask = ~((~0) << reg_i_sz);
5387         reg_i_shift = i * reg_i_sz;
5388
5389         /* clear out the current reg_i for ith brd */
5390         devpriv->rtsi_shared_mux_reg &= ~(reg_i_mask       << reg_i_shift);
5391         /* (softcopy) write the new reg_i for ith brd */
5392         devpriv->rtsi_shared_mux_reg |= (reg & reg_i_mask) << reg_i_shift;
5393         /* (hardcopy) write the new reg_i for ith brd */
5394         ni_stc_writew(dev, devpriv->rtsi_shared_mux_reg, NISTC_RTSI_BOARD_REG);
5395 }
5396
5397 static int get_ith_rtsi_brd_reg(int i, struct comedi_device *dev)
5398 {
5399         struct ni_private *devpriv = dev->private;
5400         int reg_i_sz = 3; /* value for e-series */
5401         int reg_i_mask;
5402         int reg_i_shift;
5403
5404         if (devpriv->is_m_series)
5405                 reg_i_sz = 4;
5406         reg_i_mask = ~((~0) << reg_i_sz);
5407         reg_i_shift = i * reg_i_sz;
5408
5409         return (devpriv->rtsi_shared_mux_reg >> reg_i_shift) & reg_i_mask;
5410 }
5411
5412 static inline int get_rtsi_brd_src(int brd, struct comedi_device *dev)
5413 {
5414         struct ni_private *devpriv = dev->private;
5415         int brd_index = brd;
5416         int reg;
5417
5418         if (brd >= NI_RTSI_BRD(0))
5419                 brd_index = brd - NI_RTSI_BRD(0);
5420         else
5421                 brd = NI_RTSI_BRD(brd);
5422         /*
5423          * And now:
5424          * brd : device-global name
5425          * brd_index : index number of RTSI_BRD mux
5426          */
5427
5428         reg = get_ith_rtsi_brd_reg(brd_index, dev);
5429
5430         return ni_find_route_source(reg, brd, &devpriv->routing_tables);
5431 }
5432
5433 /*
5434  * Route signals through NI_RTSI_BRD mux and increment the use counter for this
5435  * particular route.
5436  *
5437  * Return: -EINVAL if the source is not valid to route to NI_RTSI_BRD(i);
5438  *         -EBUSY if all NI_RTSI_BRD muxes are already used;
5439  *         NI_RTSI_BRD(i) of allocated ith mux if successful.
5440  */
5441 static int incr_rtsi_brd_src_use(int src, struct comedi_device *dev)
5442 {
5443         struct ni_private *devpriv = dev->private;
5444         int first_available = -1;
5445         int err = -EINVAL;
5446         s8 reg;
5447         int i;
5448
5449         /* first look for a mux that is already configured to provide src */
5450         for (i = 0; i < NUM_RTSI_SHARED_MUXS; ++i) {
5451                 reg = ni_lookup_route_register(CR_CHAN(src), NI_RTSI_BRD(i),
5452                                                &devpriv->routing_tables);
5453
5454                 if (reg < 0)
5455                         continue; /* invalid route */
5456
5457                 if (!devpriv->rtsi_shared_mux_usage[i]) {
5458                         if (first_available < 0)
5459                                 /* found the first unused, but usable mux */
5460                                 first_available = i;
5461                 } else {
5462                         /*
5463                          * we've seen at least one possible route, so change the
5464                          * final error to -EBUSY in case there are no muxes
5465                          * available.
5466                          */
5467                         err = -EBUSY;
5468
5469                         if (get_ith_rtsi_brd_reg(i, dev) == reg) {
5470                                 /*
5471                                  * we've found a mux that is already being used
5472                                  * to provide the requested signal.  Reuse it.
5473                                  */
5474                                 goto success;
5475                         }
5476                 }
5477         }
5478
5479         if (first_available < 0)
5480                 return err;
5481
5482         /* we did not find a mux to reuse, but there is at least one usable */
5483         i = first_available;
5484
5485 success:
5486         ++devpriv->rtsi_shared_mux_usage[i];
5487         set_ith_rtsi_brd_reg(i, reg, dev);
5488         return NI_RTSI_BRD(i);
5489 }
5490
5491 /*
5492  * Unroute signals through NI_RTSI_BRD mux and decrement the user counter for
5493  * this particular route.
5494  *
5495  * Return: -EINVAL if the source is not already routed to rtsi_brd(i) (or usage
5496  *      is already at zero); 0 if successful.
5497  */
5498 static int decr_rtsi_brd_src_use(int src, int rtsi_brd,
5499                                  struct comedi_device *dev)
5500 {
5501         struct ni_private *devpriv = dev->private;
5502         s8 reg = ni_lookup_route_register(CR_CHAN(src), rtsi_brd,
5503                                           &devpriv->routing_tables);
5504         const int i = rtsi_brd - NI_RTSI_BRD(0);
5505
5506         if (devpriv->rtsi_shared_mux_usage[i] > 0 &&
5507             get_ith_rtsi_brd_reg(i, dev) == reg) {
5508                 --devpriv->rtsi_shared_mux_usage[i];
5509                 if (!devpriv->rtsi_shared_mux_usage[i])
5510                         set_ith_rtsi_brd_reg(i, 0, dev); /* ok default? */
5511                 return 0;
5512         }
5513
5514         return -EINVAL;
5515 }
5516
5517 static void ni_rtsi_init(struct comedi_device *dev)
5518 {
5519         struct ni_private *devpriv = dev->private;
5520         int i;
5521
5522         /*  Initialises the RTSI bus signal switch to a default state */
5523
5524         /*
5525          * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
5526          * to have no effect, at least on pxi-6281, which always uses
5527          * 20MHz rtsi clock frequency
5528          */
5529         devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
5530         /*  Set clock mode to internal */
5531         if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
5532                 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
5533
5534         /* default internal lines routing to RTSI bus lines */
5535         for (i = 0; i < 8; ++i) {
5536                 ni_set_rtsi_direction(dev, i, COMEDI_INPUT);
5537                 ni_set_rtsi_routing(dev, i, default_rtsi_routing[i]);
5538         }
5539
5540         /*
5541          * Sets the source and direction of the 4 on board lines.
5542          * This configures all board lines to be:
5543          * for e-series:
5544          *   1) inputs (not sure what "output" would mean)
5545          *   2) copying TRIGGER_LINE(0) (or RTSI0) output
5546          * for m-series:
5547          *   copying NI_PFI(0) output
5548          */
5549         devpriv->rtsi_shared_mux_reg = 0;
5550         for (i = 0; i < 4; ++i)
5551                 set_ith_rtsi_brd_reg(i, 0, dev);
5552         memset(devpriv->rtsi_shared_mux_usage, 0,
5553                sizeof(devpriv->rtsi_shared_mux_usage));
5554
5555         /* initialize rgout0 pin as unused. */
5556         devpriv->rgout0_usage = 0;
5557         set_rgout0_reg(0, dev);
5558 }
5559
5560 /* Get route of GPFO_i/CtrOut pins */
5561 static inline int ni_get_gout_routing(unsigned int dest,
5562                                       struct comedi_device *dev)
5563 {
5564         struct ni_private *devpriv = dev->private;
5565         unsigned int reg = devpriv->an_trig_etc_reg;
5566
5567         switch (dest) {
5568         case 0:
5569                 if (reg & NISTC_ATRIG_ETC_GPFO_0_ENA)
5570                         return NISTC_ATRIG_ETC_GPFO_0_SEL_TO_SRC(reg);
5571                 break;
5572         case 1:
5573                 if (reg & NISTC_ATRIG_ETC_GPFO_1_ENA)
5574                         return NISTC_ATRIG_ETC_GPFO_1_SEL_TO_SRC(reg);
5575                 break;
5576         }
5577
5578         return -EINVAL;
5579 }
5580
5581 /* Set route of GPFO_i/CtrOut pins */
5582 static inline int ni_disable_gout_routing(unsigned int dest,
5583                                           struct comedi_device *dev)
5584 {
5585         struct ni_private *devpriv = dev->private;
5586
5587         switch (dest) {
5588         case 0:
5589                 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_ENA;
5590                 break;
5591         case 1:
5592                 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_ENA;
5593                 break;
5594         default:
5595                 return -EINVAL;
5596         }
5597
5598         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
5599         return 0;
5600 }
5601
5602 /* Set route of GPFO_i/CtrOut pins */
5603 static inline int ni_set_gout_routing(unsigned int src, unsigned int dest,
5604                                       struct comedi_device *dev)
5605 {
5606         struct ni_private *devpriv = dev->private;
5607
5608         switch (dest) {
5609         case 0:
5610                 /* clear reg */
5611                 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_SEL(-1);
5612                 /* set reg */
5613                 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_0_ENA
5614                                          |  NISTC_ATRIG_ETC_GPFO_0_SEL(src);
5615                 break;
5616         case 1:
5617                 /* clear reg */
5618                 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_SEL;
5619                 src = src ? NISTC_ATRIG_ETC_GPFO_1_SEL : 0;
5620                 /* set reg */
5621                 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_1_ENA | src;
5622                 break;
5623         default:
5624                 return -EINVAL;
5625         }
5626
5627         ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
5628         return 0;
5629 }
5630
5631 /*
5632  * Retrieves the current source of the output selector for the given
5633  * destination.  If the terminal for the destination is not already configured
5634  * as an output, this function returns -EINVAL as error.
5635  *
5636  * Return: the register value of the destination output selector;
5637  *         -EINVAL if terminal is not configured for output.
5638  */
5639 static int get_output_select_source(int dest, struct comedi_device *dev)
5640 {
5641         struct ni_private *devpriv = dev->private;
5642         int reg = -1;
5643
5644         if (channel_is_pfi(dest)) {
5645                 if (ni_get_pfi_direction(dev, dest) == COMEDI_OUTPUT)
5646                         reg = ni_get_pfi_routing(dev, dest);
5647         } else if (channel_is_rtsi(dest)) {
5648                 if (ni_get_rtsi_direction(dev, dest) == COMEDI_OUTPUT) {
5649                         reg = ni_get_rtsi_routing(dev, dest);
5650
5651                         if (reg == NI_RTSI_OUTPUT_RGOUT0) {
5652                                 dest = NI_RGOUT0; /* prepare for lookup below */
5653                                 reg = get_rgout0_reg(dev);
5654                         } else if (reg >= NI_RTSI_OUTPUT_RTSI_BRD(0) &&
5655                                    reg <= NI_RTSI_OUTPUT_RTSI_BRD(3)) {
5656                                 const int i = reg - NI_RTSI_OUTPUT_RTSI_BRD(0);
5657
5658                                 dest = NI_RTSI_BRD(i); /* prepare for lookup */
5659                                 reg = get_ith_rtsi_brd_reg(i, dev);
5660                         }
5661                 }
5662         } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) {
5663                 /*
5664                  * not handled by ni_tio.  Only available for GPFO registers in
5665                  * e/m series.
5666                  */
5667                 dest -= NI_CtrOut(0);
5668                 if (dest > 1)
5669                         /* there are only two g_out outputs. */
5670                         return -EINVAL;
5671                 reg = ni_get_gout_routing(dest, dev);
5672         } else if (channel_is_ctr(dest)) {
5673                 reg = ni_tio_get_routing(devpriv->counter_dev, dest);
5674         } else {
5675                 dev_dbg(dev->class_dev, "%s: unhandled destination (%d) queried\n",
5676                         __func__, dest);
5677         }
5678
5679         if (reg >= 0)
5680                 return ni_find_route_source(CR_CHAN(reg), dest,
5681                                             &devpriv->routing_tables);
5682         return -EINVAL;
5683 }
5684
5685 /*
5686  * Test a route:
5687  *
5688  * Return: -1 if not connectible;
5689  *          0 if connectible and not connected;
5690  *          1 if connectible and connected.
5691  */
5692 static int test_route(unsigned int src, unsigned int dest,
5693                       struct comedi_device *dev)
5694 {
5695         struct ni_private *devpriv = dev->private;
5696         s8 reg = ni_route_to_register(CR_CHAN(src), dest,
5697                                       &devpriv->routing_tables);
5698
5699         if (reg < 0)
5700                 return -1;
5701         if (get_output_select_source(dest, dev) != CR_CHAN(src))
5702                 return 0;
5703         return 1;
5704 }
5705
5706 /* Connect the actual route.  */
5707 static int connect_route(unsigned int src, unsigned int dest,
5708                          struct comedi_device *dev)
5709 {
5710         struct ni_private *devpriv = dev->private;
5711         s8 reg = ni_route_to_register(CR_CHAN(src), dest,
5712                                       &devpriv->routing_tables);
5713         s8 current_src;
5714
5715         if (reg < 0)
5716                 /* route is not valid */
5717                 return -EINVAL;
5718
5719         current_src = get_output_select_source(dest, dev);
5720         if (current_src == CR_CHAN(src))
5721                 return -EALREADY;
5722         if (current_src >= 0)
5723                 /* destination mux is already busy. complain, don't overwrite */
5724                 return -EBUSY;
5725
5726         /* The route is valid and available. Now connect... */
5727         if (channel_is_pfi(dest)) {
5728                 /* set routing source, then open output */
5729                 ni_set_pfi_routing(dev, dest, reg);
5730                 ni_set_pfi_direction(dev, dest, COMEDI_OUTPUT);
5731         } else if (channel_is_rtsi(dest)) {
5732                 if (reg == NI_RTSI_OUTPUT_RGOUT0) {
5733                         int ret = incr_rgout0_src_use(src, dev);
5734
5735                         if (ret < 0)
5736                                 return ret;
5737                 } else if (ni_rtsi_route_requires_mux(reg)) {
5738                         /* Attempt to allocate and  route (src->brd) */
5739                         int brd = incr_rtsi_brd_src_use(src, dev);
5740
5741                         if (brd < 0)
5742                                 return brd;
5743
5744                         /* Now lookup the register value for (brd->dest) */
5745                         reg = ni_lookup_route_register(
5746                                 brd, dest, &devpriv->routing_tables);
5747                 }
5748
5749                 ni_set_rtsi_direction(dev, dest, COMEDI_OUTPUT);
5750                 ni_set_rtsi_routing(dev, dest, reg);
5751         } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) {
5752                 /*
5753                  * not handled by ni_tio.  Only available for GPFO registers in
5754                  * e/m series.
5755                  */
5756                 dest -= NI_CtrOut(0);
5757                 if (dest > 1)
5758                         /* there are only two g_out outputs. */
5759                         return -EINVAL;
5760                 if (ni_set_gout_routing(src, dest, dev))
5761                         return -EINVAL;
5762         } else if (channel_is_ctr(dest)) {
5763                 /*
5764                  * we are adding back the channel modifier info to set
5765                  * invert/edge info passed by the user
5766                  */
5767                 ni_tio_set_routing(devpriv->counter_dev, dest,
5768                                    reg | (src & ~CR_CHAN(-1)));
5769         } else {
5770                 return -EINVAL;
5771         }
5772         return 0;
5773 }
5774
5775 static int disconnect_route(unsigned int src, unsigned int dest,
5776                             struct comedi_device *dev)
5777 {
5778         struct ni_private *devpriv = dev->private;
5779         s8 reg = ni_route_to_register(CR_CHAN(src), dest,
5780                                       &devpriv->routing_tables);
5781
5782         if (reg < 0)
5783                 /* route is not valid */
5784                 return -EINVAL;
5785         if (get_output_select_source(dest, dev) != src)
5786                 /* cannot disconnect something not connected */
5787                 return -EINVAL;
5788
5789         /* The route is valid and is connected.  Now disconnect... */
5790         if (channel_is_pfi(dest)) {
5791                 /* set the pfi to high impedance, and disconnect */
5792                 ni_set_pfi_direction(dev, dest, COMEDI_INPUT);
5793                 ni_set_pfi_routing(dev, dest, NI_PFI_OUTPUT_PFI_DEFAULT);
5794         } else if (channel_is_rtsi(dest)) {
5795                 if (reg == NI_RTSI_OUTPUT_RGOUT0) {
5796                         int ret = decr_rgout0_src_use(src, dev);
5797
5798                         if (ret < 0)
5799                                 return ret;
5800                 } else if (ni_rtsi_route_requires_mux(reg)) {
5801                         /* find which RTSI_BRD line is source for rtsi pin */
5802                         int brd = ni_find_route_source(
5803                                 ni_get_rtsi_routing(dev, dest), dest,
5804                                 &devpriv->routing_tables);
5805
5806                         if (brd < 0)
5807                                 return brd;
5808
5809                         /* decrement/disconnect RTSI_BRD line from source */
5810                         decr_rtsi_brd_src_use(src, brd, dev);
5811                 }
5812
5813                 /* set rtsi output selector to default state */
5814                 reg = default_rtsi_routing[dest - TRIGGER_LINE(0)];
5815                 ni_set_rtsi_direction(dev, dest, COMEDI_INPUT);
5816                 ni_set_rtsi_routing(dev, dest, reg);
5817         } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) {
5818                 /*
5819                  * not handled by ni_tio.  Only available for GPFO registers in
5820                  * e/m series.
5821                  */
5822                 dest -= NI_CtrOut(0);
5823                 if (dest > 1)
5824                         /* there are only two g_out outputs. */
5825                         return -EINVAL;
5826                 reg = ni_disable_gout_routing(dest, dev);
5827         } else if (channel_is_ctr(dest)) {
5828                 ni_tio_unset_routing(devpriv->counter_dev, dest);
5829         } else {
5830                 return -EINVAL;
5831         }
5832         return 0;
5833 }
5834
5835 static int ni_global_insn_config(struct comedi_device *dev,
5836                                  struct comedi_insn *insn,
5837                                  unsigned int *data)
5838 {
5839         switch (data[0]) {
5840         case INSN_DEVICE_CONFIG_TEST_ROUTE:
5841                 data[0] = test_route(data[1], data[2], dev);
5842                 return 2;
5843         case INSN_DEVICE_CONFIG_CONNECT_ROUTE:
5844                 return connect_route(data[1], data[2], dev);
5845         case INSN_DEVICE_CONFIG_DISCONNECT_ROUTE:
5846                 return disconnect_route(data[1], data[2], dev);
5847         /*
5848          * This case is already handled one level up.
5849          * case INSN_DEVICE_CONFIG_GET_ROUTES:
5850          */
5851         default:
5852                 return -EINVAL;
5853         }
5854         return 1;
5855 }
5856
5857 #ifdef PCIDMA
5858 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5859 {
5860         struct ni_gpct *counter = s->private;
5861         int retval;
5862
5863         retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5864                                               COMEDI_INPUT);
5865         if (retval) {
5866                 dev_err(dev->class_dev,
5867                         "no dma channel available for use by counter\n");
5868                 return retval;
5869         }
5870         ni_tio_acknowledge(counter);
5871         ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5872
5873         return ni_tio_cmd(dev, s);
5874 }
5875
5876 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5877 {
5878         struct ni_gpct *counter = s->private;
5879         int retval;
5880
5881         retval = ni_tio_cancel(counter);
5882         ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5883         ni_release_gpct_mite_channel(dev, counter->counter_index);
5884         return retval;
5885 }
5886 #endif
5887
5888 static irqreturn_t ni_E_interrupt(int irq, void *d)
5889 {
5890         struct comedi_device *dev = d;
5891         struct comedi_subdevice *s_ai = dev->read_subdev;
5892         struct comedi_subdevice *s_ao = dev->write_subdev;
5893         unsigned short a_status;
5894         unsigned short b_status;
5895         unsigned long flags;
5896 #ifdef PCIDMA
5897         struct ni_private *devpriv = dev->private;
5898 #endif
5899
5900         if (!dev->attached)
5901                 return IRQ_NONE;
5902         smp_mb();               /* make sure dev->attached is checked */
5903
5904         /*  lock to avoid race with comedi_poll */
5905         spin_lock_irqsave(&dev->spinlock, flags);
5906         a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5907         b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5908 #ifdef PCIDMA
5909         if (devpriv->mite) {
5910                 unsigned long flags_too;
5911
5912                 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5913                 if (s_ai && devpriv->ai_mite_chan)
5914                         mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false);
5915                 if (s_ao && devpriv->ao_mite_chan)
5916                         mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false);
5917                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5918         }
5919 #endif
5920         ack_a_interrupt(dev, a_status);
5921         ack_b_interrupt(dev, b_status);
5922         if (s_ai) {
5923                 if (a_status & NISTC_AI_STATUS1_INTA)
5924                         handle_a_interrupt(dev, s_ai, a_status);
5925                 /* handle any interrupt or dma events */
5926                 comedi_handle_events(dev, s_ai);
5927         }
5928         if (s_ao) {
5929                 if (b_status & NISTC_AO_STATUS1_INTB)
5930                         handle_b_interrupt(dev, s_ao, b_status);
5931                 /* handle any interrupt or dma events */
5932                 comedi_handle_events(dev, s_ao);
5933         }
5934         handle_gpct_interrupt(dev, 0);
5935         handle_gpct_interrupt(dev, 1);
5936 #ifdef PCIDMA
5937         if (devpriv->is_m_series)
5938                 handle_cdio_interrupt(dev);
5939 #endif
5940
5941         spin_unlock_irqrestore(&dev->spinlock, flags);
5942         return IRQ_HANDLED;
5943 }
5944
5945 static int ni_alloc_private(struct comedi_device *dev)
5946 {
5947         struct ni_private *devpriv;
5948
5949         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5950         if (!devpriv)
5951                 return -ENOMEM;
5952
5953         spin_lock_init(&devpriv->window_lock);
5954         spin_lock_init(&devpriv->soft_reg_copy_lock);
5955         spin_lock_init(&devpriv->mite_channel_lock);
5956
5957         return 0;
5958 }
5959
5960 static unsigned int _ni_get_valid_routes(struct comedi_device *dev,
5961                                          unsigned int n_pairs,
5962                                          unsigned int *pair_data)
5963 {
5964         struct ni_private *devpriv = dev->private;
5965
5966         return ni_get_valid_routes(&devpriv->routing_tables, n_pairs,
5967                                    pair_data);
5968 }
5969
5970 static int ni_E_init(struct comedi_device *dev,
5971                      unsigned int interrupt_pin, unsigned int irq_polarity)
5972 {
5973         const struct ni_board_struct *board = dev->board_ptr;
5974         struct ni_private *devpriv = dev->private;
5975         struct comedi_subdevice *s;
5976         int ret;
5977         int i;
5978         const char *dev_family = devpriv->is_m_series ? "ni_mseries"
5979                                                       : "ni_eseries";
5980
5981         /* prepare the device for globally-named routes. */
5982         if (ni_assign_device_routes(dev_family, board->name,
5983                                     board->alt_route_name,
5984                                     &devpriv->routing_tables) < 0) {
5985                 dev_warn(dev->class_dev, "%s: %s device has no signal routing table.\n",
5986                          __func__, board->name);
5987                 dev_warn(dev->class_dev, "%s: High level NI signal names will not be available for this %s board.\n",
5988                          __func__, board->name);
5989         } else {
5990                 /*
5991                  * only(?) assign insn_device_config if we have global names for
5992                  * this device.
5993                  */
5994                 dev->insn_device_config = ni_global_insn_config;
5995                 dev->get_valid_routes = _ni_get_valid_routes;
5996         }
5997
5998         if (board->n_aochan > MAX_N_AO_CHAN) {
5999                 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
6000                 return -EINVAL;
6001         }
6002
6003         /* initialize clock dividers */
6004         devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
6005                                   NISTC_CLK_FOUT_SLOW_TIMEBASE |
6006                                   NISTC_CLK_FOUT_TO_BOARD_DIV2 |
6007                                   NISTC_CLK_FOUT_TO_BOARD;
6008         if (!devpriv->is_6xxx) {
6009                 /* BEAM is this needed for PCI-6143 ?? */
6010                 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
6011                                             NISTC_CLK_FOUT_AO_OUT_DIV2);
6012         }
6013         ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
6014
6015         ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
6016         if (ret)
6017                 return ret;
6018
6019         /* Analog Input subdevice */
6020         s = &dev->subdevices[NI_AI_SUBDEV];
6021         if (board->n_adchan) {
6022                 s->type         = COMEDI_SUBD_AI;
6023                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
6024                 if (!devpriv->is_611x)
6025                         s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
6026                 if (board->ai_maxdata > 0xffff)
6027                         s->subdev_flags |= SDF_LSAMPL;
6028                 if (devpriv->is_m_series)
6029                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
6030                 s->n_chan       = board->n_adchan;
6031                 s->maxdata      = board->ai_maxdata;
6032                 s->range_table  = ni_range_lkup[board->gainlkup];
6033                 s->insn_read    = ni_ai_insn_read;
6034                 s->insn_config  = ni_ai_insn_config;
6035                 if (dev->irq) {
6036                         dev->read_subdev = s;
6037                         s->subdev_flags |= SDF_CMD_READ;
6038                         s->len_chanlist = 512;
6039                         s->do_cmdtest   = ni_ai_cmdtest;
6040                         s->do_cmd       = ni_ai_cmd;
6041                         s->cancel       = ni_ai_reset;
6042                         s->poll         = ni_ai_poll;
6043                         s->munge        = ni_ai_munge;
6044
6045                         if (devpriv->mite)
6046                                 s->async_dma_dir = DMA_FROM_DEVICE;
6047                 }
6048
6049                 /* reset the analog input configuration */
6050                 ni_ai_reset(dev, s);
6051         } else {
6052                 s->type         = COMEDI_SUBD_UNUSED;
6053         }
6054
6055         /* Analog Output subdevice */
6056         s = &dev->subdevices[NI_AO_SUBDEV];
6057         if (board->n_aochan) {
6058                 s->type         = COMEDI_SUBD_AO;
6059                 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
6060                 if (devpriv->is_m_series)
6061                         s->subdev_flags |= SDF_SOFT_CALIBRATED;
6062                 s->n_chan       = board->n_aochan;
6063                 s->maxdata      = board->ao_maxdata;
6064                 s->range_table  = board->ao_range_table;
6065                 s->insn_config  = ni_ao_insn_config;
6066                 s->insn_write   = ni_ao_insn_write;
6067
6068                 ret = comedi_alloc_subdev_readback(s);
6069                 if (ret)
6070                         return ret;
6071
6072                 /*
6073                  * Along with the IRQ we need either a FIFO or DMA for
6074                  * async command support.
6075                  */
6076                 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
6077                         dev->write_subdev = s;
6078                         s->subdev_flags |= SDF_CMD_WRITE;
6079                         s->len_chanlist = s->n_chan;
6080                         s->do_cmdtest   = ni_ao_cmdtest;
6081                         s->do_cmd       = ni_ao_cmd;
6082                         s->cancel       = ni_ao_reset;
6083                         if (!devpriv->is_m_series)
6084                                 s->munge        = ni_ao_munge;
6085
6086                         if (devpriv->mite)
6087                                 s->async_dma_dir = DMA_TO_DEVICE;
6088                 }
6089
6090                 if (devpriv->is_67xx)
6091                         init_ao_67xx(dev, s);
6092
6093                 /* reset the analog output configuration */
6094                 ni_ao_reset(dev, s);
6095         } else {
6096                 s->type         = COMEDI_SUBD_UNUSED;
6097         }
6098
6099         /* Digital I/O subdevice */
6100         s = &dev->subdevices[NI_DIO_SUBDEV];
6101         s->type         = COMEDI_SUBD_DIO;
6102         s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
6103         s->n_chan       = board->has_32dio_chan ? 32 : 8;
6104         s->maxdata      = 1;
6105         s->range_table  = &range_digital;
6106         if (devpriv->is_m_series) {
6107 #ifdef PCIDMA
6108                 s->subdev_flags |= SDF_LSAMPL;
6109                 s->insn_bits    = ni_m_series_dio_insn_bits;
6110                 s->insn_config  = ni_m_series_dio_insn_config;
6111                 if (dev->irq) {
6112                         s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
6113                         s->len_chanlist = s->n_chan;
6114                         s->do_cmdtest   = ni_cdio_cmdtest;
6115                         s->do_cmd       = ni_cdio_cmd;
6116                         s->cancel       = ni_cdio_cancel;
6117
6118                         /* M-series boards use DMA */
6119                         s->async_dma_dir = DMA_BIDIRECTIONAL;
6120                 }
6121
6122                 /* reset DIO and set all channels to inputs */
6123                 ni_writel(dev, NI_M_CDO_CMD_RESET |
6124                                NI_M_CDI_CMD_RESET,
6125                           NI_M_CDIO_CMD_REG);
6126                 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
6127 #endif /* PCIDMA */
6128         } else {
6129                 s->insn_bits    = ni_dio_insn_bits;
6130                 s->insn_config  = ni_dio_insn_config;
6131
6132                 /* set all channels to inputs */
6133                 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
6134                 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
6135         }
6136
6137         /* 8255 device */
6138         s = &dev->subdevices[NI_8255_DIO_SUBDEV];
6139         if (board->has_8255) {
6140                 ret = subdev_8255_init(dev, s, ni_8255_callback,
6141                                        NI_E_8255_BASE);
6142                 if (ret)
6143                         return ret;
6144         } else {
6145                 s->type = COMEDI_SUBD_UNUSED;
6146         }
6147
6148         /* formerly general purpose counter/timer device, but no longer used */
6149         s = &dev->subdevices[NI_UNUSED_SUBDEV];
6150         s->type = COMEDI_SUBD_UNUSED;
6151
6152         /* Calibration subdevice */
6153         s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
6154         s->type         = COMEDI_SUBD_CALIB;
6155         s->subdev_flags = SDF_INTERNAL;
6156         s->n_chan       = 1;
6157         s->maxdata      = 0;
6158         if (devpriv->is_m_series) {
6159                 /* internal PWM output used for AI nonlinearity calibration */
6160                 s->insn_config  = ni_m_series_pwm_config;
6161
6162                 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
6163         } else if (devpriv->is_6143) {
6164                 /* internal PWM output used for AI nonlinearity calibration */
6165                 s->insn_config  = ni_6143_pwm_config;
6166         } else {
6167                 s->subdev_flags |= SDF_WRITABLE;
6168                 s->insn_read    = ni_calib_insn_read;
6169                 s->insn_write   = ni_calib_insn_write;
6170
6171                 /* setup the caldacs and find the real n_chan and maxdata */
6172                 caldac_setup(dev, s);
6173         }
6174
6175         /* EEPROM subdevice */
6176         s = &dev->subdevices[NI_EEPROM_SUBDEV];
6177         s->type         = COMEDI_SUBD_MEMORY;
6178         s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
6179         s->maxdata      = 0xff;
6180         if (devpriv->is_m_series) {
6181                 s->n_chan       = M_SERIES_EEPROM_SIZE;
6182                 s->insn_read    = ni_m_series_eeprom_insn_read;
6183         } else {
6184                 s->n_chan       = 512;
6185                 s->insn_read    = ni_eeprom_insn_read;
6186         }
6187
6188         /* Digital I/O (PFI) subdevice */
6189         s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
6190         s->type         = COMEDI_SUBD_DIO;
6191         s->maxdata      = 1;
6192         if (devpriv->is_m_series) {
6193                 s->n_chan       = 16;
6194                 s->insn_bits    = ni_pfi_insn_bits;
6195                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6196
6197                 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
6198                 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
6199                         ni_writew(dev, devpriv->pfi_output_select_reg[i],
6200                                   NI_M_PFI_OUT_SEL_REG(i));
6201                 }
6202         } else {
6203                 s->n_chan       = 10;
6204                 s->subdev_flags = SDF_INTERNAL;
6205         }
6206         s->insn_config  = ni_pfi_insn_config;
6207
6208         ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
6209
6210         /* cs5529 calibration adc */
6211         s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
6212         if (devpriv->is_67xx) {
6213                 s->type = COMEDI_SUBD_AI;
6214                 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
6215                 /*  one channel for each analog output channel */
6216                 s->n_chan = board->n_aochan;
6217                 s->maxdata = BIT(16) - 1;
6218                 s->range_table = &range_unknown;        /* XXX */
6219                 s->insn_read = cs5529_ai_insn_read;
6220                 s->insn_config = NULL;
6221                 init_cs5529(dev);
6222         } else {
6223                 s->type = COMEDI_SUBD_UNUSED;
6224         }
6225
6226         /* Serial */
6227         s = &dev->subdevices[NI_SERIAL_SUBDEV];
6228         s->type = COMEDI_SUBD_SERIAL;
6229         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6230         s->n_chan = 1;
6231         s->maxdata = 0xff;
6232         s->insn_config = ni_serial_insn_config;
6233         devpriv->serial_interval_ns = 0;
6234         devpriv->serial_hw_mode = 0;
6235
6236         /* RTSI */
6237         s = &dev->subdevices[NI_RTSI_SUBDEV];
6238         s->type = COMEDI_SUBD_DIO;
6239         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
6240         s->n_chan = 8;
6241         s->maxdata = 1;
6242         s->insn_bits = ni_rtsi_insn_bits;
6243         s->insn_config = ni_rtsi_insn_config;
6244         ni_rtsi_init(dev);
6245
6246         /* allocate and initialize the gpct counter device */
6247         devpriv->counter_dev = ni_gpct_device_construct(dev,
6248                                         ni_gpct_write_register,
6249                                         ni_gpct_read_register,
6250                                         (devpriv->is_m_series)
6251                                                 ? ni_gpct_variant_m_series
6252                                                 : ni_gpct_variant_e_series,
6253                                         NUM_GPCT,
6254                                         NUM_GPCT,
6255                                         &devpriv->routing_tables);
6256         if (!devpriv->counter_dev)
6257                 return -ENOMEM;
6258
6259         /* Counter (gpct) subdevices */
6260         for (i = 0; i < NUM_GPCT; ++i) {
6261                 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
6262
6263                 /* setup and initialize the counter */
6264                 ni_tio_init_counter(gpct);
6265
6266                 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
6267                 s->type         = COMEDI_SUBD_COUNTER;
6268                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
6269                 s->n_chan       = 3;
6270                 s->maxdata      = (devpriv->is_m_series) ? 0xffffffff
6271                                                          : 0x00ffffff;
6272                 s->insn_read    = ni_tio_insn_read;
6273                 s->insn_write   = ni_tio_insn_write;
6274                 s->insn_config  = ni_tio_insn_config;
6275 #ifdef PCIDMA
6276                 if (dev->irq && devpriv->mite) {
6277                         s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
6278                         s->len_chanlist = 1;
6279                         s->do_cmdtest   = ni_tio_cmdtest;
6280                         s->do_cmd       = ni_gpct_cmd;
6281                         s->cancel       = ni_gpct_cancel;
6282
6283                         s->async_dma_dir = DMA_BIDIRECTIONAL;
6284                 }
6285 #endif
6286                 s->private      = gpct;
6287         }
6288
6289         /* Initialize GPFO_{0,1} to produce output of counters */
6290         ni_set_gout_routing(0, 0, dev); /* output of counter 0; DAQ STC, p338 */
6291         ni_set_gout_routing(0, 1, dev); /* output of counter 1; DAQ STC, p338 */
6292
6293         /* Frequency output subdevice */
6294         s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
6295         s->type         = COMEDI_SUBD_COUNTER;
6296         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
6297         s->n_chan       = 1;
6298         s->maxdata      = 0xf;
6299         s->insn_read    = ni_freq_out_insn_read;
6300         s->insn_write   = ni_freq_out_insn_write;
6301         s->insn_config  = ni_freq_out_insn_config;
6302
6303         if (dev->irq) {
6304                 ni_stc_writew(dev,
6305                               (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
6306                               (NISTC_INT_CTRL_3PIN_INT & 0) |
6307                               NISTC_INT_CTRL_INTA_ENA |
6308                               NISTC_INT_CTRL_INTB_ENA |
6309                               NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
6310                               NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
6311                               NISTC_INT_CTRL_REG);
6312         }
6313
6314         /* DMA setup */
6315         ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
6316         ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
6317
6318         if (devpriv->is_6xxx) {
6319                 ni_writeb(dev, 0, NI611X_MAGIC_REG);
6320         } else if (devpriv->is_m_series) {
6321                 int channel;
6322
6323                 for (channel = 0; channel < board->n_aochan; ++channel) {
6324                         ni_writeb(dev, 0xf,
6325                                   NI_M_AO_WAVEFORM_ORDER_REG(channel));
6326                         ni_writeb(dev, 0x0,
6327                                   NI_M_AO_REF_ATTENUATION_REG(channel));
6328                 }
6329                 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
6330         }
6331
6332         return 0;
6333 }
6334
6335 static void mio_common_detach(struct comedi_device *dev)
6336 {
6337         struct ni_private *devpriv = dev->private;
6338
6339         if (devpriv)
6340                 ni_gpct_device_destroy(devpriv->counter_dev);
6341 }