1 // SPDX-License-Identifier: GPL-2.0+
3 * comedi/drivers/me_daq.c
4 * Hardware driver for Meilhaus data acquisition cards:
5 * ME-2000i, ME-2600i, ME-3000vm1
7 * Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
12 * Description: Meilhaus PCI data acquisition cards
13 * Devices: [Meilhaus] ME-2600i (me-2600i), ME-2000i (me-2000i)
14 * Author: Michael Hillmann <hillmann@syscongroup.de>
15 * Status: experimental
17 * Configuration options: not applicable, uses PCI auto config
20 * Analog Input, Analog Output, Digital I/O
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
27 #include "../comedi_pci.h"
31 #define ME2600_FIRMWARE "me2600_firmware.bin"
33 #define XILINX_DOWNLOAD_RESET 0x42 /* Xilinx registers */
36 * PCI BAR2 Memory map (dev->mmio)
38 #define ME_CTRL1_REG 0x00 /* R (ai start) | W */
39 #define ME_CTRL1_INT_ENA BIT(15)
40 #define ME_CTRL1_COUNTER_B_IRQ BIT(12)
41 #define ME_CTRL1_COUNTER_A_IRQ BIT(11)
42 #define ME_CTRL1_CHANLIST_READY_IRQ BIT(10)
43 #define ME_CTRL1_EXT_IRQ BIT(9)
44 #define ME_CTRL1_ADFIFO_HALFFULL_IRQ BIT(8)
45 #define ME_CTRL1_SCAN_COUNT_ENA BIT(5)
46 #define ME_CTRL1_SIMULTANEOUS_ENA BIT(4)
47 #define ME_CTRL1_TRIGGER_FALLING_EDGE BIT(3)
48 #define ME_CTRL1_CONTINUOUS_MODE BIT(2)
49 #define ME_CTRL1_ADC_MODE(x) (((x) & 0x3) << 0)
50 #define ME_CTRL1_ADC_MODE_DISABLE ME_CTRL1_ADC_MODE(0)
51 #define ME_CTRL1_ADC_MODE_SOFT_TRIG ME_CTRL1_ADC_MODE(1)
52 #define ME_CTRL1_ADC_MODE_SCAN_TRIG ME_CTRL1_ADC_MODE(2)
53 #define ME_CTRL1_ADC_MODE_EXT_TRIG ME_CTRL1_ADC_MODE(3)
54 #define ME_CTRL1_ADC_MODE_MASK ME_CTRL1_ADC_MODE(3)
55 #define ME_CTRL2_REG 0x02 /* R (dac update) | W */
56 #define ME_CTRL2_ADFIFO_ENA BIT(10)
57 #define ME_CTRL2_CHANLIST_ENA BIT(9)
58 #define ME_CTRL2_PORT_B_ENA BIT(7)
59 #define ME_CTRL2_PORT_A_ENA BIT(6)
60 #define ME_CTRL2_COUNTER_B_ENA BIT(4)
61 #define ME_CTRL2_COUNTER_A_ENA BIT(3)
62 #define ME_CTRL2_DAC_ENA BIT(1)
63 #define ME_CTRL2_BUFFERED_DAC BIT(0)
64 #define ME_STATUS_REG 0x04 /* R | W (clears interrupts) */
65 #define ME_STATUS_COUNTER_B_IRQ BIT(12)
66 #define ME_STATUS_COUNTER_A_IRQ BIT(11)
67 #define ME_STATUS_CHANLIST_READY_IRQ BIT(10)
68 #define ME_STATUS_EXT_IRQ BIT(9)
69 #define ME_STATUS_ADFIFO_HALFFULL_IRQ BIT(8)
70 #define ME_STATUS_ADFIFO_FULL BIT(4)
71 #define ME_STATUS_ADFIFO_HALFFULL BIT(3)
72 #define ME_STATUS_ADFIFO_EMPTY BIT(2)
73 #define ME_STATUS_CHANLIST_FULL BIT(1)
74 #define ME_STATUS_FST_ACTIVE BIT(0)
75 #define ME_DIO_PORT_A_REG 0x06 /* R | W */
76 #define ME_DIO_PORT_B_REG 0x08 /* R | W */
77 #define ME_TIMER_DATA_REG(x) (0x0a + ((x) * 2)) /* - | W */
78 #define ME_AI_FIFO_REG 0x10 /* R (fifo) | W (chanlist) */
79 #define ME_AI_FIFO_CHANLIST_DIFF BIT(7)
80 #define ME_AI_FIFO_CHANLIST_UNIPOLAR BIT(6)
81 #define ME_AI_FIFO_CHANLIST_GAIN(x) (((x) & 0x3) << 4)
82 #define ME_AI_FIFO_CHANLIST_CHAN(x) (((x) & 0xf) << 0)
83 #define ME_DAC_CTRL_REG 0x12 /* R (updates) | W */
84 #define ME_DAC_CTRL_BIPOLAR(x) BIT(7 - ((x) & 0x3))
85 #define ME_DAC_CTRL_GAIN(x) BIT(11 - ((x) & 0x3))
86 #define ME_DAC_CTRL_MASK(x) (ME_DAC_CTRL_BIPOLAR(x) | \
88 #define ME_AO_DATA_REG(x) (0x14 + ((x) * 2)) /* - | W */
89 #define ME_COUNTER_ENDDATA_REG(x) (0x1c + ((x) * 2)) /* - | W */
90 #define ME_COUNTER_STARTDATA_REG(x) (0x20 + ((x) * 2)) /* - | W */
91 #define ME_COUNTER_VALUE_REG(x) (0x20 + ((x) * 2)) /* R | - */
93 static const struct comedi_lrange me_ai_range = {
106 static const struct comedi_lrange me_ao_range = {
125 static const struct me_board me_boards[] = {
136 struct me_private_data {
137 void __iomem *plx_regbase; /* PLX configuration base address */
139 unsigned short ctrl1; /* Mirror of CONTROL_1 register */
140 unsigned short ctrl2; /* Mirror of CONTROL_2 register */
141 unsigned short dac_ctrl; /* Mirror of the DAC_CONTROL register */
144 static inline void sleep(unsigned int sec)
146 schedule_timeout_interruptible(sec * HZ);
149 static int me_dio_insn_config(struct comedi_device *dev,
150 struct comedi_subdevice *s,
151 struct comedi_insn *insn,
154 struct me_private_data *devpriv = dev->private;
155 unsigned int chan = CR_CHAN(insn->chanspec);
164 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
168 if (s->io_bits & 0x0000ffff)
169 devpriv->ctrl2 |= ME_CTRL2_PORT_A_ENA;
171 devpriv->ctrl2 &= ~ME_CTRL2_PORT_A_ENA;
172 if (s->io_bits & 0xffff0000)
173 devpriv->ctrl2 |= ME_CTRL2_PORT_B_ENA;
175 devpriv->ctrl2 &= ~ME_CTRL2_PORT_B_ENA;
177 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
182 static int me_dio_insn_bits(struct comedi_device *dev,
183 struct comedi_subdevice *s,
184 struct comedi_insn *insn,
187 void __iomem *mmio_porta = dev->mmio + ME_DIO_PORT_A_REG;
188 void __iomem *mmio_portb = dev->mmio + ME_DIO_PORT_B_REG;
192 mask = comedi_dio_update_state(s, data);
194 if (mask & 0x0000ffff)
195 writew((s->state & 0xffff), mmio_porta);
196 if (mask & 0xffff0000)
197 writew(((s->state >> 16) & 0xffff), mmio_portb);
200 if (s->io_bits & 0x0000ffff)
201 val = s->state & 0xffff;
203 val = readw(mmio_porta);
205 if (s->io_bits & 0xffff0000)
206 val |= (s->state & 0xffff0000);
208 val |= (readw(mmio_portb) << 16);
215 static int me_ai_eoc(struct comedi_device *dev,
216 struct comedi_subdevice *s,
217 struct comedi_insn *insn,
218 unsigned long context)
222 status = readw(dev->mmio + ME_STATUS_REG);
223 if ((status & ME_STATUS_ADFIFO_EMPTY) == 0)
228 static int me_ai_insn_read(struct comedi_device *dev,
229 struct comedi_subdevice *s,
230 struct comedi_insn *insn,
233 struct me_private_data *devpriv = dev->private;
234 unsigned int chan = CR_CHAN(insn->chanspec);
235 unsigned int range = CR_RANGE(insn->chanspec);
236 unsigned int aref = CR_AREF(insn->chanspec);
242 * For differential operation, there are only 8 input channels
243 * and only bipolar ranges are available.
245 if (aref & AREF_DIFF) {
246 if (chan > 7 || comedi_range_is_unipolar(s, range))
250 /* clear chanlist and ad fifo */
251 devpriv->ctrl2 &= ~(ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA);
252 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
254 writew(0x00, dev->mmio + ME_STATUS_REG); /* clear interrupts */
256 /* enable the chanlist and ADC fifo */
257 devpriv->ctrl2 |= (ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA);
258 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
260 /* write to channel list fifo */
261 val = ME_AI_FIFO_CHANLIST_CHAN(chan) | ME_AI_FIFO_CHANLIST_GAIN(range);
262 if (comedi_range_is_unipolar(s, range))
263 val |= ME_AI_FIFO_CHANLIST_UNIPOLAR;
264 if (aref & AREF_DIFF)
265 val |= ME_AI_FIFO_CHANLIST_DIFF;
266 writew(val, dev->mmio + ME_AI_FIFO_REG);
268 /* set ADC mode to software trigger */
269 devpriv->ctrl1 |= ME_CTRL1_ADC_MODE_SOFT_TRIG;
270 writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG);
272 for (i = 0; i < insn->n; i++) {
273 /* start ai conversion */
274 readw(dev->mmio + ME_CTRL1_REG);
276 /* wait for ADC fifo not empty flag */
277 ret = comedi_timeout(dev, s, insn, me_ai_eoc, 0);
281 /* get value from ADC fifo */
282 val = readw(dev->mmio + ME_AI_FIFO_REG) & s->maxdata;
284 /* munge 2's complement value to offset binary */
285 data[i] = comedi_offset_munge(s, val);
288 /* stop any running conversion */
289 devpriv->ctrl1 &= ~ME_CTRL1_ADC_MODE_MASK;
290 writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG);
292 return ret ? ret : insn->n;
295 static int me_ao_insn_write(struct comedi_device *dev,
296 struct comedi_subdevice *s,
297 struct comedi_insn *insn,
300 struct me_private_data *devpriv = dev->private;
301 unsigned int chan = CR_CHAN(insn->chanspec);
302 unsigned int range = CR_RANGE(insn->chanspec);
303 unsigned int val = s->readback[chan];
307 devpriv->ctrl2 |= ME_CTRL2_DAC_ENA;
308 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
310 /* and set DAC to "buffered" mode */
311 devpriv->ctrl2 |= ME_CTRL2_BUFFERED_DAC;
312 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG);
314 /* Set dac-control register */
315 devpriv->dac_ctrl &= ~ME_DAC_CTRL_MASK(chan);
317 devpriv->dac_ctrl |= ME_DAC_CTRL_GAIN(chan);
318 if (comedi_range_is_bipolar(s, range))
319 devpriv->dac_ctrl |= ME_DAC_CTRL_BIPOLAR(chan);
320 writew(devpriv->dac_ctrl, dev->mmio + ME_DAC_CTRL_REG);
322 /* Update dac-control register */
323 readw(dev->mmio + ME_DAC_CTRL_REG);
325 /* Set data register */
326 for (i = 0; i < insn->n; i++) {
329 writew(val, dev->mmio + ME_AO_DATA_REG(chan));
331 s->readback[chan] = val;
333 /* Update dac with data registers */
334 readw(dev->mmio + ME_CTRL2_REG);
339 static int me2600_xilinx_download(struct comedi_device *dev,
340 const u8 *data, size_t size,
341 unsigned long context)
343 struct me_private_data *devpriv = dev->private;
345 unsigned int file_length;
348 /* disable irq's on PLX */
349 writel(0x00, devpriv->plx_regbase + PLX9052_INTCSR);
351 /* First, make a dummy read to reset xilinx */
352 value = readw(dev->mmio + XILINX_DOWNLOAD_RESET);
354 /* Wait until reset is over */
357 /* Write a dummy value to Xilinx */
358 writeb(0x00, dev->mmio + 0x0);
362 * Format of the firmware
363 * Build longs from the byte-wise coded header
364 * Byte 1-3: length of the array
367 * Byte 12-15: reserved
372 file_length = (((unsigned int)data[0] & 0xff) << 24) +
373 (((unsigned int)data[1] & 0xff) << 16) +
374 (((unsigned int)data[2] & 0xff) << 8) +
375 ((unsigned int)data[3] & 0xff);
378 * Loop for writing firmware byte by byte to xilinx
379 * Firmware data start at offset 16
381 for (i = 0; i < file_length; i++)
382 writeb((data[16 + i] & 0xff), dev->mmio + 0x0);
384 /* Write 5 dummy values to xilinx */
385 for (i = 0; i < 5; i++)
386 writeb(0x00, dev->mmio + 0x0);
388 /* Test if there was an error during download -> INTB was thrown */
389 value = readl(devpriv->plx_regbase + PLX9052_INTCSR);
390 if (value & PLX9052_INTCSR_LI2STAT) {
391 /* Disable interrupt */
392 writel(0x00, devpriv->plx_regbase + PLX9052_INTCSR);
393 dev_err(dev->class_dev, "Xilinx download failed\n");
397 /* Wait until the Xilinx is ready for real work */
400 /* Enable PLX-Interrupts */
401 writel(PLX9052_INTCSR_LI1ENAB |
402 PLX9052_INTCSR_LI1POL |
403 PLX9052_INTCSR_PCIENAB,
404 devpriv->plx_regbase + PLX9052_INTCSR);
409 static int me_reset(struct comedi_device *dev)
411 struct me_private_data *devpriv = dev->private;
414 writew(0x00, dev->mmio + ME_CTRL1_REG);
415 writew(0x00, dev->mmio + ME_CTRL2_REG);
416 writew(0x00, dev->mmio + ME_STATUS_REG); /* clear interrupts */
417 writew(0x00, dev->mmio + ME_DAC_CTRL_REG);
419 /* Save values in the board context */
420 devpriv->dac_ctrl = 0;
427 static int me_auto_attach(struct comedi_device *dev,
428 unsigned long context)
430 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
431 const struct me_board *board = NULL;
432 struct me_private_data *devpriv;
433 struct comedi_subdevice *s;
436 if (context < ARRAY_SIZE(me_boards))
437 board = &me_boards[context];
440 dev->board_ptr = board;
441 dev->board_name = board->name;
443 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
447 ret = comedi_pci_enable(dev);
451 devpriv->plx_regbase = pci_ioremap_bar(pcidev, 0);
452 if (!devpriv->plx_regbase)
455 dev->mmio = pci_ioremap_bar(pcidev, 2);
459 /* Download firmware and reset card */
460 if (board->needs_firmware) {
461 ret = comedi_load_firmware(dev, &comedi_to_pci_dev(dev)->dev,
463 me2600_xilinx_download, 0);
469 ret = comedi_alloc_subdevices(dev, 3);
473 s = &dev->subdevices[0];
474 s->type = COMEDI_SUBD_AI;
475 s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_DIFF;
478 s->len_chanlist = 16;
479 s->range_table = &me_ai_range;
480 s->insn_read = me_ai_insn_read;
482 s = &dev->subdevices[1];
484 s->type = COMEDI_SUBD_AO;
485 s->subdev_flags = SDF_WRITABLE | SDF_COMMON;
489 s->range_table = &me_ao_range;
490 s->insn_write = me_ao_insn_write;
492 ret = comedi_alloc_subdev_readback(s);
496 s->type = COMEDI_SUBD_UNUSED;
499 s = &dev->subdevices[2];
500 s->type = COMEDI_SUBD_DIO;
501 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
504 s->len_chanlist = 32;
505 s->range_table = &range_digital;
506 s->insn_bits = me_dio_insn_bits;
507 s->insn_config = me_dio_insn_config;
512 static void me_detach(struct comedi_device *dev)
514 struct me_private_data *devpriv = dev->private;
519 if (devpriv->plx_regbase)
520 iounmap(devpriv->plx_regbase);
522 comedi_pci_detach(dev);
525 static struct comedi_driver me_daq_driver = {
526 .driver_name = "me_daq",
527 .module = THIS_MODULE,
528 .auto_attach = me_auto_attach,
532 static int me_daq_pci_probe(struct pci_dev *dev,
533 const struct pci_device_id *id)
535 return comedi_pci_auto_config(dev, &me_daq_driver, id->driver_data);
538 static const struct pci_device_id me_daq_pci_table[] = {
539 { PCI_VDEVICE(MEILHAUS, 0x2600), BOARD_ME2600 },
540 { PCI_VDEVICE(MEILHAUS, 0x2000), BOARD_ME2000 },
543 MODULE_DEVICE_TABLE(pci, me_daq_pci_table);
545 static struct pci_driver me_daq_pci_driver = {
547 .id_table = me_daq_pci_table,
548 .probe = me_daq_pci_probe,
549 .remove = comedi_pci_auto_unconfig,
551 module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver);
553 MODULE_AUTHOR("Comedi https://www.comedi.org");
554 MODULE_DESCRIPTION("Comedi low-level driver");
555 MODULE_LICENSE("GPL");
556 MODULE_FIRMWARE(ME2600_FIRMWARE);