drivers/clocksource/timer-ti-dm-systimer.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 #include <linux/clk.h>
   3 #include <linux/clocksource.h>
   4 #include <linux/clockchips.h>
   5 #include <linux/interrupt.h>
   6 #include <linux/io.h>
   7 #include <linux/iopoll.h>
   8 #include <linux/err.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_irq.h>
  12 #include <linux/sched_clock.h>
  13
  14 #include <linux/clk/clk-conf.h>
  15
  16 #include <clocksource/timer-ti-dm.h>
  17 #include <dt-bindings/bus/ti-sysc.h>
  18
  19 /* For type1, set SYSC_OMAP2_CLOCKACTIVITY for fck off on idle, l4 clock on */
  20 #define DMTIMER_TYPE1_ENABLE    ((1 << 9) | (SYSC_IDLE_SMART << 3) | \
  21                                  SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_AUTOIDLE)
  22
  23 #define DMTIMER_TYPE2_ENABLE    (SYSC_IDLE_SMART_WKUP << 2)
  24 #define DMTIMER_RESET_WAIT      100000
  25
  26 #define DMTIMER_INST_DONT_CARE  ~0U
  27
  28 static int counter_32k;
  29 static u32 clocksource;
  30 static u32 clockevent;
  31
  32 /*
  33  * Subset of the timer registers we use. Note that the register offsets
  34  * depend on the timer revision detected.
  35  */
  36 struct dmtimer_systimer {
  37         void __iomem *base;
  38         u8 sysc;
  39         u8 irq_stat;
  40         u8 irq_ena;
  41         u8 pend;
  42         u8 load;
  43         u8 counter;
  44         u8 ctrl;
  45         u8 wakeup;
  46         u8 ifctrl;
  47         unsigned long rate;
  48 };
  49
  50 struct dmtimer_clockevent {
  51         struct clock_event_device dev;
  52         struct dmtimer_systimer t;
  53         u32 period;
  54 };
  55
  56 struct dmtimer_clocksource {
  57         struct clocksource dev;
  58         struct dmtimer_systimer t;
  59         unsigned int loadval;
  60 };
  61
  62 /* Assumes v1 ip if bits [31:16] are zero */
  63 static bool dmtimer_systimer_revision1(struct dmtimer_systimer *t)
  64 {
  65         u32 tidr = readl_relaxed(t->base);
  66
  67         return !(tidr >> 16);
  68 }
  69
  70 static int __init dmtimer_systimer_type1_reset(struct dmtimer_systimer *t)
  71 {
  72         void __iomem *syss = t->base + OMAP_TIMER_V1_SYS_STAT_OFFSET;
  73         int ret;
  74         u32 l;
  75
  76         writel_relaxed(BIT(1) | BIT(2), t->base + t->ifctrl);
  77         ret = readl_poll_timeout_atomic(syss, l, l & BIT(0), 100,
  78                                         DMTIMER_RESET_WAIT);
  79
  80         return ret;
  81 }
  82
  83 /* Note we must use io_base instead of func_base for type2 OCP regs */
  84 static int __init dmtimer_systimer_type2_reset(struct dmtimer_systimer *t)
  85 {
  86         void __iomem *sysc = t->base + t->sysc;
  87         u32 l;
  88
  89         l = readl_relaxed(sysc);
  90         l |= BIT(0);
  91         writel_relaxed(l, sysc);
  92
  93         return readl_poll_timeout_atomic(sysc, l, !(l & BIT(0)), 100,
  94                                          DMTIMER_RESET_WAIT);
  95 }
  96
  97 static int __init dmtimer_systimer_reset(struct dmtimer_systimer *t)
  98 {
  99         int ret;
 100
 101         if (dmtimer_systimer_revision1(t))
 102                 ret = dmtimer_systimer_type1_reset(t);
 103         else
 104                 ret = dmtimer_systimer_type2_reset(t);
 105         if (ret < 0) {
 106                 pr_err("%s failed with %i\n", __func__, ret);
 107
 108                 return ret;
 109         }
 110
 111         return 0;
 112 }
 113
 114 static const struct of_device_id counter_match_table[] = {
 115         { .compatible = "ti,omap-counter32k" },
 116         { /* Sentinel */ },
 117 };
 118
 119 /*
 120  * Check if the SoC als has a usable working 32 KiHz counter. The 32 KiHz
 121  * counter is handled by timer-ti-32k, but we need to detect it as it
 122  * affects the preferred dmtimer system timer configuration. There is
 123  * typically no use for a dmtimer clocksource if the 32 KiHz counter is
 124  * present, except on am437x as described below.
 125  */
 126 static void __init dmtimer_systimer_check_counter32k(void)
 127 {
 128         struct device_node *np;
 129
 130         if (counter_32k)
 131                 return;
 132
 133         np = of_find_matching_node(NULL, counter_match_table);
 134         if (!np) {
 135                 counter_32k = -ENODEV;
 136
 137                 return;
 138         }
 139
 140         if (of_device_is_available(np))
 141                 counter_32k = 1;
 142         else
 143                 counter_32k = -ENODEV;
 144
 145         of_node_put(np);
 146 }
 147
 148 static const struct of_device_id dmtimer_match_table[] = {
 149         { .compatible = "ti,omap2420-timer", },
 150         { .compatible = "ti,omap3430-timer", },
 151         { .compatible = "ti,omap4430-timer", },
 152         { .compatible = "ti,omap5430-timer", },
 153         { .compatible = "ti,am335x-timer", },
 154         { .compatible = "ti,am335x-timer-1ms", },
 155         { .compatible = "ti,dm814-timer", },
 156         { .compatible = "ti,dm816-timer", },
 157         { /* Sentinel */ },
 158 };
 159
 160 /*
 161  * Checks that system timers are configured to not reset and idle during
 162  * the generic timer-ti-dm device driver probe. And that the system timer
 163  * source clocks are properly configured. Also, let's not hog any DSP and
 164  * PWM capable timers unnecessarily as system timers.
 165  */
 166 static bool __init dmtimer_is_preferred(struct device_node *np)
 167 {
 168         if (!of_device_is_available(np))
 169                 return false;
 170
 171         if (!of_property_read_bool(np->parent,
 172                                    "ti,no-reset-on-init"))
 173                 return false;
 174
 175         if (!of_property_read_bool(np->parent, "ti,no-idle"))
 176                 return false;
 177
 178         /* Secure gptimer12 is always clocked with a fixed source */
 179         if (!of_property_read_bool(np, "ti,timer-secure")) {
 180                 if (!of_property_read_bool(np, "assigned-clocks"))
 181                         return false;
 182
 183                 if (!of_property_read_bool(np, "assigned-clock-parents"))
 184                         return false;
 185         }
 186
 187         if (of_property_read_bool(np, "ti,timer-dsp"))
 188                 return false;
 189
 190         if (of_property_read_bool(np, "ti,timer-pwm"))
 191                 return false;
 192
 193         return true;
 194 }
 195
 196 /*
 197  * Finds the first available usable always-on timer, and assigns it to either
 198  * clockevent or clocksource depending if the counter_32k is available on the
 199  * SoC or not.
 200  *
 201  * Some omap3 boards with unreliable oscillator must not use the counter_32k
 202  * or dmtimer1 with 32 KiHz source. Additionally, the boards with unreliable
 203  * oscillator should really set counter_32k as disabled, and delete dmtimer1
 204  * ti,always-on property, but let's not count on it. For these quirky cases,
 205  * we prefer using the always-on secure dmtimer12 with the internal 32 KiHz
 206  * clock as the clocksource, and any available dmtimer as clockevent.
 207  *
 208  * For am437x, we are using am335x style dmtimer clocksource. It is unclear
 209  * if this quirk handling is really needed, but let's change it separately
 210  * based on testing as it might cause side effects.
 211  */
 212 static void __init dmtimer_systimer_assign_alwon(void)
 213 {
 214         struct device_node *np;
 215         u32 pa = 0;
 216         bool quirk_unreliable_oscillator = false;
 217
 218         /* Quirk unreliable 32 KiHz oscillator with incomplete dts */
 219         if (of_machine_is_compatible("ti,omap3-beagle") ||
 220             of_machine_is_compatible("timll,omap3-devkit8000")) {
 221                 quirk_unreliable_oscillator = true;
 222                 counter_32k = -ENODEV;
 223         }
 224
 225         /* Quirk am437x using am335x style dmtimer clocksource */
 226         if (of_machine_is_compatible("ti,am43"))
 227                 counter_32k = -ENODEV;
 228
 229         for_each_matching_node(np, dmtimer_match_table) {
 230                 if (!dmtimer_is_preferred(np))
 231                         continue;
 232
 233                 if (of_property_read_bool(np, "ti,timer-alwon")) {
 234                         const __be32 *addr;
 235
 236                         addr = of_get_address(np, 0, NULL, NULL);
 237                         pa = of_translate_address(np, addr);
 238                         if (pa) {
 239                                 /* Quirky omap3 boards must use dmtimer12 */
 240                                 if (quirk_unreliable_oscillator &&
 241                                     pa == 0x48318000)
 242                                         continue;
 243
 244                                 of_node_put(np);
 245                                 break;
 246                         }
 247                 }
 248         }
 249
 250         /* Usually no need for dmtimer clocksource if we have counter32 */
 251         if (counter_32k >= 0) {
 252                 clockevent = pa;
 253                 clocksource = 0;
 254         } else {
 255                 clocksource = pa;
 256                 clockevent = DMTIMER_INST_DONT_CARE;
 257         }
 258 }
 259
 260 /* Finds the first usable dmtimer, used for the don't care case */
 261 static u32 __init dmtimer_systimer_find_first_available(void)
 262 {
 263         struct device_node *np;
 264         const __be32 *addr;
 265         u32 pa = 0;
 266
 267         for_each_matching_node(np, dmtimer_match_table) {
 268                 if (!dmtimer_is_preferred(np))
 269                         continue;
 270
 271                 addr = of_get_address(np, 0, NULL, NULL);
 272                 pa = of_translate_address(np, addr);
 273                 if (pa) {
 274                         if (pa == clocksource || pa == clockevent) {
 275                                 pa = 0;
 276                                 continue;
 277                         }
 278
 279                         of_node_put(np);
 280                         break;
 281                 }
 282         }
 283
 284         return pa;
 285 }
 286
 287 /* Selects the best clocksource and clockevent to use */
 288 static void __init dmtimer_systimer_select_best(void)
 289 {
 290         dmtimer_systimer_check_counter32k();
 291         dmtimer_systimer_assign_alwon();
 292
 293         if (clockevent == DMTIMER_INST_DONT_CARE)
 294                 clockevent = dmtimer_systimer_find_first_available();
 295
 296         pr_debug("%s: counter_32k: %i clocksource: %08x clockevent: %08x\n",
 297                  __func__, counter_32k, clocksource, clockevent);
 298 }
 299
 300 /* Interface clocks are only available on some SoCs variants */
 301 static int __init dmtimer_systimer_init_clock(struct device_node *np,
 302                                               const char *name,
 303                                               unsigned long *rate)
 304 {
 305         struct clk *clock;
 306         unsigned long r;
 307         int error;
 308
 309         clock = of_clk_get_by_name(np, name);
 310         if ((PTR_ERR(clock) == -EINVAL) && !strncmp(name, "ick", 3))
 311                 return 0;
 312         else if (IS_ERR(clock))
 313                 return PTR_ERR(clock);
 314
 315         error = clk_prepare_enable(clock);
 316         if (error)
 317                 return error;
 318
 319         r = clk_get_rate(clock);
 320         if (!r)
 321                 return -ENODEV;
 322
 323         *rate = r;
 324
 325         return 0;
 326 }
 327
 328 static void dmtimer_systimer_enable(struct dmtimer_systimer *t)
 329 {
 330         u32 val;
 331
 332         if (dmtimer_systimer_revision1(t))
 333                 val = DMTIMER_TYPE1_ENABLE;
 334         else
 335                 val = DMTIMER_TYPE2_ENABLE;
 336
 337         writel_relaxed(val, t->base + t->sysc);
 338 }
 339
 340 static void dmtimer_systimer_disable(struct dmtimer_systimer *t)
 341 {
 342         writel_relaxed(0, t->base + t->sysc);
 343 }
 344
 345 static int __init dmtimer_systimer_setup(struct device_node *np,
 346                                          struct dmtimer_systimer *t)
 347 {
 348         unsigned long rate;
 349         u8 regbase;
 350         int error;
 351
 352         if (!of_device_is_compatible(np->parent, "ti,sysc"))
 353                 return -EINVAL;
 354
 355         t->base = of_iomap(np, 0);
 356         if (!t->base)
 357                 return -ENXIO;
 358
 359         /*
 360          * Enable optional assigned-clock-parents configured at the timer
 361          * node level. For regular device drivers, this is done automatically
 362          * by bus related code such as platform_drv_probe().
 363          */
 364         error = of_clk_set_defaults(np, false);
 365         if (error < 0)
 366                 pr_err("%s: clock source init failed: %i\n", __func__, error);
 367
 368         /* For ti-sysc, we have timer clocks at the parent module level */
 369         error = dmtimer_systimer_init_clock(np->parent, "fck", &rate);
 370         if (error)
 371                 goto err_unmap;
 372
 373         t->rate = rate;
 374
 375         error = dmtimer_systimer_init_clock(np->parent, "ick", &rate);
 376         if (error)
 377                 goto err_unmap;
 378
 379         if (dmtimer_systimer_revision1(t)) {
 380                 t->irq_stat = OMAP_TIMER_V1_STAT_OFFSET;
 381                 t->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET;
 382                 t->pend = _OMAP_TIMER_WRITE_PEND_OFFSET;
 383                 regbase = 0;
 384         } else {
 385                 t->irq_stat = OMAP_TIMER_V2_IRQSTATUS;
 386                 t->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET;
 387                 regbase = OMAP_TIMER_V2_FUNC_OFFSET;
 388                 t->pend = regbase + _OMAP_TIMER_WRITE_PEND_OFFSET;
 389         }
 390
 391         t->sysc = OMAP_TIMER_OCP_CFG_OFFSET;
 392         t->load = regbase + _OMAP_TIMER_LOAD_OFFSET;
 393         t->counter = regbase + _OMAP_TIMER_COUNTER_OFFSET;
 394         t->ctrl = regbase + _OMAP_TIMER_CTRL_OFFSET;
 395         t->wakeup = regbase + _OMAP_TIMER_WAKEUP_EN_OFFSET;
 396         t->ifctrl = regbase + _OMAP_TIMER_IF_CTRL_OFFSET;
 397
 398         dmtimer_systimer_enable(t);
 399         dmtimer_systimer_reset(t);
 400         pr_debug("dmtimer rev %08x sysc %08x\n", readl_relaxed(t->base),
 401                  readl_relaxed(t->base + t->sysc));
 402
 403         return 0;
 404
 405 err_unmap:
 406         iounmap(t->base);
 407
 408         return error;
 409 }
 410
 411 /* Clockevent */
 412 static struct dmtimer_clockevent *
 413 to_dmtimer_clockevent(struct clock_event_device *clockevent)
 414 {
 415         return container_of(clockevent, struct dmtimer_clockevent, dev);
 416 }
 417
 418 static irqreturn_t dmtimer_clockevent_interrupt(int irq, void *data)
 419 {
 420         struct dmtimer_clockevent *clkevt = data;
 421         struct dmtimer_systimer *t = &clkevt->t;
 422
 423         writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
 424         clkevt->dev.event_handler(&clkevt->dev);
 425
 426         return IRQ_HANDLED;
 427 }
 428
 429 static int dmtimer_set_next_event(unsigned long cycles,
 430                                   struct clock_event_device *evt)
 431 {
 432         struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
 433         struct dmtimer_systimer *t = &clkevt->t;
 434         void __iomem *pend = t->base + t->pend;
 435
 436         writel_relaxed(0xffffffff - cycles, t->base + t->counter);
 437         while (readl_relaxed(pend) & WP_TCRR)
 438                 cpu_relax();
 439
 440         writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl);
 441         while (readl_relaxed(pend) & WP_TCLR)
 442                 cpu_relax();
 443
 444         return 0;
 445 }
 446
 447 static int dmtimer_clockevent_shutdown(struct clock_event_device *evt)
 448 {
 449         struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
 450         struct dmtimer_systimer *t = &clkevt->t;
 451         void __iomem *ctrl = t->base + t->ctrl;
 452         u32 l;
 453
 454         l = readl_relaxed(ctrl);
 455         if (l & OMAP_TIMER_CTRL_ST) {
 456                 l &= ~BIT(0);
 457                 writel_relaxed(l, ctrl);
 458                 /* Flush posted write */
 459                 l = readl_relaxed(ctrl);
 460                 /*  Wait for functional clock period x 3.5 */
 461                 udelay(3500000 / t->rate + 1);
 462         }
 463         writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
 464
 465         return 0;
 466 }
 467
 468 static int dmtimer_set_periodic(struct clock_event_device *evt)
 469 {
 470         struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
 471         struct dmtimer_systimer *t = &clkevt->t;
 472         void __iomem *pend = t->base + t->pend;
 473
 474         dmtimer_clockevent_shutdown(evt);
 475
 476         /* Looks like we need to first set the load value separately */
 477         writel_relaxed(clkevt->period, t->base + t->load);
 478         while (readl_relaxed(pend) & WP_TLDR)
 479                 cpu_relax();
 480
 481         writel_relaxed(clkevt->period, t->base + t->counter);
 482         while (readl_relaxed(pend) & WP_TCRR)
 483                 cpu_relax();
 484
 485         writel_relaxed(OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 486                        t->base + t->ctrl);
 487         while (readl_relaxed(pend) & WP_TCLR)
 488                 cpu_relax();
 489
 490         return 0;
 491 }
 492
 493 static void omap_clockevent_idle(struct clock_event_device *evt)
 494 {
 495         struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
 496         struct dmtimer_systimer *t = &clkevt->t;
 497
 498         dmtimer_systimer_disable(t);
 499 }
 500
 501 static void omap_clockevent_unidle(struct clock_event_device *evt)
 502 {
 503         struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
 504         struct dmtimer_systimer *t = &clkevt->t;
 505
 506         dmtimer_systimer_enable(t);
 507         writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
 508         writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
 509 }
 510
 511 static int __init dmtimer_clockevent_init(struct device_node *np)
 512 {
 513         struct dmtimer_clockevent *clkevt;
 514         struct clock_event_device *dev;
 515         struct dmtimer_systimer *t;
 516         int error;
 517
 518         clkevt = kzalloc(sizeof(*clkevt), GFP_KERNEL);
 519         if (!clkevt)
 520                 return -ENOMEM;
 521
 522         t = &clkevt->t;
 523         dev = &clkevt->dev;
 524
 525         /*
 526          * We mostly use cpuidle_coupled with ARM local timers for runtime,
 527          * so there's probably no use for CLOCK_EVT_FEAT_DYNIRQ here.
 528          */
 529         dev->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 530         dev->rating = 300;
 531         dev->set_next_event = dmtimer_set_next_event;
 532         dev->set_state_shutdown = dmtimer_clockevent_shutdown;
 533         dev->set_state_periodic = dmtimer_set_periodic;
 534         dev->set_state_oneshot = dmtimer_clockevent_shutdown;
 535         dev->tick_resume = dmtimer_clockevent_shutdown;
 536         dev->cpumask = cpu_possible_mask;
 537
 538         dev->irq = irq_of_parse_and_map(np, 0);
 539         if (!dev->irq) {
 540                 error = -ENXIO;
 541                 goto err_out_free;
 542         }
 543
 544         error = dmtimer_systimer_setup(np, &clkevt->t);
 545         if (error)
 546                 goto err_out_free;
 547
 548         clkevt->period = 0xffffffff - DIV_ROUND_CLOSEST(t->rate, HZ);
 549
 550         /*
 551          * For clock-event timers we never read the timer counter and
 552          * so we are not impacted by errata i103 and i767. Therefore,
 553          * we can safely ignore this errata for clock-event timers.
 554          */
 555         writel_relaxed(OMAP_TIMER_CTRL_POSTED, t->base + t->ifctrl);
 556
 557         error = request_irq(dev->irq, dmtimer_clockevent_interrupt,
 558                             IRQF_TIMER, "clockevent", clkevt);
 559         if (error)
 560                 goto err_out_unmap;
 561
 562         writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
 563         writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
 564
 565         pr_info("TI gptimer clockevent: %s%lu Hz at %pOF\n",
 566                 of_find_property(np, "ti,timer-alwon", NULL) ?
 567                 "always-on " : "", t->rate, np->parent);
 568
 569         clockevents_config_and_register(dev, t->rate,
 570                                         3, /* Timer internal resynch latency */
 571                                         0xffffffff);
 572
 573         if (of_device_is_compatible(np, "ti,am33xx") ||
 574             of_device_is_compatible(np, "ti,am43")) {
 575                 dev->suspend = omap_clockevent_idle;
 576                 dev->resume = omap_clockevent_unidle;
 577         }
 578
 579         return 0;
 580
 581 err_out_unmap:
 582         iounmap(t->base);
 583
 584 err_out_free:
 585         kfree(clkevt);
 586
 587         return error;
 588 }
 589
 590 /* Clocksource */
 591 static struct dmtimer_clocksource *
 592 to_dmtimer_clocksource(struct clocksource *cs)
 593 {
 594         return container_of(cs, struct dmtimer_clocksource, dev);
 595 }
 596
 597 static u64 dmtimer_clocksource_read_cycles(struct clocksource *cs)
 598 {
 599         struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs);
 600         struct dmtimer_systimer *t = &clksrc->t;
 601
 602         return (u64)readl_relaxed(t->base + t->counter);
 603 }
 604
 605 static void __iomem *dmtimer_sched_clock_counter;
 606
 607 static u64 notrace dmtimer_read_sched_clock(void)
 608 {
 609         return readl_relaxed(dmtimer_sched_clock_counter);
 610 }
 611
 612 static void dmtimer_clocksource_suspend(struct clocksource *cs)
 613 {
 614         struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs);
 615         struct dmtimer_systimer *t = &clksrc->t;
 616
 617         clksrc->loadval = readl_relaxed(t->base + t->counter);
 618         dmtimer_systimer_disable(t);
 619 }
 620
 621 static void dmtimer_clocksource_resume(struct clocksource *cs)
 622 {
 623         struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs);
 624         struct dmtimer_systimer *t = &clksrc->t;
 625
 626         dmtimer_systimer_enable(t);
 627         writel_relaxed(clksrc->loadval, t->base + t->counter);
 628         writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
 629                        t->base + t->ctrl);
 630 }
 631
 632 static int __init dmtimer_clocksource_init(struct device_node *np)
 633 {
 634         struct dmtimer_clocksource *clksrc;
 635         struct dmtimer_systimer *t;
 636         struct clocksource *dev;
 637         int error;
 638
 639         clksrc = kzalloc(sizeof(*clksrc), GFP_KERNEL);
 640         if (!clksrc)
 641                 return -ENOMEM;
 642
 643         dev = &clksrc->dev;
 644         t = &clksrc->t;
 645
 646         error = dmtimer_systimer_setup(np, t);
 647         if (error)
 648                 goto err_out_free;
 649
 650         dev->name = "dmtimer";
 651         dev->rating = 300;
 652         dev->read = dmtimer_clocksource_read_cycles;
 653         dev->mask = CLOCKSOURCE_MASK(32);
 654         dev->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 655
 656         if (of_device_is_compatible(np, "ti,am33xx") ||
 657             of_device_is_compatible(np, "ti,am43")) {
 658                 dev->suspend = dmtimer_clocksource_suspend;
 659                 dev->resume = dmtimer_clocksource_resume;
 660         }
 661
 662         writel_relaxed(0, t->base + t->counter);
 663         writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
 664                        t->base + t->ctrl);
 665
 666         pr_info("TI gptimer clocksource: %s%pOF\n",
 667                 of_find_property(np, "ti,timer-alwon", NULL) ?
 668                 "always-on " : "", np->parent);
 669
 670         if (!dmtimer_sched_clock_counter) {
 671                 dmtimer_sched_clock_counter = t->base + t->counter;
 672                 sched_clock_register(dmtimer_read_sched_clock, 32, t->rate);
 673         }
 674
 675         if (clocksource_register_hz(dev, t->rate))
 676                 pr_err("Could not register clocksource %pOF\n", np);
 677
 678         return 0;
 679
 680 err_out_free:
 681         kfree(clksrc);
 682
 683         return -ENODEV;
 684 }
 685
 686 /*
 687  * To detect between a clocksource and clockevent, we assume the device tree
 688  * has no interrupts configured for a clocksource timer.
 689  */
 690 static int __init dmtimer_systimer_init(struct device_node *np)
 691 {
 692         const __be32 *addr;
 693         u32 pa;
 694
 695         /* One time init for the preferred timer configuration */
 696         if (!clocksource && !clockevent)
 697                 dmtimer_systimer_select_best();
 698
 699         if (!clocksource && !clockevent) {
 700                 pr_err("%s: unable to detect system timers, update dtb?\n",
 701                        __func__);
 702
 703                 return -EINVAL;
 704         }
 705
 706         addr = of_get_address(np, 0, NULL, NULL);
 707         pa = of_translate_address(np, addr);
 708         if (!pa)
 709                 return -EINVAL;
 710
 711         if (counter_32k <= 0 && clocksource == pa)
 712                 return dmtimer_clocksource_init(np);
 713
 714         if (clockevent == pa)
 715                 return dmtimer_clockevent_init(np);
 716
 717         return 0;
 718 }
 719
 720 TIMER_OF_DECLARE(systimer_omap2, "ti,omap2420-timer", dmtimer_systimer_init);
 721 TIMER_OF_DECLARE(systimer_omap3, "ti,omap3430-timer", dmtimer_systimer_init);
 722 TIMER_OF_DECLARE(systimer_omap4, "ti,omap4430-timer", dmtimer_systimer_init);
 723 TIMER_OF_DECLARE(systimer_omap5, "ti,omap5430-timer", dmtimer_systimer_init);
 724 TIMER_OF_DECLARE(systimer_am33x, "ti,am335x-timer", dmtimer_systimer_init);
 725 TIMER_OF_DECLARE(systimer_am3ms, "ti,am335x-timer-1ms", dmtimer_systimer_init);
 726 TIMER_OF_DECLARE(systimer_dm814, "ti,dm814-timer", dmtimer_systimer_init);
 727 TIMER_OF_DECLARE(systimer_dm816, "ti,dm816-timer", dmtimer_systimer_init);