drivers/clocksource/timer-sp804.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  linux/drivers/clocksource/timer-sp.c
   4  *
   5  *  Copyright (C) 1999 - 2003 ARM Limited
   6  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/clocksource.h>
  10 #include <linux/clockchips.h>
  11 #include <linux/err.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/irq.h>
  14 #include <linux/io.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_clk.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/sched_clock.h>
  20
  21 #include "timer-sp.h"
  22
  23 /* Hisilicon 64-bit timer(a variant of ARM SP804) */
  24 #define HISI_TIMER_1_BASE       0x00
  25 #define HISI_TIMER_2_BASE       0x40
  26 #define HISI_TIMER_LOAD         0x00
  27 #define HISI_TIMER_LOAD_H       0x04
  28 #define HISI_TIMER_VALUE        0x08
  29 #define HISI_TIMER_VALUE_H      0x0c
  30 #define HISI_TIMER_CTRL         0x10
  31 #define HISI_TIMER_INTCLR       0x14
  32 #define HISI_TIMER_RIS          0x18
  33 #define HISI_TIMER_MIS          0x1c
  34 #define HISI_TIMER_BGLOAD       0x20
  35 #define HISI_TIMER_BGLOAD_H     0x24
  36
  37 static struct sp804_timer arm_sp804_timer __initdata = {
  38         .load           = TIMER_LOAD,
  39         .value          = TIMER_VALUE,
  40         .ctrl           = TIMER_CTRL,
  41         .intclr         = TIMER_INTCLR,
  42         .timer_base     = {TIMER_1_BASE, TIMER_2_BASE},
  43         .width          = 32,
  44 };
  45
  46 static struct sp804_timer hisi_sp804_timer __initdata = {
  47         .load           = HISI_TIMER_LOAD,
  48         .load_h         = HISI_TIMER_LOAD_H,
  49         .value          = HISI_TIMER_VALUE,
  50         .value_h        = HISI_TIMER_VALUE_H,
  51         .ctrl           = HISI_TIMER_CTRL,
  52         .intclr         = HISI_TIMER_INTCLR,
  53         .timer_base     = {HISI_TIMER_1_BASE, HISI_TIMER_2_BASE},
  54         .width          = 64,
  55 };
  56
  57 static struct sp804_clkevt sp804_clkevt[NR_TIMERS];
  58
  59 static long __init sp804_get_clock_rate(struct clk *clk, const char *name)
  60 {
  61         int err;
  62
  63         if (!clk)
  64                 clk = clk_get_sys("sp804", name);
  65         if (IS_ERR(clk)) {
  66                 pr_err("sp804: %s clock not found: %ld\n", name, PTR_ERR(clk));
  67                 return PTR_ERR(clk);
  68         }
  69
  70         err = clk_prepare_enable(clk);
  71         if (err) {
  72                 pr_err("sp804: clock failed to enable: %d\n", err);
  73                 clk_put(clk);
  74                 return err;
  75         }
  76
  77         return clk_get_rate(clk);
  78 }
  79
  80 static struct sp804_clkevt * __init sp804_clkevt_get(void __iomem *base)
  81 {
  82         int i;
  83
  84         for (i = 0; i < NR_TIMERS; i++) {
  85                 if (sp804_clkevt[i].base == base)
  86                         return &sp804_clkevt[i];
  87         }
  88
  89         /* It's impossible to reach here */
  90         WARN_ON(1);
  91
  92         return NULL;
  93 }
  94
  95 static struct sp804_clkevt *sched_clkevt;
  96
  97 static u64 notrace sp804_read(void)
  98 {
  99         return ~readl_relaxed(sched_clkevt->value);
 100 }
 101
 102 static int __init sp804_clocksource_and_sched_clock_init(void __iomem *base,
 103                                                          const char *name,
 104                                                          struct clk *clk,
 105                                                          int use_sched_clock)
 106 {
 107         long rate;
 108         struct sp804_clkevt *clkevt;
 109
 110         rate = sp804_get_clock_rate(clk, name);
 111         if (rate < 0)
 112                 return -EINVAL;
 113
 114         clkevt = sp804_clkevt_get(base);
 115
 116         writel(0, clkevt->ctrl);
 117         writel(0xffffffff, clkevt->load);
 118         writel(0xffffffff, clkevt->value);
 119         if (clkevt->width == 64) {
 120                 writel(0xffffffff, clkevt->load_h);
 121                 writel(0xffffffff, clkevt->value_h);
 122         }
 123         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
 124                 clkevt->ctrl);
 125
 126         clocksource_mmio_init(clkevt->value, name,
 127                 rate, 200, 32, clocksource_mmio_readl_down);
 128
 129         if (use_sched_clock) {
 130                 sched_clkevt = clkevt;
 131                 sched_clock_register(sp804_read, 32, rate);
 132         }
 133
 134         return 0;
 135 }
 136
 137
 138 static struct sp804_clkevt *common_clkevt;
 139
 140 /*
 141  * IRQ handler for the timer
 142  */
 143 static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
 144 {
 145         struct clock_event_device *evt = dev_id;
 146
 147         /* clear the interrupt */
 148         writel(1, common_clkevt->intclr);
 149
 150         evt->event_handler(evt);
 151
 152         return IRQ_HANDLED;
 153 }
 154
 155 static inline void timer_shutdown(struct clock_event_device *evt)
 156 {
 157         writel(0, common_clkevt->ctrl);
 158 }
 159
 160 static int sp804_shutdown(struct clock_event_device *evt)
 161 {
 162         timer_shutdown(evt);
 163         return 0;
 164 }
 165
 166 static int sp804_set_periodic(struct clock_event_device *evt)
 167 {
 168         unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
 169                              TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 170
 171         timer_shutdown(evt);
 172         writel(common_clkevt->reload, common_clkevt->load);
 173         writel(ctrl, common_clkevt->ctrl);
 174         return 0;
 175 }
 176
 177 static int sp804_set_next_event(unsigned long next,
 178         struct clock_event_device *evt)
 179 {
 180         unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
 181                              TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE;
 182
 183         writel(next, common_clkevt->load);
 184         writel(ctrl, common_clkevt->ctrl);
 185
 186         return 0;
 187 }
 188
 189 static struct clock_event_device sp804_clockevent = {
 190         .features               = CLOCK_EVT_FEAT_PERIODIC |
 191                                   CLOCK_EVT_FEAT_ONESHOT |
 192                                   CLOCK_EVT_FEAT_DYNIRQ,
 193         .set_state_shutdown     = sp804_shutdown,
 194         .set_state_periodic     = sp804_set_periodic,
 195         .set_state_oneshot      = sp804_shutdown,
 196         .tick_resume            = sp804_shutdown,
 197         .set_next_event         = sp804_set_next_event,
 198         .rating                 = 300,
 199 };
 200
 201 static int __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
 202                                          struct clk *clk, const char *name)
 203 {
 204         struct clock_event_device *evt = &sp804_clockevent;
 205         long rate;
 206
 207         rate = sp804_get_clock_rate(clk, name);
 208         if (rate < 0)
 209                 return -EINVAL;
 210
 211         common_clkevt = sp804_clkevt_get(base);
 212         common_clkevt->reload = DIV_ROUND_CLOSEST(rate, HZ);
 213         evt->name = name;
 214         evt->irq = irq;
 215         evt->cpumask = cpu_possible_mask;
 216
 217         writel(0, common_clkevt->ctrl);
 218
 219         if (request_irq(irq, sp804_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
 220                         "timer", &sp804_clockevent))
 221                 pr_err("%s: request_irq() failed\n", "timer");
 222         clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
 223
 224         return 0;
 225 }
 226
 227 static void __init sp804_clkevt_init(struct sp804_timer *timer, void __iomem *base)
 228 {
 229         int i;
 230
 231         for (i = 0; i < NR_TIMERS; i++) {
 232                 void __iomem *timer_base;
 233                 struct sp804_clkevt *clkevt;
 234
 235                 timer_base = base + timer->timer_base[i];
 236                 clkevt = &sp804_clkevt[i];
 237                 clkevt->base    = timer_base;
 238                 clkevt->load    = timer_base + timer->load;
 239                 clkevt->load_h  = timer_base + timer->load_h;
 240                 clkevt->value   = timer_base + timer->value;
 241                 clkevt->value_h = timer_base + timer->value_h;
 242                 clkevt->ctrl    = timer_base + timer->ctrl;
 243                 clkevt->intclr  = timer_base + timer->intclr;
 244                 clkevt->width   = timer->width;
 245         }
 246 }
 247
 248 static int __init sp804_of_init(struct device_node *np, struct sp804_timer *timer)
 249 {
 250         static bool initialized = false;
 251         void __iomem *base;
 252         void __iomem *timer1_base;
 253         void __iomem *timer2_base;
 254         int irq, ret = -EINVAL;
 255         u32 irq_num = 0;
 256         struct clk *clk1, *clk2;
 257         const char *name = of_get_property(np, "compatible", NULL);
 258
 259         base = of_iomap(np, 0);
 260         if (!base)
 261                 return -ENXIO;
 262
 263         timer1_base = base + timer->timer_base[0];
 264         timer2_base = base + timer->timer_base[1];
 265
 266         /* Ensure timers are disabled */
 267         writel(0, timer1_base + timer->ctrl);
 268         writel(0, timer2_base + timer->ctrl);
 269
 270         if (initialized || !of_device_is_available(np)) {
 271                 ret = -EINVAL;
 272                 goto err;
 273         }
 274
 275         clk1 = of_clk_get(np, 0);
 276         if (IS_ERR(clk1))
 277                 clk1 = NULL;
 278
 279         /* Get the 2nd clock if the timer has 3 timer clocks */
 280         if (of_clk_get_parent_count(np) == 3) {
 281                 clk2 = of_clk_get(np, 1);
 282                 if (IS_ERR(clk2)) {
 283                         pr_err("sp804: %pOFn clock not found: %d\n", np,
 284                                 (int)PTR_ERR(clk2));
 285                         clk2 = NULL;
 286                 }
 287         } else
 288                 clk2 = clk1;
 289
 290         irq = irq_of_parse_and_map(np, 0);
 291         if (irq <= 0)
 292                 goto err;
 293
 294         sp804_clkevt_init(timer, base);
 295
 296         of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
 297         if (irq_num == 2) {
 298
 299                 ret = sp804_clockevents_init(timer2_base, irq, clk2, name);
 300                 if (ret)
 301                         goto err;
 302
 303                 ret = sp804_clocksource_and_sched_clock_init(timer1_base,
 304                                                              name, clk1, 1);
 305                 if (ret)
 306                         goto err;
 307         } else {
 308
 309                 ret = sp804_clockevents_init(timer1_base, irq, clk1, name);
 310                 if (ret)
 311                         goto err;
 312
 313                 ret = sp804_clocksource_and_sched_clock_init(timer2_base,
 314                                                              name, clk2, 1);
 315                 if (ret)
 316                         goto err;
 317         }
 318         initialized = true;
 319
 320         return 0;
 321 err:
 322         iounmap(base);
 323         return ret;
 324 }
 325
 326 static int __init arm_sp804_of_init(struct device_node *np)
 327 {
 328         return sp804_of_init(np, &arm_sp804_timer);
 329 }
 330 TIMER_OF_DECLARE(sp804, "arm,sp804", arm_sp804_of_init);
 331
 332 static int __init hisi_sp804_of_init(struct device_node *np)
 333 {
 334         return sp804_of_init(np, &hisi_sp804_timer);
 335 }
 336 TIMER_OF_DECLARE(hisi_sp804, "hisilicon,sp804", hisi_sp804_of_init);
 337
 338 static int __init integrator_cp_of_init(struct device_node *np)
 339 {
 340         static int init_count = 0;
 341         void __iomem *base;
 342         int irq, ret = -EINVAL;
 343         const char *name = of_get_property(np, "compatible", NULL);
 344         struct clk *clk;
 345
 346         base = of_iomap(np, 0);
 347         if (!base) {
 348                 pr_err("Failed to iomap\n");
 349                 return -ENXIO;
 350         }
 351
 352         clk = of_clk_get(np, 0);
 353         if (IS_ERR(clk)) {
 354                 pr_err("Failed to get clock\n");
 355                 return PTR_ERR(clk);
 356         }
 357
 358         /* Ensure timer is disabled */
 359         writel(0, base + arm_sp804_timer.ctrl);
 360
 361         if (init_count == 2 || !of_device_is_available(np))
 362                 goto err;
 363
 364         sp804_clkevt_init(&arm_sp804_timer, base);
 365
 366         if (!init_count) {
 367                 ret = sp804_clocksource_and_sched_clock_init(base,
 368                                                              name, clk, 0);
 369                 if (ret)
 370                         goto err;
 371         } else {
 372                 irq = irq_of_parse_and_map(np, 0);
 373                 if (irq <= 0)
 374                         goto err;
 375
 376                 ret = sp804_clockevents_init(base, irq, clk, name);
 377                 if (ret)
 378                         goto err;
 379         }
 380
 381         init_count++;
 382         return 0;
 383 err:
 384         iounmap(base);
 385         return ret;
 386 }
 387 TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);