drivers/clocksource/timer-sp804.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  linux/drivers/clocksource/timer-sp.c
   4  *
   5  *  Copyright (C) 1999 - 2003 ARM Limited
   6  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/clocksource.h>
  10 #include <linux/clockchips.h>
  11 #include <linux/err.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/irq.h>
  14 #include <linux/io.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_clk.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/sched_clock.h>
  20
  21 #include "timer-sp.h"
  22
  23 static long __init sp804_get_clock_rate(struct clk *clk, const char *name)
  24 {
  25         long rate;
  26         int err;
  27
  28         if (!clk)
  29                 clk = clk_get_sys("sp804", name);
  30         if (IS_ERR(clk)) {
  31                 pr_err("sp804: %s clock not found: %ld\n", name, PTR_ERR(clk));
  32                 return PTR_ERR(clk);
  33         }
  34
  35         err = clk_prepare(clk);
  36         if (err) {
  37                 pr_err("sp804: clock failed to prepare: %d\n", err);
  38                 clk_put(clk);
  39                 return err;
  40         }
  41
  42         err = clk_enable(clk);
  43         if (err) {
  44                 pr_err("sp804: clock failed to enable: %d\n", err);
  45                 clk_unprepare(clk);
  46                 clk_put(clk);
  47                 return err;
  48         }
  49
  50         rate = clk_get_rate(clk);
  51         if (rate < 0) {
  52                 pr_err("sp804: clock failed to get rate: %ld\n", rate);
  53                 clk_disable(clk);
  54                 clk_unprepare(clk);
  55                 clk_put(clk);
  56         }
  57
  58         return rate;
  59 }
  60
  61 static void __iomem *sched_clock_base;
  62
  63 static u64 notrace sp804_read(void)
  64 {
  65         return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
  66 }
  67
  68 int __init sp804_clocksource_and_sched_clock_init(void __iomem *base,
  69                                                   const char *name,
  70                                                   struct clk *clk,
  71                                                   int use_sched_clock)
  72 {
  73         long rate;
  74
  75         rate = sp804_get_clock_rate(clk, name);
  76         if (rate < 0)
  77                 return -EINVAL;
  78
  79         /* setup timer 0 as free-running clocksource */
  80         writel(0, base + TIMER_CTRL);
  81         writel(0xffffffff, base + TIMER_LOAD);
  82         writel(0xffffffff, base + TIMER_VALUE);
  83         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
  84                 base + TIMER_CTRL);
  85
  86         clocksource_mmio_init(base + TIMER_VALUE, name,
  87                 rate, 200, 32, clocksource_mmio_readl_down);
  88
  89         if (use_sched_clock) {
  90                 sched_clock_base = base;
  91                 sched_clock_register(sp804_read, 32, rate);
  92         }
  93
  94         return 0;
  95 }
  96
  97
  98 static void __iomem *clkevt_base;
  99 static unsigned long clkevt_reload;
 100
 101 /*
 102  * IRQ handler for the timer
 103  */
 104 static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
 105 {
 106         struct clock_event_device *evt = dev_id;
 107
 108         /* clear the interrupt */
 109         writel(1, clkevt_base + TIMER_INTCLR);
 110
 111         evt->event_handler(evt);
 112
 113         return IRQ_HANDLED;
 114 }
 115
 116 static inline void timer_shutdown(struct clock_event_device *evt)
 117 {
 118         writel(0, clkevt_base + TIMER_CTRL);
 119 }
 120
 121 static int sp804_shutdown(struct clock_event_device *evt)
 122 {
 123         timer_shutdown(evt);
 124         return 0;
 125 }
 126
 127 static int sp804_set_periodic(struct clock_event_device *evt)
 128 {
 129         unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
 130                              TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 131
 132         timer_shutdown(evt);
 133         writel(clkevt_reload, clkevt_base + TIMER_LOAD);
 134         writel(ctrl, clkevt_base + TIMER_CTRL);
 135         return 0;
 136 }
 137
 138 static int sp804_set_next_event(unsigned long next,
 139         struct clock_event_device *evt)
 140 {
 141         unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
 142                              TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE;
 143
 144         writel(next, clkevt_base + TIMER_LOAD);
 145         writel(ctrl, clkevt_base + TIMER_CTRL);
 146
 147         return 0;
 148 }
 149
 150 static struct clock_event_device sp804_clockevent = {
 151         .features               = CLOCK_EVT_FEAT_PERIODIC |
 152                                   CLOCK_EVT_FEAT_ONESHOT |
 153                                   CLOCK_EVT_FEAT_DYNIRQ,
 154         .set_state_shutdown     = sp804_shutdown,
 155         .set_state_periodic     = sp804_set_periodic,
 156         .set_state_oneshot      = sp804_shutdown,
 157         .tick_resume            = sp804_shutdown,
 158         .set_next_event         = sp804_set_next_event,
 159         .rating                 = 300,
 160 };
 161
 162 int __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
 163                                   struct clk *clk, const char *name)
 164 {
 165         struct clock_event_device *evt = &sp804_clockevent;
 166         long rate;
 167
 168         rate = sp804_get_clock_rate(clk, name);
 169         if (rate < 0)
 170                 return -EINVAL;
 171
 172         clkevt_base = base;
 173         clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
 174         evt->name = name;
 175         evt->irq = irq;
 176         evt->cpumask = cpu_possible_mask;
 177
 178         writel(0, base + TIMER_CTRL);
 179
 180         if (request_irq(irq, sp804_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
 181                         "timer", &sp804_clockevent))
 182                 pr_err("%s: request_irq() failed\n", "timer");
 183         clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
 184
 185         return 0;
 186 }
 187
 188 static int __init sp804_of_init(struct device_node *np)
 189 {
 190         static bool initialized = false;
 191         void __iomem *base;
 192         int irq, ret = -EINVAL;
 193         u32 irq_num = 0;
 194         struct clk *clk1, *clk2;
 195         const char *name = of_get_property(np, "compatible", NULL);
 196
 197         base = of_iomap(np, 0);
 198         if (!base)
 199                 return -ENXIO;
 200
 201         /* Ensure timers are disabled */
 202         writel(0, base + TIMER_CTRL);
 203         writel(0, base + TIMER_2_BASE + TIMER_CTRL);
 204
 205         if (initialized || !of_device_is_available(np)) {
 206                 ret = -EINVAL;
 207                 goto err;
 208         }
 209
 210         clk1 = of_clk_get(np, 0);
 211         if (IS_ERR(clk1))
 212                 clk1 = NULL;
 213
 214         /* Get the 2nd clock if the timer has 3 timer clocks */
 215         if (of_clk_get_parent_count(np) == 3) {
 216                 clk2 = of_clk_get(np, 1);
 217                 if (IS_ERR(clk2)) {
 218                         pr_err("sp804: %pOFn clock not found: %d\n", np,
 219                                 (int)PTR_ERR(clk2));
 220                         clk2 = NULL;
 221                 }
 222         } else
 223                 clk2 = clk1;
 224
 225         irq = irq_of_parse_and_map(np, 0);
 226         if (irq <= 0)
 227                 goto err;
 228
 229         of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
 230         if (irq_num == 2) {
 231
 232                 ret = sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
 233                 if (ret)
 234                         goto err;
 235
 236                 ret = sp804_clocksource_and_sched_clock_init(base,
 237                                                              name, clk1, 1);
 238                 if (ret)
 239                         goto err;
 240         } else {
 241
 242                 ret = sp804_clockevents_init(base, irq, clk1, name);
 243                 if (ret)
 244                         goto err;
 245
 246                 ret = sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
 247                                                              name, clk2, 1);
 248                 if (ret)
 249                         goto err;
 250         }
 251         initialized = true;
 252
 253         return 0;
 254 err:
 255         iounmap(base);
 256         return ret;
 257 }
 258 TIMER_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
 259
 260 static int __init integrator_cp_of_init(struct device_node *np)
 261 {
 262         static int init_count = 0;
 263         void __iomem *base;
 264         int irq, ret = -EINVAL;
 265         const char *name = of_get_property(np, "compatible", NULL);
 266         struct clk *clk;
 267
 268         base = of_iomap(np, 0);
 269         if (!base) {
 270                 pr_err("Failed to iomap\n");
 271                 return -ENXIO;
 272         }
 273
 274         clk = of_clk_get(np, 0);
 275         if (IS_ERR(clk)) {
 276                 pr_err("Failed to get clock\n");
 277                 return PTR_ERR(clk);
 278         }
 279
 280         /* Ensure timer is disabled */
 281         writel(0, base + TIMER_CTRL);
 282
 283         if (init_count == 2 || !of_device_is_available(np))
 284                 goto err;
 285
 286         if (!init_count) {
 287                 ret = sp804_clocksource_and_sched_clock_init(base,
 288                                                              name, clk, 0);
 289                 if (ret)
 290                         goto err;
 291         } else {
 292                 irq = irq_of_parse_and_map(np, 0);
 293                 if (irq <= 0)
 294                         goto err;
 295
 296                 ret = sp804_clockevents_init(base, irq, clk, name);
 297                 if (ret)
 298                         goto err;
 299         }
 300
 301         init_count++;
 302         return 0;
 303 err:
 304         iounmap(base);
 305         return ret;
 306 }
 307 TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);