1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2012 Regents of the University of California
4 * Copyright (C) 2017 SiFive
6 * All RISC-V systems have a timer attached to every hart. These timers can
7 * either be read from the "time" and "timeh" CSRs, and can use the SBI to
8 * setup events, or directly accessed using MMIO registers.
11 #define pr_fmt(fmt) "riscv-timer: " fmt
13 #include <linux/clocksource.h>
14 #include <linux/clockchips.h>
15 #include <linux/cpu.h>
16 #include <linux/delay.h>
17 #include <linux/irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/module.h>
20 #include <linux/sched_clock.h>
21 #include <linux/io-64-nonatomic-lo-hi.h>
22 #include <linux/interrupt.h>
23 #include <linux/of_irq.h>
24 #include <clocksource/timer-riscv.h>
26 #include <asm/hwcap.h>
28 #include <asm/timex.h>
30 static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
31 static bool riscv_timer_cannot_wake_cpu;
33 static int riscv_clock_next_event(unsigned long delta,
34 struct clock_event_device *ce)
36 u64 next_tval = get_cycles64() + delta;
38 csr_set(CSR_IE, IE_TIE);
39 if (static_branch_likely(&riscv_sstc_available)) {
40 #if defined(CONFIG_32BIT)
41 csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
42 csr_write(CSR_STIMECMPH, next_tval >> 32);
44 csr_write(CSR_STIMECMP, next_tval);
47 sbi_set_timer(next_tval);
52 static unsigned int riscv_clock_event_irq;
53 static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
54 .name = "riscv_timer_clockevent",
55 .features = CLOCK_EVT_FEAT_ONESHOT,
57 .set_next_event = riscv_clock_next_event,
61 * It is guaranteed that all the timers across all the harts are synchronized
62 * within one tick of each other, so while this could technically go
63 * backwards when hopping between CPUs, practically it won't happen.
65 static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
67 return get_cycles64();
70 static u64 notrace riscv_sched_clock(void)
72 return get_cycles64();
75 static struct clocksource riscv_clocksource = {
76 .name = "riscv_clocksource",
78 .mask = CLOCKSOURCE_MASK(64),
79 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
80 .read = riscv_clocksource_rdtime,
81 #if IS_ENABLED(CONFIG_GENERIC_GETTIMEOFDAY)
82 .vdso_clock_mode = VDSO_CLOCKMODE_ARCHTIMER,
84 .vdso_clock_mode = VDSO_CLOCKMODE_NONE,
88 static int riscv_timer_starting_cpu(unsigned int cpu)
90 struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
92 ce->cpumask = cpumask_of(cpu);
93 ce->irq = riscv_clock_event_irq;
94 if (riscv_timer_cannot_wake_cpu)
95 ce->features |= CLOCK_EVT_FEAT_C3STOP;
96 clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
98 enable_percpu_irq(riscv_clock_event_irq,
99 irq_get_trigger_type(riscv_clock_event_irq));
103 static int riscv_timer_dying_cpu(unsigned int cpu)
105 disable_percpu_irq(riscv_clock_event_irq);
109 void riscv_cs_get_mult_shift(u32 *mult, u32 *shift)
111 *mult = riscv_clocksource.mult;
112 *shift = riscv_clocksource.shift;
114 EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift);
116 /* called directly from the low-level interrupt handler */
117 static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
119 struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
121 csr_clear(CSR_IE, IE_TIE);
122 evdev->event_handler(evdev);
127 static int __init riscv_timer_init_dt(struct device_node *n)
130 unsigned long hartid;
131 struct device_node *child;
132 struct irq_domain *domain;
134 error = riscv_of_processor_hartid(n, &hartid);
136 pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n",
141 cpuid = riscv_hartid_to_cpuid(hartid);
143 pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
147 if (cpuid != smp_processor_id())
150 child = of_find_compatible_node(NULL, NULL, "riscv,timer");
152 riscv_timer_cannot_wake_cpu = of_property_read_bool(child,
153 "riscv,timer-cannot-wake-cpu");
158 child = of_get_compatible_child(n, "riscv,cpu-intc");
160 pr_err("Failed to find INTC node [%pOF]\n", n);
163 domain = irq_find_host(child);
166 pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
170 riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
171 if (!riscv_clock_event_irq) {
172 pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
176 pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n",
177 __func__, cpuid, hartid);
178 error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
180 pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
185 sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
187 error = request_percpu_irq(riscv_clock_event_irq,
188 riscv_timer_interrupt,
189 "riscv-timer", &riscv_clock_event);
191 pr_err("registering percpu irq failed [%d]\n", error);
195 if (riscv_isa_extension_available(NULL, SSTC)) {
196 pr_info("Timer interrupt in S-mode is available via sstc extension\n");
197 static_branch_enable(&riscv_sstc_available);
200 error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
201 "clockevents/riscv/timer:starting",
202 riscv_timer_starting_cpu, riscv_timer_dying_cpu);
204 pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
210 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);