2 * Pistachio clocksource based on general-purpose timers
4 * Copyright (C) 2015 Imagination Technologies
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
11 #define pr_fmt(fmt) "%s: " fmt, __func__
13 #include <linux/clk.h>
14 #include <linux/clocksource.h>
15 #include <linux/clockchips.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/init.h>
19 #include <linux/spinlock.h>
20 #include <linux/mfd/syscon.h>
22 #include <linux/of_address.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/sched_clock.h>
26 #include <linux/time.h>
29 #define CR_TIMER_CTRL_CFG 0x00
30 #define TIMER_ME_GLOBAL BIT(0)
31 #define CR_TIMER_REV 0x10
33 /* Timer specific registers */
34 #define TIMER_CFG 0x20
35 #define TIMER_ME_LOCAL BIT(0)
36 #define TIMER_RELOAD_VALUE 0x24
37 #define TIMER_CURRENT_VALUE 0x28
38 #define TIMER_CURRENT_OVERFLOW_VALUE 0x2C
39 #define TIMER_IRQ_STATUS 0x30
40 #define TIMER_IRQ_CLEAR 0x34
41 #define TIMER_IRQ_MASK 0x38
43 #define PERIP_TIMER_CONTROL 0x90
45 /* Timer specific configuration Values */
46 #define RELOAD_VALUE 0xffffffff
48 struct pistachio_clocksource {
51 struct clocksource cs;
54 static struct pistachio_clocksource pcs_gpt;
56 #define to_pistachio_clocksource(cs) \
57 container_of(cs, struct pistachio_clocksource, cs)
59 static inline u32 gpt_readl(void __iomem *base, u32 offset, u32 gpt_id)
61 return readl(base + 0x20 * gpt_id + offset);
64 static inline void gpt_writel(void __iomem *base, u32 value, u32 offset,
67 writel(value, base + 0x20 * gpt_id + offset);
71 pistachio_clocksource_read_cycles(struct clocksource *cs)
73 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
74 __maybe_unused u32 overflow;
79 * The counter value is only refreshed after the overflow value is read.
80 * And they must be read in strict order, hence raw spin lock added.
83 raw_spin_lock_irqsave(&pcs->lock, flags);
84 overflow = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0);
85 counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0);
86 raw_spin_unlock_irqrestore(&pcs->lock, flags);
91 static u64 notrace pistachio_read_sched_clock(void)
93 return pistachio_clocksource_read_cycles(&pcs_gpt.cs);
96 static void pistachio_clksrc_set_mode(struct clocksource *cs, int timeridx,
99 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
102 val = gpt_readl(pcs->base, TIMER_CFG, timeridx);
104 val |= TIMER_ME_LOCAL;
106 val &= ~TIMER_ME_LOCAL;
108 gpt_writel(pcs->base, val, TIMER_CFG, timeridx);
111 static void pistachio_clksrc_enable(struct clocksource *cs, int timeridx)
113 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
115 /* Disable GPT local before loading reload value */
116 pistachio_clksrc_set_mode(cs, timeridx, false);
117 gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx);
118 pistachio_clksrc_set_mode(cs, timeridx, true);
121 static void pistachio_clksrc_disable(struct clocksource *cs, int timeridx)
123 /* Disable GPT local */
124 pistachio_clksrc_set_mode(cs, timeridx, false);
127 static int pistachio_clocksource_enable(struct clocksource *cs)
129 pistachio_clksrc_enable(cs, 0);
133 static void pistachio_clocksource_disable(struct clocksource *cs)
135 pistachio_clksrc_disable(cs, 0);
138 /* Desirable clock source for pistachio platform */
139 static struct pistachio_clocksource pcs_gpt = {
143 .enable = pistachio_clocksource_enable,
144 .disable = pistachio_clocksource_disable,
145 .read = pistachio_clocksource_read_cycles,
146 .mask = CLOCKSOURCE_MASK(32),
147 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
148 CLOCK_SOURCE_SUSPEND_NONSTOP,
152 static int __init pistachio_clksrc_of_init(struct device_node *node)
154 struct clk *sys_clk, *fast_clk;
155 struct regmap *periph_regs;
159 pcs_gpt.base = of_iomap(node, 0);
161 pr_err("cannot iomap\n");
165 periph_regs = syscon_regmap_lookup_by_phandle(node, "img,cr-periph");
166 if (IS_ERR(periph_regs)) {
167 pr_err("cannot get peripheral regmap (%ld)\n",
168 PTR_ERR(periph_regs));
169 return PTR_ERR(periph_regs);
172 /* Switch to using the fast counter clock */
173 ret = regmap_update_bits(periph_regs, PERIP_TIMER_CONTROL,
178 sys_clk = of_clk_get_by_name(node, "sys");
179 if (IS_ERR(sys_clk)) {
180 pr_err("clock get failed (%ld)\n", PTR_ERR(sys_clk));
181 return PTR_ERR(sys_clk);
184 fast_clk = of_clk_get_by_name(node, "fast");
185 if (IS_ERR(fast_clk)) {
186 pr_err("clock get failed (%lu)\n", PTR_ERR(fast_clk));
187 return PTR_ERR(fast_clk);
190 ret = clk_prepare_enable(sys_clk);
192 pr_err("failed to enable clock (%d)\n", ret);
196 ret = clk_prepare_enable(fast_clk);
198 pr_err("failed to enable clock (%d)\n", ret);
199 clk_disable_unprepare(sys_clk);
203 rate = clk_get_rate(fast_clk);
205 /* Disable irq's for clocksource usage */
206 gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 0);
207 gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 1);
208 gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 2);
209 gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 3);
211 /* Enable timer block */
212 writel(TIMER_ME_GLOBAL, pcs_gpt.base);
214 raw_spin_lock_init(&pcs_gpt.lock);
215 sched_clock_register(pistachio_read_sched_clock, 32, rate);
216 return clocksource_register_hz(&pcs_gpt.cs, rate);
218 TIMER_OF_DECLARE(pistachio_gptimer, "img,pistachio-gptimer",
219 pistachio_clksrc_of_init);