1 // SPDX-License-Identifier: GPL-2.0
3 * 64-bit Periodic Interval Timer driver
5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
7 * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
10 #include <linux/clk.h>
11 #include <linux/clockchips.h>
12 #include <linux/interrupt.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/sched_clock.h>
16 #include <linux/slab.h>
18 #define MCHP_PIT64B_CR 0x00 /* Control Register */
19 #define MCHP_PIT64B_CR_START BIT(0)
20 #define MCHP_PIT64B_CR_SWRST BIT(8)
22 #define MCHP_PIT64B_MR 0x04 /* Mode Register */
23 #define MCHP_PIT64B_MR_CONT BIT(0)
24 #define MCHP_PIT64B_MR_ONE_SHOT (0)
25 #define MCHP_PIT64B_MR_SGCLK BIT(3)
26 #define MCHP_PIT64B_MR_PRES GENMASK(11, 8)
28 #define MCHP_PIT64B_LSB_PR 0x08 /* LSB Period Register */
30 #define MCHP_PIT64B_MSB_PR 0x0C /* MSB Period Register */
32 #define MCHP_PIT64B_IER 0x10 /* Interrupt Enable Register */
33 #define MCHP_PIT64B_IER_PERIOD BIT(0)
35 #define MCHP_PIT64B_ISR 0x1C /* Interrupt Status Register */
37 #define MCHP_PIT64B_TLSBR 0x20 /* Timer LSB Register */
39 #define MCHP_PIT64B_TMSBR 0x24 /* Timer MSB Register */
41 #define MCHP_PIT64B_PRES_MAX 0x10
42 #define MCHP_PIT64B_LSBMASK GENMASK_ULL(31, 0)
43 #define MCHP_PIT64B_PRES_TO_MODE(p) (MCHP_PIT64B_MR_PRES & ((p) << 8))
44 #define MCHP_PIT64B_MODE_TO_PRES(m) ((MCHP_PIT64B_MR_PRES & (m)) >> 8)
45 #define MCHP_PIT64B_DEF_FREQ 5000000UL /* 5 MHz */
47 #define MCHP_PIT64B_NAME "pit64b"
50 * struct mchp_pit64b_timer - PIT64B timer data structure
51 * @base: base address of PIT64B hardware block
52 * @pclk: PIT64B's peripheral clock
53 * @gclk: PIT64B's generic clock
54 * @mode: precomputed value for mode register
56 struct mchp_pit64b_timer {
64 * mchp_pit64b_clkevt - PIT64B clockevent data structure
65 * @timer: PIT64B timer
68 struct mchp_pit64b_clkevt {
69 struct mchp_pit64b_timer timer;
70 struct clock_event_device clkevt;
73 #define clkevt_to_mchp_pit64b_timer(x) \
74 ((struct mchp_pit64b_timer *)container_of(x,\
75 struct mchp_pit64b_clkevt, clkevt))
78 * mchp_pit64b_clksrc - PIT64B clocksource data structure
79 * @timer: PIT64B timer
80 * @clksrc: clocksource
82 struct mchp_pit64b_clksrc {
83 struct mchp_pit64b_timer timer;
84 struct clocksource clksrc;
87 #define clksrc_to_mchp_pit64b_timer(x) \
88 ((struct mchp_pit64b_timer *)container_of(x,\
89 struct mchp_pit64b_clksrc, clksrc))
91 /* Base address for clocksource timer. */
92 static void __iomem *mchp_pit64b_cs_base;
93 /* Default cycles for clockevent timer. */
94 static u64 mchp_pit64b_ce_cycles;
96 static inline u64 mchp_pit64b_cnt_read(void __iomem *base)
101 raw_local_irq_save(flags);
104 * When using a 64 bit period TLSB must be read first, followed by the
105 * read of TMSB. This sequence generates an atomic read of the 64 bit
106 * timer value whatever the lapse of time between the accesses.
108 low = readl_relaxed(base + MCHP_PIT64B_TLSBR);
109 high = readl_relaxed(base + MCHP_PIT64B_TMSBR);
111 raw_local_irq_restore(flags);
113 return (((u64)high << 32) | low);
116 static inline void mchp_pit64b_reset(struct mchp_pit64b_timer *timer,
117 u64 cycles, u32 mode, u32 irqs)
121 low = cycles & MCHP_PIT64B_LSBMASK;
124 writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
125 writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR);
126 writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR);
127 writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR);
128 writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER);
129 writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);
132 static void mchp_pit64b_suspend(struct mchp_pit64b_timer *timer)
134 writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
135 if (timer->mode & MCHP_PIT64B_MR_SGCLK)
136 clk_disable_unprepare(timer->gclk);
137 clk_disable_unprepare(timer->pclk);
140 static void mchp_pit64b_resume(struct mchp_pit64b_timer *timer)
142 clk_prepare_enable(timer->pclk);
143 if (timer->mode & MCHP_PIT64B_MR_SGCLK)
144 clk_prepare_enable(timer->gclk);
147 static void mchp_pit64b_clksrc_suspend(struct clocksource *cs)
149 struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);
151 mchp_pit64b_suspend(timer);
154 static void mchp_pit64b_clksrc_resume(struct clocksource *cs)
156 struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);
158 mchp_pit64b_resume(timer);
159 mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
162 static u64 mchp_pit64b_clksrc_read(struct clocksource *cs)
164 return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
167 static u64 notrace mchp_pit64b_sched_read_clk(void)
169 return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
172 static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev)
174 struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
176 writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
181 static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev)
183 struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
185 mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT,
186 MCHP_PIT64B_IER_PERIOD);
191 static int mchp_pit64b_clkevt_set_next_event(unsigned long evt,
192 struct clock_event_device *cedev)
194 struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
196 mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT,
197 MCHP_PIT64B_IER_PERIOD);
202 static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev)
204 struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
206 mchp_pit64b_suspend(timer);
209 static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev)
211 struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
213 mchp_pit64b_resume(timer);
216 static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id)
218 struct mchp_pit64b_clkevt *irq_data = dev_id;
220 /* Need to clear the interrupt. */
221 readl_relaxed(irq_data->timer.base + MCHP_PIT64B_ISR);
223 irq_data->clkevt.event_handler(&irq_data->clkevt);
228 static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate,
233 for (*pres = 0; *pres < MCHP_PIT64B_PRES_MAX; (*pres)++) {
234 tmp = clk_rate / (*pres + 1);
239 /* Use the biggest prescaler if we didn't match one. */
240 if (*pres == MCHP_PIT64B_PRES_MAX)
241 *pres = MCHP_PIT64B_PRES_MAX - 1;
245 * mchp_pit64b_init_mode - prepare PIT64B mode register value to be used at
246 * runtime; this includes prescaler and SGCLK bit
248 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
249 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
250 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
251 * divided by the internal PIT64B's divider.
253 * This function, first tries to use GCLK by requesting the desired rate from
254 * PMC and then using the internal PIT64B prescaler, if any, to reach the
255 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
256 * then the function falls back on using PCLK as clock source for PIT64B timer
257 * choosing the highest prescaler in case it doesn't locate one to match the
258 * requested frequency.
260 * Below is presented the PIT64B block in relation with PMC:
263 * PMC +------------------------------------+
265 * | |-->gclk -->|-->| | +---------+ +-----+ |
266 * | | | | MUX |--->| Divider |->|timer| |
267 * | |-->pclk -->|-->| | +---------+ +-----+ |
271 * +------------------------------------+
274 * - gclk rate <= pclk rate/3
275 * - gclk rate could be requested from PMC
276 * - pclk rate is fixed (cannot be requested from PMC)
278 static int __init mchp_pit64b_init_mode(struct mchp_pit64b_timer *timer,
279 unsigned long max_rate)
281 unsigned long pclk_rate, diff = 0, best_diff = ULONG_MAX;
283 u32 pres, best_pres = 0;
285 pclk_rate = clk_get_rate(timer->pclk);
291 /* Try using GCLK. */
292 gclk_round = clk_round_rate(timer->gclk, max_rate);
296 if (pclk_rate / gclk_round < 3)
299 mchp_pit64b_pres_compute(&pres, gclk_round, max_rate);
300 best_diff = abs(gclk_round / (pres + 1) - max_rate);
304 timer->mode |= MCHP_PIT64B_MR_SGCLK;
305 clk_set_rate(timer->gclk, gclk_round);
310 /* Check if requested rate could be obtained using PCLK. */
311 mchp_pit64b_pres_compute(&pres, pclk_rate, max_rate);
312 diff = abs(pclk_rate / (pres + 1) - max_rate);
314 if (best_diff > diff) {
319 timer->mode |= MCHP_PIT64B_MR_SGCLK;
320 clk_set_rate(timer->gclk, gclk_round);
324 timer->mode |= MCHP_PIT64B_PRES_TO_MODE(best_pres);
326 pr_info("PIT64B: using clk=%s with prescaler %u, freq=%lu [Hz]\n",
327 timer->mode & MCHP_PIT64B_MR_SGCLK ? "gclk" : "pclk", best_pres,
328 timer->mode & MCHP_PIT64B_MR_SGCLK ?
329 gclk_round / (best_pres + 1) : pclk_rate / (best_pres + 1));
334 static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer,
337 struct mchp_pit64b_clksrc *cs;
340 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
344 mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
346 mchp_pit64b_cs_base = timer->base;
348 cs->timer.base = timer->base;
349 cs->timer.pclk = timer->pclk;
350 cs->timer.gclk = timer->gclk;
351 cs->timer.mode = timer->mode;
352 cs->clksrc.name = MCHP_PIT64B_NAME;
353 cs->clksrc.mask = CLOCKSOURCE_MASK(64);
354 cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
355 cs->clksrc.rating = 210;
356 cs->clksrc.read = mchp_pit64b_clksrc_read;
357 cs->clksrc.suspend = mchp_pit64b_clksrc_suspend;
358 cs->clksrc.resume = mchp_pit64b_clksrc_resume;
360 ret = clocksource_register_hz(&cs->clksrc, clk_rate);
362 pr_debug("clksrc: Failed to register PIT64B clocksource!\n");
365 writel_relaxed(MCHP_PIT64B_CR_SWRST,
366 timer->base + MCHP_PIT64B_CR);
372 sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate);
377 static int __init mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer,
378 u32 clk_rate, u32 irq)
380 struct mchp_pit64b_clkevt *ce;
383 ce = kzalloc(sizeof(*ce), GFP_KERNEL);
387 mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ);
389 ce->timer.base = timer->base;
390 ce->timer.pclk = timer->pclk;
391 ce->timer.gclk = timer->gclk;
392 ce->timer.mode = timer->mode;
393 ce->clkevt.name = MCHP_PIT64B_NAME;
394 ce->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
395 ce->clkevt.rating = 150;
396 ce->clkevt.set_state_shutdown = mchp_pit64b_clkevt_shutdown;
397 ce->clkevt.set_state_periodic = mchp_pit64b_clkevt_set_periodic;
398 ce->clkevt.set_next_event = mchp_pit64b_clkevt_set_next_event;
399 ce->clkevt.suspend = mchp_pit64b_clkevt_suspend;
400 ce->clkevt.resume = mchp_pit64b_clkevt_resume;
401 ce->clkevt.cpumask = cpumask_of(0);
402 ce->clkevt.irq = irq;
404 ret = request_irq(irq, mchp_pit64b_interrupt, IRQF_TIMER,
407 pr_debug("clkevt: Failed to setup PIT64B IRQ\n");
412 clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX);
417 static int __init mchp_pit64b_dt_init_timer(struct device_node *node,
420 struct mchp_pit64b_timer timer;
421 unsigned long clk_rate;
426 timer.pclk = of_clk_get_by_name(node, "pclk");
427 if (IS_ERR(timer.pclk))
428 return PTR_ERR(timer.pclk);
430 timer.gclk = of_clk_get_by_name(node, "gclk");
431 if (IS_ERR(timer.gclk))
432 return PTR_ERR(timer.gclk);
434 timer.base = of_iomap(node, 0);
439 irq = irq_of_parse_and_map(node, 0);
446 /* Initialize mode (prescaler + SGCK bit). To be used at runtime. */
447 ret = mchp_pit64b_init_mode(&timer, MCHP_PIT64B_DEF_FREQ);
451 ret = clk_prepare_enable(timer.pclk);
455 if (timer.mode & MCHP_PIT64B_MR_SGCLK) {
456 ret = clk_prepare_enable(timer.gclk);
460 clk_rate = clk_get_rate(timer.gclk);
462 clk_rate = clk_get_rate(timer.pclk);
464 clk_rate = clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1);
467 ret = mchp_pit64b_init_clkevt(&timer, clk_rate, irq);
469 ret = mchp_pit64b_init_clksrc(&timer, clk_rate);
477 if (timer.mode & MCHP_PIT64B_MR_SGCLK)
478 clk_disable_unprepare(timer.gclk);
480 clk_disable_unprepare(timer.pclk);
482 irq_dispose_mapping(irq);
489 static int __init mchp_pit64b_dt_init(struct device_node *node)
495 /* 1st request, register clockevent. */
496 return mchp_pit64b_dt_init_timer(node, true);
498 /* 2nd request, register clocksource. */
499 return mchp_pit64b_dt_init_timer(node, false);
502 /* The rest, don't care. */
506 TIMER_OF_DECLARE(mchp_pit64b, "microchip,sam9x60-pit64b", mchp_pit64b_dt_init);