1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Western Digital Corporation or its affiliates.
5 * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
6 * CLINT MMIO timer device.
9 #define pr_fmt(fmt) "clint: " fmt
10 #include <linux/bitops.h>
11 #include <linux/clocksource.h>
12 #include <linux/clockchips.h>
13 #include <linux/cpu.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/of_address.h>
17 #include <linux/sched_clock.h>
18 #include <linux/io-64-nonatomic-lo-hi.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_irq.h>
21 #include <linux/smp.h>
22 #include <linux/timex.h>
24 #ifndef CONFIG_RISCV_M_MODE
25 #include <asm/clint.h>
28 #define CLINT_IPI_OFF 0
29 #define CLINT_TIMER_CMP_OFF 0x4000
30 #define CLINT_TIMER_VAL_OFF 0xbff8
32 /* CLINT manages IPI and Timer for RISC-V M-mode */
33 static u32 __iomem *clint_ipi_base;
34 static u64 __iomem *clint_timer_cmp;
35 static u64 __iomem *clint_timer_val;
36 static unsigned long clint_timer_freq;
37 static unsigned int clint_timer_irq;
39 #ifdef CONFIG_RISCV_M_MODE
40 u64 __iomem *clint_time_val;
41 EXPORT_SYMBOL(clint_time_val);
44 static void clint_send_ipi(const struct cpumask *target)
48 for_each_cpu(cpu, target)
49 writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu));
52 static void clint_clear_ipi(void)
54 writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id()));
57 static struct riscv_ipi_ops clint_ipi_ops = {
58 .ipi_inject = clint_send_ipi,
59 .ipi_clear = clint_clear_ipi,
63 #define clint_get_cycles() readq_relaxed(clint_timer_val)
65 #define clint_get_cycles() readl_relaxed(clint_timer_val)
66 #define clint_get_cycles_hi() readl_relaxed(((u32 *)clint_timer_val) + 1)
70 static u64 notrace clint_get_cycles64(void)
72 return clint_get_cycles();
74 #else /* CONFIG_64BIT */
75 static u64 notrace clint_get_cycles64(void)
80 hi = clint_get_cycles_hi();
81 lo = clint_get_cycles();
82 } while (hi != clint_get_cycles_hi());
84 return ((u64)hi << 32) | lo;
86 #endif /* CONFIG_64BIT */
88 static u64 clint_rdtime(struct clocksource *cs)
90 return clint_get_cycles64();
93 static struct clocksource clint_clocksource = {
94 .name = "clint_clocksource",
96 .mask = CLOCKSOURCE_MASK(64),
97 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
101 static int clint_clock_next_event(unsigned long delta,
102 struct clock_event_device *ce)
104 void __iomem *r = clint_timer_cmp +
105 cpuid_to_hartid_map(smp_processor_id());
107 csr_set(CSR_IE, IE_TIE);
108 writeq_relaxed(clint_get_cycles64() + delta, r);
112 static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = {
113 .name = "clint_clockevent",
114 .features = CLOCK_EVT_FEAT_ONESHOT,
116 .set_next_event = clint_clock_next_event,
119 static int clint_timer_starting_cpu(unsigned int cpu)
121 struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu);
123 ce->cpumask = cpumask_of(cpu);
124 clockevents_config_and_register(ce, clint_timer_freq, 100, 0x7fffffff);
126 enable_percpu_irq(clint_timer_irq,
127 irq_get_trigger_type(clint_timer_irq));
131 static int clint_timer_dying_cpu(unsigned int cpu)
133 disable_percpu_irq(clint_timer_irq);
137 static irqreturn_t clint_timer_interrupt(int irq, void *dev_id)
139 struct clock_event_device *evdev = this_cpu_ptr(&clint_clock_event);
141 csr_clear(CSR_IE, IE_TIE);
142 evdev->event_handler(evdev);
147 static int __init clint_timer_init_dt(struct device_node *np)
152 struct of_phandle_args oirq;
155 * Ensure that CLINT device interrupts are either RV_IRQ_TIMER or
156 * RV_IRQ_SOFT. If it's anything else then we ignore the device.
158 nr_irqs = of_irq_count(np);
159 for (i = 0; i < nr_irqs; i++) {
160 if (of_irq_parse_one(np, i, &oirq)) {
161 pr_err("%pOFP: failed to parse irq %d.\n", np, i);
165 if ((oirq.args_count != 1) ||
166 (oirq.args[0] != RV_IRQ_TIMER &&
167 oirq.args[0] != RV_IRQ_SOFT)) {
168 pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
169 np, i, oirq.args[0]);
173 /* Find parent irq domain and map timer irq */
174 if (!clint_timer_irq &&
175 oirq.args[0] == RV_IRQ_TIMER &&
176 irq_find_host(oirq.np))
177 clint_timer_irq = irq_of_parse_and_map(np, i);
180 /* If CLINT timer irq not found then fail */
181 if (!clint_timer_irq) {
182 pr_err("%pOFP: timer irq not found\n", np);
186 base = of_iomap(np, 0);
188 pr_err("%pOFP: could not map registers\n", np);
192 clint_ipi_base = base + CLINT_IPI_OFF;
193 clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
194 clint_timer_val = base + CLINT_TIMER_VAL_OFF;
195 clint_timer_freq = riscv_timebase;
197 #ifdef CONFIG_RISCV_M_MODE
199 * Yes, that's an odd naming scheme. time_val is public, but hopefully
200 * will die in favor of something cleaner.
202 clint_time_val = clint_timer_val;
205 pr_info("%pOFP: timer running at %ld Hz\n", np, clint_timer_freq);
207 rc = clocksource_register_hz(&clint_clocksource, clint_timer_freq);
209 pr_err("%pOFP: clocksource register failed [%d]\n", np, rc);
213 sched_clock_register(clint_get_cycles64, 64, clint_timer_freq);
215 rc = request_percpu_irq(clint_timer_irq, clint_timer_interrupt,
216 "clint-timer", &clint_clock_event);
218 pr_err("registering percpu irq failed [%d]\n", rc);
222 rc = cpuhp_setup_state(CPUHP_AP_CLINT_TIMER_STARTING,
223 "clockevents/clint/timer:starting",
224 clint_timer_starting_cpu,
225 clint_timer_dying_cpu);
227 pr_err("%pOFP: cpuhp setup state failed [%d]\n", np, rc);
231 riscv_set_ipi_ops(&clint_ipi_ops);
237 free_irq(clint_timer_irq, &clint_clock_event);
243 TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
244 TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);