drivers/clocksource/timer-clint.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2020 Western Digital Corporation or its affiliates.
   4  *
   5  * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
   6  * CLINT MMIO timer device.
   7  */
   8
   9 #define pr_fmt(fmt) "clint: " fmt
  10 #include <linux/bitops.h>
  11 #include <linux/clocksource.h>
  12 #include <linux/clockchips.h>
  13 #include <linux/cpu.h>
  14 #include <linux/delay.h>
  15 #include <linux/module.h>
  16 #include <linux/of_address.h>
  17 #include <linux/sched_clock.h>
  18 #include <linux/io-64-nonatomic-lo-hi.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/smp.h>
  22 #include <linux/timex.h>
  23
  24 #ifndef CONFIG_RISCV_M_MODE
  25 #include <asm/clint.h>
  26 #endif
  27
  28 #define CLINT_IPI_OFF           0
  29 #define CLINT_TIMER_CMP_OFF     0x4000
  30 #define CLINT_TIMER_VAL_OFF     0xbff8
  31
  32 /* CLINT manages IPI and Timer for RISC-V M-mode  */
  33 static u32 __iomem *clint_ipi_base;
  34 static u64 __iomem *clint_timer_cmp;
  35 static u64 __iomem *clint_timer_val;
  36 static unsigned long clint_timer_freq;
  37 static unsigned int clint_timer_irq;
  38
  39 #ifdef CONFIG_RISCV_M_MODE
  40 u64 __iomem *clint_time_val;
  41 #endif
  42
  43 static void clint_send_ipi(const struct cpumask *target)
  44 {
  45         unsigned int cpu;
  46
  47         for_each_cpu(cpu, target)
  48                 writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu));
  49 }
  50
  51 static void clint_clear_ipi(void)
  52 {
  53         writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id()));
  54 }
  55
  56 static struct riscv_ipi_ops clint_ipi_ops = {
  57         .ipi_inject = clint_send_ipi,
  58         .ipi_clear = clint_clear_ipi,
  59 };
  60
  61 #ifdef CONFIG_64BIT
  62 #define clint_get_cycles()      readq_relaxed(clint_timer_val)
  63 #else
  64 #define clint_get_cycles()      readl_relaxed(clint_timer_val)
  65 #define clint_get_cycles_hi()   readl_relaxed(((u32 *)clint_timer_val) + 1)
  66 #endif
  67
  68 #ifdef CONFIG_64BIT
  69 static u64 notrace clint_get_cycles64(void)
  70 {
  71         return clint_get_cycles();
  72 }
  73 #else /* CONFIG_64BIT */
  74 static u64 notrace clint_get_cycles64(void)
  75 {
  76         u32 hi, lo;
  77
  78         do {
  79                 hi = clint_get_cycles_hi();
  80                 lo = clint_get_cycles();
  81         } while (hi != clint_get_cycles_hi());
  82
  83         return ((u64)hi << 32) | lo;
  84 }
  85 #endif /* CONFIG_64BIT */
  86
  87 static u64 clint_rdtime(struct clocksource *cs)
  88 {
  89         return clint_get_cycles64();
  90 }
  91
  92 static struct clocksource clint_clocksource = {
  93         .name           = "clint_clocksource",
  94         .rating         = 300,
  95         .mask           = CLOCKSOURCE_MASK(64),
  96         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  97         .read           = clint_rdtime,
  98 };
  99
 100 static int clint_clock_next_event(unsigned long delta,
 101                                    struct clock_event_device *ce)
 102 {
 103         void __iomem *r = clint_timer_cmp +
 104                           cpuid_to_hartid_map(smp_processor_id());
 105
 106         csr_set(CSR_IE, IE_TIE);
 107         writeq_relaxed(clint_get_cycles64() + delta, r);
 108         return 0;
 109 }
 110
 111 static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = {
 112         .name           = "clint_clockevent",
 113         .features       = CLOCK_EVT_FEAT_ONESHOT,
 114         .rating         = 100,
 115         .set_next_event = clint_clock_next_event,
 116 };
 117
 118 static int clint_timer_starting_cpu(unsigned int cpu)
 119 {
 120         struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu);
 121
 122         ce->cpumask = cpumask_of(cpu);
 123         clockevents_config_and_register(ce, clint_timer_freq, 100, 0x7fffffff);
 124
 125         enable_percpu_irq(clint_timer_irq,
 126                           irq_get_trigger_type(clint_timer_irq));
 127         return 0;
 128 }
 129
 130 static int clint_timer_dying_cpu(unsigned int cpu)
 131 {
 132         disable_percpu_irq(clint_timer_irq);
 133         return 0;
 134 }
 135
 136 static irqreturn_t clint_timer_interrupt(int irq, void *dev_id)
 137 {
 138         struct clock_event_device *evdev = this_cpu_ptr(&clint_clock_event);
 139
 140         csr_clear(CSR_IE, IE_TIE);
 141         evdev->event_handler(evdev);
 142
 143         return IRQ_HANDLED;
 144 }
 145
 146 static int __init clint_timer_init_dt(struct device_node *np)
 147 {
 148         int rc;
 149         u32 i, nr_irqs;
 150         void __iomem *base;
 151         struct of_phandle_args oirq;
 152
 153         /*
 154          * Ensure that CLINT device interrupts are either RV_IRQ_TIMER or
 155          * RV_IRQ_SOFT. If it's anything else then we ignore the device.
 156          */
 157         nr_irqs = of_irq_count(np);
 158         for (i = 0; i < nr_irqs; i++) {
 159                 if (of_irq_parse_one(np, i, &oirq)) {
 160                         pr_err("%pOFP: failed to parse irq %d.\n", np, i);
 161                         continue;
 162                 }
 163
 164                 if ((oirq.args_count != 1) ||
 165                     (oirq.args[0] != RV_IRQ_TIMER &&
 166                      oirq.args[0] != RV_IRQ_SOFT)) {
 167                         pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
 168                                np, i, oirq.args[0]);
 169                         return -ENODEV;
 170                 }
 171
 172                 /* Find parent irq domain and map timer irq */
 173                 if (!clint_timer_irq &&
 174                     oirq.args[0] == RV_IRQ_TIMER &&
 175                     irq_find_host(oirq.np))
 176                         clint_timer_irq = irq_of_parse_and_map(np, i);
 177         }
 178
 179         /* If CLINT timer irq not found then fail */
 180         if (!clint_timer_irq) {
 181                 pr_err("%pOFP: timer irq not found\n", np);
 182                 return -ENODEV;
 183         }
 184
 185         base = of_iomap(np, 0);
 186         if (!base) {
 187                 pr_err("%pOFP: could not map registers\n", np);
 188                 return -ENODEV;
 189         }
 190
 191         clint_ipi_base = base + CLINT_IPI_OFF;
 192         clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
 193         clint_timer_val = base + CLINT_TIMER_VAL_OFF;
 194         clint_timer_freq = riscv_timebase;
 195
 196 #ifdef CONFIG_RISCV_M_MODE
 197         /*
 198          * Yes, that's an odd naming scheme.  time_val is public, but hopefully
 199          * will die in favor of something cleaner.
 200          */
 201         clint_time_val = clint_timer_val;
 202 #endif
 203
 204         pr_info("%pOFP: timer running at %ld Hz\n", np, clint_timer_freq);
 205
 206         rc = clocksource_register_hz(&clint_clocksource, clint_timer_freq);
 207         if (rc) {
 208                 pr_err("%pOFP: clocksource register failed [%d]\n", np, rc);
 209                 goto fail_iounmap;
 210         }
 211
 212         sched_clock_register(clint_get_cycles64, 64, clint_timer_freq);
 213
 214         rc = request_percpu_irq(clint_timer_irq, clint_timer_interrupt,
 215                                  "clint-timer", &clint_clock_event);
 216         if (rc) {
 217                 pr_err("registering percpu irq failed [%d]\n", rc);
 218                 goto fail_iounmap;
 219         }
 220
 221         rc = cpuhp_setup_state(CPUHP_AP_CLINT_TIMER_STARTING,
 222                                 "clockevents/clint/timer:starting",
 223                                 clint_timer_starting_cpu,
 224                                 clint_timer_dying_cpu);
 225         if (rc) {
 226                 pr_err("%pOFP: cpuhp setup state failed [%d]\n", np, rc);
 227                 goto fail_free_irq;
 228         }
 229
 230         riscv_set_ipi_ops(&clint_ipi_ops);
 231         clint_clear_ipi();
 232
 233         return 0;
 234
 235 fail_free_irq:
 236         free_irq(clint_timer_irq, &clint_clock_event);
 237 fail_iounmap:
 238         iounmap(base);
 239         return rc;
 240 }
 241
 242 TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
 243 TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);