drivers/clocksource/timer-atmel-tcb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/init.h>
   3 #include <linux/clocksource.h>
   4 #include <linux/clockchips.h>
   5 #include <linux/interrupt.h>
   6 #include <linux/irq.h>
   7
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/err.h>
  11 #include <linux/ioport.h>
  12 #include <linux/io.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/sched_clock.h>
  16 #include <linux/syscore_ops.h>
  17 #include <soc/at91/atmel_tcb.h>
  18
  19
  20 /*
  21  * We're configured to use a specific TC block, one that's not hooked
  22  * up to external hardware, to provide a time solution:
  23  *
  24  *   - Two channels combine to create a free-running 32 bit counter
  25  *     with a base rate of 5+ MHz, packaged as a clocksource (with
  26  *     resolution better than 200 nsec).
  27  *   - Some chips support 32 bit counter. A single channel is used for
  28  *     this 32 bit free-running counter. the second channel is not used.
  29  *
  30  *   - The third channel may be used to provide a 16-bit clockevent
  31  *     source, used in either periodic or oneshot mode.  This runs
  32  *     at 32 KiHZ, and can handle delays of up to two seconds.
  33  *
  34  * REVISIT behavior during system suspend states... we should disable
  35  * all clocks and save the power.  Easily done for clockevent devices,
  36  * but clocksources won't necessarily get the needed notifications.
  37  * For deeper system sleep states, this will be mandatory...
  38  */
  39
  40 static void __iomem *tcaddr;
  41 static struct
  42 {
  43         u32 cmr;
  44         u32 imr;
  45         u32 rc;
  46         bool clken;
  47 } tcb_cache[3];
  48 static u32 bmr_cache;
  49
  50 static u64 tc_get_cycles(struct clocksource *cs)
  51 {
  52         unsigned long   flags;
  53         u32             lower, upper;
  54
  55         raw_local_irq_save(flags);
  56         do {
  57                 upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV));
  58                 lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
  59         } while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)));
  60
  61         raw_local_irq_restore(flags);
  62         return (upper << 16) | lower;
  63 }
  64
  65 static u64 tc_get_cycles32(struct clocksource *cs)
  66 {
  67         return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV));
  68 }
  69
  70 static void tc_clksrc_suspend(struct clocksource *cs)
  71 {
  72         int i;
  73
  74         for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
  75                 tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));
  76                 tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));
  77                 tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));
  78                 tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &
  79                                         ATMEL_TC_CLKSTA);
  80         }
  81
  82         bmr_cache = readl(tcaddr + ATMEL_TC_BMR);
  83 }
  84
  85 static void tc_clksrc_resume(struct clocksource *cs)
  86 {
  87         int i;
  88
  89         for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
  90                 /* Restore registers for the channel, RA and RB are not used  */
  91                 writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));
  92                 writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));
  93                 writel(0, tcaddr + ATMEL_TC_REG(i, RA));
  94                 writel(0, tcaddr + ATMEL_TC_REG(i, RB));
  95                 /* Disable all the interrupts */
  96                 writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));
  97                 /* Reenable interrupts that were enabled before suspending */
  98                 writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));
  99                 /* Start the clock if it was used */
 100                 if (tcb_cache[i].clken)
 101                         writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));
 102         }
 103
 104         /* Dual channel, chain channels */
 105         writel(bmr_cache, tcaddr + ATMEL_TC_BMR);
 106         /* Finally, trigger all the channels*/
 107         writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 108 }
 109
 110 static struct clocksource clksrc = {
 111         .rating         = 200,
 112         .read           = tc_get_cycles,
 113         .mask           = CLOCKSOURCE_MASK(32),
 114         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 115         .suspend        = tc_clksrc_suspend,
 116         .resume         = tc_clksrc_resume,
 117 };
 118
 119 static u64 notrace tc_sched_clock_read(void)
 120 {
 121         return tc_get_cycles(&clksrc);
 122 }
 123
 124 static u64 notrace tc_sched_clock_read32(void)
 125 {
 126         return tc_get_cycles32(&clksrc);
 127 }
 128
 129 static struct delay_timer tc_delay_timer;
 130
 131 static unsigned long tc_delay_timer_read(void)
 132 {
 133         return tc_get_cycles(&clksrc);
 134 }
 135
 136 static unsigned long notrace tc_delay_timer_read32(void)
 137 {
 138         return tc_get_cycles32(&clksrc);
 139 }
 140
 141 #ifdef CONFIG_GENERIC_CLOCKEVENTS
 142
 143 struct tc_clkevt_device {
 144         struct clock_event_device       clkevt;
 145         struct clk                      *clk;
 146         void __iomem                    *regs;
 147 };
 148
 149 static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
 150 {
 151         return container_of(clkevt, struct tc_clkevt_device, clkevt);
 152 }
 153
 154 /* For now, we always use the 32K clock ... this optimizes for NO_HZ,
 155  * because using one of the divided clocks would usually mean the
 156  * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
 157  *
 158  * A divided clock could be good for high resolution timers, since
 159  * 30.5 usec resolution can seem "low".
 160  */
 161 static u32 timer_clock;
 162
 163 static int tc_shutdown(struct clock_event_device *d)
 164 {
 165         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
 166         void __iomem            *regs = tcd->regs;
 167
 168         writel(0xff, regs + ATMEL_TC_REG(2, IDR));
 169         writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
 170         if (!clockevent_state_detached(d))
 171                 clk_disable(tcd->clk);
 172
 173         return 0;
 174 }
 175
 176 static int tc_set_oneshot(struct clock_event_device *d)
 177 {
 178         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
 179         void __iomem            *regs = tcd->regs;
 180
 181         if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
 182                 tc_shutdown(d);
 183
 184         clk_enable(tcd->clk);
 185
 186         /* slow clock, count up to RC, then irq and stop */
 187         writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
 188                      ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
 189         writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 190
 191         /* set_next_event() configures and starts the timer */
 192         return 0;
 193 }
 194
 195 static int tc_set_periodic(struct clock_event_device *d)
 196 {
 197         struct tc_clkevt_device *tcd = to_tc_clkevt(d);
 198         void __iomem            *regs = tcd->regs;
 199
 200         if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
 201                 tc_shutdown(d);
 202
 203         /* By not making the gentime core emulate periodic mode on top
 204          * of oneshot, we get lower overhead and improved accuracy.
 205          */
 206         clk_enable(tcd->clk);
 207
 208         /* slow clock, count up to RC, then irq and restart */
 209         writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
 210                      regs + ATMEL_TC_REG(2, CMR));
 211         writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
 212
 213         /* Enable clock and interrupts on RC compare */
 214         writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
 215
 216         /* go go gadget! */
 217         writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
 218                      ATMEL_TC_REG(2, CCR));
 219         return 0;
 220 }
 221
 222 static int tc_next_event(unsigned long delta, struct clock_event_device *d)
 223 {
 224         writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC));
 225
 226         /* go go gadget! */
 227         writel_relaxed(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
 228                         tcaddr + ATMEL_TC_REG(2, CCR));
 229         return 0;
 230 }
 231
 232 static struct tc_clkevt_device clkevt = {
 233         .clkevt = {
 234                 .features               = CLOCK_EVT_FEAT_PERIODIC |
 235                                           CLOCK_EVT_FEAT_ONESHOT,
 236                 /* Should be lower than at91rm9200's system timer */
 237                 .rating                 = 125,
 238                 .set_next_event         = tc_next_event,
 239                 .set_state_shutdown     = tc_shutdown,
 240                 .set_state_periodic     = tc_set_periodic,
 241                 .set_state_oneshot      = tc_set_oneshot,
 242         },
 243 };
 244
 245 static irqreturn_t ch2_irq(int irq, void *handle)
 246 {
 247         struct tc_clkevt_device *dev = handle;
 248         unsigned int            sr;
 249
 250         sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR));
 251         if (sr & ATMEL_TC_CPCS) {
 252                 dev->clkevt.event_handler(&dev->clkevt);
 253                 return IRQ_HANDLED;
 254         }
 255
 256         return IRQ_NONE;
 257 }
 258
 259 static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
 260 {
 261         int ret;
 262         struct clk *t2_clk = tc->clk[2];
 263         int irq = tc->irq[2];
 264
 265         ret = clk_prepare_enable(tc->slow_clk);
 266         if (ret)
 267                 return ret;
 268
 269         /* try to enable t2 clk to avoid future errors in mode change */
 270         ret = clk_prepare_enable(t2_clk);
 271         if (ret) {
 272                 clk_disable_unprepare(tc->slow_clk);
 273                 return ret;
 274         }
 275
 276         clk_disable(t2_clk);
 277
 278         clkevt.regs = tc->regs;
 279         clkevt.clk = t2_clk;
 280
 281         timer_clock = clk32k_divisor_idx;
 282
 283         clkevt.clkevt.cpumask = cpumask_of(0);
 284
 285         ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
 286         if (ret) {
 287                 clk_unprepare(t2_clk);
 288                 clk_disable_unprepare(tc->slow_clk);
 289                 return ret;
 290         }
 291
 292         clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
 293
 294         return ret;
 295 }
 296
 297 #else /* !CONFIG_GENERIC_CLOCKEVENTS */
 298
 299 static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
 300 {
 301         /* NOTHING */
 302         return 0;
 303 }
 304
 305 #endif
 306
 307 static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
 308 {
 309         /* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
 310         writel(mck_divisor_idx                  /* likely divide-by-8 */
 311                         | ATMEL_TC_WAVE
 312                         | ATMEL_TC_WAVESEL_UP           /* free-run */
 313                         | ATMEL_TC_ACPA_SET             /* TIOA0 rises at 0 */
 314                         | ATMEL_TC_ACPC_CLEAR,          /* (duty cycle 50%) */
 315                         tcaddr + ATMEL_TC_REG(0, CMR));
 316         writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
 317         writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
 318         writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));    /* no irqs */
 319         writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 320
 321         /* channel 1:  waveform mode, input TIOA0 */
 322         writel(ATMEL_TC_XC1                     /* input: TIOA0 */
 323                         | ATMEL_TC_WAVE
 324                         | ATMEL_TC_WAVESEL_UP,          /* free-run */
 325                         tcaddr + ATMEL_TC_REG(1, CMR));
 326         writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));    /* no irqs */
 327         writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
 328
 329         /* chain channel 0 to channel 1*/
 330         writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
 331         /* then reset all the timers */
 332         writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 333 }
 334
 335 static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
 336 {
 337         /* channel 0:  waveform mode, input mclk/8 */
 338         writel(mck_divisor_idx                  /* likely divide-by-8 */
 339                         | ATMEL_TC_WAVE
 340                         | ATMEL_TC_WAVESEL_UP,          /* free-run */
 341                         tcaddr + ATMEL_TC_REG(0, CMR));
 342         writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));    /* no irqs */
 343         writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
 344
 345         /* then reset all the timers */
 346         writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
 347 }
 348
 349 static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128 };
 350
 351 static struct atmel_tcb_config tcb_rm9200_config = {
 352         .counter_width = 16,
 353 };
 354
 355 static struct atmel_tcb_config tcb_sam9x5_config = {
 356         .counter_width = 32,
 357 };
 358
 359 static const struct of_device_id atmel_tcb_of_match[] = {
 360         { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
 361         { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
 362         { /* sentinel */ }
 363 };
 364
 365 static int __init tcb_clksrc_init(struct device_node *node)
 366 {
 367         struct atmel_tc tc;
 368         struct clk *t0_clk;
 369         const struct of_device_id *match;
 370         u64 (*tc_sched_clock)(void);
 371         u32 rate, divided_rate = 0;
 372         int best_divisor_idx = -1;
 373         int bits;
 374         int i;
 375         int ret;
 376
 377         /* Protect against multiple calls */
 378         if (tcaddr)
 379                 return 0;
 380
 381         tc.regs = of_iomap(node->parent, 0);
 382         if (!tc.regs)
 383                 return -ENXIO;
 384
 385         t0_clk = of_clk_get_by_name(node->parent, "t0_clk");
 386         if (IS_ERR(t0_clk))
 387                 return PTR_ERR(t0_clk);
 388
 389         tc.slow_clk = of_clk_get_by_name(node->parent, "slow_clk");
 390         if (IS_ERR(tc.slow_clk))
 391                 return PTR_ERR(tc.slow_clk);
 392
 393         tc.clk[0] = t0_clk;
 394         tc.clk[1] = of_clk_get_by_name(node->parent, "t1_clk");
 395         if (IS_ERR(tc.clk[1]))
 396                 tc.clk[1] = t0_clk;
 397         tc.clk[2] = of_clk_get_by_name(node->parent, "t2_clk");
 398         if (IS_ERR(tc.clk[2]))
 399                 tc.clk[2] = t0_clk;
 400
 401         tc.irq[2] = of_irq_get(node->parent, 2);
 402         if (tc.irq[2] <= 0) {
 403                 tc.irq[2] = of_irq_get(node->parent, 0);
 404                 if (tc.irq[2] <= 0)
 405                         return -EINVAL;
 406         }
 407
 408         match = of_match_node(atmel_tcb_of_match, node->parent);
 409         if (!match)
 410                 return -ENODEV;
 411
 412         tc.tcb_config = match->data;
 413         bits = tc.tcb_config->counter_width;
 414
 415         for (i = 0; i < ARRAY_SIZE(tc.irq); i++)
 416                 writel(ATMEL_TC_ALL_IRQ, tc.regs + ATMEL_TC_REG(i, IDR));
 417
 418         ret = clk_prepare_enable(t0_clk);
 419         if (ret) {
 420                 pr_debug("can't enable T0 clk\n");
 421                 return ret;
 422         }
 423
 424         /* How fast will we be counting?  Pick something over 5 MHz.  */
 425         rate = (u32) clk_get_rate(t0_clk);
 426         for (i = 0; i < ARRAY_SIZE(atmel_tcb_divisors); i++) {
 427                 unsigned divisor = atmel_tcb_divisors[i];
 428                 unsigned tmp;
 429
 430                 tmp = rate / divisor;
 431                 pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
 432                 if (best_divisor_idx > 0) {
 433                         if (tmp < 5 * 1000 * 1000)
 434                                 continue;
 435                 }
 436                 divided_rate = tmp;
 437                 best_divisor_idx = i;
 438         }
 439
 440         clksrc.name = kbasename(node->parent->full_name);
 441         clkevt.clkevt.name = kbasename(node->parent->full_name);
 442         pr_debug("%s at %d.%03d MHz\n", clksrc.name, divided_rate / 1000000,
 443                         ((divided_rate % 1000000) + 500) / 1000);
 444
 445         tcaddr = tc.regs;
 446
 447         if (bits == 32) {
 448                 /* use apropriate function to read 32 bit counter */
 449                 clksrc.read = tc_get_cycles32;
 450                 /* setup ony channel 0 */
 451                 tcb_setup_single_chan(&tc, best_divisor_idx);
 452                 tc_sched_clock = tc_sched_clock_read32;
 453                 tc_delay_timer.read_current_timer = tc_delay_timer_read32;
 454         } else {
 455                 /* we have three clocks no matter what the
 456                  * underlying platform supports.
 457                  */
 458                 ret = clk_prepare_enable(tc.clk[1]);
 459                 if (ret) {
 460                         pr_debug("can't enable T1 clk\n");
 461                         goto err_disable_t0;
 462                 }
 463                 /* setup both channel 0 & 1 */
 464                 tcb_setup_dual_chan(&tc, best_divisor_idx);
 465                 tc_sched_clock = tc_sched_clock_read;
 466                 tc_delay_timer.read_current_timer = tc_delay_timer_read;
 467         }
 468
 469         /* and away we go! */
 470         ret = clocksource_register_hz(&clksrc, divided_rate);
 471         if (ret)
 472                 goto err_disable_t1;
 473
 474         /* channel 2:  periodic and oneshot timer support */
 475         ret = setup_clkevents(&tc, ATMEL_TC_TIMER_CLOCK5);
 476         if (ret)
 477                 goto err_unregister_clksrc;
 478
 479         sched_clock_register(tc_sched_clock, 32, divided_rate);
 480
 481         tc_delay_timer.freq = divided_rate;
 482         register_current_timer_delay(&tc_delay_timer);
 483
 484         return 0;
 485
 486 err_unregister_clksrc:
 487         clocksource_unregister(&clksrc);
 488
 489 err_disable_t1:
 490         if (bits != 32)
 491                 clk_disable_unprepare(tc.clk[1]);
 492
 493 err_disable_t0:
 494         clk_disable_unprepare(t0_clk);
 495
 496         tcaddr = NULL;
 497
 498         return ret;
 499 }
 500 TIMER_OF_DECLARE(atmel_tcb_clksrc, "atmel,tcb-timer", tcb_clksrc_init);