2 * Marvell Armada 370/XP SoC timer handling.
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
14 * Timer 0 is used as free-running clocksource, while timer 1 is
15 * used as clock_event_device.
18 * Clocksource driver for Armada 370 and Armada XP SoC.
19 * This driver implements one compatible string for each SoC, given
20 * each has its own characteristics:
22 * * Armada 370 has no 25 MHz fixed timer.
24 * * Armada XP cannot work properly without such 25 MHz fixed timer as
25 * doing otherwise leads to using a clocksource whose frequency varies
26 * when doing cpufreq frequency changes.
28 * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
31 #include <linux/init.h>
32 #include <linux/platform_device.h>
33 #include <linux/kernel.h>
34 #include <linux/clk.h>
35 #include <linux/cpu.h>
36 #include <linux/timer.h>
37 #include <linux/clockchips.h>
38 #include <linux/interrupt.h>
40 #include <linux/of_irq.h>
41 #include <linux/of_address.h>
42 #include <linux/irq.h>
43 #include <linux/module.h>
44 #include <linux/sched_clock.h>
45 #include <linux/percpu.h>
46 #include <linux/syscore_ops.h>
49 * Timer block registers.
51 #define TIMER_CTRL_OFF 0x0000
52 #define TIMER0_EN BIT(0)
53 #define TIMER0_RELOAD_EN BIT(1)
54 #define TIMER0_25MHZ BIT(11)
55 #define TIMER0_DIV(div) ((div) << 19)
56 #define TIMER1_EN BIT(2)
57 #define TIMER1_RELOAD_EN BIT(3)
58 #define TIMER1_25MHZ BIT(12)
59 #define TIMER1_DIV(div) ((div) << 22)
60 #define TIMER_EVENTS_STATUS 0x0004
61 #define TIMER0_CLR_MASK (~0x1)
62 #define TIMER1_CLR_MASK (~0x100)
63 #define TIMER0_RELOAD_OFF 0x0010
64 #define TIMER0_VAL_OFF 0x0014
65 #define TIMER1_RELOAD_OFF 0x0018
66 #define TIMER1_VAL_OFF 0x001c
68 #define LCL_TIMER_EVENTS_STATUS 0x0028
69 /* Global timers are connected to the coherency fabric clock, and the
70 below divider reduces their incrementing frequency. */
71 #define TIMER_DIVIDER_SHIFT 5
72 #define TIMER_DIVIDER (1 << TIMER_DIVIDER_SHIFT)
77 static void __iomem *timer_base, *local_base;
78 static unsigned int timer_clk;
79 static bool timer25Mhz = true;
80 static u32 enable_mask;
83 * Number of timer ticks per jiffy.
85 static u32 ticks_per_jiffy;
87 static struct clock_event_device __percpu *armada_370_xp_evt;
89 static void local_timer_ctrl_clrset(u32 clr, u32 set)
91 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
92 local_base + TIMER_CTRL_OFF);
95 static u64 notrace armada_370_xp_read_sched_clock(void)
97 return ~readl(timer_base + TIMER0_VAL_OFF);
101 * Clockevent handling.
104 armada_370_xp_clkevt_next_event(unsigned long delta,
105 struct clock_event_device *dev)
108 * Clear clockevent timer interrupt.
110 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
113 * Setup new clockevent timer value.
115 writel(delta, local_base + TIMER0_VAL_OFF);
120 local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
124 static int armada_370_xp_clkevt_shutdown(struct clock_event_device *evt)
129 local_timer_ctrl_clrset(TIMER0_EN, 0);
132 * ACK pending timer interrupt.
134 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
138 static int armada_370_xp_clkevt_set_periodic(struct clock_event_device *evt)
141 * Setup timer to fire at 1/HZ intervals.
143 writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
144 writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);
149 local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
153 static int armada_370_xp_clkevt_irq;
155 static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
158 * ACK timer interrupt and call event handler.
160 struct clock_event_device *evt = dev_id;
162 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
163 evt->event_handler(evt);
169 * Setup the local clock events for a CPU.
171 static int armada_370_xp_timer_setup(struct clock_event_device *evt)
173 u32 clr = 0, set = 0;
174 int cpu = smp_processor_id();
180 local_timer_ctrl_clrset(clr, set);
182 evt->name = "armada_370_xp_per_cpu_tick",
183 evt->features = CLOCK_EVT_FEAT_ONESHOT |
184 CLOCK_EVT_FEAT_PERIODIC;
187 evt->set_next_event = armada_370_xp_clkevt_next_event,
188 evt->set_state_shutdown = armada_370_xp_clkevt_shutdown;
189 evt->set_state_periodic = armada_370_xp_clkevt_set_periodic;
190 evt->set_state_oneshot = armada_370_xp_clkevt_shutdown;
191 evt->tick_resume = armada_370_xp_clkevt_shutdown;
192 evt->irq = armada_370_xp_clkevt_irq;
193 evt->cpumask = cpumask_of(cpu);
195 clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
196 enable_percpu_irq(evt->irq, 0);
201 static void armada_370_xp_timer_stop(struct clock_event_device *evt)
203 evt->set_state_shutdown(evt);
204 disable_percpu_irq(evt->irq);
207 static int armada_370_xp_timer_cpu_notify(struct notifier_block *self,
208 unsigned long action, void *hcpu)
211 * Grab cpu pointer in each case to avoid spurious
212 * preemptible warnings
214 switch (action & ~CPU_TASKS_FROZEN) {
216 armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
219 armada_370_xp_timer_stop(this_cpu_ptr(armada_370_xp_evt));
226 static struct notifier_block armada_370_xp_timer_cpu_nb = {
227 .notifier_call = armada_370_xp_timer_cpu_notify,
230 static u32 timer0_ctrl_reg, timer0_local_ctrl_reg;
232 static int armada_370_xp_timer_suspend(void)
234 timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
235 timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF);
239 static void armada_370_xp_timer_resume(void)
241 writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
242 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
243 writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
244 writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
247 struct syscore_ops armada_370_xp_timer_syscore_ops = {
248 .suspend = armada_370_xp_timer_suspend,
249 .resume = armada_370_xp_timer_resume,
252 static void __init armada_370_xp_timer_common_init(struct device_node *np)
254 u32 clr = 0, set = 0;
257 timer_base = of_iomap(np, 0);
258 WARN_ON(!timer_base);
259 local_base = of_iomap(np, 1);
263 enable_mask = TIMER0_EN;
266 enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
268 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
269 local_timer_ctrl_clrset(clr, set);
272 * We use timer 0 as clocksource, and private(local) timer 0
275 armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
277 ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
280 * Setup free-running clocksource timer (interrupts
283 writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
284 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
286 atomic_io_modify(timer_base + TIMER_CTRL_OFF,
287 TIMER0_RELOAD_EN | enable_mask,
288 TIMER0_RELOAD_EN | enable_mask);
291 * Set scale and timer for sched_clock.
293 sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
295 clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
296 "armada_370_xp_clocksource",
297 timer_clk, 300, 32, clocksource_mmio_readl_down);
299 register_cpu_notifier(&armada_370_xp_timer_cpu_nb);
301 armada_370_xp_evt = alloc_percpu(struct clock_event_device);
305 * Setup clockevent timer (interrupt-driven).
307 res = request_percpu_irq(armada_370_xp_clkevt_irq,
308 armada_370_xp_timer_interrupt,
309 "armada_370_xp_per_cpu_tick",
311 /* Immediately configure the timer on the boot CPU */
313 armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
315 register_syscore_ops(&armada_370_xp_timer_syscore_ops);
318 static void __init armada_xp_timer_init(struct device_node *np)
320 struct clk *clk = of_clk_get_by_name(np, "fixed");
322 /* The 25Mhz fixed clock is mandatory, and must always be available */
324 clk_prepare_enable(clk);
325 timer_clk = clk_get_rate(clk);
327 armada_370_xp_timer_common_init(np);
329 CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
330 armada_xp_timer_init);
332 static void __init armada_375_timer_init(struct device_node *np)
336 clk = of_clk_get_by_name(np, "fixed");
338 clk_prepare_enable(clk);
339 timer_clk = clk_get_rate(clk);
343 * This fallback is required in order to retain proper
344 * devicetree backwards compatibility.
346 clk = of_clk_get(np, 0);
348 /* Must have at least a clock */
350 clk_prepare_enable(clk);
351 timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
355 armada_370_xp_timer_common_init(np);
357 CLOCKSOURCE_OF_DECLARE(armada_375, "marvell,armada-375-timer",
358 armada_375_timer_init);
360 static void __init armada_370_timer_init(struct device_node *np)
362 struct clk *clk = of_clk_get(np, 0);
365 clk_prepare_enable(clk);
366 timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
369 armada_370_xp_timer_common_init(np);
371 CLOCKSOURCE_OF_DECLARE(armada_370, "marvell,armada-370-timer",
372 armada_370_timer_init);