1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - CMT
5 * Copyright (C) 2008 Magnus Damm
9 #include <linux/clockchips.h>
10 #include <linux/clocksource.h>
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_domain.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/sh_timer.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
29 #include <asm/platform_early.h>
35 * The CMT comes in 5 different identified flavours, depending not only on the
36 * SoC but also on the particular instance. The following table lists the main
37 * characteristics of those flavours.
39 * 16B 32B 32B-F 48B R-Car Gen2
40 * -----------------------------------------------------------------------------
41 * Channels 2 1/4 1 6 2/8
42 * Control Width 16 16 16 16 32
43 * Counter Width 16 32 32 32/48 32/48
44 * Shared Start/Stop Y Y Y Y N
46 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
47 * located in the channel registers block. All other versions have a shared
48 * start/stop register located in the global space.
50 * Channels are indexed from 0 to N-1 in the documentation. The channel index
51 * infers the start/stop bit position in the control register and the channel
52 * registers block address. Some CMT instances have a subset of channels
53 * available, in which case the index in the documentation doesn't match the
54 * "real" index as implemented in hardware. This is for instance the case with
55 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
56 * in the documentation but using start/stop bit 5 and having its registers
59 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
60 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
72 enum sh_cmt_model model;
74 unsigned int channels_mask;
76 unsigned long width; /* 16 or 32 bit version of hardware block */
80 /* callbacks for CMSTR and CMCSR access */
81 u32 (*read_control)(void __iomem *base, unsigned long offs);
82 void (*write_control)(void __iomem *base, unsigned long offs,
85 /* callbacks for CMCNT and CMCOR access */
86 u32 (*read_count)(void __iomem *base, unsigned long offs);
87 void (*write_count)(void __iomem *base, unsigned long offs, u32 value);
90 struct sh_cmt_channel {
91 struct sh_cmt_device *cmt;
93 unsigned int index; /* Index in the documentation */
94 unsigned int hwidx; /* Real hardware index */
96 void __iomem *iostart;
99 unsigned int timer_bit;
102 u32 next_match_value;
105 struct clock_event_device ced;
106 struct clocksource cs;
111 struct sh_cmt_device {
112 struct platform_device *pdev;
114 const struct sh_cmt_info *info;
116 void __iomem *mapbase;
120 raw_spinlock_t lock; /* Protect the shared start/stop register */
122 struct sh_cmt_channel *channels;
123 unsigned int num_channels;
124 unsigned int hw_channels;
127 bool has_clocksource;
130 #define SH_CMT16_CMCSR_CMF (1 << 7)
131 #define SH_CMT16_CMCSR_CMIE (1 << 6)
132 #define SH_CMT16_CMCSR_CKS8 (0 << 0)
133 #define SH_CMT16_CMCSR_CKS32 (1 << 0)
134 #define SH_CMT16_CMCSR_CKS128 (2 << 0)
135 #define SH_CMT16_CMCSR_CKS512 (3 << 0)
136 #define SH_CMT16_CMCSR_CKS_MASK (3 << 0)
138 #define SH_CMT32_CMCSR_CMF (1 << 15)
139 #define SH_CMT32_CMCSR_OVF (1 << 14)
140 #define SH_CMT32_CMCSR_WRFLG (1 << 13)
141 #define SH_CMT32_CMCSR_STTF (1 << 12)
142 #define SH_CMT32_CMCSR_STPF (1 << 11)
143 #define SH_CMT32_CMCSR_SSIE (1 << 10)
144 #define SH_CMT32_CMCSR_CMS (1 << 9)
145 #define SH_CMT32_CMCSR_CMM (1 << 8)
146 #define SH_CMT32_CMCSR_CMTOUT_IE (1 << 7)
147 #define SH_CMT32_CMCSR_CMR_NONE (0 << 4)
148 #define SH_CMT32_CMCSR_CMR_DMA (1 << 4)
149 #define SH_CMT32_CMCSR_CMR_IRQ (2 << 4)
150 #define SH_CMT32_CMCSR_CMR_MASK (3 << 4)
151 #define SH_CMT32_CMCSR_DBGIVD (1 << 3)
152 #define SH_CMT32_CMCSR_CKS_RCLK8 (4 << 0)
153 #define SH_CMT32_CMCSR_CKS_RCLK32 (5 << 0)
154 #define SH_CMT32_CMCSR_CKS_RCLK128 (6 << 0)
155 #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0)
156 #define SH_CMT32_CMCSR_CKS_MASK (7 << 0)
158 static u32 sh_cmt_read16(void __iomem *base, unsigned long offs)
160 return ioread16(base + (offs << 1));
163 static u32 sh_cmt_read32(void __iomem *base, unsigned long offs)
165 return ioread32(base + (offs << 2));
168 static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value)
170 iowrite16(value, base + (offs << 1));
173 static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value)
175 iowrite32(value, base + (offs << 2));
178 static const struct sh_cmt_info sh_cmt_info[] = {
180 .model = SH_CMT_16BIT,
182 .overflow_bit = SH_CMT16_CMCSR_CMF,
183 .clear_bits = ~SH_CMT16_CMCSR_CMF,
184 .read_control = sh_cmt_read16,
185 .write_control = sh_cmt_write16,
186 .read_count = sh_cmt_read16,
187 .write_count = sh_cmt_write16,
190 .model = SH_CMT_32BIT,
192 .overflow_bit = SH_CMT32_CMCSR_CMF,
193 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
194 .read_control = sh_cmt_read16,
195 .write_control = sh_cmt_write16,
196 .read_count = sh_cmt_read32,
197 .write_count = sh_cmt_write32,
200 .model = SH_CMT_48BIT,
201 .channels_mask = 0x3f,
203 .overflow_bit = SH_CMT32_CMCSR_CMF,
204 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
205 .read_control = sh_cmt_read32,
206 .write_control = sh_cmt_write32,
207 .read_count = sh_cmt_read32,
208 .write_count = sh_cmt_write32,
210 [SH_CMT0_RCAR_GEN2] = {
211 .model = SH_CMT0_RCAR_GEN2,
212 .channels_mask = 0x60,
214 .overflow_bit = SH_CMT32_CMCSR_CMF,
215 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
216 .read_control = sh_cmt_read32,
217 .write_control = sh_cmt_write32,
218 .read_count = sh_cmt_read32,
219 .write_count = sh_cmt_write32,
221 [SH_CMT1_RCAR_GEN2] = {
222 .model = SH_CMT1_RCAR_GEN2,
223 .channels_mask = 0xff,
225 .overflow_bit = SH_CMT32_CMCSR_CMF,
226 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
227 .read_control = sh_cmt_read32,
228 .write_control = sh_cmt_write32,
229 .read_count = sh_cmt_read32,
230 .write_count = sh_cmt_write32,
234 #define CMCSR 0 /* channel register */
235 #define CMCNT 1 /* channel register */
236 #define CMCOR 2 /* channel register */
238 #define CMCLKE 0x1000 /* CLK Enable Register (R-Car Gen2) */
240 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
243 return ch->cmt->info->read_control(ch->iostart, 0);
245 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
248 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value)
251 ch->cmt->info->write_control(ch->iostart, 0, value);
253 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
256 static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
258 return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
261 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value)
263 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
266 static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
268 return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
271 static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value)
273 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
276 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value)
278 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
281 static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped)
286 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
288 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
291 v1 = sh_cmt_read_cmcnt(ch);
292 v2 = sh_cmt_read_cmcnt(ch);
293 v3 = sh_cmt_read_cmcnt(ch);
294 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
295 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
296 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
302 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
307 /* start stop register shared by multiple timer channels */
308 raw_spin_lock_irqsave(&ch->cmt->lock, flags);
309 value = sh_cmt_read_cmstr(ch);
312 value |= 1 << ch->timer_bit;
314 value &= ~(1 << ch->timer_bit);
316 sh_cmt_write_cmstr(ch, value);
317 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
320 static int sh_cmt_enable(struct sh_cmt_channel *ch)
324 dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
327 ret = clk_enable(ch->cmt->clk);
329 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
334 /* make sure channel is disabled */
335 sh_cmt_start_stop_ch(ch, 0);
337 /* configure channel, periodic mode and maximum timeout */
338 if (ch->cmt->info->width == 16) {
339 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
340 SH_CMT16_CMCSR_CKS512);
342 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
343 SH_CMT32_CMCSR_CMTOUT_IE |
344 SH_CMT32_CMCSR_CMR_IRQ |
345 SH_CMT32_CMCSR_CKS_RCLK8);
348 sh_cmt_write_cmcor(ch, 0xffffffff);
349 sh_cmt_write_cmcnt(ch, 0);
352 * According to the sh73a0 user's manual, as CMCNT can be operated
353 * only by the RCLK (Pseudo 32 kHz), there's one restriction on
354 * modifying CMCNT register; two RCLK cycles are necessary before
355 * this register is either read or any modification of the value
356 * it holds is reflected in the LSI's actual operation.
358 * While at it, we're supposed to clear out the CMCNT as of this
359 * moment, so make sure it's processed properly here. This will
360 * take RCLKx2 at maximum.
362 for (k = 0; k < 100; k++) {
363 if (!sh_cmt_read_cmcnt(ch))
368 if (sh_cmt_read_cmcnt(ch)) {
369 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
376 sh_cmt_start_stop_ch(ch, 1);
380 clk_disable(ch->cmt->clk);
386 static void sh_cmt_disable(struct sh_cmt_channel *ch)
388 /* disable channel */
389 sh_cmt_start_stop_ch(ch, 0);
391 /* disable interrupts in CMT block */
392 sh_cmt_write_cmcsr(ch, 0);
395 clk_disable(ch->cmt->clk);
397 dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
401 #define FLAG_CLOCKEVENT (1 << 0)
402 #define FLAG_CLOCKSOURCE (1 << 1)
403 #define FLAG_REPROGRAM (1 << 2)
404 #define FLAG_SKIPEVENT (1 << 3)
405 #define FLAG_IRQCONTEXT (1 << 4)
407 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
410 u32 value = ch->next_match_value;
416 now = sh_cmt_get_counter(ch, &has_wrapped);
417 ch->flags |= FLAG_REPROGRAM; /* force reprogram */
420 /* we're competing with the interrupt handler.
421 * -> let the interrupt handler reprogram the timer.
422 * -> interrupt number two handles the event.
424 ch->flags |= FLAG_SKIPEVENT;
432 /* reprogram the timer hardware,
433 * but don't save the new match value yet.
435 new_match = now + value + delay;
436 if (new_match > ch->max_match_value)
437 new_match = ch->max_match_value;
439 sh_cmt_write_cmcor(ch, new_match);
441 now = sh_cmt_get_counter(ch, &has_wrapped);
442 if (has_wrapped && (new_match > ch->match_value)) {
443 /* we are changing to a greater match value,
444 * so this wrap must be caused by the counter
445 * matching the old value.
446 * -> first interrupt reprograms the timer.
447 * -> interrupt number two handles the event.
449 ch->flags |= FLAG_SKIPEVENT;
454 /* we are changing to a smaller match value,
455 * so the wrap must be caused by the counter
456 * matching the new value.
457 * -> save programmed match value.
458 * -> let isr handle the event.
460 ch->match_value = new_match;
464 /* be safe: verify hardware settings */
465 if (now < new_match) {
466 /* timer value is below match value, all good.
467 * this makes sure we won't miss any match events.
468 * -> save programmed match value.
469 * -> let isr handle the event.
471 ch->match_value = new_match;
475 /* the counter has reached a value greater
476 * than our new match value. and since the
477 * has_wrapped flag isn't set we must have
478 * programmed a too close event.
479 * -> increase delay and retry.
487 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
493 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
495 if (delta > ch->max_match_value)
496 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
499 ch->next_match_value = delta;
500 sh_cmt_clock_event_program_verify(ch, 0);
503 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
507 raw_spin_lock_irqsave(&ch->lock, flags);
508 __sh_cmt_set_next(ch, delta);
509 raw_spin_unlock_irqrestore(&ch->lock, flags);
512 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
514 struct sh_cmt_channel *ch = dev_id;
517 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
518 ch->cmt->info->clear_bits);
520 /* update clock source counter to begin with if enabled
521 * the wrap flag should be cleared by the timer specific
522 * isr before we end up here.
524 if (ch->flags & FLAG_CLOCKSOURCE)
525 ch->total_cycles += ch->match_value + 1;
527 if (!(ch->flags & FLAG_REPROGRAM))
528 ch->next_match_value = ch->max_match_value;
530 ch->flags |= FLAG_IRQCONTEXT;
532 if (ch->flags & FLAG_CLOCKEVENT) {
533 if (!(ch->flags & FLAG_SKIPEVENT)) {
534 if (clockevent_state_oneshot(&ch->ced)) {
535 ch->next_match_value = ch->max_match_value;
536 ch->flags |= FLAG_REPROGRAM;
539 ch->ced.event_handler(&ch->ced);
543 ch->flags &= ~FLAG_SKIPEVENT;
545 if (ch->flags & FLAG_REPROGRAM) {
546 ch->flags &= ~FLAG_REPROGRAM;
547 sh_cmt_clock_event_program_verify(ch, 1);
549 if (ch->flags & FLAG_CLOCKEVENT)
550 if ((clockevent_state_shutdown(&ch->ced))
551 || (ch->match_value == ch->next_match_value))
552 ch->flags &= ~FLAG_REPROGRAM;
555 ch->flags &= ~FLAG_IRQCONTEXT;
560 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
565 if (flag & FLAG_CLOCKSOURCE)
566 pm_runtime_get_sync(&ch->cmt->pdev->dev);
568 raw_spin_lock_irqsave(&ch->lock, flags);
570 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {
571 if (flag & FLAG_CLOCKEVENT)
572 pm_runtime_get_sync(&ch->cmt->pdev->dev);
573 ret = sh_cmt_enable(ch);
580 /* setup timeout if no clockevent */
581 if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT)))
582 __sh_cmt_set_next(ch, ch->max_match_value);
584 raw_spin_unlock_irqrestore(&ch->lock, flags);
589 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
594 raw_spin_lock_irqsave(&ch->lock, flags);
596 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
599 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {
601 if (flag & FLAG_CLOCKEVENT)
602 pm_runtime_put(&ch->cmt->pdev->dev);
605 /* adjust the timeout to maximum if only clocksource left */
606 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
607 __sh_cmt_set_next(ch, ch->max_match_value);
609 raw_spin_unlock_irqrestore(&ch->lock, flags);
611 if (flag & FLAG_CLOCKSOURCE)
612 pm_runtime_put(&ch->cmt->pdev->dev);
615 static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
617 return container_of(cs, struct sh_cmt_channel, cs);
620 static u64 sh_cmt_clocksource_read(struct clocksource *cs)
622 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
628 raw_spin_lock_irqsave(&ch->lock, flags);
629 value = ch->total_cycles;
630 raw = sh_cmt_get_counter(ch, &has_wrapped);
632 if (unlikely(has_wrapped))
633 raw += ch->match_value + 1;
634 raw_spin_unlock_irqrestore(&ch->lock, flags);
639 static int sh_cmt_clocksource_enable(struct clocksource *cs)
642 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
644 WARN_ON(ch->cs_enabled);
646 ch->total_cycles = 0;
648 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
650 ch->cs_enabled = true;
655 static void sh_cmt_clocksource_disable(struct clocksource *cs)
657 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
659 WARN_ON(!ch->cs_enabled);
661 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
662 ch->cs_enabled = false;
665 static void sh_cmt_clocksource_suspend(struct clocksource *cs)
667 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
672 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
673 dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
676 static void sh_cmt_clocksource_resume(struct clocksource *cs)
678 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
683 dev_pm_genpd_resume(&ch->cmt->pdev->dev);
684 sh_cmt_start(ch, FLAG_CLOCKSOURCE);
687 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
690 struct clocksource *cs = &ch->cs;
694 cs->read = sh_cmt_clocksource_read;
695 cs->enable = sh_cmt_clocksource_enable;
696 cs->disable = sh_cmt_clocksource_disable;
697 cs->suspend = sh_cmt_clocksource_suspend;
698 cs->resume = sh_cmt_clocksource_resume;
699 cs->mask = CLOCKSOURCE_MASK(sizeof(u64) * 8);
700 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
702 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
705 clocksource_register_hz(cs, ch->cmt->rate);
709 static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
711 return container_of(ced, struct sh_cmt_channel, ced);
714 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
716 sh_cmt_start(ch, FLAG_CLOCKEVENT);
719 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
721 sh_cmt_set_next(ch, ch->max_match_value);
724 static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced)
726 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
728 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
732 static int sh_cmt_clock_event_set_state(struct clock_event_device *ced,
735 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
737 /* deal with old setting first */
738 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
739 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
741 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
742 ch->index, periodic ? "periodic" : "oneshot");
743 sh_cmt_clock_event_start(ch, periodic);
747 static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced)
749 return sh_cmt_clock_event_set_state(ced, 0);
752 static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced)
754 return sh_cmt_clock_event_set_state(ced, 1);
757 static int sh_cmt_clock_event_next(unsigned long delta,
758 struct clock_event_device *ced)
760 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
762 BUG_ON(!clockevent_state_oneshot(ced));
763 if (likely(ch->flags & FLAG_IRQCONTEXT))
764 ch->next_match_value = delta - 1;
766 sh_cmt_set_next(ch, delta - 1);
771 static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
773 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
775 dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
776 clk_unprepare(ch->cmt->clk);
779 static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
781 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
783 clk_prepare(ch->cmt->clk);
784 dev_pm_genpd_resume(&ch->cmt->pdev->dev);
787 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
790 struct clock_event_device *ced = &ch->ced;
794 irq = platform_get_irq(ch->cmt->pdev, ch->index);
798 ret = request_irq(irq, sh_cmt_interrupt,
799 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
800 dev_name(&ch->cmt->pdev->dev), ch);
802 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
808 ced->features = CLOCK_EVT_FEAT_PERIODIC;
809 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
811 ced->cpumask = cpu_possible_mask;
812 ced->set_next_event = sh_cmt_clock_event_next;
813 ced->set_state_shutdown = sh_cmt_clock_event_shutdown;
814 ced->set_state_periodic = sh_cmt_clock_event_set_periodic;
815 ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot;
816 ced->suspend = sh_cmt_clock_event_suspend;
817 ced->resume = sh_cmt_clock_event_resume;
819 /* TODO: calculate good shift from rate and counter bit width */
821 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
822 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
823 ced->max_delta_ticks = ch->max_match_value;
824 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
825 ced->min_delta_ticks = 0x1f;
827 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
829 clockevents_register_device(ced);
834 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
835 bool clockevent, bool clocksource)
840 ch->cmt->has_clockevent = true;
841 ret = sh_cmt_register_clockevent(ch, name);
847 ch->cmt->has_clocksource = true;
848 sh_cmt_register_clocksource(ch, name);
854 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
855 unsigned int hwidx, bool clockevent,
856 bool clocksource, struct sh_cmt_device *cmt)
861 /* Skip unused channels. */
862 if (!clockevent && !clocksource)
868 ch->timer_bit = hwidx;
871 * Compute the address of the channel control register block. For the
872 * timers with a per-channel start/stop register, compute its address
875 switch (cmt->info->model) {
877 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
881 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
883 case SH_CMT0_RCAR_GEN2:
884 case SH_CMT1_RCAR_GEN2:
885 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
886 ch->ioctrl = ch->iostart + 0x10;
889 /* Enable the clock supply to the channel */
890 value = ioread32(cmt->mapbase + CMCLKE);
892 iowrite32(value, cmt->mapbase + CMCLKE);
896 if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
897 ch->max_match_value = ~0;
899 ch->max_match_value = (1 << cmt->info->width) - 1;
901 ch->match_value = ch->max_match_value;
902 raw_spin_lock_init(&ch->lock);
904 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
905 clockevent, clocksource);
907 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
911 ch->cs_enabled = false;
916 static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
918 struct resource *mem;
920 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
922 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
926 cmt->mapbase = ioremap(mem->start, resource_size(mem));
927 if (cmt->mapbase == NULL) {
928 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
935 static const struct platform_device_id sh_cmt_id_table[] = {
936 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
937 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
940 MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
942 static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
944 /* deprecated, preserved for backward compatibility */
945 .compatible = "renesas,cmt-48",
946 .data = &sh_cmt_info[SH_CMT_48BIT]
949 /* deprecated, preserved for backward compatibility */
950 .compatible = "renesas,cmt-48-gen2",
951 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
954 .compatible = "renesas,r8a7740-cmt1",
955 .data = &sh_cmt_info[SH_CMT_48BIT]
958 .compatible = "renesas,sh73a0-cmt1",
959 .data = &sh_cmt_info[SH_CMT_48BIT]
962 .compatible = "renesas,rcar-gen2-cmt0",
963 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
966 .compatible = "renesas,rcar-gen2-cmt1",
967 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
970 .compatible = "renesas,rcar-gen3-cmt0",
971 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
974 .compatible = "renesas,rcar-gen3-cmt1",
975 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
979 MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
981 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
988 raw_spin_lock_init(&cmt->lock);
990 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
991 cmt->info = of_device_get_match_data(&pdev->dev);
992 cmt->hw_channels = cmt->info->channels_mask;
993 } else if (pdev->dev.platform_data) {
994 struct sh_timer_config *cfg = pdev->dev.platform_data;
995 const struct platform_device_id *id = pdev->id_entry;
997 cmt->info = (const struct sh_cmt_info *)id->driver_data;
998 cmt->hw_channels = cfg->channels_mask;
1000 dev_err(&cmt->pdev->dev, "missing platform data\n");
1004 /* Get hold of clock. */
1005 cmt->clk = clk_get(&cmt->pdev->dev, "fck");
1006 if (IS_ERR(cmt->clk)) {
1007 dev_err(&cmt->pdev->dev, "cannot get clock\n");
1008 return PTR_ERR(cmt->clk);
1011 ret = clk_prepare(cmt->clk);
1015 /* Determine clock rate. */
1016 ret = clk_enable(cmt->clk);
1018 goto err_clk_unprepare;
1020 if (cmt->info->width == 16)
1021 cmt->rate = clk_get_rate(cmt->clk) / 512;
1023 cmt->rate = clk_get_rate(cmt->clk) / 8;
1025 /* Map the memory resource(s). */
1026 ret = sh_cmt_map_memory(cmt);
1028 goto err_clk_disable;
1030 /* Allocate and setup the channels. */
1031 cmt->num_channels = hweight8(cmt->hw_channels);
1032 cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels),
1034 if (cmt->channels == NULL) {
1040 * Use the first channel as a clock event device and the second channel
1041 * as a clock source. If only one channel is available use it for both.
1043 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1044 unsigned int hwidx = ffs(mask) - 1;
1045 bool clocksource = i == 1 || cmt->num_channels == 1;
1046 bool clockevent = i == 0;
1048 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1049 clockevent, clocksource, cmt);
1053 mask &= ~(1 << hwidx);
1056 clk_disable(cmt->clk);
1058 platform_set_drvdata(pdev, cmt);
1063 kfree(cmt->channels);
1064 iounmap(cmt->mapbase);
1066 clk_disable(cmt->clk);
1068 clk_unprepare(cmt->clk);
1074 static int sh_cmt_probe(struct platform_device *pdev)
1076 struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1079 if (!is_sh_early_platform_device(pdev)) {
1080 pm_runtime_set_active(&pdev->dev);
1081 pm_runtime_enable(&pdev->dev);
1085 dev_info(&pdev->dev, "kept as earlytimer\n");
1089 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1093 ret = sh_cmt_setup(cmt, pdev);
1096 pm_runtime_idle(&pdev->dev);
1099 if (is_sh_early_platform_device(pdev))
1103 if (cmt->has_clockevent || cmt->has_clocksource)
1104 pm_runtime_irq_safe(&pdev->dev);
1106 pm_runtime_idle(&pdev->dev);
1111 static int sh_cmt_remove(struct platform_device *pdev)
1113 return -EBUSY; /* cannot unregister clockevent and clocksource */
1116 static struct platform_driver sh_cmt_device_driver = {
1117 .probe = sh_cmt_probe,
1118 .remove = sh_cmt_remove,
1121 .of_match_table = of_match_ptr(sh_cmt_of_table),
1123 .id_table = sh_cmt_id_table,
1126 static int __init sh_cmt_init(void)
1128 return platform_driver_register(&sh_cmt_device_driver);
1131 static void __exit sh_cmt_exit(void)
1133 platform_driver_unregister(&sh_cmt_device_driver);
1136 #ifdef CONFIG_SUPERH
1137 sh_early_platform_init("earlytimer", &sh_cmt_device_driver);
1140 subsys_initcall(sh_cmt_init);
1141 module_exit(sh_cmt_exit);
1143 MODULE_AUTHOR("Magnus Damm");
1144 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1145 MODULE_LICENSE("GPL v2");