drivers/clocksource/sh_cmt.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SuperH Timer Support - CMT
   4  *
   5  *  Copyright (C) 2008 Magnus Damm
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/clockchips.h>
  10 #include <linux/clocksource.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/ioport.h>
  17 #include <linux/irq.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_domain.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/sh_timer.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27
  28 #ifdef CONFIG_SUPERH
  29 #include <asm/platform_early.h>
  30 #endif
  31
  32 struct sh_cmt_device;
  33
  34 /*
  35  * The CMT comes in 5 different identified flavours, depending not only on the
  36  * SoC but also on the particular instance. The following table lists the main
  37  * characteristics of those flavours.
  38  *
  39  *                      16B     32B     32B-F   48B     R-Car Gen2
  40  * -----------------------------------------------------------------------------
  41  * Channels             2       1/4     1       6       2/8
  42  * Control Width        16      16      16      16      32
  43  * Counter Width        16      32      32      32/48   32/48
  44  * Shared Start/Stop    Y       Y       Y       Y       N
  45  *
  46  * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
  47  * located in the channel registers block. All other versions have a shared
  48  * start/stop register located in the global space.
  49  *
  50  * Channels are indexed from 0 to N-1 in the documentation. The channel index
  51  * infers the start/stop bit position in the control register and the channel
  52  * registers block address. Some CMT instances have a subset of channels
  53  * available, in which case the index in the documentation doesn't match the
  54  * "real" index as implemented in hardware. This is for instance the case with
  55  * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
  56  * in the documentation but using start/stop bit 5 and having its registers
  57  * block at 0x60.
  58  *
  59  * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
  60  * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
  61  */
  62
  63 enum sh_cmt_model {
  64         SH_CMT_16BIT,
  65         SH_CMT_32BIT,
  66         SH_CMT_48BIT,
  67         SH_CMT0_RCAR_GEN2,
  68         SH_CMT1_RCAR_GEN2,
  69 };
  70
  71 struct sh_cmt_info {
  72         enum sh_cmt_model model;
  73
  74         unsigned int channels_mask;
  75
  76         unsigned long width; /* 16 or 32 bit version of hardware block */
  77         u32 overflow_bit;
  78         u32 clear_bits;
  79
  80         /* callbacks for CMSTR and CMCSR access */
  81         u32 (*read_control)(void __iomem *base, unsigned long offs);
  82         void (*write_control)(void __iomem *base, unsigned long offs,
  83                               u32 value);
  84
  85         /* callbacks for CMCNT and CMCOR access */
  86         u32 (*read_count)(void __iomem *base, unsigned long offs);
  87         void (*write_count)(void __iomem *base, unsigned long offs, u32 value);
  88 };
  89
  90 struct sh_cmt_channel {
  91         struct sh_cmt_device *cmt;
  92
  93         unsigned int index;     /* Index in the documentation */
  94         unsigned int hwidx;     /* Real hardware index */
  95
  96         void __iomem *iostart;
  97         void __iomem *ioctrl;
  98
  99         unsigned int timer_bit;
 100         unsigned long flags;
 101         u32 match_value;
 102         u32 next_match_value;
 103         u32 max_match_value;
 104         raw_spinlock_t lock;
 105         struct clock_event_device ced;
 106         struct clocksource cs;
 107         u64 total_cycles;
 108         bool cs_enabled;
 109 };
 110
 111 struct sh_cmt_device {
 112         struct platform_device *pdev;
 113
 114         const struct sh_cmt_info *info;
 115
 116         void __iomem *mapbase;
 117         struct clk *clk;
 118         unsigned long rate;
 119
 120         raw_spinlock_t lock; /* Protect the shared start/stop register */
 121
 122         struct sh_cmt_channel *channels;
 123         unsigned int num_channels;
 124         unsigned int hw_channels;
 125
 126         bool has_clockevent;
 127         bool has_clocksource;
 128 };
 129
 130 #define SH_CMT16_CMCSR_CMF              (1 << 7)
 131 #define SH_CMT16_CMCSR_CMIE             (1 << 6)
 132 #define SH_CMT16_CMCSR_CKS8             (0 << 0)
 133 #define SH_CMT16_CMCSR_CKS32            (1 << 0)
 134 #define SH_CMT16_CMCSR_CKS128           (2 << 0)
 135 #define SH_CMT16_CMCSR_CKS512           (3 << 0)
 136 #define SH_CMT16_CMCSR_CKS_MASK         (3 << 0)
 137
 138 #define SH_CMT32_CMCSR_CMF              (1 << 15)
 139 #define SH_CMT32_CMCSR_OVF              (1 << 14)
 140 #define SH_CMT32_CMCSR_WRFLG            (1 << 13)
 141 #define SH_CMT32_CMCSR_STTF             (1 << 12)
 142 #define SH_CMT32_CMCSR_STPF             (1 << 11)
 143 #define SH_CMT32_CMCSR_SSIE             (1 << 10)
 144 #define SH_CMT32_CMCSR_CMS              (1 << 9)
 145 #define SH_CMT32_CMCSR_CMM              (1 << 8)
 146 #define SH_CMT32_CMCSR_CMTOUT_IE        (1 << 7)
 147 #define SH_CMT32_CMCSR_CMR_NONE         (0 << 4)
 148 #define SH_CMT32_CMCSR_CMR_DMA          (1 << 4)
 149 #define SH_CMT32_CMCSR_CMR_IRQ          (2 << 4)
 150 #define SH_CMT32_CMCSR_CMR_MASK         (3 << 4)
 151 #define SH_CMT32_CMCSR_DBGIVD           (1 << 3)
 152 #define SH_CMT32_CMCSR_CKS_RCLK8        (4 << 0)
 153 #define SH_CMT32_CMCSR_CKS_RCLK32       (5 << 0)
 154 #define SH_CMT32_CMCSR_CKS_RCLK128      (6 << 0)
 155 #define SH_CMT32_CMCSR_CKS_RCLK1        (7 << 0)
 156 #define SH_CMT32_CMCSR_CKS_MASK         (7 << 0)
 157
 158 static u32 sh_cmt_read16(void __iomem *base, unsigned long offs)
 159 {
 160         return ioread16(base + (offs << 1));
 161 }
 162
 163 static u32 sh_cmt_read32(void __iomem *base, unsigned long offs)
 164 {
 165         return ioread32(base + (offs << 2));
 166 }
 167
 168 static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value)
 169 {
 170         iowrite16(value, base + (offs << 1));
 171 }
 172
 173 static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value)
 174 {
 175         iowrite32(value, base + (offs << 2));
 176 }
 177
 178 static const struct sh_cmt_info sh_cmt_info[] = {
 179         [SH_CMT_16BIT] = {
 180                 .model = SH_CMT_16BIT,
 181                 .width = 16,
 182                 .overflow_bit = SH_CMT16_CMCSR_CMF,
 183                 .clear_bits = ~SH_CMT16_CMCSR_CMF,
 184                 .read_control = sh_cmt_read16,
 185                 .write_control = sh_cmt_write16,
 186                 .read_count = sh_cmt_read16,
 187                 .write_count = sh_cmt_write16,
 188         },
 189         [SH_CMT_32BIT] = {
 190                 .model = SH_CMT_32BIT,
 191                 .width = 32,
 192                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 193                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 194                 .read_control = sh_cmt_read16,
 195                 .write_control = sh_cmt_write16,
 196                 .read_count = sh_cmt_read32,
 197                 .write_count = sh_cmt_write32,
 198         },
 199         [SH_CMT_48BIT] = {
 200                 .model = SH_CMT_48BIT,
 201                 .channels_mask = 0x3f,
 202                 .width = 32,
 203                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 204                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 205                 .read_control = sh_cmt_read32,
 206                 .write_control = sh_cmt_write32,
 207                 .read_count = sh_cmt_read32,
 208                 .write_count = sh_cmt_write32,
 209         },
 210         [SH_CMT0_RCAR_GEN2] = {
 211                 .model = SH_CMT0_RCAR_GEN2,
 212                 .channels_mask = 0x60,
 213                 .width = 32,
 214                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 215                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 216                 .read_control = sh_cmt_read32,
 217                 .write_control = sh_cmt_write32,
 218                 .read_count = sh_cmt_read32,
 219                 .write_count = sh_cmt_write32,
 220         },
 221         [SH_CMT1_RCAR_GEN2] = {
 222                 .model = SH_CMT1_RCAR_GEN2,
 223                 .channels_mask = 0xff,
 224                 .width = 32,
 225                 .overflow_bit = SH_CMT32_CMCSR_CMF,
 226                 .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 227                 .read_control = sh_cmt_read32,
 228                 .write_control = sh_cmt_write32,
 229                 .read_count = sh_cmt_read32,
 230                 .write_count = sh_cmt_write32,
 231         },
 232 };
 233
 234 #define CMCSR 0 /* channel register */
 235 #define CMCNT 1 /* channel register */
 236 #define CMCOR 2 /* channel register */
 237
 238 #define CMCLKE  0x1000  /* CLK Enable Register (R-Car Gen2) */
 239
 240 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
 241 {
 242         if (ch->iostart)
 243                 return ch->cmt->info->read_control(ch->iostart, 0);
 244         else
 245                 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
 246 }
 247
 248 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value)
 249 {
 250         if (ch->iostart)
 251                 ch->cmt->info->write_control(ch->iostart, 0, value);
 252         else
 253                 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
 254 }
 255
 256 static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
 257 {
 258         return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
 259 }
 260
 261 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value)
 262 {
 263         ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
 264 }
 265
 266 static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
 267 {
 268         return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
 269 }
 270
 271 static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value)
 272 {
 273         ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
 274 }
 275
 276 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value)
 277 {
 278         ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
 279 }
 280
 281 static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped)
 282 {
 283         u32 v1, v2, v3;
 284         u32 o1, o2;
 285
 286         o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 287
 288         /* Make sure the timer value is stable. Stolen from acpi_pm.c */
 289         do {
 290                 o2 = o1;
 291                 v1 = sh_cmt_read_cmcnt(ch);
 292                 v2 = sh_cmt_read_cmcnt(ch);
 293                 v3 = sh_cmt_read_cmcnt(ch);
 294                 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 295         } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
 296                           || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
 297
 298         *has_wrapped = o1;
 299         return v2;
 300 }
 301
 302 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
 303 {
 304         unsigned long flags;
 305         u32 value;
 306
 307         /* start stop register shared by multiple timer channels */
 308         raw_spin_lock_irqsave(&ch->cmt->lock, flags);
 309         value = sh_cmt_read_cmstr(ch);
 310
 311         if (start)
 312                 value |= 1 << ch->timer_bit;
 313         else
 314                 value &= ~(1 << ch->timer_bit);
 315
 316         sh_cmt_write_cmstr(ch, value);
 317         raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
 318 }
 319
 320 static int sh_cmt_enable(struct sh_cmt_channel *ch)
 321 {
 322         int k, ret;
 323
 324         dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
 325
 326         /* enable clock */
 327         ret = clk_enable(ch->cmt->clk);
 328         if (ret) {
 329                 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
 330                         ch->index);
 331                 goto err0;
 332         }
 333
 334         /* make sure channel is disabled */
 335         sh_cmt_start_stop_ch(ch, 0);
 336
 337         /* configure channel, periodic mode and maximum timeout */
 338         if (ch->cmt->info->width == 16) {
 339                 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
 340                                    SH_CMT16_CMCSR_CKS512);
 341         } else {
 342                 sh_cmt_write_cmcsr(ch, SH_CMT32_CMCSR_CMM |
 343                                    SH_CMT32_CMCSR_CMTOUT_IE |
 344                                    SH_CMT32_CMCSR_CMR_IRQ |
 345                                    SH_CMT32_CMCSR_CKS_RCLK8);
 346         }
 347
 348         sh_cmt_write_cmcor(ch, 0xffffffff);
 349         sh_cmt_write_cmcnt(ch, 0);
 350
 351         /*
 352          * According to the sh73a0 user's manual, as CMCNT can be operated
 353          * only by the RCLK (Pseudo 32 kHz), there's one restriction on
 354          * modifying CMCNT register; two RCLK cycles are necessary before
 355          * this register is either read or any modification of the value
 356          * it holds is reflected in the LSI's actual operation.
 357          *
 358          * While at it, we're supposed to clear out the CMCNT as of this
 359          * moment, so make sure it's processed properly here.  This will
 360          * take RCLKx2 at maximum.
 361          */
 362         for (k = 0; k < 100; k++) {
 363                 if (!sh_cmt_read_cmcnt(ch))
 364                         break;
 365                 udelay(1);
 366         }
 367
 368         if (sh_cmt_read_cmcnt(ch)) {
 369                 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
 370                         ch->index);
 371                 ret = -ETIMEDOUT;
 372                 goto err1;
 373         }
 374
 375         /* enable channel */
 376         sh_cmt_start_stop_ch(ch, 1);
 377         return 0;
 378  err1:
 379         /* stop clock */
 380         clk_disable(ch->cmt->clk);
 381
 382  err0:
 383         return ret;
 384 }
 385
 386 static void sh_cmt_disable(struct sh_cmt_channel *ch)
 387 {
 388         /* disable channel */
 389         sh_cmt_start_stop_ch(ch, 0);
 390
 391         /* disable interrupts in CMT block */
 392         sh_cmt_write_cmcsr(ch, 0);
 393
 394         /* stop clock */
 395         clk_disable(ch->cmt->clk);
 396
 397         dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
 398 }
 399
 400 /* private flags */
 401 #define FLAG_CLOCKEVENT (1 << 0)
 402 #define FLAG_CLOCKSOURCE (1 << 1)
 403 #define FLAG_REPROGRAM (1 << 2)
 404 #define FLAG_SKIPEVENT (1 << 3)
 405 #define FLAG_IRQCONTEXT (1 << 4)
 406
 407 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
 408                                               int absolute)
 409 {
 410         u32 value = ch->next_match_value;
 411         u32 new_match;
 412         u32 delay = 0;
 413         u32 now = 0;
 414         u32 has_wrapped;
 415
 416         now = sh_cmt_get_counter(ch, &has_wrapped);
 417         ch->flags |= FLAG_REPROGRAM; /* force reprogram */
 418
 419         if (has_wrapped) {
 420                 /* we're competing with the interrupt handler.
 421                  *  -> let the interrupt handler reprogram the timer.
 422                  *  -> interrupt number two handles the event.
 423                  */
 424                 ch->flags |= FLAG_SKIPEVENT;
 425                 return;
 426         }
 427
 428         if (absolute)
 429                 now = 0;
 430
 431         do {
 432                 /* reprogram the timer hardware,
 433                  * but don't save the new match value yet.
 434                  */
 435                 new_match = now + value + delay;
 436                 if (new_match > ch->max_match_value)
 437                         new_match = ch->max_match_value;
 438
 439                 sh_cmt_write_cmcor(ch, new_match);
 440
 441                 now = sh_cmt_get_counter(ch, &has_wrapped);
 442                 if (has_wrapped && (new_match > ch->match_value)) {
 443                         /* we are changing to a greater match value,
 444                          * so this wrap must be caused by the counter
 445                          * matching the old value.
 446                          * -> first interrupt reprograms the timer.
 447                          * -> interrupt number two handles the event.
 448                          */
 449                         ch->flags |= FLAG_SKIPEVENT;
 450                         break;
 451                 }
 452
 453                 if (has_wrapped) {
 454                         /* we are changing to a smaller match value,
 455                          * so the wrap must be caused by the counter
 456                          * matching the new value.
 457                          * -> save programmed match value.
 458                          * -> let isr handle the event.
 459                          */
 460                         ch->match_value = new_match;
 461                         break;
 462                 }
 463
 464                 /* be safe: verify hardware settings */
 465                 if (now < new_match) {
 466                         /* timer value is below match value, all good.
 467                          * this makes sure we won't miss any match events.
 468                          * -> save programmed match value.
 469                          * -> let isr handle the event.
 470                          */
 471                         ch->match_value = new_match;
 472                         break;
 473                 }
 474
 475                 /* the counter has reached a value greater
 476                  * than our new match value. and since the
 477                  * has_wrapped flag isn't set we must have
 478                  * programmed a too close event.
 479                  * -> increase delay and retry.
 480                  */
 481                 if (delay)
 482                         delay <<= 1;
 483                 else
 484                         delay = 1;
 485
 486                 if (!delay)
 487                         dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
 488                                  ch->index);
 489
 490         } while (delay);
 491 }
 492
 493 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 494 {
 495         if (delta > ch->max_match_value)
 496                 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
 497                          ch->index);
 498
 499         ch->next_match_value = delta;
 500         sh_cmt_clock_event_program_verify(ch, 0);
 501 }
 502
 503 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 504 {
 505         unsigned long flags;
 506
 507         raw_spin_lock_irqsave(&ch->lock, flags);
 508         __sh_cmt_set_next(ch, delta);
 509         raw_spin_unlock_irqrestore(&ch->lock, flags);
 510 }
 511
 512 static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
 513 {
 514         struct sh_cmt_channel *ch = dev_id;
 515
 516         /* clear flags */
 517         sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
 518                            ch->cmt->info->clear_bits);
 519
 520         /* update clock source counter to begin with if enabled
 521          * the wrap flag should be cleared by the timer specific
 522          * isr before we end up here.
 523          */
 524         if (ch->flags & FLAG_CLOCKSOURCE)
 525                 ch->total_cycles += ch->match_value + 1;
 526
 527         if (!(ch->flags & FLAG_REPROGRAM))
 528                 ch->next_match_value = ch->max_match_value;
 529
 530         ch->flags |= FLAG_IRQCONTEXT;
 531
 532         if (ch->flags & FLAG_CLOCKEVENT) {
 533                 if (!(ch->flags & FLAG_SKIPEVENT)) {
 534                         if (clockevent_state_oneshot(&ch->ced)) {
 535                                 ch->next_match_value = ch->max_match_value;
 536                                 ch->flags |= FLAG_REPROGRAM;
 537                         }
 538
 539                         ch->ced.event_handler(&ch->ced);
 540                 }
 541         }
 542
 543         ch->flags &= ~FLAG_SKIPEVENT;
 544
 545         if (ch->flags & FLAG_REPROGRAM) {
 546                 ch->flags &= ~FLAG_REPROGRAM;
 547                 sh_cmt_clock_event_program_verify(ch, 1);
 548
 549                 if (ch->flags & FLAG_CLOCKEVENT)
 550                         if ((clockevent_state_shutdown(&ch->ced))
 551                             || (ch->match_value == ch->next_match_value))
 552                                 ch->flags &= ~FLAG_REPROGRAM;
 553         }
 554
 555         ch->flags &= ~FLAG_IRQCONTEXT;
 556
 557         return IRQ_HANDLED;
 558 }
 559
 560 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
 561 {
 562         int ret = 0;
 563         unsigned long flags;
 564
 565         if (flag & FLAG_CLOCKSOURCE)
 566                 pm_runtime_get_sync(&ch->cmt->pdev->dev);
 567
 568         raw_spin_lock_irqsave(&ch->lock, flags);
 569
 570         if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {
 571                 if (flag & FLAG_CLOCKEVENT)
 572                         pm_runtime_get_sync(&ch->cmt->pdev->dev);
 573                 ret = sh_cmt_enable(ch);
 574         }
 575
 576         if (ret)
 577                 goto out;
 578         ch->flags |= flag;
 579
 580         /* setup timeout if no clockevent */
 581         if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT)))
 582                 __sh_cmt_set_next(ch, ch->max_match_value);
 583  out:
 584         raw_spin_unlock_irqrestore(&ch->lock, flags);
 585
 586         return ret;
 587 }
 588
 589 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
 590 {
 591         unsigned long flags;
 592         unsigned long f;
 593
 594         raw_spin_lock_irqsave(&ch->lock, flags);
 595
 596         f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
 597         ch->flags &= ~flag;
 598
 599         if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {
 600                 sh_cmt_disable(ch);
 601                 if (flag & FLAG_CLOCKEVENT)
 602                         pm_runtime_put(&ch->cmt->pdev->dev);
 603         }
 604
 605         /* adjust the timeout to maximum if only clocksource left */
 606         if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
 607                 __sh_cmt_set_next(ch, ch->max_match_value);
 608
 609         raw_spin_unlock_irqrestore(&ch->lock, flags);
 610
 611         if (flag & FLAG_CLOCKSOURCE)
 612                 pm_runtime_put(&ch->cmt->pdev->dev);
 613 }
 614
 615 static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
 616 {
 617         return container_of(cs, struct sh_cmt_channel, cs);
 618 }
 619
 620 static u64 sh_cmt_clocksource_read(struct clocksource *cs)
 621 {
 622         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 623         unsigned long flags;
 624         u32 has_wrapped;
 625         u64 value;
 626         u32 raw;
 627
 628         raw_spin_lock_irqsave(&ch->lock, flags);
 629         value = ch->total_cycles;
 630         raw = sh_cmt_get_counter(ch, &has_wrapped);
 631
 632         if (unlikely(has_wrapped))
 633                 raw += ch->match_value + 1;
 634         raw_spin_unlock_irqrestore(&ch->lock, flags);
 635
 636         return value + raw;
 637 }
 638
 639 static int sh_cmt_clocksource_enable(struct clocksource *cs)
 640 {
 641         int ret;
 642         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 643
 644         WARN_ON(ch->cs_enabled);
 645
 646         ch->total_cycles = 0;
 647
 648         ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 649         if (!ret)
 650                 ch->cs_enabled = true;
 651
 652         return ret;
 653 }
 654
 655 static void sh_cmt_clocksource_disable(struct clocksource *cs)
 656 {
 657         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 658
 659         WARN_ON(!ch->cs_enabled);
 660
 661         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 662         ch->cs_enabled = false;
 663 }
 664
 665 static void sh_cmt_clocksource_suspend(struct clocksource *cs)
 666 {
 667         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 668
 669         if (!ch->cs_enabled)
 670                 return;
 671
 672         sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 673         dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
 674 }
 675
 676 static void sh_cmt_clocksource_resume(struct clocksource *cs)
 677 {
 678         struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 679
 680         if (!ch->cs_enabled)
 681                 return;
 682
 683         dev_pm_genpd_resume(&ch->cmt->pdev->dev);
 684         sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 685 }
 686
 687 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
 688                                        const char *name)
 689 {
 690         struct clocksource *cs = &ch->cs;
 691
 692         cs->name = name;
 693         cs->rating = 125;
 694         cs->read = sh_cmt_clocksource_read;
 695         cs->enable = sh_cmt_clocksource_enable;
 696         cs->disable = sh_cmt_clocksource_disable;
 697         cs->suspend = sh_cmt_clocksource_suspend;
 698         cs->resume = sh_cmt_clocksource_resume;
 699         cs->mask = CLOCKSOURCE_MASK(sizeof(u64) * 8);
 700         cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 701
 702         dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
 703                  ch->index);
 704
 705         clocksource_register_hz(cs, ch->cmt->rate);
 706         return 0;
 707 }
 708
 709 static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
 710 {
 711         return container_of(ced, struct sh_cmt_channel, ced);
 712 }
 713
 714 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
 715 {
 716         sh_cmt_start(ch, FLAG_CLOCKEVENT);
 717
 718         if (periodic)
 719                 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
 720         else
 721                 sh_cmt_set_next(ch, ch->max_match_value);
 722 }
 723
 724 static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced)
 725 {
 726         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 727
 728         sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 729         return 0;
 730 }
 731
 732 static int sh_cmt_clock_event_set_state(struct clock_event_device *ced,
 733                                         int periodic)
 734 {
 735         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 736
 737         /* deal with old setting first */
 738         if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
 739                 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 740
 741         dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
 742                  ch->index, periodic ? "periodic" : "oneshot");
 743         sh_cmt_clock_event_start(ch, periodic);
 744         return 0;
 745 }
 746
 747 static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced)
 748 {
 749         return sh_cmt_clock_event_set_state(ced, 0);
 750 }
 751
 752 static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced)
 753 {
 754         return sh_cmt_clock_event_set_state(ced, 1);
 755 }
 756
 757 static int sh_cmt_clock_event_next(unsigned long delta,
 758                                    struct clock_event_device *ced)
 759 {
 760         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 761
 762         BUG_ON(!clockevent_state_oneshot(ced));
 763         if (likely(ch->flags & FLAG_IRQCONTEXT))
 764                 ch->next_match_value = delta - 1;
 765         else
 766                 sh_cmt_set_next(ch, delta - 1);
 767
 768         return 0;
 769 }
 770
 771 static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
 772 {
 773         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 774
 775         dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
 776         clk_unprepare(ch->cmt->clk);
 777 }
 778
 779 static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
 780 {
 781         struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 782
 783         clk_prepare(ch->cmt->clk);
 784         dev_pm_genpd_resume(&ch->cmt->pdev->dev);
 785 }
 786
 787 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
 788                                       const char *name)
 789 {
 790         struct clock_event_device *ced = &ch->ced;
 791         int irq;
 792         int ret;
 793
 794         irq = platform_get_irq(ch->cmt->pdev, ch->index);
 795         if (irq < 0)
 796                 return irq;
 797
 798         ret = request_irq(irq, sh_cmt_interrupt,
 799                           IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 800                           dev_name(&ch->cmt->pdev->dev), ch);
 801         if (ret) {
 802                 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
 803                         ch->index, irq);
 804                 return ret;
 805         }
 806
 807         ced->name = name;
 808         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 809         ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 810         ced->rating = 125;
 811         ced->cpumask = cpu_possible_mask;
 812         ced->set_next_event = sh_cmt_clock_event_next;
 813         ced->set_state_shutdown = sh_cmt_clock_event_shutdown;
 814         ced->set_state_periodic = sh_cmt_clock_event_set_periodic;
 815         ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot;
 816         ced->suspend = sh_cmt_clock_event_suspend;
 817         ced->resume = sh_cmt_clock_event_resume;
 818
 819         /* TODO: calculate good shift from rate and counter bit width */
 820         ced->shift = 32;
 821         ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
 822         ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
 823         ced->max_delta_ticks = ch->max_match_value;
 824         ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
 825         ced->min_delta_ticks = 0x1f;
 826
 827         dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
 828                  ch->index);
 829         clockevents_register_device(ced);
 830
 831         return 0;
 832 }
 833
 834 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
 835                            bool clockevent, bool clocksource)
 836 {
 837         int ret;
 838
 839         if (clockevent) {
 840                 ch->cmt->has_clockevent = true;
 841                 ret = sh_cmt_register_clockevent(ch, name);
 842                 if (ret < 0)
 843                         return ret;
 844         }
 845
 846         if (clocksource) {
 847                 ch->cmt->has_clocksource = true;
 848                 sh_cmt_register_clocksource(ch, name);
 849         }
 850
 851         return 0;
 852 }
 853
 854 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
 855                                 unsigned int hwidx, bool clockevent,
 856                                 bool clocksource, struct sh_cmt_device *cmt)
 857 {
 858         u32 value;
 859         int ret;
 860
 861         /* Skip unused channels. */
 862         if (!clockevent && !clocksource)
 863                 return 0;
 864
 865         ch->cmt = cmt;
 866         ch->index = index;
 867         ch->hwidx = hwidx;
 868         ch->timer_bit = hwidx;
 869
 870         /*
 871          * Compute the address of the channel control register block. For the
 872          * timers with a per-channel start/stop register, compute its address
 873          * as well.
 874          */
 875         switch (cmt->info->model) {
 876         case SH_CMT_16BIT:
 877                 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
 878                 break;
 879         case SH_CMT_32BIT:
 880         case SH_CMT_48BIT:
 881                 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
 882                 break;
 883         case SH_CMT0_RCAR_GEN2:
 884         case SH_CMT1_RCAR_GEN2:
 885                 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
 886                 ch->ioctrl = ch->iostart + 0x10;
 887                 ch->timer_bit = 0;
 888
 889                 /* Enable the clock supply to the channel */
 890                 value = ioread32(cmt->mapbase + CMCLKE);
 891                 value |= BIT(hwidx);
 892                 iowrite32(value, cmt->mapbase + CMCLKE);
 893                 break;
 894         }
 895
 896         if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
 897                 ch->max_match_value = ~0;
 898         else
 899                 ch->max_match_value = (1 << cmt->info->width) - 1;
 900
 901         ch->match_value = ch->max_match_value;
 902         raw_spin_lock_init(&ch->lock);
 903
 904         ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
 905                               clockevent, clocksource);
 906         if (ret) {
 907                 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
 908                         ch->index);
 909                 return ret;
 910         }
 911         ch->cs_enabled = false;
 912
 913         return 0;
 914 }
 915
 916 static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
 917 {
 918         struct resource *mem;
 919
 920         mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
 921         if (!mem) {
 922                 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
 923                 return -ENXIO;
 924         }
 925
 926         cmt->mapbase = ioremap(mem->start, resource_size(mem));
 927         if (cmt->mapbase == NULL) {
 928                 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
 929                 return -ENXIO;
 930         }
 931
 932         return 0;
 933 }
 934
 935 static const struct platform_device_id sh_cmt_id_table[] = {
 936         { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
 937         { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
 938         { }
 939 };
 940 MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
 941
 942 static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
 943         {
 944                 /* deprecated, preserved for backward compatibility */
 945                 .compatible = "renesas,cmt-48",
 946                 .data = &sh_cmt_info[SH_CMT_48BIT]
 947         },
 948         {
 949                 /* deprecated, preserved for backward compatibility */
 950                 .compatible = "renesas,cmt-48-gen2",
 951                 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 952         },
 953         {
 954                 .compatible = "renesas,r8a7740-cmt1",
 955                 .data = &sh_cmt_info[SH_CMT_48BIT]
 956         },
 957         {
 958                 .compatible = "renesas,sh73a0-cmt1",
 959                 .data = &sh_cmt_info[SH_CMT_48BIT]
 960         },
 961         {
 962                 .compatible = "renesas,rcar-gen2-cmt0",
 963                 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 964         },
 965         {
 966                 .compatible = "renesas,rcar-gen2-cmt1",
 967                 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
 968         },
 969         {
 970                 .compatible = "renesas,rcar-gen3-cmt0",
 971                 .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 972         },
 973         {
 974                 .compatible = "renesas,rcar-gen3-cmt1",
 975                 .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
 976         },
 977         { }
 978 };
 979 MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
 980
 981 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
 982 {
 983         unsigned int mask;
 984         unsigned int i;
 985         int ret;
 986
 987         cmt->pdev = pdev;
 988         raw_spin_lock_init(&cmt->lock);
 989
 990         if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
 991                 cmt->info = of_device_get_match_data(&pdev->dev);
 992                 cmt->hw_channels = cmt->info->channels_mask;
 993         } else if (pdev->dev.platform_data) {
 994                 struct sh_timer_config *cfg = pdev->dev.platform_data;
 995                 const struct platform_device_id *id = pdev->id_entry;
 996
 997                 cmt->info = (const struct sh_cmt_info *)id->driver_data;
 998                 cmt->hw_channels = cfg->channels_mask;
 999         } else {
1000                 dev_err(&cmt->pdev->dev, "missing platform data\n");
1001                 return -ENXIO;
1002         }
1003
1004         /* Get hold of clock. */
1005         cmt->clk = clk_get(&cmt->pdev->dev, "fck");
1006         if (IS_ERR(cmt->clk)) {
1007                 dev_err(&cmt->pdev->dev, "cannot get clock\n");
1008                 return PTR_ERR(cmt->clk);
1009         }
1010
1011         ret = clk_prepare(cmt->clk);
1012         if (ret < 0)
1013                 goto err_clk_put;
1014
1015         /* Determine clock rate. */
1016         ret = clk_enable(cmt->clk);
1017         if (ret < 0)
1018                 goto err_clk_unprepare;
1019
1020         if (cmt->info->width == 16)
1021                 cmt->rate = clk_get_rate(cmt->clk) / 512;
1022         else
1023                 cmt->rate = clk_get_rate(cmt->clk) / 8;
1024
1025         /* Map the memory resource(s). */
1026         ret = sh_cmt_map_memory(cmt);
1027         if (ret < 0)
1028                 goto err_clk_disable;
1029
1030         /* Allocate and setup the channels. */
1031         cmt->num_channels = hweight8(cmt->hw_channels);
1032         cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels),
1033                                 GFP_KERNEL);
1034         if (cmt->channels == NULL) {
1035                 ret = -ENOMEM;
1036                 goto err_unmap;
1037         }
1038
1039         /*
1040          * Use the first channel as a clock event device and the second channel
1041          * as a clock source. If only one channel is available use it for both.
1042          */
1043         for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1044                 unsigned int hwidx = ffs(mask) - 1;
1045                 bool clocksource = i == 1 || cmt->num_channels == 1;
1046                 bool clockevent = i == 0;
1047
1048                 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1049                                            clockevent, clocksource, cmt);
1050                 if (ret < 0)
1051                         goto err_unmap;
1052
1053                 mask &= ~(1 << hwidx);
1054         }
1055
1056         clk_disable(cmt->clk);
1057
1058         platform_set_drvdata(pdev, cmt);
1059
1060         return 0;
1061
1062 err_unmap:
1063         kfree(cmt->channels);
1064         iounmap(cmt->mapbase);
1065 err_clk_disable:
1066         clk_disable(cmt->clk);
1067 err_clk_unprepare:
1068         clk_unprepare(cmt->clk);
1069 err_clk_put:
1070         clk_put(cmt->clk);
1071         return ret;
1072 }
1073
1074 static int sh_cmt_probe(struct platform_device *pdev)
1075 {
1076         struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1077         int ret;
1078
1079         if (!is_sh_early_platform_device(pdev)) {
1080                 pm_runtime_set_active(&pdev->dev);
1081                 pm_runtime_enable(&pdev->dev);
1082         }
1083
1084         if (cmt) {
1085                 dev_info(&pdev->dev, "kept as earlytimer\n");
1086                 goto out;
1087         }
1088
1089         cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1090         if (cmt == NULL)
1091                 return -ENOMEM;
1092
1093         ret = sh_cmt_setup(cmt, pdev);
1094         if (ret) {
1095                 kfree(cmt);
1096                 pm_runtime_idle(&pdev->dev);
1097                 return ret;
1098         }
1099         if (is_sh_early_platform_device(pdev))
1100                 return 0;
1101
1102  out:
1103         if (cmt->has_clockevent || cmt->has_clocksource)
1104                 pm_runtime_irq_safe(&pdev->dev);
1105         else
1106                 pm_runtime_idle(&pdev->dev);
1107
1108         return 0;
1109 }
1110
1111 static int sh_cmt_remove(struct platform_device *pdev)
1112 {
1113         return -EBUSY; /* cannot unregister clockevent and clocksource */
1114 }
1115
1116 static struct platform_driver sh_cmt_device_driver = {
1117         .probe          = sh_cmt_probe,
1118         .remove         = sh_cmt_remove,
1119         .driver         = {
1120                 .name   = "sh_cmt",
1121                 .of_match_table = of_match_ptr(sh_cmt_of_table),
1122         },
1123         .id_table       = sh_cmt_id_table,
1124 };
1125
1126 static int __init sh_cmt_init(void)
1127 {
1128         return platform_driver_register(&sh_cmt_device_driver);
1129 }
1130
1131 static void __exit sh_cmt_exit(void)
1132 {
1133         platform_driver_unregister(&sh_cmt_device_driver);
1134 }
1135
1136 #ifdef CONFIG_SUPERH
1137 sh_early_platform_init("earlytimer", &sh_cmt_device_driver);
1138 #endif
1139
1140 subsys_initcall(sh_cmt_init);
1141 module_exit(sh_cmt_exit);
1142
1143 MODULE_AUTHOR("Magnus Damm");
1144 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1145 MODULE_LICENSE("GPL v2");