2 * linux/drivers/clocksource/arm_arch_timer.c
4 * Copyright (C) 2011 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #define pr_fmt(fmt) "arch_timer: " fmt
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/device.h>
17 #include <linux/smp.h>
18 #include <linux/cpu.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/clockchips.h>
21 #include <linux/clocksource.h>
22 #include <linux/interrupt.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_address.h>
26 #include <linux/slab.h>
27 #include <linux/sched/clock.h>
28 #include <linux/sched_clock.h>
29 #include <linux/acpi.h>
31 #include <asm/arch_timer.h>
34 #include <clocksource/arm_arch_timer.h>
37 #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
39 #define CNTACR(n) (0x40 + ((n) * 4))
40 #define CNTACR_RPCT BIT(0)
41 #define CNTACR_RVCT BIT(1)
42 #define CNTACR_RFRQ BIT(2)
43 #define CNTACR_RVOFF BIT(3)
44 #define CNTACR_RWVT BIT(4)
45 #define CNTACR_RWPT BIT(5)
47 #define CNTVCT_LO 0x08
48 #define CNTVCT_HI 0x0c
50 #define CNTP_TVAL 0x28
52 #define CNTV_TVAL 0x38
55 static unsigned arch_timers_present __initdata;
57 static void __iomem *arch_counter_base;
61 struct clock_event_device evt;
64 #define to_arch_timer(e) container_of(e, struct arch_timer, evt)
66 static u32 arch_timer_rate;
67 static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI];
69 static struct clock_event_device __percpu *arch_timer_evt;
71 static enum arch_timer_ppi_nr arch_timer_uses_ppi = ARCH_TIMER_VIRT_PPI;
72 static bool arch_timer_c3stop;
73 static bool arch_timer_mem_use_virtual;
74 static bool arch_counter_suspend_stop;
75 static bool vdso_default = true;
77 static cpumask_t evtstrm_available = CPU_MASK_NONE;
78 static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
80 static int __init early_evtstrm_cfg(char *buf)
82 return strtobool(buf, &evtstrm_enable);
84 early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
87 * Architected system timer support.
90 static __always_inline
91 void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
92 struct clock_event_device *clk)
94 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
95 struct arch_timer *timer = to_arch_timer(clk);
97 case ARCH_TIMER_REG_CTRL:
98 writel_relaxed(val, timer->base + CNTP_CTL);
100 case ARCH_TIMER_REG_TVAL:
101 writel_relaxed(val, timer->base + CNTP_TVAL);
104 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
105 struct arch_timer *timer = to_arch_timer(clk);
107 case ARCH_TIMER_REG_CTRL:
108 writel_relaxed(val, timer->base + CNTV_CTL);
110 case ARCH_TIMER_REG_TVAL:
111 writel_relaxed(val, timer->base + CNTV_TVAL);
115 arch_timer_reg_write_cp15(access, reg, val);
119 static __always_inline
120 u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
121 struct clock_event_device *clk)
125 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
126 struct arch_timer *timer = to_arch_timer(clk);
128 case ARCH_TIMER_REG_CTRL:
129 val = readl_relaxed(timer->base + CNTP_CTL);
131 case ARCH_TIMER_REG_TVAL:
132 val = readl_relaxed(timer->base + CNTP_TVAL);
135 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
136 struct arch_timer *timer = to_arch_timer(clk);
138 case ARCH_TIMER_REG_CTRL:
139 val = readl_relaxed(timer->base + CNTV_CTL);
141 case ARCH_TIMER_REG_TVAL:
142 val = readl_relaxed(timer->base + CNTV_TVAL);
146 val = arch_timer_reg_read_cp15(access, reg);
153 * Default to cp15 based access because arm64 uses this function for
154 * sched_clock() before DT is probed and the cp15 method is guaranteed
155 * to exist on arm64. arm doesn't use this before DT is probed so even
156 * if we don't have the cp15 accessors we won't have a problem.
158 u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
159 EXPORT_SYMBOL_GPL(arch_timer_read_counter);
161 static u64 arch_counter_read(struct clocksource *cs)
163 return arch_timer_read_counter();
166 static u64 arch_counter_read_cc(const struct cyclecounter *cc)
168 return arch_timer_read_counter();
171 static struct clocksource clocksource_counter = {
172 .name = "arch_sys_counter",
174 .read = arch_counter_read,
175 .mask = CLOCKSOURCE_MASK(56),
176 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
179 static struct cyclecounter cyclecounter __ro_after_init = {
180 .read = arch_counter_read_cc,
181 .mask = CLOCKSOURCE_MASK(56),
184 struct ate_acpi_oem_info {
185 char oem_id[ACPI_OEM_ID_SIZE + 1];
186 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
190 #ifdef CONFIG_FSL_ERRATUM_A008585
192 * The number of retries is an arbitrary value well beyond the highest number
193 * of iterations the loop has been observed to take.
195 #define __fsl_a008585_read_reg(reg) ({ \
197 int _retries = 200; \
200 _old = read_sysreg(reg); \
201 _new = read_sysreg(reg); \
203 } while (unlikely(_old != _new) && _retries); \
205 WARN_ON_ONCE(!_retries); \
209 static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
211 return __fsl_a008585_read_reg(cntp_tval_el0);
214 static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
216 return __fsl_a008585_read_reg(cntv_tval_el0);
219 static u64 notrace fsl_a008585_read_cntpct_el0(void)
221 return __fsl_a008585_read_reg(cntpct_el0);
224 static u64 notrace fsl_a008585_read_cntvct_el0(void)
226 return __fsl_a008585_read_reg(cntvct_el0);
230 #ifdef CONFIG_HISILICON_ERRATUM_161010101
232 * Verify whether the value of the second read is larger than the first by
233 * less than 32 is the only way to confirm the value is correct, so clear the
234 * lower 5 bits to check whether the difference is greater than 32 or not.
235 * Theoretically the erratum should not occur more than twice in succession
236 * when reading the system counter, but it is possible that some interrupts
237 * may lead to more than twice read errors, triggering the warning, so setting
238 * the number of retries far beyond the number of iterations the loop has been
241 #define __hisi_161010101_read_reg(reg) ({ \
246 _old = read_sysreg(reg); \
247 _new = read_sysreg(reg); \
249 } while (unlikely((_new - _old) >> 5) && _retries); \
251 WARN_ON_ONCE(!_retries); \
255 static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
257 return __hisi_161010101_read_reg(cntp_tval_el0);
260 static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
262 return __hisi_161010101_read_reg(cntv_tval_el0);
265 static u64 notrace hisi_161010101_read_cntpct_el0(void)
267 return __hisi_161010101_read_reg(cntpct_el0);
270 static u64 notrace hisi_161010101_read_cntvct_el0(void)
272 return __hisi_161010101_read_reg(cntvct_el0);
275 static struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
277 * Note that trailing spaces are required to properly match
278 * the OEM table information.
282 .oem_table_id = "HIP05 ",
287 .oem_table_id = "HIP06 ",
292 .oem_table_id = "HIP07 ",
295 { /* Sentinel indicating the end of the OEM array */ },
299 #ifdef CONFIG_ARM64_ERRATUM_858921
300 static u64 notrace arm64_858921_read_cntpct_el0(void)
304 old = read_sysreg(cntpct_el0);
305 new = read_sysreg(cntpct_el0);
306 return (((old ^ new) >> 32) & 1) ? old : new;
309 static u64 notrace arm64_858921_read_cntvct_el0(void)
313 old = read_sysreg(cntvct_el0);
314 new = read_sysreg(cntvct_el0);
315 return (((old ^ new) >> 32) & 1) ? old : new;
319 #ifdef CONFIG_ARM64_ERRATUM_1188873
320 static u64 notrace arm64_1188873_read_cntvct_el0(void)
322 return read_sysreg(cntvct_el0);
326 #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
328 * The low bits of the counter registers are indeterminate while bit 10 or
329 * greater is rolling over. Since the counter value can jump both backward
330 * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
331 * with all ones or all zeros in the low bits. Bound the loop by the maximum
332 * number of CPU cycles in 3 consecutive 24 MHz counter periods.
334 #define __sun50i_a64_read_reg(reg) ({ \
336 int _retries = 150; \
339 _val = read_sysreg(reg); \
341 } while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \
343 WARN_ON_ONCE(!_retries); \
347 static u64 notrace sun50i_a64_read_cntpct_el0(void)
349 return __sun50i_a64_read_reg(cntpct_el0);
352 static u64 notrace sun50i_a64_read_cntvct_el0(void)
354 return __sun50i_a64_read_reg(cntvct_el0);
357 static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
359 return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
362 static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
364 return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
368 #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
369 DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
370 EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
372 DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
373 EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
375 static void erratum_set_next_event_tval_generic(const int access, unsigned long evt,
376 struct clock_event_device *clk)
381 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
382 ctrl |= ARCH_TIMER_CTRL_ENABLE;
383 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
385 if (access == ARCH_TIMER_PHYS_ACCESS) {
386 cval = evt + arch_counter_get_cntpct();
387 write_sysreg(cval, cntp_cval_el0);
389 cval = evt + arch_counter_get_cntvct();
390 write_sysreg(cval, cntv_cval_el0);
393 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
396 static __maybe_unused int erratum_set_next_event_tval_virt(unsigned long evt,
397 struct clock_event_device *clk)
399 erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
403 static __maybe_unused int erratum_set_next_event_tval_phys(unsigned long evt,
404 struct clock_event_device *clk)
406 erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
410 static const struct arch_timer_erratum_workaround ool_workarounds[] = {
411 #ifdef CONFIG_FSL_ERRATUM_A008585
413 .match_type = ate_match_dt,
414 .id = "fsl,erratum-a008585",
415 .desc = "Freescale erratum a005858",
416 .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
417 .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
418 .read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
419 .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
420 .set_next_event_phys = erratum_set_next_event_tval_phys,
421 .set_next_event_virt = erratum_set_next_event_tval_virt,
424 #ifdef CONFIG_HISILICON_ERRATUM_161010101
426 .match_type = ate_match_dt,
427 .id = "hisilicon,erratum-161010101",
428 .desc = "HiSilicon erratum 161010101",
429 .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
430 .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
431 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
432 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
433 .set_next_event_phys = erratum_set_next_event_tval_phys,
434 .set_next_event_virt = erratum_set_next_event_tval_virt,
437 .match_type = ate_match_acpi_oem_info,
438 .id = hisi_161010101_oem_info,
439 .desc = "HiSilicon erratum 161010101",
440 .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
441 .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
442 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
443 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
444 .set_next_event_phys = erratum_set_next_event_tval_phys,
445 .set_next_event_virt = erratum_set_next_event_tval_virt,
448 #ifdef CONFIG_ARM64_ERRATUM_858921
450 .match_type = ate_match_local_cap_id,
451 .id = (void *)ARM64_WORKAROUND_858921,
452 .desc = "ARM erratum 858921",
453 .read_cntpct_el0 = arm64_858921_read_cntpct_el0,
454 .read_cntvct_el0 = arm64_858921_read_cntvct_el0,
457 #ifdef CONFIG_ARM64_ERRATUM_1188873
459 .match_type = ate_match_local_cap_id,
460 .id = (void *)ARM64_WORKAROUND_1188873,
461 .desc = "ARM erratum 1188873",
462 .read_cntvct_el0 = arm64_1188873_read_cntvct_el0,
465 #ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
467 .match_type = ate_match_dt,
468 .id = "allwinner,erratum-unknown1",
469 .desc = "Allwinner erratum UNKNOWN1",
470 .read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
471 .read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
472 .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
473 .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
474 .set_next_event_phys = erratum_set_next_event_tval_phys,
475 .set_next_event_virt = erratum_set_next_event_tval_virt,
480 typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
484 bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa,
487 const struct device_node *np = arg;
489 return of_property_read_bool(np, wa->id);
493 bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
496 return this_cpu_has_cap((uintptr_t)wa->id);
501 bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa,
504 static const struct ate_acpi_oem_info empty_oem_info = {};
505 const struct ate_acpi_oem_info *info = wa->id;
506 const struct acpi_table_header *table = arg;
508 /* Iterate over the ACPI OEM info array, looking for a match */
509 while (memcmp(info, &empty_oem_info, sizeof(*info))) {
510 if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) &&
511 !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
512 info->oem_revision == table->oem_revision)
521 static const struct arch_timer_erratum_workaround *
522 arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
523 ate_match_fn_t match_fn,
528 for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
529 if (ool_workarounds[i].match_type != type)
532 if (match_fn(&ool_workarounds[i], arg))
533 return &ool_workarounds[i];
540 void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa,
546 __this_cpu_write(timer_unstable_counter_workaround, wa);
548 for_each_possible_cpu(i)
549 per_cpu(timer_unstable_counter_workaround, i) = wa;
553 * Use the locked version, as we're called from the CPU
554 * hotplug framework. Otherwise, we end-up in deadlock-land.
556 static_branch_enable_cpuslocked(&arch_timer_read_ool_enabled);
559 * Don't use the vdso fastpath if errata require using the
560 * out-of-line counter accessor. We may change our mind pretty
561 * late in the game (with a per-CPU erratum, for example), so
562 * change both the default value and the vdso itself.
564 if (wa->read_cntvct_el0) {
565 clocksource_counter.archdata.vdso_direct = false;
566 vdso_default = false;
570 static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
573 const struct arch_timer_erratum_workaround *wa;
574 ate_match_fn_t match_fn = NULL;
579 match_fn = arch_timer_check_dt_erratum;
581 case ate_match_local_cap_id:
582 match_fn = arch_timer_check_local_cap_erratum;
585 case ate_match_acpi_oem_info:
586 match_fn = arch_timer_check_acpi_oem_erratum;
593 wa = arch_timer_iterate_errata(type, match_fn, arg);
597 if (needs_unstable_timer_counter_workaround()) {
598 const struct arch_timer_erratum_workaround *__wa;
599 __wa = __this_cpu_read(timer_unstable_counter_workaround);
600 if (__wa && wa != __wa)
601 pr_warn("Can't enable workaround for %s (clashes with %s\n)",
602 wa->desc, __wa->desc);
608 arch_timer_enable_workaround(wa, local);
609 pr_info("Enabling %s workaround for %s\n",
610 local ? "local" : "global", wa->desc);
613 #define erratum_handler(fn, r, ...) \
616 if (needs_unstable_timer_counter_workaround()) { \
617 const struct arch_timer_erratum_workaround *__wa; \
618 __wa = __this_cpu_read(timer_unstable_counter_workaround); \
619 if (__wa && __wa->fn) { \
620 r = __wa->fn(__VA_ARGS__); \
631 static bool arch_timer_this_cpu_has_cntvct_wa(void)
633 const struct arch_timer_erratum_workaround *wa;
635 wa = __this_cpu_read(timer_unstable_counter_workaround);
636 return wa && wa->read_cntvct_el0;
639 #define arch_timer_check_ool_workaround(t,a) do { } while(0)
640 #define erratum_set_next_event_tval_virt(...) ({BUG(); 0;})
641 #define erratum_set_next_event_tval_phys(...) ({BUG(); 0;})
642 #define erratum_handler(fn, r, ...) ({false;})
643 #define arch_timer_this_cpu_has_cntvct_wa() ({false;})
644 #endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
646 static __always_inline irqreturn_t timer_handler(const int access,
647 struct clock_event_device *evt)
651 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
652 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
653 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
654 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
655 evt->event_handler(evt);
662 static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
664 struct clock_event_device *evt = dev_id;
666 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
669 static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
671 struct clock_event_device *evt = dev_id;
673 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
676 static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
678 struct clock_event_device *evt = dev_id;
680 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
683 static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
685 struct clock_event_device *evt = dev_id;
687 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
690 static __always_inline int timer_shutdown(const int access,
691 struct clock_event_device *clk)
695 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
696 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
697 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
702 static int arch_timer_shutdown_virt(struct clock_event_device *clk)
704 return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
707 static int arch_timer_shutdown_phys(struct clock_event_device *clk)
709 return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
712 static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
714 return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
717 static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
719 return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
722 static __always_inline void set_next_event(const int access, unsigned long evt,
723 struct clock_event_device *clk)
726 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
727 ctrl |= ARCH_TIMER_CTRL_ENABLE;
728 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
729 arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
730 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
733 static int arch_timer_set_next_event_virt(unsigned long evt,
734 struct clock_event_device *clk)
738 if (erratum_handler(set_next_event_virt, ret, evt, clk))
741 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
745 static int arch_timer_set_next_event_phys(unsigned long evt,
746 struct clock_event_device *clk)
750 if (erratum_handler(set_next_event_phys, ret, evt, clk))
753 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
757 static int arch_timer_set_next_event_virt_mem(unsigned long evt,
758 struct clock_event_device *clk)
760 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
764 static int arch_timer_set_next_event_phys_mem(unsigned long evt,
765 struct clock_event_device *clk)
767 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
771 static void __arch_timer_setup(unsigned type,
772 struct clock_event_device *clk)
774 clk->features = CLOCK_EVT_FEAT_ONESHOT;
776 if (type == ARCH_TIMER_TYPE_CP15) {
777 if (arch_timer_c3stop)
778 clk->features |= CLOCK_EVT_FEAT_C3STOP;
779 clk->name = "arch_sys_timer";
781 clk->cpumask = cpumask_of(smp_processor_id());
782 clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
783 switch (arch_timer_uses_ppi) {
784 case ARCH_TIMER_VIRT_PPI:
785 clk->set_state_shutdown = arch_timer_shutdown_virt;
786 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
787 clk->set_next_event = arch_timer_set_next_event_virt;
789 case ARCH_TIMER_PHYS_SECURE_PPI:
790 case ARCH_TIMER_PHYS_NONSECURE_PPI:
791 case ARCH_TIMER_HYP_PPI:
792 clk->set_state_shutdown = arch_timer_shutdown_phys;
793 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
794 clk->set_next_event = arch_timer_set_next_event_phys;
800 arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
802 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
803 clk->name = "arch_mem_timer";
805 clk->cpumask = cpu_possible_mask;
806 if (arch_timer_mem_use_virtual) {
807 clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
808 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
809 clk->set_next_event =
810 arch_timer_set_next_event_virt_mem;
812 clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
813 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
814 clk->set_next_event =
815 arch_timer_set_next_event_phys_mem;
819 clk->set_state_shutdown(clk);
821 clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
824 static void arch_timer_evtstrm_enable(int divider)
826 u32 cntkctl = arch_timer_get_cntkctl();
828 cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
829 /* Set the divider and enable virtual event stream */
830 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
831 | ARCH_TIMER_VIRT_EVT_EN;
832 arch_timer_set_cntkctl(cntkctl);
833 elf_hwcap |= HWCAP_EVTSTRM;
835 compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
837 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
840 static void arch_timer_configure_evtstream(void)
842 int evt_stream_div, pos;
844 /* Find the closest power of two to the divisor */
845 evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
846 pos = fls(evt_stream_div);
847 if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
849 /* enable event stream */
850 arch_timer_evtstrm_enable(min(pos, 15));
853 static void arch_counter_set_user_access(void)
855 u32 cntkctl = arch_timer_get_cntkctl();
857 /* Disable user access to the timers and both counters */
858 /* Also disable virtual event stream */
859 cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
860 | ARCH_TIMER_USR_VT_ACCESS_EN
861 | ARCH_TIMER_USR_VCT_ACCESS_EN
862 | ARCH_TIMER_VIRT_EVT_EN
863 | ARCH_TIMER_USR_PCT_ACCESS_EN);
866 * Enable user access to the virtual counter if it doesn't
867 * need to be workaround. The vdso may have been already
870 if (arch_timer_this_cpu_has_cntvct_wa())
871 pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
873 cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
875 arch_timer_set_cntkctl(cntkctl);
878 static bool arch_timer_has_nonsecure_ppi(void)
880 return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
881 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
884 static u32 check_ppi_trigger(int irq)
886 u32 flags = irq_get_trigger_type(irq);
888 if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
889 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
890 pr_warn("WARNING: Please fix your firmware\n");
891 flags = IRQF_TRIGGER_LOW;
897 static int arch_timer_starting_cpu(unsigned int cpu)
899 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
902 __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk);
904 flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
905 enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
907 if (arch_timer_has_nonsecure_ppi()) {
908 flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
909 enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
913 arch_counter_set_user_access();
915 arch_timer_configure_evtstream();
921 * For historical reasons, when probing with DT we use whichever (non-zero)
922 * rate was probed first, and don't verify that others match. If the first node
923 * probed has a clock-frequency property, this overrides the HW register.
925 static void arch_timer_of_configure_rate(u32 rate, struct device_node *np)
927 /* Who has more than one independent system counter? */
931 if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
932 arch_timer_rate = rate;
934 /* Check the timer frequency. */
935 if (arch_timer_rate == 0)
936 pr_warn("frequency not available\n");
939 static void arch_timer_banner(unsigned type)
941 pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
942 type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "",
943 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ?
945 type & ARCH_TIMER_TYPE_MEM ? "mmio" : "",
946 (unsigned long)arch_timer_rate / 1000000,
947 (unsigned long)(arch_timer_rate / 10000) % 100,
948 type & ARCH_TIMER_TYPE_CP15 ?
949 (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" :
951 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
952 type & ARCH_TIMER_TYPE_MEM ?
953 arch_timer_mem_use_virtual ? "virt" : "phys" :
957 u32 arch_timer_get_rate(void)
959 return arch_timer_rate;
962 bool arch_timer_evtstrm_available(void)
965 * We might get called from a preemptible context. This is fine
966 * because availability of the event stream should be always the same
967 * for a preemptible context and context where we might resume a task.
969 return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available);
972 static u64 arch_counter_get_cntvct_mem(void)
974 u32 vct_lo, vct_hi, tmp_hi;
977 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
978 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
979 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
980 } while (vct_hi != tmp_hi);
982 return ((u64) vct_hi << 32) | vct_lo;
985 static struct arch_timer_kvm_info arch_timer_kvm_info;
987 struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
989 return &arch_timer_kvm_info;
992 static void __init arch_counter_register(unsigned type)
996 /* Register the CP15 based counter if we have one */
997 if (type & ARCH_TIMER_TYPE_CP15) {
998 if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) ||
999 arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI)
1000 arch_timer_read_counter = arch_counter_get_cntvct;
1002 arch_timer_read_counter = arch_counter_get_cntpct;
1004 clocksource_counter.archdata.vdso_direct = vdso_default;
1006 arch_timer_read_counter = arch_counter_get_cntvct_mem;
1009 if (!arch_counter_suspend_stop)
1010 clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1011 start_count = arch_timer_read_counter();
1012 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
1013 cyclecounter.mult = clocksource_counter.mult;
1014 cyclecounter.shift = clocksource_counter.shift;
1015 timecounter_init(&arch_timer_kvm_info.timecounter,
1016 &cyclecounter, start_count);
1018 /* 56 bits minimum, so we assume worst case rollover */
1019 sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
1022 static void arch_timer_stop(struct clock_event_device *clk)
1024 pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
1026 disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
1027 if (arch_timer_has_nonsecure_ppi())
1028 disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
1030 clk->set_state_shutdown(clk);
1033 static int arch_timer_dying_cpu(unsigned int cpu)
1035 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
1037 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1039 arch_timer_stop(clk);
1043 #ifdef CONFIG_CPU_PM
1044 static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
1045 static int arch_timer_cpu_pm_notify(struct notifier_block *self,
1046 unsigned long action, void *hcpu)
1048 if (action == CPU_PM_ENTER) {
1049 __this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
1051 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1052 } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) {
1053 arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
1055 if (elf_hwcap & HWCAP_EVTSTRM)
1056 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
1061 static struct notifier_block arch_timer_cpu_pm_notifier = {
1062 .notifier_call = arch_timer_cpu_pm_notify,
1065 static int __init arch_timer_cpu_pm_init(void)
1067 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
1070 static void __init arch_timer_cpu_pm_deinit(void)
1072 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
1076 static int __init arch_timer_cpu_pm_init(void)
1081 static void __init arch_timer_cpu_pm_deinit(void)
1086 static int __init arch_timer_register(void)
1091 arch_timer_evt = alloc_percpu(struct clock_event_device);
1092 if (!arch_timer_evt) {
1097 ppi = arch_timer_ppi[arch_timer_uses_ppi];
1098 switch (arch_timer_uses_ppi) {
1099 case ARCH_TIMER_VIRT_PPI:
1100 err = request_percpu_irq(ppi, arch_timer_handler_virt,
1101 "arch_timer", arch_timer_evt);
1103 case ARCH_TIMER_PHYS_SECURE_PPI:
1104 case ARCH_TIMER_PHYS_NONSECURE_PPI:
1105 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1106 "arch_timer", arch_timer_evt);
1107 if (!err && arch_timer_has_nonsecure_ppi()) {
1108 ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1109 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1110 "arch_timer", arch_timer_evt);
1112 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
1116 case ARCH_TIMER_HYP_PPI:
1117 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1118 "arch_timer", arch_timer_evt);
1125 pr_err("can't register interrupt %d (%d)\n", ppi, err);
1129 err = arch_timer_cpu_pm_init();
1131 goto out_unreg_notify;
1133 /* Register and immediately configure the timer on the boot CPU */
1134 err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
1135 "clockevents/arm/arch_timer:starting",
1136 arch_timer_starting_cpu, arch_timer_dying_cpu);
1138 goto out_unreg_cpupm;
1142 arch_timer_cpu_pm_deinit();
1145 free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
1146 if (arch_timer_has_nonsecure_ppi())
1147 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
1151 free_percpu(arch_timer_evt);
1156 static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
1160 struct arch_timer *t;
1162 t = kzalloc(sizeof(*t), GFP_KERNEL);
1168 __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &t->evt);
1170 if (arch_timer_mem_use_virtual)
1171 func = arch_timer_handler_virt_mem;
1173 func = arch_timer_handler_phys_mem;
1175 ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
1177 pr_err("Failed to request mem timer irq\n");
1184 static const struct of_device_id arch_timer_of_match[] __initconst = {
1185 { .compatible = "arm,armv7-timer", },
1186 { .compatible = "arm,armv8-timer", },
1190 static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
1191 { .compatible = "arm,armv7-timer-mem", },
1195 static bool __init arch_timer_needs_of_probing(void)
1197 struct device_node *dn;
1198 bool needs_probing = false;
1199 unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM;
1201 /* We have two timers, and both device-tree nodes are probed. */
1202 if ((arch_timers_present & mask) == mask)
1206 * Only one type of timer is probed,
1207 * check if we have another type of timer node in device-tree.
1209 if (arch_timers_present & ARCH_TIMER_TYPE_CP15)
1210 dn = of_find_matching_node(NULL, arch_timer_mem_of_match);
1212 dn = of_find_matching_node(NULL, arch_timer_of_match);
1214 if (dn && of_device_is_available(dn))
1215 needs_probing = true;
1219 return needs_probing;
1222 static int __init arch_timer_common_init(void)
1224 arch_timer_banner(arch_timers_present);
1225 arch_counter_register(arch_timers_present);
1226 return arch_timer_arch_init();
1230 * arch_timer_select_ppi() - Select suitable PPI for the current system.
1232 * If HYP mode is available, we know that the physical timer
1233 * has been configured to be accessible from PL1. Use it, so
1234 * that a guest can use the virtual timer instead.
1236 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
1237 * accesses to CNTP_*_EL1 registers are silently redirected to
1238 * their CNTHP_*_EL2 counterparts, and use a different PPI
1241 * If no interrupt provided for virtual timer, we'll have to
1242 * stick to the physical timer. It'd better be accessible...
1243 * For arm64 we never use the secure interrupt.
1245 * Return: a suitable PPI type for the current system.
1247 static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void)
1249 if (is_kernel_in_hyp_mode())
1250 return ARCH_TIMER_HYP_PPI;
1252 if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
1253 return ARCH_TIMER_VIRT_PPI;
1255 if (IS_ENABLED(CONFIG_ARM64))
1256 return ARCH_TIMER_PHYS_NONSECURE_PPI;
1258 return ARCH_TIMER_PHYS_SECURE_PPI;
1261 static void __init arch_timer_populate_kvm_info(void)
1263 arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
1264 if (is_kernel_in_hyp_mode())
1265 arch_timer_kvm_info.physical_irq = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1268 static int __init arch_timer_of_init(struct device_node *np)
1273 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1274 pr_warn("multiple nodes in dt, skipping\n");
1278 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1279 for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++)
1280 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
1282 arch_timer_populate_kvm_info();
1284 rate = arch_timer_get_cntfrq();
1285 arch_timer_of_configure_rate(rate, np);
1287 arch_timer_c3stop = !of_property_read_bool(np, "always-on");
1289 /* Check for globally applicable workarounds */
1290 arch_timer_check_ool_workaround(ate_match_dt, np);
1293 * If we cannot rely on firmware initializing the timer registers then
1294 * we should use the physical timers instead.
1296 if (IS_ENABLED(CONFIG_ARM) &&
1297 of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
1298 arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
1300 arch_timer_uses_ppi = arch_timer_select_ppi();
1302 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1303 pr_err("No interrupt available, giving up\n");
1307 /* On some systems, the counter stops ticking when in suspend. */
1308 arch_counter_suspend_stop = of_property_read_bool(np,
1309 "arm,no-tick-in-suspend");
1311 ret = arch_timer_register();
1315 if (arch_timer_needs_of_probing())
1318 return arch_timer_common_init();
1320 TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
1321 TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
1324 arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame)
1329 base = ioremap(frame->cntbase, frame->size);
1331 pr_err("Unable to map frame @ %pa\n", &frame->cntbase);
1335 rate = readl_relaxed(base + CNTFRQ);
1342 static struct arch_timer_mem_frame * __init
1343 arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem)
1345 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1346 void __iomem *cntctlbase;
1350 cntctlbase = ioremap(timer_mem->cntctlbase, timer_mem->size);
1352 pr_err("Can't map CNTCTLBase @ %pa\n",
1353 &timer_mem->cntctlbase);
1357 cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
1360 * Try to find a virtual capable frame. Otherwise fall back to a
1361 * physical capable frame.
1363 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1364 u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
1365 CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
1367 frame = &timer_mem->frame[i];
1371 /* Try enabling everything, and see what sticks */
1372 writel_relaxed(cntacr, cntctlbase + CNTACR(i));
1373 cntacr = readl_relaxed(cntctlbase + CNTACR(i));
1375 if ((cnttidr & CNTTIDR_VIRT(i)) &&
1376 !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
1378 arch_timer_mem_use_virtual = true;
1382 if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
1388 iounmap(cntctlbase);
1394 arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame)
1399 if (arch_timer_mem_use_virtual)
1400 irq = frame->virt_irq;
1402 irq = frame->phys_irq;
1405 pr_err("Frame missing %s irq.\n",
1406 arch_timer_mem_use_virtual ? "virt" : "phys");
1410 if (!request_mem_region(frame->cntbase, frame->size,
1414 base = ioremap(frame->cntbase, frame->size);
1416 pr_err("Can't map frame's registers\n");
1420 ret = arch_timer_mem_register(base, irq);
1426 arch_counter_base = base;
1427 arch_timers_present |= ARCH_TIMER_TYPE_MEM;
1432 static int __init arch_timer_mem_of_init(struct device_node *np)
1434 struct arch_timer_mem *timer_mem;
1435 struct arch_timer_mem_frame *frame;
1436 struct device_node *frame_node;
1437 struct resource res;
1441 timer_mem = kzalloc(sizeof(*timer_mem), GFP_KERNEL);
1445 if (of_address_to_resource(np, 0, &res))
1447 timer_mem->cntctlbase = res.start;
1448 timer_mem->size = resource_size(&res);
1450 for_each_available_child_of_node(np, frame_node) {
1452 struct arch_timer_mem_frame *frame;
1454 if (of_property_read_u32(frame_node, "frame-number", &n)) {
1455 pr_err(FW_BUG "Missing frame-number.\n");
1456 of_node_put(frame_node);
1459 if (n >= ARCH_TIMER_MEM_MAX_FRAMES) {
1460 pr_err(FW_BUG "Wrong frame-number, only 0-%u are permitted.\n",
1461 ARCH_TIMER_MEM_MAX_FRAMES - 1);
1462 of_node_put(frame_node);
1465 frame = &timer_mem->frame[n];
1468 pr_err(FW_BUG "Duplicated frame-number.\n");
1469 of_node_put(frame_node);
1473 if (of_address_to_resource(frame_node, 0, &res)) {
1474 of_node_put(frame_node);
1477 frame->cntbase = res.start;
1478 frame->size = resource_size(&res);
1480 frame->virt_irq = irq_of_parse_and_map(frame_node,
1481 ARCH_TIMER_VIRT_SPI);
1482 frame->phys_irq = irq_of_parse_and_map(frame_node,
1483 ARCH_TIMER_PHYS_SPI);
1485 frame->valid = true;
1488 frame = arch_timer_mem_find_best_frame(timer_mem);
1490 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1491 &timer_mem->cntctlbase);
1496 rate = arch_timer_mem_frame_get_cntfrq(frame);
1497 arch_timer_of_configure_rate(rate, np);
1499 ret = arch_timer_mem_frame_register(frame);
1500 if (!ret && !arch_timer_needs_of_probing())
1501 ret = arch_timer_common_init();
1506 TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
1507 arch_timer_mem_of_init);
1509 #ifdef CONFIG_ACPI_GTDT
1511 arch_timer_mem_verify_cntfrq(struct arch_timer_mem *timer_mem)
1513 struct arch_timer_mem_frame *frame;
1517 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1518 frame = &timer_mem->frame[i];
1523 rate = arch_timer_mem_frame_get_cntfrq(frame);
1524 if (rate == arch_timer_rate)
1527 pr_err(FW_BUG "CNTFRQ mismatch: frame @ %pa: (0x%08lx), CPU: (0x%08lx)\n",
1529 (unsigned long)rate, (unsigned long)arch_timer_rate);
1537 static int __init arch_timer_mem_acpi_init(int platform_timer_count)
1539 struct arch_timer_mem *timers, *timer;
1540 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1541 int timer_count, i, ret = 0;
1543 timers = kcalloc(platform_timer_count, sizeof(*timers),
1548 ret = acpi_arch_timer_mem_init(timers, &timer_count);
1549 if (ret || !timer_count)
1553 * While unlikely, it's theoretically possible that none of the frames
1554 * in a timer expose the combination of feature we want.
1556 for (i = 0; i < timer_count; i++) {
1559 frame = arch_timer_mem_find_best_frame(timer);
1563 ret = arch_timer_mem_verify_cntfrq(timer);
1565 pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n");
1569 if (!best_frame) /* implies !frame */
1571 * Only complain about missing suitable frames if we
1572 * haven't already found one in a previous iteration.
1574 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1575 &timer->cntctlbase);
1579 ret = arch_timer_mem_frame_register(best_frame);
1585 /* Initialize per-processor generic timer and memory-mapped timer(if present) */
1586 static int __init arch_timer_acpi_init(struct acpi_table_header *table)
1588 int ret, platform_timer_count;
1590 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1591 pr_warn("already initialized, skipping\n");
1595 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1597 ret = acpi_gtdt_init(table, &platform_timer_count);
1599 pr_err("Failed to init GTDT table.\n");
1603 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
1604 acpi_gtdt_map_ppi(ARCH_TIMER_PHYS_NONSECURE_PPI);
1606 arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
1607 acpi_gtdt_map_ppi(ARCH_TIMER_VIRT_PPI);
1609 arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
1610 acpi_gtdt_map_ppi(ARCH_TIMER_HYP_PPI);
1612 arch_timer_populate_kvm_info();
1615 * When probing via ACPI, we have no mechanism to override the sysreg
1616 * CNTFRQ value. This *must* be correct.
1618 arch_timer_rate = arch_timer_get_cntfrq();
1619 if (!arch_timer_rate) {
1620 pr_err(FW_BUG "frequency not available.\n");
1624 arch_timer_uses_ppi = arch_timer_select_ppi();
1625 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1626 pr_err("No interrupt available, giving up\n");
1630 /* Always-on capability */
1631 arch_timer_c3stop = acpi_gtdt_c3stop(arch_timer_uses_ppi);
1633 /* Check for globally applicable workarounds */
1634 arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table);
1636 ret = arch_timer_register();
1640 if (platform_timer_count &&
1641 arch_timer_mem_acpi_init(platform_timer_count))
1642 pr_err("Failed to initialize memory-mapped timer.\n");
1644 return arch_timer_common_init();
1646 TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);