1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC PLL driver
5 * Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
10 #include <linux/slab.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
16 * @clk_id: PLL clock ID
17 * @set_pll_mode: Whether an IOCTL_SET_PLL_FRAC_MODE request be sent to ATF
25 #define to_zynqmp_pll(_hw) container_of(_hw, struct zynqmp_pll, hw)
27 #define PLL_FBDIV_MIN 25
28 #define PLL_FBDIV_MAX 125
30 #define PS_PLL_VCO_MIN 1500000000
31 #define PS_PLL_VCO_MAX 3000000000UL
38 #define FRAC_OFFSET 0x8
39 #define PLLFCFG_FRAC_EN BIT(31)
40 #define FRAC_DIV BIT(16) /* 2^16 */
43 * zynqmp_pll_get_mode() - Get mode of PLL
44 * @hw: Handle between common and hardware-specific interfaces
48 static inline enum pll_mode zynqmp_pll_get_mode(struct clk_hw *hw)
50 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
51 u32 clk_id = clk->clk_id;
52 const char *clk_name = clk_hw_get_name(hw);
53 u32 ret_payload[PAYLOAD_ARG_CNT];
56 ret = zynqmp_pm_get_pll_frac_mode(clk_id, ret_payload);
58 pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n",
59 __func__, clk_name, ret);
61 return ret_payload[1];
65 * zynqmp_pll_set_mode() - Set the PLL mode
66 * @hw: Handle between common and hardware-specific interfaces
67 * @on: Flag to determine the mode
69 static inline void zynqmp_pll_set_mode(struct clk_hw *hw, bool on)
71 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
72 u32 clk_id = clk->clk_id;
73 const char *clk_name = clk_hw_get_name(hw);
82 ret = zynqmp_pm_set_pll_frac_mode(clk_id, mode);
84 pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n",
85 __func__, clk_name, ret);
87 clk->set_pll_mode = true;
91 * zynqmp_pll_round_rate() - Round a clock frequency
92 * @hw: Handle between common and hardware-specific interfaces
93 * @rate: Desired clock frequency
94 * @prate: Clock frequency of parent clock
96 * Return: Frequency closest to @rate the hardware can generate
98 static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
104 /* Enable the fractional mode if needed */
105 rate_div = (rate * FRAC_DIV) / *prate;
106 f = rate_div % FRAC_DIV;
108 if (rate > PS_PLL_VCO_MAX) {
109 fbdiv = rate / PS_PLL_VCO_MAX;
110 rate = rate / (fbdiv + 1);
112 if (rate < PS_PLL_VCO_MIN) {
113 fbdiv = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);
119 fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
120 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
121 return *prate * fbdiv;
125 * zynqmp_pll_recalc_rate() - Recalculate clock frequency
126 * @hw: Handle between common and hardware-specific interfaces
127 * @parent_rate: Clock frequency of parent clock
129 * Return: Current clock frequency
131 static unsigned long zynqmp_pll_recalc_rate(struct clk_hw *hw,
132 unsigned long parent_rate)
134 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
135 u32 clk_id = clk->clk_id;
136 const char *clk_name = clk_hw_get_name(hw);
138 unsigned long rate, frac;
139 u32 ret_payload[PAYLOAD_ARG_CNT];
142 ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv);
144 pr_warn_once("%s() get divider failed for %s, ret = %d\n",
145 __func__, clk_name, ret);
147 rate = parent_rate * fbdiv;
148 if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
149 zynqmp_pm_get_pll_frac_data(clk_id, ret_payload);
150 data = ret_payload[1];
151 frac = (parent_rate * data) / FRAC_DIV;
159 * zynqmp_pll_set_rate() - Set rate of PLL
160 * @hw: Handle between common and hardware-specific interfaces
161 * @rate: Frequency of clock to be set
162 * @parent_rate: Clock frequency of parent clock
164 * Set PLL divider to set desired rate.
166 * Returns: rate which is set on success else error code
168 static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
169 unsigned long parent_rate)
171 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
172 u32 clk_id = clk->clk_id;
173 const char *clk_name = clk_hw_get_name(hw);
175 long rate_div, frac, m, f;
178 rate_div = (rate * FRAC_DIV) / parent_rate;
179 f = rate_div % FRAC_DIV;
180 zynqmp_pll_set_mode(hw, !!f);
183 m = rate_div / FRAC_DIV;
184 m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX));
185 rate = parent_rate * m;
186 frac = (parent_rate * f) / FRAC_DIV;
188 ret = zynqmp_pm_clock_setdivider(clk_id, m);
190 WARN(1, "More than allowed devices are using the %s, which is forbidden\n",
193 pr_warn_once("%s() set divider failed for %s, ret = %d\n",
194 __func__, clk_name, ret);
195 zynqmp_pm_set_pll_frac_data(clk_id, f);
200 fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);
201 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX);
202 ret = zynqmp_pm_clock_setdivider(clk_id, fbdiv);
204 pr_warn_once("%s() set divider failed for %s, ret = %d\n",
205 __func__, clk_name, ret);
207 return parent_rate * fbdiv;
211 * zynqmp_pll_is_enabled() - Check if a clock is enabled
212 * @hw: Handle between common and hardware-specific interfaces
214 * Return: 1 if the clock is enabled, 0 otherwise
216 static int zynqmp_pll_is_enabled(struct clk_hw *hw)
218 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
219 const char *clk_name = clk_hw_get_name(hw);
220 u32 clk_id = clk->clk_id;
224 ret = zynqmp_pm_clock_getstate(clk_id, &state);
226 pr_warn_once("%s() clock get state failed for %s, ret = %d\n",
227 __func__, clk_name, ret);
231 return state ? 1 : 0;
235 * zynqmp_pll_enable() - Enable clock
236 * @hw: Handle between common and hardware-specific interfaces
238 * Return: 0 on success else error code
240 static int zynqmp_pll_enable(struct clk_hw *hw)
242 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
243 const char *clk_name = clk_hw_get_name(hw);
244 u32 clk_id = clk->clk_id;
248 * Don't skip enabling clock if there is an IOCTL_SET_PLL_FRAC_MODE request
249 * that has been sent to ATF.
251 if (zynqmp_pll_is_enabled(hw) && (!clk->set_pll_mode))
254 clk->set_pll_mode = false;
256 ret = zynqmp_pm_clock_enable(clk_id);
258 pr_warn_once("%s() clock enable failed for %s, ret = %d\n",
259 __func__, clk_name, ret);
265 * zynqmp_pll_disable() - Disable clock
266 * @hw: Handle between common and hardware-specific interfaces
268 static void zynqmp_pll_disable(struct clk_hw *hw)
270 struct zynqmp_pll *clk = to_zynqmp_pll(hw);
271 const char *clk_name = clk_hw_get_name(hw);
272 u32 clk_id = clk->clk_id;
275 if (!zynqmp_pll_is_enabled(hw))
278 ret = zynqmp_pm_clock_disable(clk_id);
280 pr_warn_once("%s() clock disable failed for %s, ret = %d\n",
281 __func__, clk_name, ret);
284 static const struct clk_ops zynqmp_pll_ops = {
285 .enable = zynqmp_pll_enable,
286 .disable = zynqmp_pll_disable,
287 .is_enabled = zynqmp_pll_is_enabled,
288 .round_rate = zynqmp_pll_round_rate,
289 .recalc_rate = zynqmp_pll_recalc_rate,
290 .set_rate = zynqmp_pll_set_rate,
294 * zynqmp_clk_register_pll() - Register PLL with the clock framework
297 * @parents: Name of this clock's parents
298 * @num_parents: Number of parents
299 * @nodes: Clock topology node
301 * Return: clock hardware to the registered clock
303 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
304 const char * const *parents,
306 const struct clock_topology *nodes)
308 struct zynqmp_pll *pll;
310 struct clk_init_data init;
314 init.ops = &zynqmp_pll_ops;
315 init.flags = nodes->flag;
316 init.parent_names = parents;
317 init.num_parents = 1;
319 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
321 return ERR_PTR(-ENOMEM);
323 pll->hw.init = &init;
324 pll->clk_id = clk_id;
327 ret = clk_hw_register(NULL, hw);
333 clk_hw_set_rate_range(hw, PS_PLL_VCO_MIN, PS_PLL_VCO_MAX);
335 pr_err("%s:ERROR clk_set_rate_range failed %d\n", name, ret);