1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC Divider support
5 * Copyright (C) 2016-2019 Xilinx
7 * Adjustable divider clock implementation
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/slab.h>
13 #include "clk-zynqmp.h"
16 * DOC: basic adjustable divider clock that cannot gate
18 * Traits of this clock:
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
22 * parent - fixed parent. No clk_set_parent support
25 #define to_zynqmp_clk_divider(_hw) \
26 container_of(_hw, struct zynqmp_clk_divider, hw)
28 #define CLK_FRAC BIT(13) /* has a fractional parent */
31 * struct zynqmp_clk_divider - adjustable divider clock
32 * @hw: handle between common and hardware-specific interfaces
33 * @flags: Hardware specific flags
34 * @is_frac: The divider is a fractional divider
35 * @clk_id: Id of clock
36 * @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2)
38 struct zynqmp_clk_divider {
47 static inline int zynqmp_divider_get_val(unsigned long parent_rate,
48 unsigned long rate, u16 flags)
51 unsigned long up_rate, down_rate;
53 if (flags & CLK_DIVIDER_POWER_OF_TWO) {
54 up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
55 down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate);
57 up = __roundup_pow_of_two(up);
58 down = __rounddown_pow_of_two(down);
60 up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up);
61 down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down);
63 return (rate - up_rate) <= (down_rate - rate) ? up : down;
66 return DIV_ROUND_CLOSEST(parent_rate, rate);
71 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
72 * @hw: handle between common and hardware-specific interfaces
73 * @parent_rate: rate of parent clock
75 * Return: 0 on success else error+reason
77 static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
78 unsigned long parent_rate)
80 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
81 const char *clk_name = clk_hw_get_name(hw);
82 u32 clk_id = divider->clk_id;
83 u32 div_type = divider->div_type;
86 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
88 ret = eemi_ops->clock_getdivider(clk_id, &div);
91 pr_warn_once("%s() get divider failed for %s, ret = %d\n",
92 __func__, clk_name, ret);
94 if (div_type == TYPE_DIV1)
99 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
103 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
104 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
109 return DIV_ROUND_UP_ULL(parent_rate, value);
112 static void zynqmp_get_divider2_val(struct clk_hw *hw,
114 unsigned long parent_rate,
115 struct zynqmp_clk_divider *divider,
120 long error = LONG_MAX;
121 struct clk_hw *parent_hw = clk_hw_get_parent(hw);
122 struct zynqmp_clk_divider *pdivider = to_zynqmp_clk_divider(parent_hw);
128 for (div1 = 1; div1 <= pdivider->max_div;) {
129 for (div2 = 1; div2 <= divider->max_div;) {
130 long new_error = ((parent_rate / div1) / div2) - rate;
132 if (abs(new_error) < abs(error)) {
136 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
141 if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO)
149 * zynqmp_clk_divider_round_rate() - Round rate of divider clock
150 * @hw: handle between common and hardware-specific interfaces
151 * @rate: rate of clock to be set
152 * @prate: rate of parent clock
154 * Return: 0 on success else error+reason
156 static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
158 unsigned long *prate)
160 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
161 const char *clk_name = clk_hw_get_name(hw);
162 u32 clk_id = divider->clk_id;
163 u32 div_type = divider->div_type;
166 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
168 /* if read only, just return current value */
169 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
170 ret = eemi_ops->clock_getdivider(clk_id, &bestdiv);
173 pr_warn_once("%s() get divider failed for %s, ret = %d\n",
174 __func__, clk_name, ret);
175 if (div_type == TYPE_DIV1)
176 bestdiv = bestdiv & 0xFFFF;
178 bestdiv = bestdiv >> 16;
180 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
181 bestdiv = 1 << bestdiv;
183 return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
186 bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags);
189 * In case of two divisors, compute best divider values and return
190 * divider2 value based on compute value. div1 will be automatically
191 * set to optimum based on required total divider value.
193 if (div_type == TYPE_DIV2 &&
194 (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
195 zynqmp_get_divider2_val(hw, rate, *prate, divider, &bestdiv);
198 if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)
199 bestdiv = rate % *prate ? 1 : bestdiv;
200 *prate = rate * bestdiv;
206 * zynqmp_clk_divider_set_rate() - Set rate of divider clock
207 * @hw: handle between common and hardware-specific interfaces
208 * @rate: rate of clock to be set
209 * @parent_rate: rate of parent clock
211 * Return: 0 on success else error+reason
213 static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
214 unsigned long parent_rate)
216 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
217 const char *clk_name = clk_hw_get_name(hw);
218 u32 clk_id = divider->clk_id;
219 u32 div_type = divider->div_type;
222 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
224 value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);
225 if (div_type == TYPE_DIV1) {
226 div = value & 0xFFFF;
233 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
236 ret = eemi_ops->clock_setdivider(clk_id, div);
239 pr_warn_once("%s() set divider failed for %s, ret = %d\n",
240 __func__, clk_name, ret);
245 static const struct clk_ops zynqmp_clk_divider_ops = {
246 .recalc_rate = zynqmp_clk_divider_recalc_rate,
247 .round_rate = zynqmp_clk_divider_round_rate,
248 .set_rate = zynqmp_clk_divider_set_rate,
252 * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware.
253 * @clk_id: Id of clock
254 * @type: Divider type
256 * Return: Maximum divisor of a clock if query data is successful
257 * U16_MAX in case of query data is not success
259 u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type)
261 const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
262 struct zynqmp_pm_query_data qdata = {0};
263 u32 ret_payload[PAYLOAD_ARG_CNT];
266 qdata.qid = PM_QID_CLOCK_GET_MAX_DIVISOR;
269 ret = eemi_ops->query_data(qdata, ret_payload);
271 * To maintain backward compatibility return maximum possible value
272 * (0xFFFF) if query for max divisor is not successful.
277 return ret_payload[1];
281 * zynqmp_clk_register_divider() - Register a divider clock
282 * @name: Name of this clock
283 * @clk_id: Id of clock
284 * @parents: Name of this clock's parents
285 * @num_parents: Number of parents
286 * @nodes: Clock topology node
288 * Return: clock hardware to registered clock divider
290 struct clk_hw *zynqmp_clk_register_divider(const char *name,
292 const char * const *parents,
294 const struct clock_topology *nodes)
296 struct zynqmp_clk_divider *div;
298 struct clk_init_data init;
301 /* allocate the divider */
302 div = kzalloc(sizeof(*div), GFP_KERNEL);
304 return ERR_PTR(-ENOMEM);
307 init.ops = &zynqmp_clk_divider_ops;
308 /* CLK_FRAC is not defined in the common clk framework */
309 init.flags = nodes->flag & ~CLK_FRAC;
310 init.parent_names = parents;
311 init.num_parents = 1;
313 /* struct clk_divider assignments */
314 div->is_frac = !!(nodes->flag & CLK_FRAC);
315 div->flags = nodes->type_flag;
316 div->hw.init = &init;
317 div->clk_id = clk_id;
318 div->div_type = nodes->type;
321 * To achieve best possible rate, maximum limit of divider is required
324 div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type);
327 ret = clk_hw_register(NULL, hw);