1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2016-2018 Xilinx
6 #ifndef __LINUX_CLK_ZYNQMP_H_
7 #define __LINUX_CLK_ZYNQMP_H_
9 #include <linux/spinlock.h>
11 #include <linux/firmware/xlnx-zynqmp.h>
14 /* must be gated across rate change */
15 #define ZYNQMP_CLK_SET_RATE_GATE BIT(0)
16 /* must be gated across re-parent */
17 #define ZYNQMP_CLK_SET_PARENT_GATE BIT(1)
18 /* propagate rate change up one level */
19 #define ZYNQMP_CLK_SET_RATE_PARENT BIT(2)
20 /* do not gate even if unused */
21 #define ZYNQMP_CLK_IGNORE_UNUSED BIT(3)
22 /* don't re-parent on rate change */
23 #define ZYNQMP_CLK_SET_RATE_NO_REPARENT BIT(7)
24 /* do not gate, ever */
25 #define ZYNQMP_CLK_IS_CRITICAL BIT(11)
27 /* Type Flags for divider clock */
28 #define ZYNQMP_CLK_DIVIDER_ONE_BASED BIT(0)
29 #define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO BIT(1)
30 #define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO BIT(2)
31 #define ZYNQMP_CLK_DIVIDER_HIWORD_MASK BIT(3)
32 #define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST BIT(4)
33 #define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5)
34 #define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6)
36 /* Type Flags for mux clock */
37 #define ZYNQMP_CLK_MUX_INDEX_ONE BIT(0)
38 #define ZYNQMP_CLK_MUX_INDEX_BIT BIT(1)
39 #define ZYNQMP_CLK_MUX_HIWORD_MASK BIT(2)
40 #define ZYNQMP_CLK_MUX_READ_ONLY BIT(3)
41 #define ZYNQMP_CLK_MUX_ROUND_CLOSEST BIT(4)
42 #define ZYNQMP_CLK_MUX_BIG_ENDIAN BIT(5)
55 * struct clock_topology - Clock topology
56 * @type: Type of topology
57 * @flag: Topology flags
58 * @type_flag: Topology type specific flag
59 * @custom_type_flag: Topology type specific custom flag
61 struct clock_topology {
68 unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag);
70 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
71 const char * const *parents,
73 const struct clock_topology *nodes);
75 struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
76 const char * const *parents,
78 const struct clock_topology *nodes);
80 struct clk_hw *zynqmp_clk_register_divider(const char *name,
82 const char * const *parents,
84 const struct clock_topology *nodes);
86 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
87 const char * const *parents,
89 const struct clock_topology *nodes);
91 struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name,
93 const char * const *parents,
95 const struct clock_topology *nodes);