1 // SPDX-License-Identifier: GPL-2.0-only
3 * Zynq clock controller
5 * Copyright (C) 2012 - 2013 Xilinx
7 * Sören Brinkmann <soren.brinkmann@xilinx.com>
10 #include <linux/clk/zynq.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
14 #include <linux/of_address.h>
15 #include <linux/slab.h>
16 #include <linux/string.h>
19 static void __iomem *zynq_clkc_base;
21 #define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00)
22 #define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04)
23 #define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08)
24 #define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c)
25 #define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20)
26 #define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24)
27 #define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28)
28 #define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c)
29 #define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40)
30 #define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44)
31 #define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48)
32 #define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c)
33 #define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50)
34 #define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54)
35 #define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58)
36 #define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c)
37 #define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60)
38 #define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64)
39 #define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68)
40 #define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70)
41 #define SLCR_621_TRUE (zynq_clkc_base + 0xc4)
42 #define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204)
44 #define NUM_MIO_PINS 54
46 #define DBG_CLK_CTRL_CLKACT_TRC BIT(0)
47 #define DBG_CLK_CTRL_CPU_1XCLKACT BIT(1)
50 armpll, ddrpll, iopll,
51 cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
53 lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
54 sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
55 usb0_aper, usb1_aper, gem0_aper, gem1_aper,
56 sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
57 i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
58 smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
60 static struct clk *ps_clk;
61 static struct clk *clks[clk_max];
62 static struct clk_onecell_data clk_data;
64 static DEFINE_SPINLOCK(armpll_lock);
65 static DEFINE_SPINLOCK(ddrpll_lock);
66 static DEFINE_SPINLOCK(iopll_lock);
67 static DEFINE_SPINLOCK(armclk_lock);
68 static DEFINE_SPINLOCK(swdtclk_lock);
69 static DEFINE_SPINLOCK(ddrclk_lock);
70 static DEFINE_SPINLOCK(dciclk_lock);
71 static DEFINE_SPINLOCK(gem0clk_lock);
72 static DEFINE_SPINLOCK(gem1clk_lock);
73 static DEFINE_SPINLOCK(canclk_lock);
74 static DEFINE_SPINLOCK(canmioclk_lock);
75 static DEFINE_SPINLOCK(dbgclk_lock);
76 static DEFINE_SPINLOCK(aperclk_lock);
78 static const char *const armpll_parents[] __initconst = {"armpll_int",
80 static const char *const ddrpll_parents[] __initconst = {"ddrpll_int",
82 static const char *const iopll_parents[] __initconst = {"iopll_int",
84 static const char *gem0_mux_parents[] __initdata = {"gem0_div1", "dummy_name"};
85 static const char *gem1_mux_parents[] __initdata = {"gem1_div1", "dummy_name"};
86 static const char *const can0_mio_mux2_parents[] __initconst = {"can0_gate",
88 static const char *const can1_mio_mux2_parents[] __initconst = {"can1_gate",
90 static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
93 static const char *const dbgtrc_emio_input_names[] __initconst = {
95 static const char *const gem0_emio_input_names[] __initconst = {
97 static const char *const gem1_emio_input_names[] __initconst = {
99 static const char *const swdt_ext_clk_input_names[] __initconst = {
102 static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
103 const char *clk_name, void __iomem *fclk_ctrl_reg,
104 const char **parents, int enable)
110 spinlock_t *fclk_lock;
111 spinlock_t *fclk_gate_lock;
112 void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
114 fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
117 fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
119 goto err_fclk_gate_lock;
120 spin_lock_init(fclk_lock);
121 spin_lock_init(fclk_gate_lock);
123 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
126 div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
129 div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
133 clk_register_mux(NULL, mux_name, parents, 4,
134 CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
137 clk_register_divider(NULL, div0_name, mux_name,
138 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
139 CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
141 clk_register_divider(NULL, div1_name, div0_name,
142 CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
143 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
146 clks[fclk] = clk_register_gate(NULL, clk_name,
147 div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
148 0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
149 enable_reg = readl(fclk_gate_reg) & 1;
150 if (enable && !enable_reg) {
151 if (clk_prepare_enable(clks[fclk]))
152 pr_warn("%s: FCLK%u enable failed\n", __func__,
166 kfree(fclk_gate_lock);
170 clks[fclk] = ERR_PTR(-ENOMEM);
173 static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
174 enum zynq_clk clk1, const char *clk_name0,
175 const char *clk_name1, void __iomem *clk_ctrl,
176 const char **parents, unsigned int two_gates)
182 lock = kmalloc(sizeof(*lock), GFP_KERNEL);
185 spin_lock_init(lock);
187 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
188 div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
190 clk_register_mux(NULL, mux_name, parents, 4,
191 CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
193 clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
194 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
196 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
197 CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
199 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
200 CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
208 clks[clk0] = ERR_PTR(-ENOMEM);
210 clks[clk1] = ERR_PTR(-ENOMEM);
213 static void __init zynq_clk_setup(struct device_node *np)
219 unsigned int fclk_enable = 0;
220 const char *clk_output_name[clk_max];
221 const char *cpu_parents[4];
222 const char *periph_parents[4];
223 const char *swdt_ext_clk_mux_parents[2];
224 const char *can_mio_mux_parents[NUM_MIO_PINS];
225 const char *dummy_nm = "dummy_name";
227 pr_info("Zynq clock init\n");
229 /* get clock output names from DT */
230 for (i = 0; i < clk_max; i++) {
231 if (of_property_read_string_index(np, "clock-output-names",
232 i, &clk_output_name[i])) {
233 pr_err("%s: clock output name not in DT\n", __func__);
237 cpu_parents[0] = clk_output_name[armpll];
238 cpu_parents[1] = clk_output_name[armpll];
239 cpu_parents[2] = clk_output_name[ddrpll];
240 cpu_parents[3] = clk_output_name[iopll];
241 periph_parents[0] = clk_output_name[iopll];
242 periph_parents[1] = clk_output_name[iopll];
243 periph_parents[2] = clk_output_name[armpll];
244 periph_parents[3] = clk_output_name[ddrpll];
246 of_property_read_u32(np, "fclk-enable", &fclk_enable);
249 ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
251 pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
254 ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp);
257 clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
258 SLCR_PLL_STATUS, 0, &armpll_lock);
259 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
260 armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
261 SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
263 clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
264 SLCR_PLL_STATUS, 1, &ddrpll_lock);
265 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
266 ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
267 SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
269 clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
270 SLCR_PLL_STATUS, 2, &iopll_lock);
271 clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
272 iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
273 SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
276 tmp = readl(SLCR_621_TRUE) & 1;
277 clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
278 CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
280 clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
281 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
282 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
284 clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
285 "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
286 SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
288 clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
290 clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
291 "cpu_3or2x_div", CLK_IGNORE_UNUSED,
292 SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
294 clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
296 clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
297 "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
298 26, 0, &armclk_lock);
299 clk_prepare_enable(clks[cpu_2x]);
301 clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
303 clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
304 "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
308 swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
309 for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
310 int idx = of_property_match_string(np, "clock-names",
311 swdt_ext_clk_input_names[i]);
313 swdt_ext_clk_mux_parents[i + 1] =
314 of_clk_get_parent_name(np, idx);
316 swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
318 clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
319 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
320 CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
324 clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
325 SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
326 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
327 clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
328 "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
329 clk_prepare_enable(clks[ddr2x]);
330 clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
331 SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
332 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
333 clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
334 "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
335 clk_prepare_enable(clks[ddr3x]);
337 clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
338 SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
339 CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
340 clk_register_divider(NULL, "dci_div1", "dci_div0",
341 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
342 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
344 clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
345 CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
347 clk_prepare_enable(clks[dci]);
349 /* Peripheral clocks */
350 for (i = fclk0; i <= fclk3; i++) {
351 int enable = !!(fclk_enable & BIT(i - fclk0));
353 zynq_clk_register_fclk(i, clk_output_name[i],
354 SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
355 periph_parents, enable);
358 zynq_clk_register_periph_clk(lqspi, clk_max, clk_output_name[lqspi], NULL,
359 SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
361 zynq_clk_register_periph_clk(smc, clk_max, clk_output_name[smc], NULL,
362 SLCR_SMC_CLK_CTRL, periph_parents, 0);
364 zynq_clk_register_periph_clk(pcap, clk_max, clk_output_name[pcap], NULL,
365 SLCR_PCAP_CLK_CTRL, periph_parents, 0);
367 zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
368 clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
371 zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
372 clk_output_name[uart1], SLCR_UART_CLK_CTRL,
375 zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
376 clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
379 for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
380 int idx = of_property_match_string(np, "clock-names",
381 gem0_emio_input_names[i]);
383 gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
386 clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
387 CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
389 clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
390 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
391 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
392 clk_register_divider(NULL, "gem0_div1", "gem0_div0",
393 CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
394 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
396 clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
397 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
398 SLCR_GEM0_CLK_CTRL, 6, 1, 0,
400 clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
401 "gem0_emio_mux", CLK_SET_RATE_PARENT,
402 SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
404 for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
405 int idx = of_property_match_string(np, "clock-names",
406 gem1_emio_input_names[i]);
408 gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
411 clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
412 CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
414 clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
415 SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
416 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
417 clk_register_divider(NULL, "gem1_div1", "gem1_div0",
418 CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
419 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
421 clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
422 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
423 SLCR_GEM1_CLK_CTRL, 6, 1, 0,
425 clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
426 "gem1_emio_mux", CLK_SET_RATE_PARENT,
427 SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
429 tmp = strlen("mio_clk_00x");
430 clk_name = kmalloc(tmp, GFP_KERNEL);
431 for (i = 0; i < NUM_MIO_PINS; i++) {
434 snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
435 idx = of_property_match_string(np, "clock-names", clk_name);
437 can_mio_mux_parents[i] = of_clk_get_parent_name(np,
440 can_mio_mux_parents[i] = dummy_nm;
443 clk_register_mux(NULL, "can_mux", periph_parents, 4,
444 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
446 clk_register_divider(NULL, "can_div0", "can_mux", 0,
447 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
448 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
449 clk_register_divider(NULL, "can_div1", "can_div0",
450 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
451 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
453 clk_register_gate(NULL, "can0_gate", "can_div1",
454 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
456 clk_register_gate(NULL, "can1_gate", "can_div1",
457 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
459 clk_register_mux(NULL, "can0_mio_mux",
460 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
461 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
463 clk_register_mux(NULL, "can1_mio_mux",
464 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
465 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
467 clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
468 can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
469 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0,
471 clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
472 can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
473 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1,
476 for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
477 int idx = of_property_match_string(np, "clock-names",
478 dbgtrc_emio_input_names[i]);
480 dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
483 clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
484 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
486 clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
487 SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
488 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
489 clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
490 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
492 clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
493 "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
495 clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
496 clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
499 /* leave debug clocks in the state the bootloader set them up to */
500 tmp = readl(SLCR_DBG_CLK_CTRL);
501 if (tmp & DBG_CLK_CTRL_CLKACT_TRC)
502 if (clk_prepare_enable(clks[dbg_trc]))
503 pr_warn("%s: trace clk enable failed\n", __func__);
504 if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT)
505 if (clk_prepare_enable(clks[dbg_apb]))
506 pr_warn("%s: debug APB clk enable failed\n", __func__);
508 /* One gated clock for all APER clocks. */
509 clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
510 clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
512 clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
513 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
515 clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
516 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
518 clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
519 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
521 clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
522 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
524 clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
525 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
527 clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
528 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
530 clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
531 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
533 clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
534 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
536 clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
537 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
539 clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
540 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
542 clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
543 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
545 clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
546 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
548 clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
549 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
551 clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
552 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
554 clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
555 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
557 clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
558 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
560 clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
561 clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
564 for (i = 0; i < ARRAY_SIZE(clks); i++) {
565 if (IS_ERR(clks[i])) {
566 pr_err("Zynq clk %d: register failed with %ld\n",
567 i, PTR_ERR(clks[i]));
572 clk_data.clks = clks;
573 clk_data.clk_num = ARRAY_SIZE(clks);
574 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
577 CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
579 void __init zynq_clock_init(void)
581 struct device_node *np;
582 struct device_node *slcr;
585 np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");
587 pr_err("%s: clkc node not found\n", __func__);
591 if (of_address_to_resource(np, 0, &res)) {
592 pr_err("%pOFn: failed to get resource\n", np);
596 slcr = of_get_parent(np);
599 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
601 pr_err("%pOFn: Unable to get I/O memory\n", np);
606 pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base);