1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
4 * Copyright (C) 2020 Intel Corporation.
5 * Zhu Yixin <yzhu@maxlinear.com>
6 * Rahul Tanwar <rtanwar@maxlinear.com>
12 #include <linux/regmap.h>
16 struct regmap *membase;
23 struct lgm_clk_divider {
25 struct regmap *membase;
32 const struct clk_div_table *table;
37 struct regmap *membase;
54 struct regmap *membase;
64 CLK_TYPE_FIXED_FACTOR,
70 * struct lgm_clk_provider
71 * @membase: IO mem base address for CGU.
74 * @clk_data: array of hw clocks and clk number.
76 struct lgm_clk_provider {
77 struct regmap *membase;
78 struct device_node *np;
80 struct clk_hw_onecell_data clk_data;
91 struct regmap *membase;
98 * struct lgm_pll_clk_data
99 * @id: platform specific id of the clock.
100 * @name: name of this pll clock.
101 * @parent_data: parent clock data.
102 * @num_parents: number of parents.
103 * @flags: optional flags for basic clock.
104 * @type: platform type of pll.
105 * @reg: offset of the register.
107 struct lgm_pll_clk_data {
110 const struct clk_parent_data *parent_data;
117 #define LGM_PLL(_id, _name, _pdata, _flags, \
122 .parent_data = _pdata, \
123 .num_parents = ARRAY_SIZE(_pdata), \
129 struct lgm_clk_ddiv_data {
132 const struct clk_parent_data *parent_data;
134 unsigned long div_flags;
146 #define LGM_DDIV(_id, _name, _pname, _flags, _reg, \
147 _shft0, _wdth0, _shft1, _wdth1, \
148 _shft_gate, _wdth_gate, _xshft, _df) \
152 .parent_data = &(const struct clk_parent_data){ \
162 .shift_gate = _shft_gate, \
163 .width_gate = _wdth_gate, \
164 .ex_shift = _xshft, \
169 struct lgm_clk_branch {
171 enum lgm_clk_type type;
173 const struct clk_parent_data *parent_data;
176 unsigned int mux_off;
179 unsigned long mux_flags;
180 unsigned int mux_val;
181 unsigned int div_off;
186 unsigned long div_flags;
187 unsigned int div_val;
188 const struct clk_div_table *div_table;
189 unsigned int gate_off;
191 unsigned long gate_flags;
192 unsigned int gate_val;
197 /* clock flags definition */
198 #define CLOCK_FLAG_VAL_INIT BIT(16)
199 #define MUX_CLK_SW BIT(17)
200 #define GATE_CLK_HW BIT(18)
201 #define DIV_CLK_NO_MASK BIT(19)
203 #define LGM_MUX(_id, _name, _pdata, _f, _reg, \
204 _shift, _width, _cf, _v) \
207 .type = CLK_TYPE_MUX, \
209 .parent_data = _pdata, \
210 .num_parents = ARRAY_SIZE(_pdata), \
213 .mux_shift = _shift, \
214 .mux_width = _width, \
219 #define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \
220 _shift_gate, _width_gate, _cf, _v, _dtable) \
223 .type = CLK_TYPE_DIVIDER, \
225 .parent_data = &(const struct clk_parent_data){ \
232 .div_shift = _shift, \
233 .div_width = _width, \
234 .div_shift_gate = _shift_gate, \
235 .div_width_gate = _width_gate, \
238 .div_table = _dtable, \
241 #define LGM_GATE(_id, _name, _pname, _f, _reg, \
245 .type = CLK_TYPE_GATE, \
247 .parent_data = &(const struct clk_parent_data){ \
251 .num_parents = !_pname ? 0 : 1, \
254 .gate_shift = _shift, \
259 #define LGM_FIXED(_id, _name, _pname, _f, _reg, \
260 _shift, _width, _cf, _freq, _v) \
263 .type = CLK_TYPE_FIXED, \
265 .parent_data = &(const struct clk_parent_data){ \
269 .num_parents = !_pname ? 0 : 1, \
272 .div_shift = _shift, \
273 .div_width = _width, \
276 .mux_flags = _freq, \
279 #define LGM_FIXED_FACTOR(_id, _name, _pname, _f, _reg, \
280 _shift, _width, _cf, _v, _m, _d) \
283 .type = CLK_TYPE_FIXED_FACTOR, \
285 .parent_data = &(const struct clk_parent_data){ \
292 .div_shift = _shift, \
293 .div_width = _width, \
300 static inline void lgm_set_clk_val(struct regmap *membase, u32 reg,
301 u8 shift, u8 width, u32 set_val)
303 u32 mask = (GENMASK(width - 1, 0) << shift);
305 regmap_update_bits(membase, reg, mask, set_val << shift);
308 static inline u32 lgm_get_clk_val(struct regmap *membase, u32 reg,
311 u32 mask = (GENMASK(width - 1, 0) << shift);
314 if (regmap_read(membase, reg, &val)) {
315 WARN_ONCE(1, "Failed to read clk reg: 0x%x\n", reg);
319 val = (val & mask) >> shift;
326 int lgm_clk_register_branches(struct lgm_clk_provider *ctx,
327 const struct lgm_clk_branch *list,
328 unsigned int nr_clk);
329 int lgm_clk_register_plls(struct lgm_clk_provider *ctx,
330 const struct lgm_pll_clk_data *list,
331 unsigned int nr_clk);
332 int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
333 const struct lgm_clk_ddiv_data *list,
334 unsigned int nr_clk);
335 #endif /* __CLK_CGU_H */