1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments, Inc.
7 * Tero Kristo (t-kristo@ti.com)
10 #include <linux/kernel.h>
11 #include <linux/list.h>
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
15 #include <linux/clk/ti.h>
16 #include <dt-bindings/clock/omap5.h>
20 #define OMAP5_DPLL_ABE_DEFFREQ 98304000
23 * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
24 * states it must be at 960MHz
26 #define OMAP5_DPLL_USB_DEFFREQ 960000000
28 static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = {
29 { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
33 static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
34 { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h11x2_ck" },
38 static const char * const omap5_aess_fclk_parents[] __initconst = {
43 static const struct omap_clkctrl_div_data omap5_aess_fclk_data __initconst = {
47 static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = {
48 { 24, TI_CLK_DIVIDER, omap5_aess_fclk_parents, &omap5_aess_fclk_data },
52 static const char * const omap5_dmic_gfclk_parents[] __initconst = {
59 static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
66 static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
67 { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
68 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
72 static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
79 static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = {
80 { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
81 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
85 static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
92 static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = {
93 { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
94 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
98 static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
105 static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = {
106 { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
107 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
111 static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = {
117 static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = {
118 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
122 static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = {
123 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
127 static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = {
128 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
132 static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = {
133 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
137 static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
138 { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
139 { OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
140 { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
141 { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
142 { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
143 { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
144 { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
145 { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
146 { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
147 { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
148 { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
152 static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = {
153 { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
157 static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = {
158 { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
162 static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = {
163 { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
167 static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = {
168 { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
172 static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = {
173 { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
174 { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
175 { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
179 static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = {
180 { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" },
181 { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" },
182 { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" },
186 static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = {
187 { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
188 { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
192 static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = {
198 static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = {
199 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
203 static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = {
204 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
208 static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = {
209 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
213 static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = {
214 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
218 static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = {
219 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
223 static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = {
224 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
228 static const char * const omap5_gpio2_dbclk_parents[] __initconst = {
233 static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = {
234 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
238 static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = {
239 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
243 static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = {
244 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
248 static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = {
249 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
253 static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = {
254 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
258 static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = {
259 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
263 static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
264 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
268 static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
269 { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" },
270 { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" },
271 { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" },
272 { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" },
273 { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
274 { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
275 { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
276 { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
277 { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
278 { OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
279 { OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
280 { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
281 { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
282 { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
283 { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
284 { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" },
285 { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
286 { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
287 { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
288 { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
289 { OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
290 { OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
291 { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
292 { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
293 { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
294 { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
295 { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
296 { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
297 { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
298 { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
299 { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
300 { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
304 static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = {
305 { OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
306 { OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
310 static const char * const omap5_dss_dss_clk_parents[] __initconst = {
315 static const char * const omap5_dss_48mhz_clk_parents[] __initconst = {
320 static const char * const omap5_dss_sys_clk_parents[] __initconst = {
325 static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = {
326 { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
327 { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
328 { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
329 { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
333 static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
334 { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
338 static const char * const omap5_gpu_core_mux_parents[] __initconst = {
339 "dpll_core_h14x2_ck",
344 static const char * const omap5_gpu_hyd_mux_parents[] __initconst = {
345 "dpll_core_h14x2_ck",
350 static const char * const omap5_gpu_sys_clk_parents[] __initconst = {
355 static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = {
359 static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = {
360 { 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
361 { 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
362 { 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data },
366 static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
367 { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" },
371 static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
377 static const char * const omap5_mmc1_fclk_parents[] __initconst = {
378 "l3init_cm:clk:0008:24",
382 static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = {
386 static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
387 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
388 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
389 { 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data },
393 static const char * const omap5_mmc2_fclk_parents[] __initconst = {
394 "l3init_cm:clk:0010:24",
398 static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = {
402 static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = {
403 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
404 { 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data },
408 static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = {
413 static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = {
418 static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
419 "l3init_cm:clk:0038:24",
423 static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
424 "l3init_cm:clk:0038:25",
428 static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = {
434 static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = {
440 static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = {
441 { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
442 { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
443 { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
444 { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
445 { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
446 { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
447 { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
448 { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
449 { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
450 { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
451 { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
455 static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = {
456 { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
457 { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
458 { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
462 static const char * const omap5_sata_ref_clk_parents[] __initconst = {
467 static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = {
468 { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
472 static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = {
473 "dpll_usb_clkdcoldo",
477 static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = {
478 { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
482 static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
483 { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
484 { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
485 { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
486 { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
487 { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
488 { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
489 { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
490 { OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
494 static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = {
495 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
499 static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = {
500 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
504 static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = {
505 { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
506 { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
507 { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
508 { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
509 { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
510 { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
514 const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
515 { 0x4a004320, omap5_mpu_clkctrl_regs },
516 { 0x4a004420, omap5_dsp_clkctrl_regs },
517 { 0x4a004520, omap5_abe_clkctrl_regs },
518 { 0x4a008720, omap5_l3main1_clkctrl_regs },
519 { 0x4a008820, omap5_l3main2_clkctrl_regs },
520 { 0x4a008920, omap5_ipu_clkctrl_regs },
521 { 0x4a008a20, omap5_dma_clkctrl_regs },
522 { 0x4a008b20, omap5_emif_clkctrl_regs },
523 { 0x4a008d20, omap5_l4cfg_clkctrl_regs },
524 { 0x4a008e20, omap5_l3instr_clkctrl_regs },
525 { 0x4a009020, omap5_l4per_clkctrl_regs },
526 { 0x4a009220, omap5_iva_clkctrl_regs },
527 { 0x4a009420, omap5_dss_clkctrl_regs },
528 { 0x4a009520, omap5_gpu_clkctrl_regs },
529 { 0x4a009620, omap5_l3init_clkctrl_regs },
530 { 0x4ae07920, omap5_wkupaon_clkctrl_regs },
534 static struct ti_dt_clk omap54xx_clks[] = {
535 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
536 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
537 DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
538 DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
539 DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
540 DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
541 DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
542 DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"),
543 DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
544 DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"),
545 DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"),
546 DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"),
547 DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"),
548 DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"),
549 DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"),
550 DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"),
551 DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
552 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
553 DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
554 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
555 DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
556 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
557 DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"),
558 DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"),
559 DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
560 DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"),
561 DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
562 DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
563 DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
564 DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
565 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
566 DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
567 DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
568 DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
569 DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
570 DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
571 DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
572 DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
573 DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
574 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"),
575 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"),
576 DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"),
577 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"),
578 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"),
579 DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"),
580 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"),
581 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"),
582 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"),
583 DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"),
584 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"),
585 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"),
586 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"),
587 DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),
588 DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"),
589 { .node_name = NULL },
592 int __init omap5xxx_dt_clk_init(void)
595 struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
597 ti_dt_clocks_register(omap54xx_clks);
599 omap2_clk_disable_autoidle_all();
601 ti_clk_add_aliases();
603 abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
604 sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
605 rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
606 abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
608 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
610 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
612 abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
614 rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2);
616 pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__);
618 usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
619 rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
621 pr_err("%s: failed to configure USB DPLL!\n", __func__);
623 usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
624 rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
626 pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);