1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
9 #include <linux/clkdev.h>
11 #include <linux/of_address.h>
12 #include <linux/syscore_ops.h>
13 #include <linux/delay.h>
14 #include <linux/export.h>
15 #include <linux/mutex.h>
16 #include <linux/clk/tegra.h>
17 #include <dt-bindings/clock/tegra210-car.h>
18 #include <dt-bindings/reset/tegra210-car.h>
19 #include <linux/sizes.h>
20 #include <soc/tegra/pmc.h>
26 * TEGRA210_CAR_BANK_COUNT: the number of peripheral clock register
27 * banks present in the Tegra210 CAR IP block. The banks are
28 * identified by single letters, e.g.: L, H, U, V, W, X, Y. See
29 * periph_regs[] in drivers/clk/tegra/clk.c
31 #define TEGRA210_CAR_BANK_COUNT 7
33 #define CLK_SOURCE_CSITE 0x1d4
34 #define CLK_SOURCE_EMC 0x19c
35 #define CLK_SOURCE_SOR1 0x410
36 #define CLK_SOURCE_SOR0 0x414
37 #define CLK_SOURCE_LA 0x1f8
38 #define CLK_SOURCE_SDMMC2 0x154
39 #define CLK_SOURCE_SDMMC4 0x164
41 #define PLLC_BASE 0x80
43 #define PLLC_MISC0 0x88
44 #define PLLC_MISC1 0x8c
45 #define PLLC_MISC2 0x5d0
46 #define PLLC_MISC3 0x5d4
48 #define PLLC2_BASE 0x4e8
49 #define PLLC2_MISC0 0x4ec
50 #define PLLC2_MISC1 0x4f0
51 #define PLLC2_MISC2 0x4f4
52 #define PLLC2_MISC3 0x4f8
54 #define PLLC3_BASE 0x4fc
55 #define PLLC3_MISC0 0x500
56 #define PLLC3_MISC1 0x504
57 #define PLLC3_MISC2 0x508
58 #define PLLC3_MISC3 0x50c
60 #define PLLM_BASE 0x90
61 #define PLLM_MISC1 0x98
62 #define PLLM_MISC2 0x9c
63 #define PLLP_BASE 0xa0
64 #define PLLP_MISC0 0xac
65 #define PLLP_MISC1 0x680
66 #define PLLA_BASE 0xb0
67 #define PLLA_MISC0 0xbc
68 #define PLLA_MISC1 0xb8
69 #define PLLA_MISC2 0x5d8
70 #define PLLD_BASE 0xd0
71 #define PLLD_MISC0 0xdc
72 #define PLLD_MISC1 0xd8
73 #define PLLU_BASE 0xc0
74 #define PLLU_OUTA 0xc4
75 #define PLLU_MISC0 0xcc
76 #define PLLU_MISC1 0xc8
77 #define PLLX_BASE 0xe0
78 #define PLLX_MISC0 0xe4
79 #define PLLX_MISC1 0x510
80 #define PLLX_MISC2 0x514
81 #define PLLX_MISC3 0x518
82 #define PLLX_MISC4 0x5f0
83 #define PLLX_MISC5 0x5f4
84 #define PLLE_BASE 0xe8
85 #define PLLE_MISC0 0xec
86 #define PLLD2_BASE 0x4b8
87 #define PLLD2_MISC0 0x4bc
88 #define PLLD2_MISC1 0x570
89 #define PLLD2_MISC2 0x574
90 #define PLLD2_MISC3 0x578
91 #define PLLE_AUX 0x48c
92 #define PLLRE_BASE 0x4c4
93 #define PLLRE_MISC0 0x4c8
94 #define PLLRE_OUT1 0x4cc
95 #define PLLDP_BASE 0x590
96 #define PLLDP_MISC 0x594
98 #define PLLC4_BASE 0x5a4
99 #define PLLC4_MISC0 0x5a8
100 #define PLLC4_OUT 0x5e4
101 #define PLLMB_BASE 0x5e8
102 #define PLLMB_MISC1 0x5ec
103 #define PLLA1_BASE 0x6a4
104 #define PLLA1_MISC0 0x6a8
105 #define PLLA1_MISC1 0x6ac
106 #define PLLA1_MISC2 0x6b0
107 #define PLLA1_MISC3 0x6b4
109 #define PLLU_IDDQ_BIT 31
110 #define PLLCX_IDDQ_BIT 27
111 #define PLLRE_IDDQ_BIT 24
112 #define PLLA_IDDQ_BIT 25
113 #define PLLD_IDDQ_BIT 20
114 #define PLLSS_IDDQ_BIT 18
115 #define PLLM_IDDQ_BIT 5
116 #define PLLMB_IDDQ_BIT 17
117 #define PLLXP_IDDQ_BIT 3
119 #define PLLCX_RESET_BIT 30
121 #define PLL_BASE_LOCK BIT(27)
122 #define PLLCX_BASE_LOCK BIT(26)
123 #define PLLE_MISC_LOCK BIT(11)
124 #define PLLRE_MISC_LOCK BIT(27)
126 #define PLL_MISC_LOCK_ENABLE 18
127 #define PLLC_MISC_LOCK_ENABLE 24
128 #define PLLDU_MISC_LOCK_ENABLE 22
129 #define PLLU_MISC_LOCK_ENABLE 29
130 #define PLLE_MISC_LOCK_ENABLE 9
131 #define PLLRE_MISC_LOCK_ENABLE 30
132 #define PLLSS_MISC_LOCK_ENABLE 30
133 #define PLLP_MISC_LOCK_ENABLE 18
134 #define PLLM_MISC_LOCK_ENABLE 4
135 #define PLLMB_MISC_LOCK_ENABLE 16
136 #define PLLA_MISC_LOCK_ENABLE 28
137 #define PLLU_MISC_LOCK_ENABLE 29
138 #define PLLD_MISC_LOCK_ENABLE 18
140 #define PLLA_SDM_DIN_MASK 0xffff
141 #define PLLA_SDM_EN_MASK BIT(26)
143 #define PLLD_SDM_EN_MASK BIT(16)
145 #define PLLD2_SDM_EN_MASK BIT(31)
146 #define PLLD2_SSC_EN_MASK 0
148 #define PLLDP_SS_CFG 0x598
149 #define PLLDP_SDM_EN_MASK BIT(31)
150 #define PLLDP_SSC_EN_MASK BIT(30)
151 #define PLLDP_SS_CTRL1 0x59c
152 #define PLLDP_SS_CTRL2 0x5a0
154 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
155 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
157 #define UTMIP_PLL_CFG2 0x488
158 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
159 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
160 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
161 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
162 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
163 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
164 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
165 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
166 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
167 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
169 #define UTMIP_PLL_CFG1 0x484
170 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
171 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
172 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
173 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
174 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
175 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
176 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
178 #define SATA_PLL_CFG0 0x490
179 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
180 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
181 #define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL BIT(4)
182 #define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE BIT(5)
183 #define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6)
184 #define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE BIT(7)
186 #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13)
187 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
189 #define XUSBIO_PLL_CFG0 0x51c
190 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
191 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
192 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
193 #define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13)
194 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
196 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
197 #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31)
198 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
199 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
200 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7)
201 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
202 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
203 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
204 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
205 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
206 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
208 #define PLLU_HW_PWRDN_CFG0 0x530
209 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
210 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
211 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
212 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
213 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
214 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
216 #define XUSB_PLL_CFG0 0x534
217 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
218 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14)
220 #define SPARE_REG0 0x55c
221 #define CLK_M_DIVISOR_SHIFT 2
222 #define CLK_M_DIVISOR_MASK 0x3
224 #define CLK_MASK_ARM 0x44
225 #define MISC_CLK_ENB 0x48
227 #define RST_DFLL_DVCO 0x2f4
228 #define DVFS_DFLL_RESET_SHIFT 0
230 #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
231 #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
232 #define CPU_SOFTRST_CTRL 0x380
234 #define LVL2_CLK_GATE_OVRA 0xf8
235 #define LVL2_CLK_GATE_OVRC 0x3a0
236 #define LVL2_CLK_GATE_OVRD 0x3a4
237 #define LVL2_CLK_GATE_OVRE 0x554
239 /* I2S registers to handle during APE MBIST WAR */
240 #define TEGRA210_I2S_BASE 0x1000
241 #define TEGRA210_I2S_SIZE 0x100
242 #define TEGRA210_I2S_CTRLS 5
243 #define TEGRA210_I2S_CG 0x88
244 #define TEGRA210_I2S_CTRL 0xa0
246 /* DISPA registers to handle during MBIST WAR */
247 #define DC_CMD_DISPLAY_COMMAND 0xc8
248 #define DC_COM_DSC_TOP_CTL 0xcf8
250 /* VIC register to handle during MBIST WAR */
251 #define NV_PVIC_THI_SLCG_OVERRIDE_LOW 0x8c
253 /* APE, DISPA and VIC base addesses needed for MBIST WAR */
254 #define TEGRA210_AHUB_BASE 0x702d0000
255 #define TEGRA210_DISPA_BASE 0x54200000
256 #define TEGRA210_VIC_BASE 0x54340000
259 * SDM fractional divisor is 16-bit 2's complement signed number within
260 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
261 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
262 * indicate that SDM is disabled.
264 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
266 #define PLL_SDM_COEFF BIT(13)
267 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
268 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
269 /* This macro returns ndiv effective scaled to SDM range */
270 #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \
271 (PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0))
273 /* Tegra CPU clock and reset control regs */
274 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
276 #ifdef CONFIG_PM_SLEEP
277 static struct cpu_clk_suspend_context {
279 } tegra210_cpu_clk_sctx;
282 struct tegra210_domain_mbist_war {
283 void (*handle_lvl2_ovr)(struct tegra210_domain_mbist_war *mbist);
284 const u32 lvl2_offset;
286 const unsigned int num_clks;
287 const unsigned int *clk_init_data;
288 struct clk_bulk_data *clks;
291 static struct clk **clks;
293 static void __iomem *clk_base;
294 static void __iomem *pmc_base;
295 static void __iomem *ahub_base;
296 static void __iomem *dispa_base;
297 static void __iomem *vic_base;
299 static unsigned long osc_freq;
300 static unsigned long pll_ref_freq;
302 static DEFINE_SPINLOCK(pll_d_lock);
303 static DEFINE_SPINLOCK(pll_e_lock);
304 static DEFINE_SPINLOCK(pll_re_lock);
305 static DEFINE_SPINLOCK(pll_u_lock);
306 static DEFINE_SPINLOCK(sor0_lock);
307 static DEFINE_SPINLOCK(sor1_lock);
308 static DEFINE_SPINLOCK(emc_lock);
309 static DEFINE_MUTEX(lvl2_ovr_lock);
311 /* possible OSC frequencies in Hz */
312 static unsigned long tegra210_input_freq[] = {
317 static const char *mux_pllmcp_clkm[] = {
318 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
321 #define mux_pllmcp_clkm_idx NULL
323 #define PLL_ENABLE (1 << 30)
325 #define PLLCX_MISC1_IDDQ (1 << 27)
326 #define PLLCX_MISC0_RESET (1 << 30)
328 #define PLLCX_MISC0_DEFAULT_VALUE 0x40080000
329 #define PLLCX_MISC0_WRITE_MASK 0x400ffffb
330 #define PLLCX_MISC1_DEFAULT_VALUE 0x08000000
331 #define PLLCX_MISC1_WRITE_MASK 0x08003cff
332 #define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05
333 #define PLLCX_MISC2_WRITE_MASK 0xffffff17
334 #define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4
335 #define PLLCX_MISC3_WRITE_MASK 0x00ffffff
338 #define PLLA_BASE_IDDQ (1 << 25)
339 #define PLLA_BASE_LOCK (1 << 27)
341 #define PLLA_MISC0_LOCK_ENABLE (1 << 28)
342 #define PLLA_MISC0_LOCK_OVERRIDE (1 << 27)
344 #define PLLA_MISC2_EN_SDM (1 << 26)
345 #define PLLA_MISC2_EN_DYNRAMP (1 << 25)
347 #define PLLA_MISC0_DEFAULT_VALUE 0x12000020
348 #define PLLA_MISC0_WRITE_MASK 0x7fffffff
349 #define PLLA_MISC2_DEFAULT_VALUE 0x0
350 #define PLLA_MISC2_WRITE_MASK 0x06ffffff
353 #define PLLD_BASE_CSI_CLKSOURCE (1 << 23)
355 #define PLLD_MISC0_EN_SDM (1 << 16)
356 #define PLLD_MISC0_LOCK_OVERRIDE (1 << 17)
357 #define PLLD_MISC0_LOCK_ENABLE (1 << 18)
358 #define PLLD_MISC0_IDDQ (1 << 20)
359 #define PLLD_MISC0_DSI_CLKENABLE (1 << 21)
361 #define PLLD_MISC0_DEFAULT_VALUE 0x00140000
362 #define PLLD_MISC0_WRITE_MASK 0x3ff7ffff
363 #define PLLD_MISC1_DEFAULT_VALUE 0x20
364 #define PLLD_MISC1_WRITE_MASK 0x00ffffff
366 /* PLLD2 and PLLDP and PLLC4 */
367 #define PLLDSS_BASE_LOCK (1 << 27)
368 #define PLLDSS_BASE_LOCK_OVERRIDE (1 << 24)
369 #define PLLDSS_BASE_IDDQ (1 << 18)
370 #define PLLDSS_BASE_REF_SEL_SHIFT 25
371 #define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT)
373 #define PLLDSS_MISC0_LOCK_ENABLE (1 << 30)
375 #define PLLDSS_MISC1_CFG_EN_SDM (1 << 31)
376 #define PLLDSS_MISC1_CFG_EN_SSC (1 << 30)
378 #define PLLD2_MISC0_DEFAULT_VALUE 0x40000020
379 #define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000
380 #define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0
381 #define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0
383 #define PLLDP_MISC0_DEFAULT_VALUE 0x40000020
384 #define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000
385 #define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da
386 #define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400
388 #define PLLDSS_MISC0_WRITE_MASK 0x47ffffff
389 #define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000
390 #define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff
391 #define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff
393 #define PLLC4_MISC0_DEFAULT_VALUE 0x40000000
396 #define PLLRE_MISC0_LOCK_ENABLE (1 << 30)
397 #define PLLRE_MISC0_LOCK_OVERRIDE (1 << 29)
398 #define PLLRE_MISC0_LOCK (1 << 27)
399 #define PLLRE_MISC0_IDDQ (1 << 24)
401 #define PLLRE_BASE_DEFAULT_VALUE 0x0
402 #define PLLRE_MISC0_DEFAULT_VALUE 0x41000000
404 #define PLLRE_BASE_DEFAULT_MASK 0x1c000000
405 #define PLLRE_MISC0_WRITE_MASK 0x67ffffff
408 #define PLLX_USE_DYN_RAMP 1
409 #define PLLX_BASE_LOCK (1 << 27)
411 #define PLLX_MISC0_FO_G_DISABLE (0x1 << 28)
412 #define PLLX_MISC0_LOCK_ENABLE (0x1 << 18)
414 #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24
415 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
416 #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16
417 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
418 #define PLLX_MISC2_NDIV_NEW_SHIFT 8
419 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
420 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
421 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
422 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
424 #define PLLX_MISC3_IDDQ (0x1 << 3)
426 #define PLLX_MISC0_DEFAULT_VALUE PLLX_MISC0_LOCK_ENABLE
427 #define PLLX_MISC0_WRITE_MASK 0x10c40000
428 #define PLLX_MISC1_DEFAULT_VALUE 0x20
429 #define PLLX_MISC1_WRITE_MASK 0x00ffffff
430 #define PLLX_MISC2_DEFAULT_VALUE 0x0
431 #define PLLX_MISC2_WRITE_MASK 0xffffff11
432 #define PLLX_MISC3_DEFAULT_VALUE PLLX_MISC3_IDDQ
433 #define PLLX_MISC3_WRITE_MASK 0x01ff0f0f
434 #define PLLX_MISC4_DEFAULT_VALUE 0x0
435 #define PLLX_MISC4_WRITE_MASK 0x8000ffff
436 #define PLLX_MISC5_DEFAULT_VALUE 0x0
437 #define PLLX_MISC5_WRITE_MASK 0x0000ffff
439 #define PLLX_HW_CTRL_CFG 0x548
440 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
443 #define PLLMB_BASE_LOCK (1 << 27)
445 #define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18)
446 #define PLLMB_MISC1_IDDQ (1 << 17)
447 #define PLLMB_MISC1_LOCK_ENABLE (1 << 16)
449 #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000
450 #define PLLMB_MISC1_WRITE_MASK 0x0007ffff
453 #define PLLP_BASE_OVERRIDE (1 << 28)
454 #define PLLP_BASE_LOCK (1 << 27)
456 #define PLLP_MISC0_LOCK_ENABLE (1 << 18)
457 #define PLLP_MISC0_LOCK_OVERRIDE (1 << 17)
458 #define PLLP_MISC0_IDDQ (1 << 3)
460 #define PLLP_MISC1_HSIO_EN_SHIFT 29
461 #define PLLP_MISC1_HSIO_EN (1 << PLLP_MISC1_HSIO_EN_SHIFT)
462 #define PLLP_MISC1_XUSB_EN_SHIFT 28
463 #define PLLP_MISC1_XUSB_EN (1 << PLLP_MISC1_XUSB_EN_SHIFT)
465 #define PLLP_MISC0_DEFAULT_VALUE 0x00040008
466 #define PLLP_MISC1_DEFAULT_VALUE 0x0
468 #define PLLP_MISC0_WRITE_MASK 0xdc6000f
469 #define PLLP_MISC1_WRITE_MASK 0x70ffffff
472 #define PLLU_BASE_LOCK (1 << 27)
473 #define PLLU_BASE_OVERRIDE (1 << 24)
474 #define PLLU_BASE_CLKENABLE_USB (1 << 21)
475 #define PLLU_BASE_CLKENABLE_HSIC (1 << 22)
476 #define PLLU_BASE_CLKENABLE_ICUSB (1 << 23)
477 #define PLLU_BASE_CLKENABLE_48M (1 << 25)
478 #define PLLU_BASE_CLKENABLE_ALL (PLLU_BASE_CLKENABLE_USB |\
479 PLLU_BASE_CLKENABLE_HSIC |\
480 PLLU_BASE_CLKENABLE_ICUSB |\
481 PLLU_BASE_CLKENABLE_48M)
483 #define PLLU_MISC0_IDDQ (1 << 31)
484 #define PLLU_MISC0_LOCK_ENABLE (1 << 29)
485 #define PLLU_MISC1_LOCK_OVERRIDE (1 << 0)
487 #define PLLU_MISC0_DEFAULT_VALUE 0xa0000000
488 #define PLLU_MISC1_DEFAULT_VALUE 0x0
490 #define PLLU_MISC0_WRITE_MASK 0xbfffffff
491 #define PLLU_MISC1_WRITE_MASK 0x00000007
493 void tegra210_xusb_pll_hw_control_enable(void)
497 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
498 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
499 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
500 val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
501 XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
502 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
504 EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_control_enable);
506 void tegra210_xusb_pll_hw_sequence_start(void)
510 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
511 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
512 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
514 EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_sequence_start);
516 void tegra210_sata_pll_hw_control_enable(void)
520 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
521 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
522 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET |
523 SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ;
524 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
526 EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_control_enable);
528 void tegra210_sata_pll_hw_sequence_start(void)
532 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
533 val |= SATA_PLL_CFG0_SEQ_ENABLE;
534 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
536 EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start);
538 void tegra210_set_sata_pll_seq_sw(bool state)
542 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
544 val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
545 val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
546 val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
547 val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
549 val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
550 val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
551 val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
552 val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
554 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
556 EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw);
558 static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist)
562 val = readl_relaxed(clk_base + mbist->lvl2_offset);
563 writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset);
564 fence_udelay(1, clk_base);
565 writel_relaxed(val, clk_base + mbist->lvl2_offset);
566 fence_udelay(1, clk_base);
569 static void tegra210_venc_mbist_war(struct tegra210_domain_mbist_war *mbist)
571 u32 csi_src, ovra, ovre;
572 unsigned long flags = 0;
574 spin_lock_irqsave(&pll_d_lock, flags);
576 csi_src = readl_relaxed(clk_base + PLLD_BASE);
577 writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE);
578 fence_udelay(1, clk_base);
580 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
581 writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA);
582 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
583 writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE);
584 fence_udelay(1, clk_base);
586 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
587 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
588 writel_relaxed(csi_src, clk_base + PLLD_BASE);
589 fence_udelay(1, clk_base);
591 spin_unlock_irqrestore(&pll_d_lock, flags);
594 static void tegra210_disp_mbist_war(struct tegra210_domain_mbist_war *mbist)
596 u32 ovra, dsc_top_ctrl;
598 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
599 writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA);
600 fence_udelay(1, clk_base);
602 dsc_top_ctrl = readl_relaxed(dispa_base + DC_COM_DSC_TOP_CTL);
603 writel_relaxed(dsc_top_ctrl | BIT(2), dispa_base + DC_COM_DSC_TOP_CTL);
604 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
605 writel_relaxed(dsc_top_ctrl, dispa_base + DC_COM_DSC_TOP_CTL);
606 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
608 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
609 fence_udelay(1, clk_base);
612 static void tegra210_vic_mbist_war(struct tegra210_domain_mbist_war *mbist)
616 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
617 writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE);
618 fence_udelay(1, clk_base);
620 val = readl_relaxed(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
621 writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24),
622 vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
623 fence_udelay(1, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
625 writel_relaxed(val, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
626 readl(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
628 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
629 fence_udelay(1, clk_base);
632 static void tegra210_ape_mbist_war(struct tegra210_domain_mbist_war *mbist)
634 void __iomem *i2s_base;
638 ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC);
639 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
640 writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC);
641 writel_relaxed(ovre | BIT(10) | BIT(11),
642 clk_base + LVL2_CLK_GATE_OVRE);
643 fence_udelay(1, clk_base);
645 i2s_base = ahub_base + TEGRA210_I2S_BASE;
647 for (i = 0; i < TEGRA210_I2S_CTRLS; i++) {
650 i2s_ctrl = readl_relaxed(i2s_base + TEGRA210_I2S_CTRL);
651 writel_relaxed(i2s_ctrl | BIT(10),
652 i2s_base + TEGRA210_I2S_CTRL);
653 writel_relaxed(0, i2s_base + TEGRA210_I2S_CG);
654 readl(i2s_base + TEGRA210_I2S_CG);
655 writel_relaxed(1, i2s_base + TEGRA210_I2S_CG);
656 writel_relaxed(i2s_ctrl, i2s_base + TEGRA210_I2S_CTRL);
657 readl(i2s_base + TEGRA210_I2S_CTRL);
659 i2s_base += TEGRA210_I2S_SIZE;
662 writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC);
663 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
664 fence_udelay(1, clk_base);
667 static inline void _pll_misc_chk_default(void __iomem *base,
668 struct tegra_clk_pll_params *params,
669 u8 misc_num, u32 default_val, u32 mask)
671 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]);
675 if (boot_val != default_val) {
676 pr_warn("boot misc%d 0x%x: expected 0x%x\n",
677 misc_num, boot_val, default_val);
678 pr_warn(" (comparison mask = 0x%x)\n", mask);
679 params->defaults_set = false;
684 * PLLCX: PLLC, PLLC2, PLLC3, PLLA1
685 * Hybrid PLLs with dynamic ramp. Dynamic ramp is allowed for any transition
686 * that changes NDIV only, while PLL is already locked.
688 static void pllcx_check_defaults(struct tegra_clk_pll_params *params)
692 default_val = PLLCX_MISC0_DEFAULT_VALUE & (~PLLCX_MISC0_RESET);
693 _pll_misc_chk_default(clk_base, params, 0, default_val,
694 PLLCX_MISC0_WRITE_MASK);
696 default_val = PLLCX_MISC1_DEFAULT_VALUE & (~PLLCX_MISC1_IDDQ);
697 _pll_misc_chk_default(clk_base, params, 1, default_val,
698 PLLCX_MISC1_WRITE_MASK);
700 default_val = PLLCX_MISC2_DEFAULT_VALUE;
701 _pll_misc_chk_default(clk_base, params, 2, default_val,
702 PLLCX_MISC2_WRITE_MASK);
704 default_val = PLLCX_MISC3_DEFAULT_VALUE;
705 _pll_misc_chk_default(clk_base, params, 3, default_val,
706 PLLCX_MISC3_WRITE_MASK);
709 static void tegra210_pllcx_set_defaults(const char *name,
710 struct tegra_clk_pll *pllcx)
712 pllcx->params->defaults_set = true;
714 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {
715 /* PLL is ON: only check if defaults already set */
716 pllcx_check_defaults(pllcx->params);
717 if (!pllcx->params->defaults_set)
718 pr_warn("%s already enabled. Postponing set full defaults\n",
723 /* Defaults assert PLL reset, and set IDDQ */
724 writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE,
725 clk_base + pllcx->params->ext_misc_reg[0]);
726 writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE,
727 clk_base + pllcx->params->ext_misc_reg[1]);
728 writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE,
729 clk_base + pllcx->params->ext_misc_reg[2]);
730 writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE,
731 clk_base + pllcx->params->ext_misc_reg[3]);
735 static void _pllc_set_defaults(struct tegra_clk_pll *pllcx)
737 tegra210_pllcx_set_defaults("PLL_C", pllcx);
740 static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx)
742 tegra210_pllcx_set_defaults("PLL_C2", pllcx);
745 static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx)
747 tegra210_pllcx_set_defaults("PLL_C3", pllcx);
750 static void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
752 tegra210_pllcx_set_defaults("PLL_A1", pllcx);
757 * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used.
758 * Fractional SDM is allowed to provide exact audio rates.
760 static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
763 u32 val = readl_relaxed(clk_base + plla->params->base_reg);
765 plla->params->defaults_set = true;
767 if (val & PLL_ENABLE) {
769 * PLL is ON: check if defaults already set, then set those
770 * that can be updated in flight.
772 if (val & PLLA_BASE_IDDQ) {
773 pr_warn("PLL_A boot enabled with IDDQ set\n");
774 plla->params->defaults_set = false;
777 pr_warn("PLL_A already enabled. Postponing set full defaults\n");
779 val = PLLA_MISC0_DEFAULT_VALUE; /* ignore lock enable */
780 mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE;
781 _pll_misc_chk_default(clk_base, plla->params, 0, val,
782 ~mask & PLLA_MISC0_WRITE_MASK);
784 val = PLLA_MISC2_DEFAULT_VALUE; /* ignore all but control bit */
785 _pll_misc_chk_default(clk_base, plla->params, 2, val,
786 PLLA_MISC2_EN_DYNRAMP);
788 /* Enable lock detect */
789 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);
791 val |= PLLA_MISC0_DEFAULT_VALUE & mask;
792 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);
798 /* set IDDQ, enable lock detect, disable dynamic ramp and SDM */
799 val |= PLLA_BASE_IDDQ;
800 writel_relaxed(val, clk_base + plla->params->base_reg);
801 writel_relaxed(PLLA_MISC0_DEFAULT_VALUE,
802 clk_base + plla->params->ext_misc_reg[0]);
803 writel_relaxed(PLLA_MISC2_DEFAULT_VALUE,
804 clk_base + plla->params->ext_misc_reg[2]);
810 * PLL with fractional SDM.
812 static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
817 plld->params->defaults_set = true;
819 if (readl_relaxed(clk_base + plld->params->base_reg) &
823 * PLL is ON: check if defaults already set, then set those
824 * that can be updated in flight.
826 val = PLLD_MISC1_DEFAULT_VALUE;
827 _pll_misc_chk_default(clk_base, plld->params, 1,
828 val, PLLD_MISC1_WRITE_MASK);
830 /* ignore lock, DSI and SDM controls, make sure IDDQ not set */
831 val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ);
832 mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE |
833 PLLD_MISC0_LOCK_OVERRIDE | PLLD_MISC0_EN_SDM;
834 _pll_misc_chk_default(clk_base, plld->params, 0, val,
835 ~mask & PLLD_MISC0_WRITE_MASK);
837 if (!plld->params->defaults_set)
838 pr_warn("PLL_D already enabled. Postponing set full defaults\n");
840 /* Enable lock detect */
841 mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE;
842 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
844 val |= PLLD_MISC0_DEFAULT_VALUE & mask;
845 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
851 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
852 val &= PLLD_MISC0_DSI_CLKENABLE;
853 val |= PLLD_MISC0_DEFAULT_VALUE;
854 /* set IDDQ, enable lock detect, disable SDM */
855 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
856 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base +
857 plld->params->ext_misc_reg[1]);
863 * PLL with fractional SDM and Spread Spectrum (SDM is a must if SSC is used).
865 static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss,
866 u32 misc0_val, u32 misc1_val, u32 misc2_val, u32 misc3_val)
869 u32 val = readl_relaxed(clk_base + plldss->params->base_reg);
871 plldss->params->defaults_set = true;
873 if (val & PLL_ENABLE) {
876 * PLL is ON: check if defaults already set, then set those
877 * that can be updated in flight.
879 if (val & PLLDSS_BASE_IDDQ) {
880 pr_warn("plldss boot enabled with IDDQ set\n");
881 plldss->params->defaults_set = false;
884 /* ignore lock enable */
885 default_val = misc0_val;
886 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val,
887 PLLDSS_MISC0_WRITE_MASK &
888 (~PLLDSS_MISC0_LOCK_ENABLE));
891 * If SSC is used, check all settings, otherwise just confirm
892 * that SSC is not used on boot as well. Do nothing when using
893 * this function for PLLC4 that has only MISC0.
895 if (plldss->params->ssc_ctrl_en_mask) {
896 default_val = misc1_val;
897 _pll_misc_chk_default(clk_base, plldss->params, 1,
898 default_val, PLLDSS_MISC1_CFG_WRITE_MASK);
899 default_val = misc2_val;
900 _pll_misc_chk_default(clk_base, plldss->params, 2,
901 default_val, PLLDSS_MISC2_CTRL1_WRITE_MASK);
902 default_val = misc3_val;
903 _pll_misc_chk_default(clk_base, plldss->params, 3,
904 default_val, PLLDSS_MISC3_CTRL2_WRITE_MASK);
905 } else if (plldss->params->ext_misc_reg[1]) {
906 default_val = misc1_val;
907 _pll_misc_chk_default(clk_base, plldss->params, 1,
908 default_val, PLLDSS_MISC1_CFG_WRITE_MASK &
909 (~PLLDSS_MISC1_CFG_EN_SDM));
912 if (!plldss->params->defaults_set)
913 pr_warn("%s already enabled. Postponing set full defaults\n",
916 /* Enable lock detect */
917 if (val & PLLDSS_BASE_LOCK_OVERRIDE) {
918 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
919 writel_relaxed(val, clk_base +
920 plldss->params->base_reg);
923 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);
924 val &= ~PLLDSS_MISC0_LOCK_ENABLE;
925 val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE;
926 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);
932 /* set IDDQ, enable lock detect, configure SDM/SSC */
933 val |= PLLDSS_BASE_IDDQ;
934 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
935 writel_relaxed(val, clk_base + plldss->params->base_reg);
937 /* When using this function for PLLC4 exit here */
938 if (!plldss->params->ext_misc_reg[1]) {
939 writel_relaxed(misc0_val, clk_base +
940 plldss->params->ext_misc_reg[0]);
945 writel_relaxed(misc0_val, clk_base +
946 plldss->params->ext_misc_reg[0]);
947 /* if SSC used set by 1st enable */
948 writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC),
949 clk_base + plldss->params->ext_misc_reg[1]);
950 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);
951 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);
955 static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
957 plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE,
958 PLLD2_MISC1_CFG_DEFAULT_VALUE,
959 PLLD2_MISC2_CTRL1_DEFAULT_VALUE,
960 PLLD2_MISC3_CTRL2_DEFAULT_VALUE);
963 static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
965 plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE,
966 PLLDP_MISC1_CFG_DEFAULT_VALUE,
967 PLLDP_MISC2_CTRL1_DEFAULT_VALUE,
968 PLLDP_MISC3_CTRL2_DEFAULT_VALUE);
973 * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support.
974 * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers.
976 static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
978 plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0);
983 * VCO is exposed to the clock tree directly along with post-divider output
985 static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
988 u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
990 pllre->params->defaults_set = true;
992 if (val & PLL_ENABLE) {
994 * PLL is ON: check if defaults already set, then set those
995 * that can be updated in flight.
997 val &= PLLRE_BASE_DEFAULT_MASK;
998 if (val != PLLRE_BASE_DEFAULT_VALUE) {
999 pr_warn("pllre boot base 0x%x : expected 0x%x\n",
1000 val, PLLRE_BASE_DEFAULT_VALUE);
1001 pr_warn("(comparison mask = 0x%x)\n",
1002 PLLRE_BASE_DEFAULT_MASK);
1003 pllre->params->defaults_set = false;
1006 /* Ignore lock enable */
1007 val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ);
1008 mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE;
1009 _pll_misc_chk_default(clk_base, pllre->params, 0, val,
1010 ~mask & PLLRE_MISC0_WRITE_MASK);
1012 /* The PLL doesn't work if it's in IDDQ. */
1013 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
1014 if (val & PLLRE_MISC0_IDDQ)
1015 pr_warn("unexpected IDDQ bit set for enabled clock\n");
1017 /* Enable lock detect */
1019 val |= PLLRE_MISC0_DEFAULT_VALUE & mask;
1020 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);
1023 if (!pllre->params->defaults_set)
1024 pr_warn("PLL_RE already enabled. Postponing set full defaults\n");
1029 /* set IDDQ, enable lock detect */
1030 val &= ~PLLRE_BASE_DEFAULT_MASK;
1031 val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK;
1032 writel_relaxed(val, clk_base + pllre->params->base_reg);
1033 writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE,
1034 clk_base + pllre->params->ext_misc_reg[0]);
1038 static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b)
1040 unsigned long input_rate;
1043 if (!IS_ERR_OR_NULL(hw->clk))
1044 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1046 input_rate = 38400000;
1048 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
1050 switch (input_rate) {
1066 pr_err("%s: Unexpected reference rate %lu\n",
1067 __func__, input_rate);
1072 static void pllx_check_defaults(struct tegra_clk_pll *pll)
1076 default_val = PLLX_MISC0_DEFAULT_VALUE;
1077 /* ignore lock enable */
1078 _pll_misc_chk_default(clk_base, pll->params, 0, default_val,
1079 PLLX_MISC0_WRITE_MASK & (~PLLX_MISC0_LOCK_ENABLE));
1081 default_val = PLLX_MISC1_DEFAULT_VALUE;
1082 _pll_misc_chk_default(clk_base, pll->params, 1, default_val,
1083 PLLX_MISC1_WRITE_MASK);
1085 /* ignore all but control bit */
1086 default_val = PLLX_MISC2_DEFAULT_VALUE;
1087 _pll_misc_chk_default(clk_base, pll->params, 2,
1088 default_val, PLLX_MISC2_EN_DYNRAMP);
1090 default_val = PLLX_MISC3_DEFAULT_VALUE & (~PLLX_MISC3_IDDQ);
1091 _pll_misc_chk_default(clk_base, pll->params, 3, default_val,
1092 PLLX_MISC3_WRITE_MASK);
1094 default_val = PLLX_MISC4_DEFAULT_VALUE;
1095 _pll_misc_chk_default(clk_base, pll->params, 4, default_val,
1096 PLLX_MISC4_WRITE_MASK);
1098 default_val = PLLX_MISC5_DEFAULT_VALUE;
1099 _pll_misc_chk_default(clk_base, pll->params, 5, default_val,
1100 PLLX_MISC5_WRITE_MASK);
1103 static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
1108 pllx->params->defaults_set = true;
1110 /* Get ready dyn ramp state machine settings */
1111 pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b);
1112 val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) &
1113 (~PLLX_MISC2_DYNRAMP_STEPB_MASK);
1114 val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
1115 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
1117 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
1120 * PLL is ON: check if defaults already set, then set those
1121 * that can be updated in flight.
1123 pllx_check_defaults(pllx);
1125 if (!pllx->params->defaults_set)
1126 pr_warn("PLL_X already enabled. Postponing set full defaults\n");
1127 /* Configure dyn ramp, disable lock override */
1128 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1130 /* Enable lock detect */
1131 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);
1132 val &= ~PLLX_MISC0_LOCK_ENABLE;
1133 val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE;
1134 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);
1140 /* Enable lock detect and CPU output */
1141 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base +
1142 pllx->params->ext_misc_reg[0]);
1145 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base +
1146 pllx->params->ext_misc_reg[1]);
1148 /* Configure dyn ramp state machine, disable lock override */
1149 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1152 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base +
1153 pllx->params->ext_misc_reg[3]);
1156 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base +
1157 pllx->params->ext_misc_reg[4]);
1158 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base +
1159 pllx->params->ext_misc_reg[5]);
1164 static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
1166 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
1168 pllmb->params->defaults_set = true;
1170 if (val & PLL_ENABLE) {
1173 * PLL is ON: check if defaults already set, then set those
1174 * that can be updated in flight.
1176 val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ);
1177 mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE;
1178 _pll_misc_chk_default(clk_base, pllmb->params, 0, val,
1179 ~mask & PLLMB_MISC1_WRITE_MASK);
1181 if (!pllmb->params->defaults_set)
1182 pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
1183 /* Enable lock detect */
1184 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
1186 val |= PLLMB_MISC1_DEFAULT_VALUE & mask;
1187 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
1193 /* set IDDQ, enable lock detect */
1194 writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE,
1195 clk_base + pllmb->params->ext_misc_reg[0]);
1201 * VCO is exposed to the clock tree directly along with post-divider output.
1202 * Both VCO and post-divider output rates are fixed at 408MHz and 204MHz,
1205 static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled)
1209 /* Ignore lock enable (will be set), make sure not in IDDQ if enabled */
1210 val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ);
1211 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
1213 mask |= PLLP_MISC0_IDDQ;
1214 _pll_misc_chk_default(clk_base, pll->params, 0, val,
1215 ~mask & PLLP_MISC0_WRITE_MASK);
1217 /* Ignore branch controls */
1218 val = PLLP_MISC1_DEFAULT_VALUE;
1219 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
1220 _pll_misc_chk_default(clk_base, pll->params, 1, val,
1221 ~mask & PLLP_MISC1_WRITE_MASK);
1224 static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
1227 u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
1229 pllp->params->defaults_set = true;
1231 if (val & PLL_ENABLE) {
1234 * PLL is ON: check if defaults already set, then set those
1235 * that can be updated in flight.
1237 pllp_check_defaults(pllp, true);
1238 if (!pllp->params->defaults_set)
1239 pr_warn("PLL_P already enabled. Postponing set full defaults\n");
1241 /* Enable lock detect */
1242 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
1243 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
1245 val |= PLLP_MISC0_DEFAULT_VALUE & mask;
1246 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);
1252 /* set IDDQ, enable lock detect */
1253 writel_relaxed(PLLP_MISC0_DEFAULT_VALUE,
1254 clk_base + pllp->params->ext_misc_reg[0]);
1256 /* Preserve branch control */
1257 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);
1258 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
1260 val |= ~mask & PLLP_MISC1_DEFAULT_VALUE;
1261 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);
1267 * VCO is exposed to the clock tree directly along with post-divider output.
1268 * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz,
1271 static void pllu_check_defaults(struct tegra_clk_pll_params *params,
1276 /* Ignore lock enable (will be set) and IDDQ if under h/w control */
1277 val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ);
1278 mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0);
1279 _pll_misc_chk_default(clk_base, params, 0, val,
1280 ~mask & PLLU_MISC0_WRITE_MASK);
1282 val = PLLU_MISC1_DEFAULT_VALUE;
1283 mask = PLLU_MISC1_LOCK_OVERRIDE;
1284 _pll_misc_chk_default(clk_base, params, 1, val,
1285 ~mask & PLLU_MISC1_WRITE_MASK);
1288 static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu)
1290 u32 val = readl_relaxed(clk_base + pllu->base_reg);
1292 pllu->defaults_set = true;
1294 if (val & PLL_ENABLE) {
1297 * PLL is ON: check if defaults already set, then set those
1298 * that can be updated in flight.
1300 pllu_check_defaults(pllu, false);
1301 if (!pllu->defaults_set)
1302 pr_warn("PLL_U already enabled. Postponing set full defaults\n");
1304 /* Enable lock detect */
1305 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]);
1306 val &= ~PLLU_MISC0_LOCK_ENABLE;
1307 val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE;
1308 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]);
1310 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]);
1311 val &= ~PLLU_MISC1_LOCK_OVERRIDE;
1312 val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE;
1313 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]);
1319 /* set IDDQ, enable lock detect */
1320 writel_relaxed(PLLU_MISC0_DEFAULT_VALUE,
1321 clk_base + pllu->ext_misc_reg[0]);
1322 writel_relaxed(PLLU_MISC1_DEFAULT_VALUE,
1323 clk_base + pllu->ext_misc_reg[1]);
1327 #define mask(w) ((1 << (w)) - 1)
1328 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
1329 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
1330 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
1331 mask(p->params->div_nmp->divp_width))
1333 #define divm_shift(p) ((p)->params->div_nmp->divm_shift)
1334 #define divn_shift(p) ((p)->params->div_nmp->divn_shift)
1335 #define divp_shift(p) ((p)->params->div_nmp->divp_shift)
1337 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
1338 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
1339 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
1341 #define PLL_LOCKDET_DELAY 2 /* Lock detection safety delays */
1342 static int tegra210_wait_for_mask(struct tegra_clk_pll *pll,
1348 for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) {
1349 udelay(PLL_LOCKDET_DELAY);
1350 val = readl_relaxed(clk_base + reg);
1351 if ((val & mask) == mask) {
1352 udelay(PLL_LOCKDET_DELAY);
1359 static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx,
1360 struct tegra_clk_pll_freq_table *cfg)
1362 u32 val, base, ndiv_new_mask;
1364 ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift)
1365 << PLLX_MISC2_NDIV_NEW_SHIFT;
1367 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1368 val &= (~ndiv_new_mask);
1369 val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT;
1370 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1373 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1374 val |= PLLX_MISC2_EN_DYNRAMP;
1375 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1378 tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2],
1379 PLLX_MISC2_DYNRAMP_DONE);
1381 base = readl_relaxed(clk_base + pllx->params->base_reg) &
1382 (~divn_mask_shifted(pllx));
1383 base |= cfg->n << pllx->params->div_nmp->divn_shift;
1384 writel_relaxed(base, clk_base + pllx->params->base_reg);
1387 val &= ~PLLX_MISC2_EN_DYNRAMP;
1388 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1391 pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n",
1392 __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p,
1393 cfg->input_rate / cfg->m * cfg->n /
1394 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000);
1400 * Common configuration for PLLs with fixed input divider policy:
1401 * - always set fixed M-value based on the reference rate
1402 * - always set P-value value 1:1 for output rates above VCO minimum, and
1403 * choose minimum necessary P-value for output rates below VCO maximum
1404 * - calculate N-value based on selected M and P
1405 * - calculate SDM_DIN fractional part
1407 static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,
1408 struct tegra_clk_pll_freq_table *cfg,
1409 unsigned long rate, unsigned long input_rate)
1411 struct tegra_clk_pll *pll = to_clk_pll(hw);
1412 struct tegra_clk_pll_params *params = pll->params;
1414 unsigned long cf, p_rate;
1420 if (!(params->flags & TEGRA_PLL_VCO_OUT)) {
1421 p = DIV_ROUND_UP(params->vco_min, rate);
1422 p = params->round_p_to_pdiv(p, &pdiv);
1424 p = rate >= params->vco_min ? 1 : -EINVAL;
1430 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate);
1433 /* Store P as HW value, as that is what is expected */
1434 cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p);
1437 if (p_rate > params->vco_max)
1438 p_rate = params->vco_max;
1439 cf = input_rate / cfg->m;
1440 cfg->n = p_rate / cf;
1443 cfg->output_rate = input_rate;
1444 if (params->sdm_ctrl_reg) {
1445 unsigned long rem = p_rate - cf * cfg->n;
1446 /* If ssc is enabled SDM enabled as well, even for integer n */
1447 if (rem || params->ssc_ctrl_reg) {
1448 u64 s = rem * PLL_SDM_COEFF;
1451 s -= PLL_SDM_COEFF / 2;
1452 cfg->sdm_data = sdin_din_to_data(s);
1454 cfg->output_rate *= sdin_get_n_eff(cfg);
1455 cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF;
1457 cfg->output_rate *= cfg->n;
1458 cfg->output_rate /= p * cfg->m;
1461 cfg->input_rate = input_rate;
1467 * clk_pll_set_gain - set gain to m, n to calculate correct VCO rate
1469 * @cfg: struct tegra_clk_pll_freq_table * cfg
1472 * Fvco = Fref * NDIV / MDIV
1474 * For fractional mode:
1475 * Fvco = Fref * (NDIV + 0.5 + SDM_DIN / PLL_SDM_COEFF) / MDIV
1477 static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)
1479 cfg->n = sdin_get_n_eff(cfg);
1480 cfg->m *= PLL_SDM_COEFF;
1483 static unsigned long
1484 tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
1485 unsigned long parent_rate)
1487 unsigned long vco_min = params->vco_min;
1489 params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF);
1490 vco_min = min(vco_min, params->vco_min);
1495 static struct div_nmp pllx_nmp = {
1504 * PLL post divider maps - two types: quasi-linear and exponential
1507 #define PLL_QLIN_PDIV_MAX 16
1508 static const struct pdiv_map pll_qlin_pdiv_to_hw[] = {
1509 { .pdiv = 1, .hw_val = 0 },
1510 { .pdiv = 2, .hw_val = 1 },
1511 { .pdiv = 3, .hw_val = 2 },
1512 { .pdiv = 4, .hw_val = 3 },
1513 { .pdiv = 5, .hw_val = 4 },
1514 { .pdiv = 6, .hw_val = 5 },
1515 { .pdiv = 8, .hw_val = 6 },
1516 { .pdiv = 9, .hw_val = 7 },
1517 { .pdiv = 10, .hw_val = 8 },
1518 { .pdiv = 12, .hw_val = 9 },
1519 { .pdiv = 15, .hw_val = 10 },
1520 { .pdiv = 16, .hw_val = 11 },
1521 { .pdiv = 18, .hw_val = 12 },
1522 { .pdiv = 20, .hw_val = 13 },
1523 { .pdiv = 24, .hw_val = 14 },
1524 { .pdiv = 30, .hw_val = 15 },
1525 { .pdiv = 32, .hw_val = 16 },
1528 static u32 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv)
1533 for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) {
1534 if (p <= pll_qlin_pdiv_to_hw[i].pdiv) {
1537 return pll_qlin_pdiv_to_hw[i].pdiv;
1545 #define PLL_EXPO_PDIV_MAX 7
1546 static const struct pdiv_map pll_expo_pdiv_to_hw[] = {
1547 { .pdiv = 1, .hw_val = 0 },
1548 { .pdiv = 2, .hw_val = 1 },
1549 { .pdiv = 4, .hw_val = 2 },
1550 { .pdiv = 8, .hw_val = 3 },
1551 { .pdiv = 16, .hw_val = 4 },
1552 { .pdiv = 32, .hw_val = 5 },
1553 { .pdiv = 64, .hw_val = 6 },
1554 { .pdiv = 128, .hw_val = 7 },
1557 static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
1565 if (i <= PLL_EXPO_PDIV_MAX) {
1574 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
1576 { 12000000, 1000000000, 166, 1, 2, 0 }, /* actual: 996.0 MHz */
1577 { 13000000, 1000000000, 153, 1, 2, 0 }, /* actual: 994.0 MHz */
1578 { 38400000, 1000000000, 156, 3, 2, 0 }, /* actual: 998.4 MHz */
1579 { 0, 0, 0, 0, 0, 0 },
1582 static struct tegra_clk_pll_params pll_x_params = {
1583 .input_min = 12000000,
1584 .input_max = 800000000,
1587 .vco_min = 1350000000,
1588 .vco_max = 3000000000UL,
1589 .base_reg = PLLX_BASE,
1590 .misc_reg = PLLX_MISC0,
1591 .lock_mask = PLL_BASE_LOCK,
1592 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
1594 .ext_misc_reg[0] = PLLX_MISC0,
1595 .ext_misc_reg[1] = PLLX_MISC1,
1596 .ext_misc_reg[2] = PLLX_MISC2,
1597 .ext_misc_reg[3] = PLLX_MISC3,
1598 .ext_misc_reg[4] = PLLX_MISC4,
1599 .ext_misc_reg[5] = PLLX_MISC5,
1600 .iddq_reg = PLLX_MISC3,
1601 .iddq_bit_idx = PLLXP_IDDQ_BIT,
1602 .max_p = PLL_QLIN_PDIV_MAX,
1604 .dyn_ramp_reg = PLLX_MISC2,
1607 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1608 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1609 .div_nmp = &pllx_nmp,
1610 .freq_table = pll_x_freq_table,
1611 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1612 .dyn_ramp = tegra210_pllx_dyn_ramp,
1613 .set_defaults = tegra210_pllx_set_defaults,
1614 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1617 static struct div_nmp pllc_nmp = {
1626 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
1627 { 12000000, 510000000, 85, 1, 2, 0 },
1628 { 13000000, 510000000, 78, 1, 2, 0 }, /* actual: 507.0 MHz */
1629 { 38400000, 510000000, 79, 3, 2, 0 }, /* actual: 505.6 MHz */
1630 { 0, 0, 0, 0, 0, 0 },
1633 static struct tegra_clk_pll_params pll_c_params = {
1634 .input_min = 12000000,
1635 .input_max = 700000000,
1638 .vco_min = 600000000,
1639 .vco_max = 1200000000,
1640 .base_reg = PLLC_BASE,
1641 .misc_reg = PLLC_MISC0,
1642 .lock_mask = PLL_BASE_LOCK,
1644 .iddq_reg = PLLC_MISC1,
1645 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1646 .reset_reg = PLLC_MISC0,
1647 .reset_bit_idx = PLLCX_RESET_BIT,
1648 .max_p = PLL_QLIN_PDIV_MAX,
1649 .ext_misc_reg[0] = PLLC_MISC0,
1650 .ext_misc_reg[1] = PLLC_MISC1,
1651 .ext_misc_reg[2] = PLLC_MISC2,
1652 .ext_misc_reg[3] = PLLC_MISC3,
1653 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1654 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1656 .div_nmp = &pllc_nmp,
1657 .freq_table = pll_cx_freq_table,
1658 .flags = TEGRA_PLL_USE_LOCK,
1659 .set_defaults = _pllc_set_defaults,
1660 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1663 static struct div_nmp pllcx_nmp = {
1672 static struct tegra_clk_pll_params pll_c2_params = {
1673 .input_min = 12000000,
1674 .input_max = 700000000,
1677 .vco_min = 600000000,
1678 .vco_max = 1200000000,
1679 .base_reg = PLLC2_BASE,
1680 .misc_reg = PLLC2_MISC0,
1681 .iddq_reg = PLLC2_MISC1,
1682 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1683 .reset_reg = PLLC2_MISC0,
1684 .reset_bit_idx = PLLCX_RESET_BIT,
1685 .lock_mask = PLLCX_BASE_LOCK,
1687 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1688 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1690 .div_nmp = &pllcx_nmp,
1691 .max_p = PLL_QLIN_PDIV_MAX,
1692 .ext_misc_reg[0] = PLLC2_MISC0,
1693 .ext_misc_reg[1] = PLLC2_MISC1,
1694 .ext_misc_reg[2] = PLLC2_MISC2,
1695 .ext_misc_reg[3] = PLLC2_MISC3,
1696 .freq_table = pll_cx_freq_table,
1697 .flags = TEGRA_PLL_USE_LOCK,
1698 .set_defaults = _pllc2_set_defaults,
1699 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1702 static struct tegra_clk_pll_params pll_c3_params = {
1703 .input_min = 12000000,
1704 .input_max = 700000000,
1707 .vco_min = 600000000,
1708 .vco_max = 1200000000,
1709 .base_reg = PLLC3_BASE,
1710 .misc_reg = PLLC3_MISC0,
1711 .lock_mask = PLLCX_BASE_LOCK,
1713 .iddq_reg = PLLC3_MISC1,
1714 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1715 .reset_reg = PLLC3_MISC0,
1716 .reset_bit_idx = PLLCX_RESET_BIT,
1717 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1718 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1720 .div_nmp = &pllcx_nmp,
1721 .max_p = PLL_QLIN_PDIV_MAX,
1722 .ext_misc_reg[0] = PLLC3_MISC0,
1723 .ext_misc_reg[1] = PLLC3_MISC1,
1724 .ext_misc_reg[2] = PLLC3_MISC2,
1725 .ext_misc_reg[3] = PLLC3_MISC3,
1726 .freq_table = pll_cx_freq_table,
1727 .flags = TEGRA_PLL_USE_LOCK,
1728 .set_defaults = _pllc3_set_defaults,
1729 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1732 static struct div_nmp pllss_nmp = {
1741 static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = {
1742 { 12000000, 600000000, 50, 1, 1, 0 },
1743 { 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */
1744 { 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */
1745 { 0, 0, 0, 0, 0, 0 },
1748 static const struct clk_div_table pll_vco_post_div_table[] = {
1749 { .val = 0, .div = 1 },
1750 { .val = 1, .div = 2 },
1751 { .val = 2, .div = 3 },
1752 { .val = 3, .div = 4 },
1753 { .val = 4, .div = 5 },
1754 { .val = 5, .div = 6 },
1755 { .val = 6, .div = 8 },
1756 { .val = 7, .div = 10 },
1757 { .val = 8, .div = 12 },
1758 { .val = 9, .div = 16 },
1759 { .val = 10, .div = 12 },
1760 { .val = 11, .div = 16 },
1761 { .val = 12, .div = 20 },
1762 { .val = 13, .div = 24 },
1763 { .val = 14, .div = 32 },
1764 { .val = 0, .div = 0 },
1767 static struct tegra_clk_pll_params pll_c4_vco_params = {
1768 .input_min = 9600000,
1769 .input_max = 800000000,
1772 .vco_min = 500000000,
1773 .vco_max = 1080000000,
1774 .base_reg = PLLC4_BASE,
1775 .misc_reg = PLLC4_MISC0,
1776 .lock_mask = PLL_BASE_LOCK,
1778 .max_p = PLL_QLIN_PDIV_MAX,
1779 .ext_misc_reg[0] = PLLC4_MISC0,
1780 .iddq_reg = PLLC4_BASE,
1781 .iddq_bit_idx = PLLSS_IDDQ_BIT,
1782 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1783 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1785 .div_nmp = &pllss_nmp,
1786 .freq_table = pll_c4_vco_freq_table,
1787 .set_defaults = tegra210_pllc4_set_defaults,
1788 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1789 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1792 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
1793 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
1794 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
1795 { 38400000, 297600000, 93, 4, 3, 0 },
1796 { 38400000, 400000000, 125, 4, 3, 0 },
1797 { 38400000, 532800000, 111, 4, 2, 0 },
1798 { 38400000, 665600000, 104, 3, 2, 0 },
1799 { 38400000, 800000000, 125, 3, 2, 0 },
1800 { 38400000, 931200000, 97, 4, 1, 0 },
1801 { 38400000, 1065600000, 111, 4, 1, 0 },
1802 { 38400000, 1200000000, 125, 4, 1, 0 },
1803 { 38400000, 1331200000, 104, 3, 1, 0 },
1804 { 38400000, 1459200000, 76, 2, 1, 0 },
1805 { 38400000, 1600000000, 125, 3, 1, 0 },
1806 { 0, 0, 0, 0, 0, 0 },
1809 static struct div_nmp pllm_nmp = {
1812 .override_divm_shift = 0,
1815 .override_divn_shift = 8,
1818 .override_divp_shift = 27,
1821 static struct tegra_clk_pll_params pll_m_params = {
1822 .input_min = 9600000,
1823 .input_max = 500000000,
1826 .vco_min = 800000000,
1827 .vco_max = 1866000000,
1828 .base_reg = PLLM_BASE,
1829 .misc_reg = PLLM_MISC2,
1830 .lock_mask = PLL_BASE_LOCK,
1831 .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE,
1833 .iddq_reg = PLLM_MISC2,
1834 .iddq_bit_idx = PLLM_IDDQ_BIT,
1835 .max_p = PLL_QLIN_PDIV_MAX,
1836 .ext_misc_reg[0] = PLLM_MISC2,
1837 .ext_misc_reg[1] = PLLM_MISC1,
1838 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1839 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1840 .div_nmp = &pllm_nmp,
1841 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
1842 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
1843 .freq_table = pll_m_freq_table,
1844 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1845 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1848 static struct tegra_clk_pll_params pll_mb_params = {
1849 .input_min = 9600000,
1850 .input_max = 500000000,
1853 .vco_min = 800000000,
1854 .vco_max = 1866000000,
1855 .base_reg = PLLMB_BASE,
1856 .misc_reg = PLLMB_MISC1,
1857 .lock_mask = PLL_BASE_LOCK,
1859 .iddq_reg = PLLMB_MISC1,
1860 .iddq_bit_idx = PLLMB_IDDQ_BIT,
1861 .max_p = PLL_QLIN_PDIV_MAX,
1862 .ext_misc_reg[0] = PLLMB_MISC1,
1863 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1864 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1865 .div_nmp = &pllm_nmp,
1866 .freq_table = pll_m_freq_table,
1867 .flags = TEGRA_PLL_USE_LOCK,
1868 .set_defaults = tegra210_pllmb_set_defaults,
1869 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1873 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
1874 /* PLLE special case: use cpcon field to store cml divider value */
1875 { 672000000, 100000000, 125, 42, 0, 13 },
1876 { 624000000, 100000000, 125, 39, 0, 13 },
1877 { 336000000, 100000000, 125, 21, 0, 13 },
1878 { 312000000, 100000000, 200, 26, 0, 14 },
1879 { 38400000, 100000000, 125, 2, 0, 14 },
1880 { 12000000, 100000000, 200, 1, 0, 14 },
1881 { 0, 0, 0, 0, 0, 0 },
1884 static struct div_nmp plle_nmp = {
1893 static struct tegra_clk_pll_params pll_e_params = {
1894 .input_min = 12000000,
1895 .input_max = 800000000,
1898 .vco_min = 1600000000,
1899 .vco_max = 2500000000U,
1900 .base_reg = PLLE_BASE,
1901 .misc_reg = PLLE_MISC0,
1902 .aux_reg = PLLE_AUX,
1903 .lock_mask = PLLE_MISC_LOCK,
1904 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
1906 .div_nmp = &plle_nmp,
1907 .freq_table = pll_e_freq_table,
1908 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK |
1909 TEGRA_PLL_HAS_LOCK_ENABLE,
1910 .fixed_rate = 100000000,
1911 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1914 static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = {
1915 { 12000000, 672000000, 56, 1, 1, 0 },
1916 { 13000000, 672000000, 51, 1, 1, 0 }, /* actual: 663.0 MHz */
1917 { 38400000, 672000000, 70, 4, 1, 0 },
1918 { 0, 0, 0, 0, 0, 0 },
1921 static struct div_nmp pllre_nmp = {
1930 static struct tegra_clk_pll_params pll_re_vco_params = {
1931 .input_min = 9600000,
1932 .input_max = 800000000,
1935 .vco_min = 350000000,
1936 .vco_max = 700000000,
1937 .base_reg = PLLRE_BASE,
1938 .misc_reg = PLLRE_MISC0,
1939 .lock_mask = PLLRE_MISC_LOCK,
1941 .max_p = PLL_QLIN_PDIV_MAX,
1942 .ext_misc_reg[0] = PLLRE_MISC0,
1943 .iddq_reg = PLLRE_MISC0,
1944 .iddq_bit_idx = PLLRE_IDDQ_BIT,
1945 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1946 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1947 .div_nmp = &pllre_nmp,
1948 .freq_table = pll_re_vco_freq_table,
1949 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT,
1950 .set_defaults = tegra210_pllre_set_defaults,
1951 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1954 static struct div_nmp pllp_nmp = {
1963 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
1964 { 12000000, 408000000, 34, 1, 1, 0 },
1965 { 38400000, 408000000, 85, 8, 1, 0 }, /* cf = 4.8MHz, allowed exception */
1966 { 0, 0, 0, 0, 0, 0 },
1969 static struct tegra_clk_pll_params pll_p_params = {
1970 .input_min = 9600000,
1971 .input_max = 800000000,
1974 .vco_min = 350000000,
1975 .vco_max = 700000000,
1976 .base_reg = PLLP_BASE,
1977 .misc_reg = PLLP_MISC0,
1978 .lock_mask = PLL_BASE_LOCK,
1980 .iddq_reg = PLLP_MISC0,
1981 .iddq_bit_idx = PLLXP_IDDQ_BIT,
1982 .ext_misc_reg[0] = PLLP_MISC0,
1983 .ext_misc_reg[1] = PLLP_MISC1,
1984 .div_nmp = &pllp_nmp,
1985 .freq_table = pll_p_freq_table,
1986 .fixed_rate = 408000000,
1987 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1988 .set_defaults = tegra210_pllp_set_defaults,
1989 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1992 static struct tegra_clk_pll_params pll_a1_params = {
1993 .input_min = 12000000,
1994 .input_max = 700000000,
1997 .vco_min = 600000000,
1998 .vco_max = 1200000000,
1999 .base_reg = PLLA1_BASE,
2000 .misc_reg = PLLA1_MISC0,
2001 .lock_mask = PLLCX_BASE_LOCK,
2003 .iddq_reg = PLLA1_MISC1,
2004 .iddq_bit_idx = PLLCX_IDDQ_BIT,
2005 .reset_reg = PLLA1_MISC0,
2006 .reset_bit_idx = PLLCX_RESET_BIT,
2007 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2008 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2009 .div_nmp = &pllc_nmp,
2010 .ext_misc_reg[0] = PLLA1_MISC0,
2011 .ext_misc_reg[1] = PLLA1_MISC1,
2012 .ext_misc_reg[2] = PLLA1_MISC2,
2013 .ext_misc_reg[3] = PLLA1_MISC3,
2014 .freq_table = pll_cx_freq_table,
2015 .flags = TEGRA_PLL_USE_LOCK,
2016 .set_defaults = _plla1_set_defaults,
2017 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2020 static struct div_nmp plla_nmp = {
2029 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
2030 { 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */
2031 { 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */
2032 { 12000000, 240000000, 60, 1, 3, 1, 0 },
2033 { 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */
2034 { 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */
2035 { 13000000, 240000000, 55, 1, 3, 1, 0 }, /* actual: 238.3 MHz */
2036 { 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */
2037 { 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */
2038 { 38400000, 240000000, 75, 3, 3, 1, 0 },
2039 { 0, 0, 0, 0, 0, 0, 0 },
2042 static struct tegra_clk_pll_params pll_a_params = {
2043 .input_min = 12000000,
2044 .input_max = 800000000,
2047 .vco_min = 500000000,
2048 .vco_max = 1000000000,
2049 .base_reg = PLLA_BASE,
2050 .misc_reg = PLLA_MISC0,
2051 .lock_mask = PLL_BASE_LOCK,
2053 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2054 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2055 .iddq_reg = PLLA_BASE,
2056 .iddq_bit_idx = PLLA_IDDQ_BIT,
2057 .div_nmp = &plla_nmp,
2058 .sdm_din_reg = PLLA_MISC1,
2059 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2060 .sdm_ctrl_reg = PLLA_MISC2,
2061 .sdm_ctrl_en_mask = PLLA_SDM_EN_MASK,
2062 .ext_misc_reg[0] = PLLA_MISC0,
2063 .ext_misc_reg[1] = PLLA_MISC1,
2064 .ext_misc_reg[2] = PLLA_MISC2,
2065 .freq_table = pll_a_freq_table,
2066 .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW,
2067 .set_defaults = tegra210_plla_set_defaults,
2068 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2069 .set_gain = tegra210_clk_pll_set_gain,
2070 .adjust_vco = tegra210_clk_adjust_vco_min,
2073 static struct div_nmp plld_nmp = {
2082 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
2083 { 12000000, 594000000, 99, 1, 2, 0, 0 },
2084 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
2085 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
2086 { 0, 0, 0, 0, 0, 0, 0 },
2089 static struct tegra_clk_pll_params pll_d_params = {
2090 .input_min = 12000000,
2091 .input_max = 800000000,
2094 .vco_min = 750000000,
2095 .vco_max = 1500000000,
2096 .base_reg = PLLD_BASE,
2097 .misc_reg = PLLD_MISC0,
2098 .lock_mask = PLL_BASE_LOCK,
2100 .iddq_reg = PLLD_MISC0,
2101 .iddq_bit_idx = PLLD_IDDQ_BIT,
2102 .round_p_to_pdiv = pll_expo_p_to_pdiv,
2103 .pdiv_tohw = pll_expo_pdiv_to_hw,
2104 .div_nmp = &plld_nmp,
2105 .sdm_din_reg = PLLD_MISC0,
2106 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2107 .sdm_ctrl_reg = PLLD_MISC0,
2108 .sdm_ctrl_en_mask = PLLD_SDM_EN_MASK,
2109 .ext_misc_reg[0] = PLLD_MISC0,
2110 .ext_misc_reg[1] = PLLD_MISC1,
2111 .freq_table = pll_d_freq_table,
2112 .flags = TEGRA_PLL_USE_LOCK,
2114 .set_defaults = tegra210_plld_set_defaults,
2115 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2116 .set_gain = tegra210_clk_pll_set_gain,
2117 .adjust_vco = tegra210_clk_adjust_vco_min,
2120 static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = {
2121 { 12000000, 594000000, 99, 1, 2, 0, 0xf000 },
2122 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
2123 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
2124 { 0, 0, 0, 0, 0, 0, 0 },
2127 /* s/w policy, always tegra_pll_ref */
2128 static struct tegra_clk_pll_params pll_d2_params = {
2129 .input_min = 12000000,
2130 .input_max = 800000000,
2133 .vco_min = 750000000,
2134 .vco_max = 1500000000,
2135 .base_reg = PLLD2_BASE,
2136 .misc_reg = PLLD2_MISC0,
2137 .lock_mask = PLL_BASE_LOCK,
2139 .iddq_reg = PLLD2_BASE,
2140 .iddq_bit_idx = PLLSS_IDDQ_BIT,
2141 .sdm_din_reg = PLLD2_MISC3,
2142 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2143 .sdm_ctrl_reg = PLLD2_MISC1,
2144 .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK,
2145 /* disable spread-spectrum for pll_d2 */
2147 .ssc_ctrl_en_mask = 0,
2148 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2149 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2150 .div_nmp = &pllss_nmp,
2151 .ext_misc_reg[0] = PLLD2_MISC0,
2152 .ext_misc_reg[1] = PLLD2_MISC1,
2153 .ext_misc_reg[2] = PLLD2_MISC2,
2154 .ext_misc_reg[3] = PLLD2_MISC3,
2155 .max_p = PLL_QLIN_PDIV_MAX,
2157 .freq_table = tegra210_pll_d2_freq_table,
2158 .set_defaults = tegra210_plld2_set_defaults,
2159 .flags = TEGRA_PLL_USE_LOCK,
2160 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2161 .set_gain = tegra210_clk_pll_set_gain,
2162 .adjust_vco = tegra210_clk_adjust_vco_min,
2165 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
2166 { 12000000, 270000000, 90, 1, 4, 0, 0xf000 },
2167 { 13000000, 270000000, 83, 1, 4, 0, 0xf000 }, /* actual: 269.8 MHz */
2168 { 38400000, 270000000, 28, 1, 4, 0, 0xf400 },
2169 { 0, 0, 0, 0, 0, 0, 0 },
2172 static struct tegra_clk_pll_params pll_dp_params = {
2173 .input_min = 12000000,
2174 .input_max = 800000000,
2177 .vco_min = 750000000,
2178 .vco_max = 1500000000,
2179 .base_reg = PLLDP_BASE,
2180 .misc_reg = PLLDP_MISC,
2181 .lock_mask = PLL_BASE_LOCK,
2183 .iddq_reg = PLLDP_BASE,
2184 .iddq_bit_idx = PLLSS_IDDQ_BIT,
2185 .sdm_din_reg = PLLDP_SS_CTRL2,
2186 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2187 .sdm_ctrl_reg = PLLDP_SS_CFG,
2188 .sdm_ctrl_en_mask = PLLDP_SDM_EN_MASK,
2189 .ssc_ctrl_reg = PLLDP_SS_CFG,
2190 .ssc_ctrl_en_mask = PLLDP_SSC_EN_MASK,
2191 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2192 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2193 .div_nmp = &pllss_nmp,
2194 .ext_misc_reg[0] = PLLDP_MISC,
2195 .ext_misc_reg[1] = PLLDP_SS_CFG,
2196 .ext_misc_reg[2] = PLLDP_SS_CTRL1,
2197 .ext_misc_reg[3] = PLLDP_SS_CTRL2,
2198 .max_p = PLL_QLIN_PDIV_MAX,
2200 .freq_table = pll_dp_freq_table,
2201 .set_defaults = tegra210_plldp_set_defaults,
2202 .flags = TEGRA_PLL_USE_LOCK,
2203 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2204 .set_gain = tegra210_clk_pll_set_gain,
2205 .adjust_vco = tegra210_clk_adjust_vco_min,
2208 static struct div_nmp pllu_nmp = {
2217 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
2218 { 12000000, 480000000, 40, 1, 1, 0 },
2219 { 13000000, 480000000, 36, 1, 1, 0 }, /* actual: 468.0 MHz */
2220 { 38400000, 480000000, 25, 2, 1, 0 },
2221 { 0, 0, 0, 0, 0, 0 },
2224 static struct tegra_clk_pll_params pll_u_vco_params = {
2225 .input_min = 9600000,
2226 .input_max = 800000000,
2229 .vco_min = 350000000,
2230 .vco_max = 700000000,
2231 .base_reg = PLLU_BASE,
2232 .misc_reg = PLLU_MISC0,
2233 .lock_mask = PLL_BASE_LOCK,
2235 .iddq_reg = PLLU_MISC0,
2236 .iddq_bit_idx = PLLU_IDDQ_BIT,
2237 .ext_misc_reg[0] = PLLU_MISC0,
2238 .ext_misc_reg[1] = PLLU_MISC1,
2239 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2240 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2241 .div_nmp = &pllu_nmp,
2242 .freq_table = pll_u_freq_table,
2243 .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
2246 struct utmi_clk_param {
2247 /* Oscillator Frequency in KHz */
2249 /* UTMIP PLL Enable Delay Count */
2250 u8 enable_delay_count;
2251 /* UTMIP PLL Stable count */
2253 /* UTMIP PLL Active delay count */
2254 u8 active_delay_count;
2255 /* UTMIP PLL Xtal frequency count */
2256 u16 xtal_freq_count;
2259 static const struct utmi_clk_param utmi_parameters[] = {
2261 .osc_frequency = 38400000, .enable_delay_count = 0x0,
2262 .stable_count = 0x0, .active_delay_count = 0x6,
2263 .xtal_freq_count = 0x80
2265 .osc_frequency = 13000000, .enable_delay_count = 0x02,
2266 .stable_count = 0x33, .active_delay_count = 0x05,
2267 .xtal_freq_count = 0x7f
2269 .osc_frequency = 19200000, .enable_delay_count = 0x03,
2270 .stable_count = 0x4b, .active_delay_count = 0x06,
2271 .xtal_freq_count = 0xbb
2273 .osc_frequency = 12000000, .enable_delay_count = 0x02,
2274 .stable_count = 0x2f, .active_delay_count = 0x08,
2275 .xtal_freq_count = 0x76
2277 .osc_frequency = 26000000, .enable_delay_count = 0x04,
2278 .stable_count = 0x66, .active_delay_count = 0x09,
2279 .xtal_freq_count = 0xfe
2281 .osc_frequency = 16800000, .enable_delay_count = 0x03,
2282 .stable_count = 0x41, .active_delay_count = 0x0a,
2283 .xtal_freq_count = 0xa4
2287 static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
2288 [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true },
2289 [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
2290 [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },
2291 [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },
2292 [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },
2293 [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },
2294 [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },
2295 [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },
2296 [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },
2297 [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },
2298 [tegra_clk_isp_9] = { .dt_id = TEGRA210_CLK_ISP, .present = true },
2299 [tegra_clk_disp2_8] = { .dt_id = TEGRA210_CLK_DISP2, .present = true },
2300 [tegra_clk_disp1_8] = { .dt_id = TEGRA210_CLK_DISP1, .present = true },
2301 [tegra_clk_host1x_9] = { .dt_id = TEGRA210_CLK_HOST1X, .present = true },
2302 [tegra_clk_i2s0] = { .dt_id = TEGRA210_CLK_I2S0, .present = true },
2303 [tegra_clk_apbdma] = { .dt_id = TEGRA210_CLK_APBDMA, .present = true },
2304 [tegra_clk_kfuse] = { .dt_id = TEGRA210_CLK_KFUSE, .present = true },
2305 [tegra_clk_sbc1_9] = { .dt_id = TEGRA210_CLK_SBC1, .present = true },
2306 [tegra_clk_sbc2_9] = { .dt_id = TEGRA210_CLK_SBC2, .present = true },
2307 [tegra_clk_sbc3_9] = { .dt_id = TEGRA210_CLK_SBC3, .present = true },
2308 [tegra_clk_i2c5] = { .dt_id = TEGRA210_CLK_I2C5, .present = true },
2309 [tegra_clk_csi] = { .dt_id = TEGRA210_CLK_CSI, .present = true },
2310 [tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true },
2311 [tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true },
2312 [tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true },
2313 [tegra_clk_emc] = { .dt_id = TEGRA210_CLK_EMC, .present = true },
2314 [tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true },
2315 [tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true },
2316 [tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true },
2317 [tegra_clk_i2c3] = { .dt_id = TEGRA210_CLK_I2C3, .present = true },
2318 [tegra_clk_sbc4_9] = { .dt_id = TEGRA210_CLK_SBC4, .present = true },
2319 [tegra_clk_sdmmc3_9] = { .dt_id = TEGRA210_CLK_SDMMC3, .present = true },
2320 [tegra_clk_pcie] = { .dt_id = TEGRA210_CLK_PCIE, .present = true },
2321 [tegra_clk_owr_8] = { .dt_id = TEGRA210_CLK_OWR, .present = true },
2322 [tegra_clk_afi] = { .dt_id = TEGRA210_CLK_AFI, .present = true },
2323 [tegra_clk_csite_8] = { .dt_id = TEGRA210_CLK_CSITE, .present = true },
2324 [tegra_clk_soc_therm_8] = { .dt_id = TEGRA210_CLK_SOC_THERM, .present = true },
2325 [tegra_clk_dtv] = { .dt_id = TEGRA210_CLK_DTV, .present = true },
2326 [tegra_clk_i2cslow] = { .dt_id = TEGRA210_CLK_I2CSLOW, .present = true },
2327 [tegra_clk_tsec_8] = { .dt_id = TEGRA210_CLK_TSEC, .present = true },
2328 [tegra_clk_xusb_host] = { .dt_id = TEGRA210_CLK_XUSB_HOST, .present = true },
2329 [tegra_clk_csus] = { .dt_id = TEGRA210_CLK_CSUS, .present = true },
2330 [tegra_clk_mselect] = { .dt_id = TEGRA210_CLK_MSELECT, .present = true },
2331 [tegra_clk_tsensor] = { .dt_id = TEGRA210_CLK_TSENSOR, .present = true },
2332 [tegra_clk_i2s3] = { .dt_id = TEGRA210_CLK_I2S3, .present = true },
2333 [tegra_clk_i2s4] = { .dt_id = TEGRA210_CLK_I2S4, .present = true },
2334 [tegra_clk_i2c4] = { .dt_id = TEGRA210_CLK_I2C4, .present = true },
2335 [tegra_clk_d_audio] = { .dt_id = TEGRA210_CLK_D_AUDIO, .present = true },
2336 [tegra_clk_hda2codec_2x_8] = { .dt_id = TEGRA210_CLK_HDA2CODEC_2X, .present = true },
2337 [tegra_clk_spdif_2x] = { .dt_id = TEGRA210_CLK_SPDIF_2X, .present = true },
2338 [tegra_clk_actmon] = { .dt_id = TEGRA210_CLK_ACTMON, .present = true },
2339 [tegra_clk_extern1] = { .dt_id = TEGRA210_CLK_EXTERN1, .present = true },
2340 [tegra_clk_extern2] = { .dt_id = TEGRA210_CLK_EXTERN2, .present = true },
2341 [tegra_clk_extern3] = { .dt_id = TEGRA210_CLK_EXTERN3, .present = true },
2342 [tegra_clk_sata_oob_8] = { .dt_id = TEGRA210_CLK_SATA_OOB, .present = true },
2343 [tegra_clk_sata_8] = { .dt_id = TEGRA210_CLK_SATA, .present = true },
2344 [tegra_clk_hda_8] = { .dt_id = TEGRA210_CLK_HDA, .present = true },
2345 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA210_CLK_HDA2HDMI, .present = true },
2346 [tegra_clk_cilab] = { .dt_id = TEGRA210_CLK_CILAB, .present = true },
2347 [tegra_clk_cilcd] = { .dt_id = TEGRA210_CLK_CILCD, .present = true },
2348 [tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true },
2349 [tegra_clk_dsialp] = { .dt_id = TEGRA210_CLK_DSIALP, .present = true },
2350 [tegra_clk_dsiblp] = { .dt_id = TEGRA210_CLK_DSIBLP, .present = true },
2351 [tegra_clk_entropy_8] = { .dt_id = TEGRA210_CLK_ENTROPY, .present = true },
2352 [tegra_clk_xusb_ss] = { .dt_id = TEGRA210_CLK_XUSB_SS, .present = true },
2353 [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true },
2354 [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true },
2355 [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true },
2356 [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true },
2357 [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },
2358 [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },
2359 [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
2360 [tegra_clk_sor0_out] = { .dt_id = TEGRA210_CLK_SOR0_OUT, .present = true },
2361 [tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },
2362 [tegra_clk_sor1_out] = { .dt_id = TEGRA210_CLK_SOR1_OUT, .present = true },
2363 [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
2364 [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },
2365 [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },
2366 [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true },
2367 [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true },
2368 [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true },
2369 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true },
2370 [tegra_clk_fuse] = { .dt_id = TEGRA210_CLK_FUSE, .present = true },
2371 [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true },
2372 [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true },
2373 [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
2374 [tegra_clk_osc] = { .dt_id = TEGRA210_CLK_OSC, .present = true },
2375 [tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true },
2376 [tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true },
2377 [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
2378 [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
2379 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
2380 [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true },
2381 [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true },
2382 [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true },
2383 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },
2384 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true },
2385 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true },
2386 [tegra_clk_pll_p_out4_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT4, .present = true },
2387 [tegra_clk_pll_p_out_hsio] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_HSIO, .present = true },
2388 [tegra_clk_pll_p_out_xusb] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_XUSB, .present = true },
2389 [tegra_clk_pll_p_out_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_CPU, .present = true },
2390 [tegra_clk_pll_p_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_ADSP, .present = true },
2391 [tegra_clk_pll_a] = { .dt_id = TEGRA210_CLK_PLL_A, .present = true },
2392 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true },
2393 [tegra_clk_pll_d] = { .dt_id = TEGRA210_CLK_PLL_D, .present = true },
2394 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA210_CLK_PLL_D_OUT0, .present = true },
2395 [tegra_clk_pll_d2] = { .dt_id = TEGRA210_CLK_PLL_D2, .present = true },
2396 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA210_CLK_PLL_D2_OUT0, .present = true },
2397 [tegra_clk_pll_u] = { .dt_id = TEGRA210_CLK_PLL_U, .present = true },
2398 [tegra_clk_pll_u_out] = { .dt_id = TEGRA210_CLK_PLL_U_OUT, .present = true },
2399 [tegra_clk_pll_u_out1] = { .dt_id = TEGRA210_CLK_PLL_U_OUT1, .present = true },
2400 [tegra_clk_pll_u_out2] = { .dt_id = TEGRA210_CLK_PLL_U_OUT2, .present = true },
2401 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA210_CLK_PLL_U_480M, .present = true },
2402 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA210_CLK_PLL_U_60M, .present = true },
2403 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA210_CLK_PLL_U_48M, .present = true },
2404 [tegra_clk_pll_x] = { .dt_id = TEGRA210_CLK_PLL_X, .present = true },
2405 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA210_CLK_PLL_X_OUT0, .present = true },
2406 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA210_CLK_PLL_RE_VCO, .present = true },
2407 [tegra_clk_pll_re_out] = { .dt_id = TEGRA210_CLK_PLL_RE_OUT, .present = true },
2408 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC, .present = true },
2409 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA210_CLK_I2S0_SYNC, .present = true },
2410 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA210_CLK_I2S1_SYNC, .present = true },
2411 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA210_CLK_I2S2_SYNC, .present = true },
2412 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA210_CLK_I2S3_SYNC, .present = true },
2413 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA210_CLK_I2S4_SYNC, .present = true },
2414 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA210_CLK_VIMCLK_SYNC, .present = true },
2415 [tegra_clk_audio0] = { .dt_id = TEGRA210_CLK_AUDIO0, .present = true },
2416 [tegra_clk_audio1] = { .dt_id = TEGRA210_CLK_AUDIO1, .present = true },
2417 [tegra_clk_audio2] = { .dt_id = TEGRA210_CLK_AUDIO2, .present = true },
2418 [tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },
2419 [tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },
2420 [tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },
2421 [tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },
2422 [tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },
2423 [tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },
2424 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA210_CLK_XUSB_FS_SRC, .present = true },
2425 [tegra_clk_xusb_ss_src_8] = { .dt_id = TEGRA210_CLK_XUSB_SS_SRC, .present = true },
2426 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA210_CLK_XUSB_SS_DIV2, .present = true },
2427 [tegra_clk_xusb_dev_src_8] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SRC, .present = true },
2428 [tegra_clk_xusb_dev] = { .dt_id = TEGRA210_CLK_XUSB_DEV, .present = true },
2429 [tegra_clk_xusb_hs_src_4] = { .dt_id = TEGRA210_CLK_XUSB_HS_SRC, .present = true },
2430 [tegra_clk_xusb_ssp_src] = { .dt_id = TEGRA210_CLK_XUSB_SSP_SRC, .present = true },
2431 [tegra_clk_usb2_hsic_trk] = { .dt_id = TEGRA210_CLK_USB2_HSIC_TRK, .present = true },
2432 [tegra_clk_hsic_trk] = { .dt_id = TEGRA210_CLK_HSIC_TRK, .present = true },
2433 [tegra_clk_usb2_trk] = { .dt_id = TEGRA210_CLK_USB2_TRK, .present = true },
2434 [tegra_clk_sclk] = { .dt_id = TEGRA210_CLK_SCLK, .present = true },
2435 [tegra_clk_sclk_mux] = { .dt_id = TEGRA210_CLK_SCLK_MUX, .present = true },
2436 [tegra_clk_hclk] = { .dt_id = TEGRA210_CLK_HCLK, .present = true },
2437 [tegra_clk_pclk] = { .dt_id = TEGRA210_CLK_PCLK, .present = true },
2438 [tegra_clk_cclk_g] = { .dt_id = TEGRA210_CLK_CCLK_G, .present = true },
2439 [tegra_clk_cclk_lp] = { .dt_id = TEGRA210_CLK_CCLK_LP, .present = true },
2440 [tegra_clk_dfll_ref] = { .dt_id = TEGRA210_CLK_DFLL_REF, .present = true },
2441 [tegra_clk_dfll_soc] = { .dt_id = TEGRA210_CLK_DFLL_SOC, .present = true },
2442 [tegra_clk_vi_sensor2_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR2, .present = true },
2443 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA210_CLK_PLL_P_OUT5, .present = true },
2444 [tegra_clk_pll_c4] = { .dt_id = TEGRA210_CLK_PLL_C4, .present = true },
2445 [tegra_clk_pll_dp] = { .dt_id = TEGRA210_CLK_PLL_DP, .present = true },
2446 [tegra_clk_audio0_mux] = { .dt_id = TEGRA210_CLK_AUDIO0_MUX, .present = true },
2447 [tegra_clk_audio1_mux] = { .dt_id = TEGRA210_CLK_AUDIO1_MUX, .present = true },
2448 [tegra_clk_audio2_mux] = { .dt_id = TEGRA210_CLK_AUDIO2_MUX, .present = true },
2449 [tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },
2450 [tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },
2451 [tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },
2452 [tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },
2453 [tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },
2454 [tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },
2455 [tegra_clk_sdmmc_legacy] = { .dt_id = TEGRA210_CLK_SDMMC_LEGACY, .present = true },
2456 [tegra_clk_tsecb] = { .dt_id = TEGRA210_CLK_TSECB, .present = true },
2457 [tegra_clk_uartape] = { .dt_id = TEGRA210_CLK_UARTAPE, .present = true },
2458 [tegra_clk_vi_i2c] = { .dt_id = TEGRA210_CLK_VI_I2C, .present = true },
2459 [tegra_clk_ape] = { .dt_id = TEGRA210_CLK_APE, .present = true },
2460 [tegra_clk_dbgapb] = { .dt_id = TEGRA210_CLK_DBGAPB, .present = true },
2461 [tegra_clk_nvdec] = { .dt_id = TEGRA210_CLK_NVDEC, .present = true },
2462 [tegra_clk_nvenc] = { .dt_id = TEGRA210_CLK_NVENC, .present = true },
2463 [tegra_clk_nvjpg] = { .dt_id = TEGRA210_CLK_NVJPG, .present = true },
2464 [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true },
2465 [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true },
2466 [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
2467 [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
2468 [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
2469 [tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
2470 [tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true },
2471 [tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true },
2472 [tegra_clk_dmic1] = { .dt_id = TEGRA210_CLK_DMIC1, .present = true },
2473 [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true },
2474 [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true },
2475 [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true },
2476 [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true },
2477 [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true },
2478 [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true },
2479 [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true },
2480 [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true },
2481 [tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true },
2482 [tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true },
2483 [tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true },
2484 [tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true },
2485 [tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true },
2486 [tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true },
2487 [tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true },
2490 static struct tegra_devclk devclks[] __initdata = {
2491 { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
2492 { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
2493 { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
2494 { .con_id = "osc", .dt_id = TEGRA210_CLK_OSC },
2495 { .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 },
2496 { .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 },
2497 { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
2498 { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
2499 { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },
2500 { .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 },
2501 { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P },
2502 { .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 },
2503 { .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 },
2504 { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 },
2505 { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 },
2506 { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M },
2507 { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X },
2508 { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 },
2509 { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U },
2510 { .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT },
2511 { .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 },
2512 { .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 },
2513 { .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M },
2514 { .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M },
2515 { .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M },
2516 { .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D },
2517 { .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 },
2518 { .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 },
2519 { .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 },
2520 { .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A },
2521 { .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 },
2522 { .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO },
2523 { .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT },
2524 { .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC },
2525 { .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC },
2526 { .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC },
2527 { .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC },
2528 { .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC },
2529 { .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC },
2530 { .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC },
2531 { .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 },
2532 { .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 },
2533 { .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 },
2534 { .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 },
2535 { .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
2536 { .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
2537 { .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
2538 { .con_id = "extern1", .dt_id = TEGRA210_CLK_EXTERN1 },
2539 { .con_id = "extern2", .dt_id = TEGRA210_CLK_EXTERN2 },
2540 { .con_id = "extern3", .dt_id = TEGRA210_CLK_EXTERN3 },
2541 { .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
2542 { .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
2543 { .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
2544 { .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK },
2545 { .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK },
2546 { .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE },
2547 { .dev_id = "rtc-tegra", .dt_id = TEGRA210_CLK_RTC },
2548 { .dev_id = "timer", .dt_id = TEGRA210_CLK_TIMER },
2549 { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 },
2550 { .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 },
2551 { .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 },
2552 { .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 },
2553 { .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX },
2556 static struct tegra_audio_clk_info tegra210_audio_plls[] = {
2557 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" },
2558 { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" },
2561 static const char * const aclk_parents[] = {
2562 "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3",
2566 static const unsigned int nvjpg_slcg_clkids[] = { TEGRA210_CLK_NVDEC };
2567 static const unsigned int nvdec_slcg_clkids[] = { TEGRA210_CLK_NVJPG };
2568 static const unsigned int sor_slcg_clkids[] = { TEGRA210_CLK_HDA2CODEC_2X,
2569 TEGRA210_CLK_HDA2HDMI, TEGRA210_CLK_DISP1, TEGRA210_CLK_DISP2 };
2570 static const unsigned int disp_slcg_clkids[] = { TEGRA210_CLK_LA,
2571 TEGRA210_CLK_HOST1X};
2572 static const unsigned int xusba_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,
2573 TEGRA210_CLK_XUSB_DEV };
2574 static const unsigned int xusbb_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,
2575 TEGRA210_CLK_XUSB_SS };
2576 static const unsigned int xusbc_slcg_clkids[] = { TEGRA210_CLK_XUSB_DEV,
2577 TEGRA210_CLK_XUSB_SS };
2578 static const unsigned int venc_slcg_clkids[] = { TEGRA210_CLK_HOST1X,
2579 TEGRA210_CLK_PLL_D };
2580 static const unsigned int ape_slcg_clkids[] = { TEGRA210_CLK_ACLK,
2581 TEGRA210_CLK_I2S0, TEGRA210_CLK_I2S1, TEGRA210_CLK_I2S2,
2582 TEGRA210_CLK_I2S3, TEGRA210_CLK_I2S4, TEGRA210_CLK_SPDIF_OUT,
2583 TEGRA210_CLK_D_AUDIO };
2584 static const unsigned int vic_slcg_clkids[] = { TEGRA210_CLK_HOST1X };
2586 static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = {
2587 [TEGRA_POWERGATE_VENC] = {
2588 .handle_lvl2_ovr = tegra210_venc_mbist_war,
2589 .num_clks = ARRAY_SIZE(venc_slcg_clkids),
2590 .clk_init_data = venc_slcg_clkids,
2592 [TEGRA_POWERGATE_SATA] = {
2593 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2594 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2595 .lvl2_mask = BIT(0) | BIT(17) | BIT(19),
2597 [TEGRA_POWERGATE_MPE] = {
2598 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2599 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2600 .lvl2_mask = BIT(29),
2602 [TEGRA_POWERGATE_SOR] = {
2603 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2604 .num_clks = ARRAY_SIZE(sor_slcg_clkids),
2605 .clk_init_data = sor_slcg_clkids,
2606 .lvl2_offset = LVL2_CLK_GATE_OVRA,
2607 .lvl2_mask = BIT(1) | BIT(2),
2609 [TEGRA_POWERGATE_DIS] = {
2610 .handle_lvl2_ovr = tegra210_disp_mbist_war,
2611 .num_clks = ARRAY_SIZE(disp_slcg_clkids),
2612 .clk_init_data = disp_slcg_clkids,
2614 [TEGRA_POWERGATE_DISB] = {
2615 .num_clks = ARRAY_SIZE(disp_slcg_clkids),
2616 .clk_init_data = disp_slcg_clkids,
2617 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2618 .lvl2_offset = LVL2_CLK_GATE_OVRA,
2619 .lvl2_mask = BIT(2),
2621 [TEGRA_POWERGATE_XUSBA] = {
2622 .num_clks = ARRAY_SIZE(xusba_slcg_clkids),
2623 .clk_init_data = xusba_slcg_clkids,
2624 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2625 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2626 .lvl2_mask = BIT(30) | BIT(31),
2628 [TEGRA_POWERGATE_XUSBB] = {
2629 .num_clks = ARRAY_SIZE(xusbb_slcg_clkids),
2630 .clk_init_data = xusbb_slcg_clkids,
2631 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2632 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2633 .lvl2_mask = BIT(30) | BIT(31),
2635 [TEGRA_POWERGATE_XUSBC] = {
2636 .num_clks = ARRAY_SIZE(xusbc_slcg_clkids),
2637 .clk_init_data = xusbc_slcg_clkids,
2638 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2639 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2640 .lvl2_mask = BIT(30) | BIT(31),
2642 [TEGRA_POWERGATE_VIC] = {
2643 .num_clks = ARRAY_SIZE(vic_slcg_clkids),
2644 .clk_init_data = vic_slcg_clkids,
2645 .handle_lvl2_ovr = tegra210_vic_mbist_war,
2647 [TEGRA_POWERGATE_NVDEC] = {
2648 .num_clks = ARRAY_SIZE(nvdec_slcg_clkids),
2649 .clk_init_data = nvdec_slcg_clkids,
2650 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2651 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2652 .lvl2_mask = BIT(9) | BIT(31),
2654 [TEGRA_POWERGATE_NVJPG] = {
2655 .num_clks = ARRAY_SIZE(nvjpg_slcg_clkids),
2656 .clk_init_data = nvjpg_slcg_clkids,
2657 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2658 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2659 .lvl2_mask = BIT(9) | BIT(31),
2661 [TEGRA_POWERGATE_AUD] = {
2662 .num_clks = ARRAY_SIZE(ape_slcg_clkids),
2663 .clk_init_data = ape_slcg_clkids,
2664 .handle_lvl2_ovr = tegra210_ape_mbist_war,
2666 [TEGRA_POWERGATE_VE2] = {
2667 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2668 .lvl2_offset = LVL2_CLK_GATE_OVRD,
2669 .lvl2_mask = BIT(22),
2673 int tegra210_clk_handle_mbist_war(unsigned int id)
2676 struct tegra210_domain_mbist_war *mbist_war;
2678 if (id >= ARRAY_SIZE(tegra210_pg_mbist_war)) {
2679 WARN(1, "unknown domain id in MBIST WAR handler\n");
2683 mbist_war = &tegra210_pg_mbist_war[id];
2684 if (!mbist_war->handle_lvl2_ovr)
2687 if (mbist_war->num_clks && !mbist_war->clks)
2690 err = clk_bulk_prepare_enable(mbist_war->num_clks, mbist_war->clks);
2694 mutex_lock(&lvl2_ovr_lock);
2696 mbist_war->handle_lvl2_ovr(mbist_war);
2698 mutex_unlock(&lvl2_ovr_lock);
2700 clk_bulk_disable_unprepare(mbist_war->num_clks, mbist_war->clks);
2705 void tegra210_put_utmipll_in_iddq(void)
2709 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2711 if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) {
2712 pr_err("trying to assert IDDQ while UTMIPLL is locked\n");
2716 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2717 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2719 EXPORT_SYMBOL_GPL(tegra210_put_utmipll_in_iddq);
2721 void tegra210_put_utmipll_out_iddq(void)
2725 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2726 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2727 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2729 EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq);
2731 static void tegra210_utmi_param_configure(void)
2736 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2737 if (osc_freq == utmi_parameters[i].osc_frequency)
2741 if (i >= ARRAY_SIZE(utmi_parameters)) {
2742 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
2747 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2748 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2749 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2753 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2755 /* Program UTMIP PLL stable and active counts */
2756 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
2757 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2758 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
2760 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2762 UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count);
2763 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2765 /* Program UTMIP PLL delay and oscillator frequency counts */
2766 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2768 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2770 UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count);
2772 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2774 UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].xtal_freq_count);
2776 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
2777 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2779 /* Remove power downs from UTMIP PLL control bits */
2780 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2781 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2782 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2783 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2787 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
2788 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2789 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2790 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2791 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2792 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2793 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2794 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2795 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2797 /* Setup HW control of UTMIPLL */
2798 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2799 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2800 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2801 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2803 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2804 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2805 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2806 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2810 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2811 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
2812 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2816 /* Enable HW control UTMIPLL */
2817 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2818 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2819 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2822 static int tegra210_enable_pllu(void)
2824 struct tegra_clk_pll_freq_table *fentry;
2825 struct tegra_clk_pll pllu;
2829 for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
2830 if (fentry->input_rate == pll_ref_freq)
2834 if (!fentry->input_rate) {
2835 pr_err("Unknown PLL_U reference frequency %lu\n", pll_ref_freq);
2839 /* clear IDDQ bit */
2840 pllu.params = &pll_u_vco_params;
2841 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
2842 reg &= ~BIT(pllu.params->iddq_bit_idx);
2843 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
2844 fence_udelay(5, clk_base);
2846 reg = readl_relaxed(clk_base + PLLU_BASE);
2847 reg &= ~GENMASK(20, 0);
2849 reg |= fentry->n << 8;
2850 reg |= fentry->p << 16;
2851 writel(reg, clk_base + PLLU_BASE);
2852 fence_udelay(1, clk_base);
2854 writel(reg, clk_base + PLLU_BASE);
2857 * During clocks resume, same PLLU init and enable sequence get
2858 * executed. So, readx_poll_timeout_atomic can't be used here as it
2859 * uses ktime_get() and timekeeping resume doesn't happen by that
2860 * time. So, using tegra210_wait_for_mask for PLL LOCK.
2862 ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK);
2864 pr_err("Timed out waiting for PLL_U to lock\n");
2871 static int tegra210_init_pllu(void)
2876 tegra210_pllu_set_defaults(&pll_u_vco_params);
2877 /* skip initialization when pllu is in hw controlled mode */
2878 reg = readl_relaxed(clk_base + PLLU_BASE);
2879 if (reg & PLLU_BASE_OVERRIDE) {
2880 if (!(reg & PLL_ENABLE)) {
2881 err = tegra210_enable_pllu();
2887 /* enable hw controlled mode */
2888 reg = readl_relaxed(clk_base + PLLU_BASE);
2889 reg &= ~PLLU_BASE_OVERRIDE;
2890 writel(reg, clk_base + PLLU_BASE);
2892 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2893 reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
2894 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
2895 PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
2896 reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
2897 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
2898 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2900 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2901 reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK;
2902 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2903 fence_udelay(1, clk_base);
2905 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2906 reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
2907 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2908 fence_udelay(1, clk_base);
2910 reg = readl_relaxed(clk_base + PLLU_BASE);
2911 reg &= ~PLLU_BASE_CLKENABLE_USB;
2912 writel_relaxed(reg, clk_base + PLLU_BASE);
2915 /* enable UTMIPLL hw control if not yet done by the bootloader */
2916 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2917 if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE))
2918 tegra210_utmi_param_configure();
2924 * The SOR hardware blocks are driven by two clocks: a module clock that is
2925 * used to access registers and a pixel clock that is sourced from the same
2926 * pixel clock that also drives the head attached to the SOR. The module
2927 * clock is typically called sorX (with X being the SOR instance) and the
2928 * pixel clock is called sorX_out. The source for the SOR pixel clock is
2929 * referred to as the "parent" clock.
2931 * On Tegra186 and newer, clocks are provided by the BPMP. Unfortunately the
2932 * BPMP implementation for the SOR clocks doesn't exactly match the above in
2933 * some aspects. For example, the SOR module is really clocked by the pad or
2934 * sor_safe clocks, but BPMP models the sorX clock as being sourced by the
2935 * pixel clocks. Conversely the sorX_out clock is sourced by the sor_safe or
2936 * pad clocks on BPMP.
2938 * In order to allow the display driver to deal with all SoC generations in
2939 * a unified way, implement the BPMP semantics in this driver.
2942 static const char * const sor0_parents[] = {
2946 static const char * const sor0_out_parents[] = {
2947 "sor_safe", "sor0_pad_clkout",
2950 static const char * const sor1_parents[] = {
2951 "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m",
2954 static u32 sor1_parents_idx[] = { 0, 2, 5, 6 };
2956 static const char * const sor1_out_parents[] = {
2958 * Bit 0 of the mux selects sor1_pad_clkout, irrespective of bit 1, so
2959 * the sor1_pad_clkout parent appears twice in the list below. This is
2960 * merely to support clk_get_parent() if firmware happened to set
2961 * these bits to 0b11. While not an invalid setting, code should
2962 * always set the bits to 0b01 to select sor1_pad_clkout.
2964 "sor_safe", "sor1_pad_clkout", "sor1_out", "sor1_pad_clkout",
2967 static struct tegra_periph_init_data tegra210_periph[] = {
2969 * On Tegra210, the sor0 clock doesn't have a mux it bitfield 31:29,
2970 * but it is hardwired to the pll_d_out0 clock.
2972 TEGRA_INIT_DATA_TABLE("sor0", NULL, NULL, sor0_parents,
2973 CLK_SOURCE_SOR0, 29, 0x0, 0, 0, 0, 0,
2974 0, 182, 0, tegra_clk_sor0, NULL, 0,
2976 TEGRA_INIT_DATA_TABLE("sor0_out", NULL, NULL, sor0_out_parents,
2977 CLK_SOURCE_SOR0, 14, 0x1, 0, 0, 0, 0,
2978 0, 0, TEGRA_PERIPH_NO_GATE, tegra_clk_sor0_out,
2979 NULL, 0, &sor0_lock),
2980 TEGRA_INIT_DATA_TABLE("sor1", NULL, NULL, sor1_parents,
2981 CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1,
2982 TEGRA_DIVIDER_ROUND_UP, 183, 0,
2983 tegra_clk_sor1, sor1_parents_idx, 0,
2985 TEGRA_INIT_DATA_TABLE("sor1_out", NULL, NULL, sor1_out_parents,
2986 CLK_SOURCE_SOR1, 14, 0x3, 0, 0, 0, 0,
2987 0, 0, TEGRA_PERIPH_NO_GATE,
2988 tegra_clk_sor1_out, NULL, 0, &sor1_lock),
2991 static const char * const la_parents[] = {
2992 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_re_out1", "pll_a1", "clk_m", "pll_c4_out0"
2995 static struct tegra_clk_periph tegra210_la =
2996 TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, NULL);
2998 static __init void tegra210_periph_clk_init(void __iomem *clk_base,
2999 void __iomem *pmc_base)
3005 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
3007 clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
3009 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
3011 clks[TEGRA210_CLK_SOR_SAFE] = clk;
3013 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
3015 clks[TEGRA210_CLK_DPAUX] = clk;
3017 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
3019 clks[TEGRA210_CLK_DPAUX1] = clk;
3022 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
3023 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
3024 clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk;
3027 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
3029 periph_clk_enb_refcnt);
3030 clks[TEGRA210_CLK_DSIA] = clk;
3033 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
3035 periph_clk_enb_refcnt);
3036 clks[TEGRA210_CLK_DSIB] = clk;
3039 clk = tegra_clk_register_periph("la", la_parents,
3040 ARRAY_SIZE(la_parents), &tegra210_la, clk_base,
3042 clks[TEGRA210_CLK_LA] = clk;
3045 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
3046 ARRAY_SIZE(mux_pllmcp_clkm), 0,
3047 clk_base + CLK_SOURCE_EMC,
3048 29, 3, 0, &emc_lock);
3050 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
3052 clks[TEGRA210_CLK_MC] = clk;
3055 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
3057 clk_register_clkdev(clk, "cml0", NULL);
3058 clks[TEGRA210_CLK_CML0] = clk;
3061 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
3063 clk_register_clkdev(clk, "cml1", NULL);
3064 clks[TEGRA210_CLK_CML1] = clk;
3066 clk = tegra_clk_register_super_clk("aclk", aclk_parents,
3067 ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,
3069 clks[TEGRA210_CLK_ACLK] = clk;
3071 clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
3072 CLK_SOURCE_SDMMC2, 9,
3073 TEGRA_DIVIDER_ROUND_UP, 0, NULL);
3074 clks[TEGRA210_CLK_SDMMC2] = clk;
3076 clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
3077 CLK_SOURCE_SDMMC4, 15,
3078 TEGRA_DIVIDER_ROUND_UP, 0, NULL);
3079 clks[TEGRA210_CLK_SDMMC4] = clk;
3081 for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) {
3082 struct tegra_periph_init_data *init = &tegra210_periph[i];
3085 clkp = tegra_lookup_dt_id(init->clk_id, tegra210_clks);
3087 pr_warn("clock %u not found\n", init->clk_id);
3091 clk = tegra_clk_register_periph_data(clk_base, init);
3095 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
3098 static void __init tegra210_pll_init(void __iomem *clk_base,
3104 clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base,
3105 pmc, 0, &pll_c_params, NULL);
3106 if (!WARN_ON(IS_ERR(clk)))
3107 clk_register_clkdev(clk, "pll_c", NULL);
3108 clks[TEGRA210_CLK_PLL_C] = clk;
3111 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
3112 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3114 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
3115 clk_base + PLLC_OUT, 1, 0,
3116 CLK_SET_RATE_PARENT, 0, NULL);
3117 clk_register_clkdev(clk, "pll_c_out1", NULL);
3118 clks[TEGRA210_CLK_PLL_C_OUT1] = clk;
3121 clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
3122 CLK_SET_RATE_PARENT, 1, 1);
3123 clk_register_clkdev(clk, "pll_c_ud", NULL);
3124 clks[TEGRA210_CLK_PLL_C_UD] = clk;
3127 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base,
3128 pmc, 0, &pll_c2_params, NULL);
3129 clk_register_clkdev(clk, "pll_c2", NULL);
3130 clks[TEGRA210_CLK_PLL_C2] = clk;
3133 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base,
3134 pmc, 0, &pll_c3_params, NULL);
3135 clk_register_clkdev(clk, "pll_c3", NULL);
3136 clks[TEGRA210_CLK_PLL_C3] = clk;
3139 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc,
3140 CLK_SET_RATE_GATE, &pll_m_params, NULL);
3141 clk_register_clkdev(clk, "pll_m", NULL);
3142 clks[TEGRA210_CLK_PLL_M] = clk;
3145 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc,
3146 CLK_SET_RATE_GATE, &pll_mb_params, NULL);
3147 clk_register_clkdev(clk, "pll_mb", NULL);
3148 clks[TEGRA210_CLK_PLL_MB] = clk;
3151 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
3152 CLK_SET_RATE_PARENT, 1, 1);
3153 clk_register_clkdev(clk, "pll_m_ud", NULL);
3154 clks[TEGRA210_CLK_PLL_M_UD] = clk;
3157 if (!tegra210_init_pllu()) {
3158 clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0,
3160 clk_register_clkdev(clk, "pll_u_vco", NULL);
3161 clks[TEGRA210_CLK_PLL_U] = clk;
3165 clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0,
3166 clk_base + PLLU_BASE, 16, 4, 0,
3167 pll_vco_post_div_table, NULL);
3168 clk_register_clkdev(clk, "pll_u_out", NULL);
3169 clks[TEGRA210_CLK_PLL_U_OUT] = clk;
3172 clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out",
3173 clk_base + PLLU_OUTA, 0,
3174 TEGRA_DIVIDER_ROUND_UP,
3175 8, 8, 1, &pll_u_lock);
3176 clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div",
3177 clk_base + PLLU_OUTA, 1, 0,
3178 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
3179 clk_register_clkdev(clk, "pll_u_out1", NULL);
3180 clks[TEGRA210_CLK_PLL_U_OUT1] = clk;
3183 clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out",
3184 clk_base + PLLU_OUTA, 0,
3185 TEGRA_DIVIDER_ROUND_UP,
3186 24, 8, 1, &pll_u_lock);
3187 clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div",
3188 clk_base + PLLU_OUTA, 17, 16,
3189 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
3190 clk_register_clkdev(clk, "pll_u_out2", NULL);
3191 clks[TEGRA210_CLK_PLL_U_OUT2] = clk;
3194 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco",
3195 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3196 22, 0, &pll_u_lock);
3197 clk_register_clkdev(clk, "pll_u_480M", NULL);
3198 clks[TEGRA210_CLK_PLL_U_480M] = clk;
3201 clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",
3202 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3203 23, 0, &pll_u_lock);
3204 clk_register_clkdev(clk, "pll_u_60M", NULL);
3205 clks[TEGRA210_CLK_PLL_U_60M] = clk;
3208 clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",
3209 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3210 25, 0, &pll_u_lock);
3211 clk_register_clkdev(clk, "pll_u_48M", NULL);
3212 clks[TEGRA210_CLK_PLL_U_48M] = clk;
3215 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
3216 &pll_d_params, &pll_d_lock);
3217 clk_register_clkdev(clk, "pll_d", NULL);
3218 clks[TEGRA210_CLK_PLL_D] = clk;
3221 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
3222 CLK_SET_RATE_PARENT, 1, 2);
3223 clk_register_clkdev(clk, "pll_d_out0", NULL);
3224 clks[TEGRA210_CLK_PLL_D_OUT0] = clk;
3227 clk = tegra_clk_register_pllre_tegra210("pll_re_vco", "pll_ref",
3230 &pll_re_lock, pll_ref_freq);
3231 clk_register_clkdev(clk, "pll_re_vco", NULL);
3232 clks[TEGRA210_CLK_PLL_RE_VCO] = clk;
3234 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
3235 clk_base + PLLRE_BASE, 16, 5, 0,
3236 pll_vco_post_div_table, &pll_re_lock);
3237 clk_register_clkdev(clk, "pll_re_out", NULL);
3238 clks[TEGRA210_CLK_PLL_RE_OUT] = clk;
3240 clk = tegra_clk_register_divider("pll_re_out1_div", "pll_re_vco",
3241 clk_base + PLLRE_OUT1, 0,
3242 TEGRA_DIVIDER_ROUND_UP,
3244 clk = tegra_clk_register_pll_out("pll_re_out1", "pll_re_out1_div",
3245 clk_base + PLLRE_OUT1, 1, 0,
3246 CLK_SET_RATE_PARENT, 0, NULL);
3247 clks[TEGRA210_CLK_PLL_RE_OUT1] = clk;
3250 clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref",
3251 clk_base, 0, &pll_e_params, NULL);
3252 clk_register_clkdev(clk, "pll_e", NULL);
3253 clks[TEGRA210_CLK_PLL_E] = clk;
3256 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc,
3257 0, &pll_c4_vco_params, NULL, pll_ref_freq);
3258 clk_register_clkdev(clk, "pll_c4_vco", NULL);
3259 clks[TEGRA210_CLK_PLL_C4] = clk;
3262 clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0,
3263 clk_base + PLLC4_BASE, 19, 4, 0,
3264 pll_vco_post_div_table, NULL);
3265 clk_register_clkdev(clk, "pll_c4_out0", NULL);
3266 clks[TEGRA210_CLK_PLL_C4_OUT0] = clk;
3269 clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco",
3270 CLK_SET_RATE_PARENT, 1, 3);
3271 clk_register_clkdev(clk, "pll_c4_out1", NULL);
3272 clks[TEGRA210_CLK_PLL_C4_OUT1] = clk;
3275 clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco",
3276 CLK_SET_RATE_PARENT, 1, 5);
3277 clk_register_clkdev(clk, "pll_c4_out2", NULL);
3278 clks[TEGRA210_CLK_PLL_C4_OUT2] = clk;
3281 clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0",
3282 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3284 clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div",
3285 clk_base + PLLC4_OUT, 1, 0,
3286 CLK_SET_RATE_PARENT, 0, NULL);
3287 clk_register_clkdev(clk, "pll_c4_out3", NULL);
3288 clks[TEGRA210_CLK_PLL_C4_OUT3] = clk;
3291 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base,
3292 0, &pll_dp_params, NULL);
3293 clk_register_clkdev(clk, "pll_dp", NULL);
3294 clks[TEGRA210_CLK_PLL_DP] = clk;
3297 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base,
3298 0, &pll_d2_params, NULL);
3299 clk_register_clkdev(clk, "pll_d2", NULL);
3300 clks[TEGRA210_CLK_PLL_D2] = clk;
3303 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
3304 CLK_SET_RATE_PARENT, 1, 1);
3305 clk_register_clkdev(clk, "pll_d2_out0", NULL);
3306 clks[TEGRA210_CLK_PLL_D2_OUT0] = clk;
3309 clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p",
3310 CLK_SET_RATE_PARENT, 1, 2);
3311 clk_register_clkdev(clk, "pll_p_out2", NULL);
3312 clks[TEGRA210_CLK_PLL_P_OUT2] = clk;
3316 /* Tegra210 CPU clock and reset control functions */
3317 static void tegra210_wait_cpu_in_reset(u32 cpu)
3322 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
3324 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
3327 static void tegra210_disable_cpu_clock(u32 cpu)
3329 /* flow controller would take care in the power sequence. */
3332 #ifdef CONFIG_PM_SLEEP
3333 #define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4))
3334 #define car_writel(_val, _base, _off) \
3335 writel_relaxed(_val, clk_base + (_base) + ((_off) * 4))
3337 static u32 spare_reg_ctx, misc_clk_enb_ctx, clk_msk_arm_ctx;
3338 static u32 cpu_softrst_ctx[3];
3340 static int tegra210_clk_suspend(void)
3347 * Save the bootloader configured clock registers SPARE_REG0,
3348 * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL.
3350 spare_reg_ctx = readl_relaxed(clk_base + SPARE_REG0);
3351 misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB);
3352 clk_msk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM);
3354 for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
3355 cpu_softrst_ctx[i] = car_readl(CPU_SOFTRST_CTRL, i);
3357 tegra_clk_periph_suspend();
3361 static void tegra210_clk_resume(void)
3365 tegra_clk_osc_resume(clk_base);
3368 * Restore the bootloader configured clock registers SPARE_REG0,
3369 * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL from saved context.
3371 writel_relaxed(spare_reg_ctx, clk_base + SPARE_REG0);
3372 writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB);
3373 writel_relaxed(clk_msk_arm_ctx, clk_base + CLK_MASK_ARM);
3375 for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
3376 car_writel(cpu_softrst_ctx[i], CPU_SOFTRST_CTRL, i);
3379 * Tegra clock programming sequence recommends peripheral clock to
3380 * be enabled prior to changing its clock source and divider to
3381 * prevent glitchless frequency switch.
3382 * So, enable all peripheral clocks before restoring their source
3385 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_L, clk_base + CLK_OUT_ENB_L);
3386 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_H, clk_base + CLK_OUT_ENB_H);
3387 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_U, clk_base + CLK_OUT_ENB_U);
3388 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_V, clk_base + CLK_OUT_ENB_V);
3389 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_W, clk_base + CLK_OUT_ENB_W);
3390 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_X, clk_base + CLK_OUT_ENB_X);
3391 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_Y, clk_base + CLK_OUT_ENB_Y);
3393 /* wait for all writes to happen to have all the clocks enabled */
3394 fence_udelay(2, clk_base);
3396 /* restore PLLs and all peripheral clock rates */
3397 tegra210_init_pllu();
3398 clk_restore_context();
3400 /* restore saved context of peripheral clocks and reset state */
3401 tegra_clk_periph_resume();
3404 static void tegra210_cpu_clock_suspend(void)
3406 /* switch coresite to clk_m, save off original source */
3407 tegra210_cpu_clk_sctx.clk_csite_src =
3408 readl(clk_base + CLK_SOURCE_CSITE);
3409 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
3412 static void tegra210_cpu_clock_resume(void)
3414 writel(tegra210_cpu_clk_sctx.clk_csite_src,
3415 clk_base + CLK_SOURCE_CSITE);
3419 static struct syscore_ops tegra_clk_syscore_ops = {
3420 #ifdef CONFIG_PM_SLEEP
3421 .suspend = tegra210_clk_suspend,
3422 .resume = tegra210_clk_resume,
3426 static struct tegra_cpu_car_ops tegra210_cpu_car_ops = {
3427 .wait_for_reset = tegra210_wait_cpu_in_reset,
3428 .disable_clock = tegra210_disable_cpu_clock,
3429 #ifdef CONFIG_PM_SLEEP
3430 .suspend = tegra210_cpu_clock_suspend,
3431 .resume = tegra210_cpu_clock_resume,
3435 static const struct of_device_id pmc_match[] __initconst = {
3436 { .compatible = "nvidia,tegra210-pmc" },
3440 static struct tegra_clk_init_table init_table[] __initdata = {
3441 { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 },
3442 { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
3443 { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
3444 { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
3445 { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 0 },
3446 { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 0 },
3447 { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3448 { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3449 { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3450 { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3451 { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3452 { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 },
3453 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
3454 { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 0 },
3455 { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 },
3456 { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
3457 { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
3458 { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
3459 { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
3460 { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
3461 { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
3462 { TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
3463 { TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
3464 { TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 },
3465 { TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
3466 { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
3467 { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 },
3468 { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 },
3469 { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
3470 { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
3471 /* TODO find a way to enable this on-demand */
3472 { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
3473 { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
3474 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
3475 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
3476 { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 },
3477 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },
3478 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },
3479 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },
3480 { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 },
3481 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
3482 { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
3483 { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
3484 { TEGRA210_CLK_SPDIF_IN_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3485 { TEGRA210_CLK_I2S0_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3486 { TEGRA210_CLK_I2S1_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3487 { TEGRA210_CLK_I2S2_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3488 { TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3489 { TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3490 { TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3491 { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
3492 { TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },
3493 /* This MUST be the last entry. */
3494 { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
3498 * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs
3500 * Program an initial clock rate and enable or disable clocks needed
3501 * by the rest of the kernel, for Tegra210 SoCs. It is intended to be
3502 * called by assigning a pointer to it to tegra_clk_apply_init_table -
3503 * this will be called as an arch_initcall. No return value.
3505 static void __init tegra210_clock_apply_init_table(void)
3507 tegra_init_from_table(init_table, clks, TEGRA210_CLK_CLK_MAX);
3511 * tegra210_car_barrier - wait for pending writes to the CAR to complete
3513 * Wait for any outstanding writes to the CAR MMIO space from this CPU
3514 * to complete before continuing execution. No return value.
3516 static void tegra210_car_barrier(void)
3518 readl_relaxed(clk_base + RST_DFLL_DVCO);
3522 * tegra210_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
3524 * Assert the reset line of the DFLL's DVCO. No return value.
3526 static void tegra210_clock_assert_dfll_dvco_reset(void)
3530 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3531 v |= (1 << DVFS_DFLL_RESET_SHIFT);
3532 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3533 tegra210_car_barrier();
3537 * tegra210_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
3539 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
3540 * operate. No return value.
3542 static void tegra210_clock_deassert_dfll_dvco_reset(void)
3546 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3547 v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
3548 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3549 tegra210_car_barrier();
3552 static int tegra210_reset_assert(unsigned long id)
3554 if (id == TEGRA210_RST_DFLL_DVCO)
3555 tegra210_clock_assert_dfll_dvco_reset();
3556 else if (id == TEGRA210_RST_ADSP)
3557 writel(GENMASK(26, 21) | BIT(7),
3558 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET);
3565 static int tegra210_reset_deassert(unsigned long id)
3567 if (id == TEGRA210_RST_DFLL_DVCO)
3568 tegra210_clock_deassert_dfll_dvco_reset();
3569 else if (id == TEGRA210_RST_ADSP) {
3570 writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3572 * Considering adsp cpu clock (min: 12.5MHZ, max: 1GHz)
3573 * a delay of 5us ensures that it's at least
3574 * 6 * adsp_cpu_cycle_period long.
3577 writel(GENMASK(26, 22) | BIT(7),
3578 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3585 static void tegra210_mbist_clk_init(void)
3589 for (i = 0; i < ARRAY_SIZE(tegra210_pg_mbist_war); i++) {
3590 unsigned int num_clks = tegra210_pg_mbist_war[i].num_clks;
3591 struct clk_bulk_data *clk_data;
3596 clk_data = kmalloc_array(num_clks, sizeof(*clk_data),
3598 if (WARN_ON(!clk_data))
3601 tegra210_pg_mbist_war[i].clks = clk_data;
3602 for (j = 0; j < num_clks; j++) {
3603 int clk_id = tegra210_pg_mbist_war[i].clk_init_data[j];
3604 struct clk *clk = clks[clk_id];
3606 if (WARN(IS_ERR(clk), "clk_id: %d\n", clk_id)) {
3608 tegra210_pg_mbist_war[i].clks = NULL;
3611 clk_data[j].clk = clk;
3617 * tegra210_clock_init - Tegra210-specific clock initialization
3618 * @np: struct device_node * of the DT node for the SoC CAR IP block
3620 * Register most SoC clocks for the Tegra210 system-on-chip. Intended
3621 * to be called by the OF init code when a DT node with the
3622 * "nvidia,tegra210-car" string is encountered, and declared with
3623 * CLK_OF_DECLARE. No return value.
3625 static void __init tegra210_clock_init(struct device_node *np)
3627 struct device_node *node;
3628 u32 value, clk_m_div;
3630 clk_base = of_iomap(np, 0);
3632 pr_err("ioremap tegra210 CAR failed\n");
3636 node = of_find_matching_node(NULL, pmc_match);
3638 pr_err("Failed to find pmc node\n");
3643 pmc_base = of_iomap(node, 0);
3645 pr_err("Can't map pmc registers\n");
3650 ahub_base = ioremap(TEGRA210_AHUB_BASE, SZ_64K);
3652 pr_err("ioremap tegra210 APE failed\n");
3656 dispa_base = ioremap(TEGRA210_DISPA_BASE, SZ_256K);
3658 pr_err("ioremap tegra210 DISPA failed\n");
3662 vic_base = ioremap(TEGRA210_VIC_BASE, SZ_256K);
3664 pr_err("ioremap tegra210 VIC failed\n");
3668 clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX,
3669 TEGRA210_CAR_BANK_COUNT);
3673 value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
3674 clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1;
3676 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,
3677 ARRAY_SIZE(tegra210_input_freq), clk_m_div,
3678 &osc_freq, &pll_ref_freq) < 0)
3681 tegra_fixed_clk_init(tegra210_clks);
3682 tegra210_pll_init(clk_base, pmc_base);
3683 tegra210_periph_clk_init(clk_base, pmc_base);
3684 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
3685 tegra210_audio_plls,
3686 ARRAY_SIZE(tegra210_audio_plls), 24576000);
3688 /* For Tegra210, PLLD is the only source for DSIA & DSIB */
3689 value = readl(clk_base + PLLD_BASE);
3691 writel(value, clk_base + PLLD_BASE);
3693 tegra_clk_apply_init_table = tegra210_clock_apply_init_table;
3695 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks,
3697 tegra_init_special_resets(2, tegra210_reset_assert,
3698 tegra210_reset_deassert);
3700 tegra_add_of_provider(np, of_clk_src_onecell_get);
3701 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
3703 tegra210_mbist_clk_init();
3705 tegra_cpu_car_ops = &tegra210_cpu_car_ops;
3707 register_syscore_ops(&tegra_clk_syscore_ops);
3709 CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init);