2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 #include <linux/clkdev.h>
22 #include <linux/of_address.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/mutex.h>
26 #include <linux/clk/tegra.h>
27 #include <dt-bindings/clock/tegra210-car.h>
28 #include <dt-bindings/reset/tegra210-car.h>
29 #include <linux/iopoll.h>
30 #include <linux/sizes.h>
31 #include <soc/tegra/pmc.h>
37 * TEGRA210_CAR_BANK_COUNT: the number of peripheral clock register
38 * banks present in the Tegra210 CAR IP block. The banks are
39 * identified by single letters, e.g.: L, H, U, V, W, X, Y. See
40 * periph_regs[] in drivers/clk/tegra/clk.c
42 #define TEGRA210_CAR_BANK_COUNT 7
44 #define CLK_SOURCE_CSITE 0x1d4
45 #define CLK_SOURCE_EMC 0x19c
46 #define CLK_SOURCE_SOR1 0x410
47 #define CLK_SOURCE_LA 0x1f8
48 #define CLK_SOURCE_SDMMC2 0x154
49 #define CLK_SOURCE_SDMMC4 0x164
51 #define PLLC_BASE 0x80
53 #define PLLC_MISC0 0x88
54 #define PLLC_MISC1 0x8c
55 #define PLLC_MISC2 0x5d0
56 #define PLLC_MISC3 0x5d4
58 #define PLLC2_BASE 0x4e8
59 #define PLLC2_MISC0 0x4ec
60 #define PLLC2_MISC1 0x4f0
61 #define PLLC2_MISC2 0x4f4
62 #define PLLC2_MISC3 0x4f8
64 #define PLLC3_BASE 0x4fc
65 #define PLLC3_MISC0 0x500
66 #define PLLC3_MISC1 0x504
67 #define PLLC3_MISC2 0x508
68 #define PLLC3_MISC3 0x50c
70 #define PLLM_BASE 0x90
71 #define PLLM_MISC1 0x98
72 #define PLLM_MISC2 0x9c
73 #define PLLP_BASE 0xa0
74 #define PLLP_MISC0 0xac
75 #define PLLP_MISC1 0x680
76 #define PLLA_BASE 0xb0
77 #define PLLA_MISC0 0xbc
78 #define PLLA_MISC1 0xb8
79 #define PLLA_MISC2 0x5d8
80 #define PLLD_BASE 0xd0
81 #define PLLD_MISC0 0xdc
82 #define PLLD_MISC1 0xd8
83 #define PLLU_BASE 0xc0
84 #define PLLU_OUTA 0xc4
85 #define PLLU_MISC0 0xcc
86 #define PLLU_MISC1 0xc8
87 #define PLLX_BASE 0xe0
88 #define PLLX_MISC0 0xe4
89 #define PLLX_MISC1 0x510
90 #define PLLX_MISC2 0x514
91 #define PLLX_MISC3 0x518
92 #define PLLX_MISC4 0x5f0
93 #define PLLX_MISC5 0x5f4
94 #define PLLE_BASE 0xe8
95 #define PLLE_MISC0 0xec
96 #define PLLD2_BASE 0x4b8
97 #define PLLD2_MISC0 0x4bc
98 #define PLLD2_MISC1 0x570
99 #define PLLD2_MISC2 0x574
100 #define PLLD2_MISC3 0x578
101 #define PLLE_AUX 0x48c
102 #define PLLRE_BASE 0x4c4
103 #define PLLRE_MISC0 0x4c8
104 #define PLLRE_OUT1 0x4cc
105 #define PLLDP_BASE 0x590
106 #define PLLDP_MISC 0x594
108 #define PLLC4_BASE 0x5a4
109 #define PLLC4_MISC0 0x5a8
110 #define PLLC4_OUT 0x5e4
111 #define PLLMB_BASE 0x5e8
112 #define PLLMB_MISC1 0x5ec
113 #define PLLA1_BASE 0x6a4
114 #define PLLA1_MISC0 0x6a8
115 #define PLLA1_MISC1 0x6ac
116 #define PLLA1_MISC2 0x6b0
117 #define PLLA1_MISC3 0x6b4
119 #define PLLU_IDDQ_BIT 31
120 #define PLLCX_IDDQ_BIT 27
121 #define PLLRE_IDDQ_BIT 24
122 #define PLLA_IDDQ_BIT 25
123 #define PLLD_IDDQ_BIT 20
124 #define PLLSS_IDDQ_BIT 18
125 #define PLLM_IDDQ_BIT 5
126 #define PLLMB_IDDQ_BIT 17
127 #define PLLXP_IDDQ_BIT 3
129 #define PLLCX_RESET_BIT 30
131 #define PLL_BASE_LOCK BIT(27)
132 #define PLLCX_BASE_LOCK BIT(26)
133 #define PLLE_MISC_LOCK BIT(11)
134 #define PLLRE_MISC_LOCK BIT(27)
136 #define PLL_MISC_LOCK_ENABLE 18
137 #define PLLC_MISC_LOCK_ENABLE 24
138 #define PLLDU_MISC_LOCK_ENABLE 22
139 #define PLLU_MISC_LOCK_ENABLE 29
140 #define PLLE_MISC_LOCK_ENABLE 9
141 #define PLLRE_MISC_LOCK_ENABLE 30
142 #define PLLSS_MISC_LOCK_ENABLE 30
143 #define PLLP_MISC_LOCK_ENABLE 18
144 #define PLLM_MISC_LOCK_ENABLE 4
145 #define PLLMB_MISC_LOCK_ENABLE 16
146 #define PLLA_MISC_LOCK_ENABLE 28
147 #define PLLU_MISC_LOCK_ENABLE 29
148 #define PLLD_MISC_LOCK_ENABLE 18
150 #define PLLA_SDM_DIN_MASK 0xffff
151 #define PLLA_SDM_EN_MASK BIT(26)
153 #define PLLD_SDM_EN_MASK BIT(16)
155 #define PLLD2_SDM_EN_MASK BIT(31)
156 #define PLLD2_SSC_EN_MASK 0
158 #define PLLDP_SS_CFG 0x598
159 #define PLLDP_SDM_EN_MASK BIT(31)
160 #define PLLDP_SSC_EN_MASK BIT(30)
161 #define PLLDP_SS_CTRL1 0x59c
162 #define PLLDP_SS_CTRL2 0x5a0
164 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
165 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
167 #define UTMIP_PLL_CFG2 0x488
168 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
169 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
170 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
171 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
172 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
173 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
174 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
175 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
176 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
177 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
179 #define UTMIP_PLL_CFG1 0x484
180 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
181 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
182 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
183 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
184 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
185 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
186 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
188 #define SATA_PLL_CFG0 0x490
189 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
190 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
191 #define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL BIT(4)
192 #define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE BIT(5)
193 #define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6)
194 #define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE BIT(7)
196 #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13)
197 #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
199 #define XUSBIO_PLL_CFG0 0x51c
200 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
201 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2)
202 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6)
203 #define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13)
204 #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
206 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
207 #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31)
208 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
209 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
210 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(7)
211 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
212 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
213 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
214 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
215 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
216 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
218 #define PLLU_HW_PWRDN_CFG0 0x530
219 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
220 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
221 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
222 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
223 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
224 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
226 #define XUSB_PLL_CFG0 0x534
227 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
228 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK (0x3ff << 14)
230 #define SPARE_REG0 0x55c
231 #define CLK_M_DIVISOR_SHIFT 2
232 #define CLK_M_DIVISOR_MASK 0x3
234 #define RST_DFLL_DVCO 0x2f4
235 #define DVFS_DFLL_RESET_SHIFT 0
237 #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
238 #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
240 #define LVL2_CLK_GATE_OVRA 0xf8
241 #define LVL2_CLK_GATE_OVRC 0x3a0
242 #define LVL2_CLK_GATE_OVRD 0x3a4
243 #define LVL2_CLK_GATE_OVRE 0x554
245 /* I2S registers to handle during APE MBIST WAR */
246 #define TEGRA210_I2S_BASE 0x1000
247 #define TEGRA210_I2S_SIZE 0x100
248 #define TEGRA210_I2S_CTRLS 5
249 #define TEGRA210_I2S_CG 0x88
250 #define TEGRA210_I2S_CTRL 0xa0
252 /* DISPA registers to handle during MBIST WAR */
253 #define DC_CMD_DISPLAY_COMMAND 0xc8
254 #define DC_COM_DSC_TOP_CTL 0xcf8
256 /* VIC register to handle during MBIST WAR */
257 #define NV_PVIC_THI_SLCG_OVERRIDE_LOW 0x8c
259 /* APE, DISPA and VIC base addesses needed for MBIST WAR */
260 #define TEGRA210_AHUB_BASE 0x702d0000
261 #define TEGRA210_DISPA_BASE 0x54200000
262 #define TEGRA210_VIC_BASE 0x54340000
265 * SDM fractional divisor is 16-bit 2's complement signed number within
266 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
267 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
268 * indicate that SDM is disabled.
270 * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
272 #define PLL_SDM_COEFF BIT(13)
273 #define sdin_din_to_data(din) ((u16)((din) ? : 0xFFFFU))
274 #define sdin_data_to_din(dat) (((dat) == 0xFFFFU) ? 0 : (s16)dat)
275 /* This macro returns ndiv effective scaled to SDM range */
276 #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \
277 (PLL_SDM_COEFF/2 + sdin_data_to_din((cfg)->sdm_data)) : 0))
279 /* Tegra CPU clock and reset control regs */
280 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
282 #ifdef CONFIG_PM_SLEEP
283 static struct cpu_clk_suspend_context {
285 } tegra210_cpu_clk_sctx;
288 struct tegra210_domain_mbist_war {
289 void (*handle_lvl2_ovr)(struct tegra210_domain_mbist_war *mbist);
290 const u32 lvl2_offset;
292 const unsigned int num_clks;
293 const unsigned int *clk_init_data;
294 struct clk_bulk_data *clks;
297 static struct clk **clks;
299 static void __iomem *clk_base;
300 static void __iomem *pmc_base;
301 static void __iomem *ahub_base;
302 static void __iomem *dispa_base;
303 static void __iomem *vic_base;
305 static unsigned long osc_freq;
306 static unsigned long pll_ref_freq;
308 static DEFINE_SPINLOCK(pll_d_lock);
309 static DEFINE_SPINLOCK(pll_e_lock);
310 static DEFINE_SPINLOCK(pll_re_lock);
311 static DEFINE_SPINLOCK(pll_u_lock);
312 static DEFINE_SPINLOCK(sor1_lock);
313 static DEFINE_SPINLOCK(emc_lock);
314 static DEFINE_MUTEX(lvl2_ovr_lock);
316 /* possible OSC frequencies in Hz */
317 static unsigned long tegra210_input_freq[] = {
322 static const char *mux_pllmcp_clkm[] = {
323 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
326 #define mux_pllmcp_clkm_idx NULL
328 #define PLL_ENABLE (1 << 30)
330 #define PLLCX_MISC1_IDDQ (1 << 27)
331 #define PLLCX_MISC0_RESET (1 << 30)
333 #define PLLCX_MISC0_DEFAULT_VALUE 0x40080000
334 #define PLLCX_MISC0_WRITE_MASK 0x400ffffb
335 #define PLLCX_MISC1_DEFAULT_VALUE 0x08000000
336 #define PLLCX_MISC1_WRITE_MASK 0x08003cff
337 #define PLLCX_MISC2_DEFAULT_VALUE 0x1f720f05
338 #define PLLCX_MISC2_WRITE_MASK 0xffffff17
339 #define PLLCX_MISC3_DEFAULT_VALUE 0x000000c4
340 #define PLLCX_MISC3_WRITE_MASK 0x00ffffff
343 #define PLLA_BASE_IDDQ (1 << 25)
344 #define PLLA_BASE_LOCK (1 << 27)
346 #define PLLA_MISC0_LOCK_ENABLE (1 << 28)
347 #define PLLA_MISC0_LOCK_OVERRIDE (1 << 27)
349 #define PLLA_MISC2_EN_SDM (1 << 26)
350 #define PLLA_MISC2_EN_DYNRAMP (1 << 25)
352 #define PLLA_MISC0_DEFAULT_VALUE 0x12000020
353 #define PLLA_MISC0_WRITE_MASK 0x7fffffff
354 #define PLLA_MISC2_DEFAULT_VALUE 0x0
355 #define PLLA_MISC2_WRITE_MASK 0x06ffffff
358 #define PLLD_BASE_CSI_CLKSOURCE (1 << 23)
360 #define PLLD_MISC0_EN_SDM (1 << 16)
361 #define PLLD_MISC0_LOCK_OVERRIDE (1 << 17)
362 #define PLLD_MISC0_LOCK_ENABLE (1 << 18)
363 #define PLLD_MISC0_IDDQ (1 << 20)
364 #define PLLD_MISC0_DSI_CLKENABLE (1 << 21)
366 #define PLLD_MISC0_DEFAULT_VALUE 0x00140000
367 #define PLLD_MISC0_WRITE_MASK 0x3ff7ffff
368 #define PLLD_MISC1_DEFAULT_VALUE 0x20
369 #define PLLD_MISC1_WRITE_MASK 0x00ffffff
371 /* PLLD2 and PLLDP and PLLC4 */
372 #define PLLDSS_BASE_LOCK (1 << 27)
373 #define PLLDSS_BASE_LOCK_OVERRIDE (1 << 24)
374 #define PLLDSS_BASE_IDDQ (1 << 18)
375 #define PLLDSS_BASE_REF_SEL_SHIFT 25
376 #define PLLDSS_BASE_REF_SEL_MASK (0x3 << PLLDSS_BASE_REF_SEL_SHIFT)
378 #define PLLDSS_MISC0_LOCK_ENABLE (1 << 30)
380 #define PLLDSS_MISC1_CFG_EN_SDM (1 << 31)
381 #define PLLDSS_MISC1_CFG_EN_SSC (1 << 30)
383 #define PLLD2_MISC0_DEFAULT_VALUE 0x40000020
384 #define PLLD2_MISC1_CFG_DEFAULT_VALUE 0x10000000
385 #define PLLD2_MISC2_CTRL1_DEFAULT_VALUE 0x0
386 #define PLLD2_MISC3_CTRL2_DEFAULT_VALUE 0x0
388 #define PLLDP_MISC0_DEFAULT_VALUE 0x40000020
389 #define PLLDP_MISC1_CFG_DEFAULT_VALUE 0xc0000000
390 #define PLLDP_MISC2_CTRL1_DEFAULT_VALUE 0xf400f0da
391 #define PLLDP_MISC3_CTRL2_DEFAULT_VALUE 0x2004f400
393 #define PLLDSS_MISC0_WRITE_MASK 0x47ffffff
394 #define PLLDSS_MISC1_CFG_WRITE_MASK 0xf8000000
395 #define PLLDSS_MISC2_CTRL1_WRITE_MASK 0xffffffff
396 #define PLLDSS_MISC3_CTRL2_WRITE_MASK 0xffffffff
398 #define PLLC4_MISC0_DEFAULT_VALUE 0x40000000
401 #define PLLRE_MISC0_LOCK_ENABLE (1 << 30)
402 #define PLLRE_MISC0_LOCK_OVERRIDE (1 << 29)
403 #define PLLRE_MISC0_LOCK (1 << 27)
404 #define PLLRE_MISC0_IDDQ (1 << 24)
406 #define PLLRE_BASE_DEFAULT_VALUE 0x0
407 #define PLLRE_MISC0_DEFAULT_VALUE 0x41000000
409 #define PLLRE_BASE_DEFAULT_MASK 0x1c000000
410 #define PLLRE_MISC0_WRITE_MASK 0x67ffffff
413 #define PLLX_USE_DYN_RAMP 1
414 #define PLLX_BASE_LOCK (1 << 27)
416 #define PLLX_MISC0_FO_G_DISABLE (0x1 << 28)
417 #define PLLX_MISC0_LOCK_ENABLE (0x1 << 18)
419 #define PLLX_MISC2_DYNRAMP_STEPB_SHIFT 24
420 #define PLLX_MISC2_DYNRAMP_STEPB_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPB_SHIFT)
421 #define PLLX_MISC2_DYNRAMP_STEPA_SHIFT 16
422 #define PLLX_MISC2_DYNRAMP_STEPA_MASK (0xFF << PLLX_MISC2_DYNRAMP_STEPA_SHIFT)
423 #define PLLX_MISC2_NDIV_NEW_SHIFT 8
424 #define PLLX_MISC2_NDIV_NEW_MASK (0xFF << PLLX_MISC2_NDIV_NEW_SHIFT)
425 #define PLLX_MISC2_LOCK_OVERRIDE (0x1 << 4)
426 #define PLLX_MISC2_DYNRAMP_DONE (0x1 << 2)
427 #define PLLX_MISC2_EN_DYNRAMP (0x1 << 0)
429 #define PLLX_MISC3_IDDQ (0x1 << 3)
431 #define PLLX_MISC0_DEFAULT_VALUE PLLX_MISC0_LOCK_ENABLE
432 #define PLLX_MISC0_WRITE_MASK 0x10c40000
433 #define PLLX_MISC1_DEFAULT_VALUE 0x20
434 #define PLLX_MISC1_WRITE_MASK 0x00ffffff
435 #define PLLX_MISC2_DEFAULT_VALUE 0x0
436 #define PLLX_MISC2_WRITE_MASK 0xffffff11
437 #define PLLX_MISC3_DEFAULT_VALUE PLLX_MISC3_IDDQ
438 #define PLLX_MISC3_WRITE_MASK 0x01ff0f0f
439 #define PLLX_MISC4_DEFAULT_VALUE 0x0
440 #define PLLX_MISC4_WRITE_MASK 0x8000ffff
441 #define PLLX_MISC5_DEFAULT_VALUE 0x0
442 #define PLLX_MISC5_WRITE_MASK 0x0000ffff
444 #define PLLX_HW_CTRL_CFG 0x548
445 #define PLLX_HW_CTRL_CFG_SWCTRL (0x1 << 0)
448 #define PLLMB_BASE_LOCK (1 << 27)
450 #define PLLMB_MISC1_LOCK_OVERRIDE (1 << 18)
451 #define PLLMB_MISC1_IDDQ (1 << 17)
452 #define PLLMB_MISC1_LOCK_ENABLE (1 << 16)
454 #define PLLMB_MISC1_DEFAULT_VALUE 0x00030000
455 #define PLLMB_MISC1_WRITE_MASK 0x0007ffff
458 #define PLLP_BASE_OVERRIDE (1 << 28)
459 #define PLLP_BASE_LOCK (1 << 27)
461 #define PLLP_MISC0_LOCK_ENABLE (1 << 18)
462 #define PLLP_MISC0_LOCK_OVERRIDE (1 << 17)
463 #define PLLP_MISC0_IDDQ (1 << 3)
465 #define PLLP_MISC1_HSIO_EN_SHIFT 29
466 #define PLLP_MISC1_HSIO_EN (1 << PLLP_MISC1_HSIO_EN_SHIFT)
467 #define PLLP_MISC1_XUSB_EN_SHIFT 28
468 #define PLLP_MISC1_XUSB_EN (1 << PLLP_MISC1_XUSB_EN_SHIFT)
470 #define PLLP_MISC0_DEFAULT_VALUE 0x00040008
471 #define PLLP_MISC1_DEFAULT_VALUE 0x0
473 #define PLLP_MISC0_WRITE_MASK 0xdc6000f
474 #define PLLP_MISC1_WRITE_MASK 0x70ffffff
477 #define PLLU_BASE_LOCK (1 << 27)
478 #define PLLU_BASE_OVERRIDE (1 << 24)
479 #define PLLU_BASE_CLKENABLE_USB (1 << 21)
480 #define PLLU_BASE_CLKENABLE_HSIC (1 << 22)
481 #define PLLU_BASE_CLKENABLE_ICUSB (1 << 23)
482 #define PLLU_BASE_CLKENABLE_48M (1 << 25)
483 #define PLLU_BASE_CLKENABLE_ALL (PLLU_BASE_CLKENABLE_USB |\
484 PLLU_BASE_CLKENABLE_HSIC |\
485 PLLU_BASE_CLKENABLE_ICUSB |\
486 PLLU_BASE_CLKENABLE_48M)
488 #define PLLU_MISC0_IDDQ (1 << 31)
489 #define PLLU_MISC0_LOCK_ENABLE (1 << 29)
490 #define PLLU_MISC1_LOCK_OVERRIDE (1 << 0)
492 #define PLLU_MISC0_DEFAULT_VALUE 0xa0000000
493 #define PLLU_MISC1_DEFAULT_VALUE 0x0
495 #define PLLU_MISC0_WRITE_MASK 0xbfffffff
496 #define PLLU_MISC1_WRITE_MASK 0x00000007
498 void tegra210_xusb_pll_hw_control_enable(void)
502 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
503 val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
504 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
505 val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
506 XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
507 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
509 EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_control_enable);
511 void tegra210_xusb_pll_hw_sequence_start(void)
515 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
516 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
517 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
519 EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_sequence_start);
521 void tegra210_sata_pll_hw_control_enable(void)
525 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
526 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
527 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET |
528 SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ;
529 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
531 EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_control_enable);
533 void tegra210_sata_pll_hw_sequence_start(void)
537 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
538 val |= SATA_PLL_CFG0_SEQ_ENABLE;
539 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
541 EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start);
543 void tegra210_set_sata_pll_seq_sw(bool state)
547 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
549 val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
550 val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
551 val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
552 val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
554 val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
555 val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
556 val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
557 val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
559 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
561 EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw);
563 static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist)
567 val = readl_relaxed(clk_base + mbist->lvl2_offset);
568 writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset);
569 fence_udelay(1, clk_base);
570 writel_relaxed(val, clk_base + mbist->lvl2_offset);
571 fence_udelay(1, clk_base);
574 static void tegra210_venc_mbist_war(struct tegra210_domain_mbist_war *mbist)
576 u32 csi_src, ovra, ovre;
577 unsigned long flags = 0;
579 spin_lock_irqsave(&pll_d_lock, flags);
581 csi_src = readl_relaxed(clk_base + PLLD_BASE);
582 writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE);
583 fence_udelay(1, clk_base);
585 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
586 writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA);
587 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
588 writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE);
589 fence_udelay(1, clk_base);
591 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
592 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
593 writel_relaxed(csi_src, clk_base + PLLD_BASE);
594 fence_udelay(1, clk_base);
596 spin_unlock_irqrestore(&pll_d_lock, flags);
599 static void tegra210_disp_mbist_war(struct tegra210_domain_mbist_war *mbist)
601 u32 ovra, dsc_top_ctrl;
603 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
604 writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA);
605 fence_udelay(1, clk_base);
607 dsc_top_ctrl = readl_relaxed(dispa_base + DC_COM_DSC_TOP_CTL);
608 writel_relaxed(dsc_top_ctrl | BIT(2), dispa_base + DC_COM_DSC_TOP_CTL);
609 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
610 writel_relaxed(dsc_top_ctrl, dispa_base + DC_COM_DSC_TOP_CTL);
611 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
613 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA);
614 fence_udelay(1, clk_base);
617 static void tegra210_vic_mbist_war(struct tegra210_domain_mbist_war *mbist)
621 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
622 writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE);
623 fence_udelay(1, clk_base);
625 val = readl_relaxed(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
626 writel_relaxed(val | BIT(0) | GENMASK(7, 2) | BIT(24),
627 vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
628 fence_udelay(1, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
630 writel_relaxed(val, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
631 readl(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
633 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
634 fence_udelay(1, clk_base);
637 static void tegra210_ape_mbist_war(struct tegra210_domain_mbist_war *mbist)
639 void __iomem *i2s_base;
643 ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC);
644 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
645 writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC);
646 writel_relaxed(ovre | BIT(10) | BIT(11),
647 clk_base + LVL2_CLK_GATE_OVRE);
648 fence_udelay(1, clk_base);
650 i2s_base = ahub_base + TEGRA210_I2S_BASE;
652 for (i = 0; i < TEGRA210_I2S_CTRLS; i++) {
655 i2s_ctrl = readl_relaxed(i2s_base + TEGRA210_I2S_CTRL);
656 writel_relaxed(i2s_ctrl | BIT(10),
657 i2s_base + TEGRA210_I2S_CTRL);
658 writel_relaxed(0, i2s_base + TEGRA210_I2S_CG);
659 readl(i2s_base + TEGRA210_I2S_CG);
660 writel_relaxed(1, i2s_base + TEGRA210_I2S_CG);
661 writel_relaxed(i2s_ctrl, i2s_base + TEGRA210_I2S_CTRL);
662 readl(i2s_base + TEGRA210_I2S_CTRL);
664 i2s_base += TEGRA210_I2S_SIZE;
667 writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC);
668 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE);
669 fence_udelay(1, clk_base);
672 static inline void _pll_misc_chk_default(void __iomem *base,
673 struct tegra_clk_pll_params *params,
674 u8 misc_num, u32 default_val, u32 mask)
676 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]);
680 if (boot_val != default_val) {
681 pr_warn("boot misc%d 0x%x: expected 0x%x\n",
682 misc_num, boot_val, default_val);
683 pr_warn(" (comparison mask = 0x%x)\n", mask);
684 params->defaults_set = false;
689 * PLLCX: PLLC, PLLC2, PLLC3, PLLA1
690 * Hybrid PLLs with dynamic ramp. Dynamic ramp is allowed for any transition
691 * that changes NDIV only, while PLL is already locked.
693 static void pllcx_check_defaults(struct tegra_clk_pll_params *params)
697 default_val = PLLCX_MISC0_DEFAULT_VALUE & (~PLLCX_MISC0_RESET);
698 _pll_misc_chk_default(clk_base, params, 0, default_val,
699 PLLCX_MISC0_WRITE_MASK);
701 default_val = PLLCX_MISC1_DEFAULT_VALUE & (~PLLCX_MISC1_IDDQ);
702 _pll_misc_chk_default(clk_base, params, 1, default_val,
703 PLLCX_MISC1_WRITE_MASK);
705 default_val = PLLCX_MISC2_DEFAULT_VALUE;
706 _pll_misc_chk_default(clk_base, params, 2, default_val,
707 PLLCX_MISC2_WRITE_MASK);
709 default_val = PLLCX_MISC3_DEFAULT_VALUE;
710 _pll_misc_chk_default(clk_base, params, 3, default_val,
711 PLLCX_MISC3_WRITE_MASK);
714 static void tegra210_pllcx_set_defaults(const char *name,
715 struct tegra_clk_pll *pllcx)
717 pllcx->params->defaults_set = true;
719 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {
720 /* PLL is ON: only check if defaults already set */
721 pllcx_check_defaults(pllcx->params);
722 if (!pllcx->params->defaults_set)
723 pr_warn("%s already enabled. Postponing set full defaults\n",
728 /* Defaults assert PLL reset, and set IDDQ */
729 writel_relaxed(PLLCX_MISC0_DEFAULT_VALUE,
730 clk_base + pllcx->params->ext_misc_reg[0]);
731 writel_relaxed(PLLCX_MISC1_DEFAULT_VALUE,
732 clk_base + pllcx->params->ext_misc_reg[1]);
733 writel_relaxed(PLLCX_MISC2_DEFAULT_VALUE,
734 clk_base + pllcx->params->ext_misc_reg[2]);
735 writel_relaxed(PLLCX_MISC3_DEFAULT_VALUE,
736 clk_base + pllcx->params->ext_misc_reg[3]);
740 static void _pllc_set_defaults(struct tegra_clk_pll *pllcx)
742 tegra210_pllcx_set_defaults("PLL_C", pllcx);
745 static void _pllc2_set_defaults(struct tegra_clk_pll *pllcx)
747 tegra210_pllcx_set_defaults("PLL_C2", pllcx);
750 static void _pllc3_set_defaults(struct tegra_clk_pll *pllcx)
752 tegra210_pllcx_set_defaults("PLL_C3", pllcx);
755 static void _plla1_set_defaults(struct tegra_clk_pll *pllcx)
757 tegra210_pllcx_set_defaults("PLL_A1", pllcx);
762 * PLL with dynamic ramp and fractional SDM. Dynamic ramp is not used.
763 * Fractional SDM is allowed to provide exact audio rates.
765 static void tegra210_plla_set_defaults(struct tegra_clk_pll *plla)
768 u32 val = readl_relaxed(clk_base + plla->params->base_reg);
770 plla->params->defaults_set = true;
772 if (val & PLL_ENABLE) {
774 * PLL is ON: check if defaults already set, then set those
775 * that can be updated in flight.
777 if (val & PLLA_BASE_IDDQ) {
778 pr_warn("PLL_A boot enabled with IDDQ set\n");
779 plla->params->defaults_set = false;
782 pr_warn("PLL_A already enabled. Postponing set full defaults\n");
784 val = PLLA_MISC0_DEFAULT_VALUE; /* ignore lock enable */
785 mask = PLLA_MISC0_LOCK_ENABLE | PLLA_MISC0_LOCK_OVERRIDE;
786 _pll_misc_chk_default(clk_base, plla->params, 0, val,
787 ~mask & PLLA_MISC0_WRITE_MASK);
789 val = PLLA_MISC2_DEFAULT_VALUE; /* ignore all but control bit */
790 _pll_misc_chk_default(clk_base, plla->params, 2, val,
791 PLLA_MISC2_EN_DYNRAMP);
793 /* Enable lock detect */
794 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);
796 val |= PLLA_MISC0_DEFAULT_VALUE & mask;
797 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]);
803 /* set IDDQ, enable lock detect, disable dynamic ramp and SDM */
804 val |= PLLA_BASE_IDDQ;
805 writel_relaxed(val, clk_base + plla->params->base_reg);
806 writel_relaxed(PLLA_MISC0_DEFAULT_VALUE,
807 clk_base + plla->params->ext_misc_reg[0]);
808 writel_relaxed(PLLA_MISC2_DEFAULT_VALUE,
809 clk_base + plla->params->ext_misc_reg[2]);
815 * PLL with fractional SDM.
817 static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
822 plld->params->defaults_set = true;
824 if (readl_relaxed(clk_base + plld->params->base_reg) &
828 * PLL is ON: check if defaults already set, then set those
829 * that can be updated in flight.
831 val = PLLD_MISC1_DEFAULT_VALUE;
832 _pll_misc_chk_default(clk_base, plld->params, 1,
833 val, PLLD_MISC1_WRITE_MASK);
835 /* ignore lock, DSI and SDM controls, make sure IDDQ not set */
836 val = PLLD_MISC0_DEFAULT_VALUE & (~PLLD_MISC0_IDDQ);
837 mask |= PLLD_MISC0_DSI_CLKENABLE | PLLD_MISC0_LOCK_ENABLE |
838 PLLD_MISC0_LOCK_OVERRIDE | PLLD_MISC0_EN_SDM;
839 _pll_misc_chk_default(clk_base, plld->params, 0, val,
840 ~mask & PLLD_MISC0_WRITE_MASK);
842 if (!plld->params->defaults_set)
843 pr_warn("PLL_D already enabled. Postponing set full defaults\n");
845 /* Enable lock detect */
846 mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE;
847 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
849 val |= PLLD_MISC0_DEFAULT_VALUE & mask;
850 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
856 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
857 val &= PLLD_MISC0_DSI_CLKENABLE;
858 val |= PLLD_MISC0_DEFAULT_VALUE;
859 /* set IDDQ, enable lock detect, disable SDM */
860 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]);
861 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base +
862 plld->params->ext_misc_reg[1]);
868 * PLL with fractional SDM and Spread Spectrum (SDM is a must if SSC is used).
870 static void plldss_defaults(const char *pll_name, struct tegra_clk_pll *plldss,
871 u32 misc0_val, u32 misc1_val, u32 misc2_val, u32 misc3_val)
874 u32 val = readl_relaxed(clk_base + plldss->params->base_reg);
876 plldss->params->defaults_set = true;
878 if (val & PLL_ENABLE) {
881 * PLL is ON: check if defaults already set, then set those
882 * that can be updated in flight.
884 if (val & PLLDSS_BASE_IDDQ) {
885 pr_warn("plldss boot enabled with IDDQ set\n");
886 plldss->params->defaults_set = false;
889 /* ignore lock enable */
890 default_val = misc0_val;
891 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val,
892 PLLDSS_MISC0_WRITE_MASK &
893 (~PLLDSS_MISC0_LOCK_ENABLE));
896 * If SSC is used, check all settings, otherwise just confirm
897 * that SSC is not used on boot as well. Do nothing when using
898 * this function for PLLC4 that has only MISC0.
900 if (plldss->params->ssc_ctrl_en_mask) {
901 default_val = misc1_val;
902 _pll_misc_chk_default(clk_base, plldss->params, 1,
903 default_val, PLLDSS_MISC1_CFG_WRITE_MASK);
904 default_val = misc2_val;
905 _pll_misc_chk_default(clk_base, plldss->params, 2,
906 default_val, PLLDSS_MISC2_CTRL1_WRITE_MASK);
907 default_val = misc3_val;
908 _pll_misc_chk_default(clk_base, plldss->params, 3,
909 default_val, PLLDSS_MISC3_CTRL2_WRITE_MASK);
910 } else if (plldss->params->ext_misc_reg[1]) {
911 default_val = misc1_val;
912 _pll_misc_chk_default(clk_base, plldss->params, 1,
913 default_val, PLLDSS_MISC1_CFG_WRITE_MASK &
914 (~PLLDSS_MISC1_CFG_EN_SDM));
917 if (!plldss->params->defaults_set)
918 pr_warn("%s already enabled. Postponing set full defaults\n",
921 /* Enable lock detect */
922 if (val & PLLDSS_BASE_LOCK_OVERRIDE) {
923 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
924 writel_relaxed(val, clk_base +
925 plldss->params->base_reg);
928 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);
929 val &= ~PLLDSS_MISC0_LOCK_ENABLE;
930 val |= misc0_val & PLLDSS_MISC0_LOCK_ENABLE;
931 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]);
937 /* set IDDQ, enable lock detect, configure SDM/SSC */
938 val |= PLLDSS_BASE_IDDQ;
939 val &= ~PLLDSS_BASE_LOCK_OVERRIDE;
940 writel_relaxed(val, clk_base + plldss->params->base_reg);
942 /* When using this function for PLLC4 exit here */
943 if (!plldss->params->ext_misc_reg[1]) {
944 writel_relaxed(misc0_val, clk_base +
945 plldss->params->ext_misc_reg[0]);
950 writel_relaxed(misc0_val, clk_base +
951 plldss->params->ext_misc_reg[0]);
952 /* if SSC used set by 1st enable */
953 writel_relaxed(misc1_val & (~PLLDSS_MISC1_CFG_EN_SSC),
954 clk_base + plldss->params->ext_misc_reg[1]);
955 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]);
956 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]);
960 static void tegra210_plld2_set_defaults(struct tegra_clk_pll *plld2)
962 plldss_defaults("PLL_D2", plld2, PLLD2_MISC0_DEFAULT_VALUE,
963 PLLD2_MISC1_CFG_DEFAULT_VALUE,
964 PLLD2_MISC2_CTRL1_DEFAULT_VALUE,
965 PLLD2_MISC3_CTRL2_DEFAULT_VALUE);
968 static void tegra210_plldp_set_defaults(struct tegra_clk_pll *plldp)
970 plldss_defaults("PLL_DP", plldp, PLLDP_MISC0_DEFAULT_VALUE,
971 PLLDP_MISC1_CFG_DEFAULT_VALUE,
972 PLLDP_MISC2_CTRL1_DEFAULT_VALUE,
973 PLLDP_MISC3_CTRL2_DEFAULT_VALUE);
978 * Base and misc0 layout is the same as PLLD2/PLLDP, but no SDM/SSC support.
979 * VCO is exposed to the clock tree via fixed 1/3 and 1/5 dividers.
981 static void tegra210_pllc4_set_defaults(struct tegra_clk_pll *pllc4)
983 plldss_defaults("PLL_C4", pllc4, PLLC4_MISC0_DEFAULT_VALUE, 0, 0, 0);
988 * VCO is exposed to the clock tree directly along with post-divider output
990 static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
993 u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
995 pllre->params->defaults_set = true;
997 if (val & PLL_ENABLE) {
998 pr_warn("PLL_RE already enabled. Postponing set full defaults\n");
1001 * PLL is ON: check if defaults already set, then set those
1002 * that can be updated in flight.
1004 val &= PLLRE_BASE_DEFAULT_MASK;
1005 if (val != PLLRE_BASE_DEFAULT_VALUE) {
1006 pr_warn("pllre boot base 0x%x : expected 0x%x\n",
1007 val, PLLRE_BASE_DEFAULT_VALUE);
1008 pr_warn("(comparison mask = 0x%x)\n",
1009 PLLRE_BASE_DEFAULT_MASK);
1010 pllre->params->defaults_set = false;
1013 /* Ignore lock enable */
1014 val = PLLRE_MISC0_DEFAULT_VALUE & (~PLLRE_MISC0_IDDQ);
1015 mask = PLLRE_MISC0_LOCK_ENABLE | PLLRE_MISC0_LOCK_OVERRIDE;
1016 _pll_misc_chk_default(clk_base, pllre->params, 0, val,
1017 ~mask & PLLRE_MISC0_WRITE_MASK);
1019 /* Enable lock detect */
1020 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
1022 val |= PLLRE_MISC0_DEFAULT_VALUE & mask;
1023 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);
1029 /* set IDDQ, enable lock detect */
1030 val &= ~PLLRE_BASE_DEFAULT_MASK;
1031 val |= PLLRE_BASE_DEFAULT_VALUE & PLLRE_BASE_DEFAULT_MASK;
1032 writel_relaxed(val, clk_base + pllre->params->base_reg);
1033 writel_relaxed(PLLRE_MISC0_DEFAULT_VALUE,
1034 clk_base + pllre->params->ext_misc_reg[0]);
1038 static void pllx_get_dyn_steps(struct clk_hw *hw, u32 *step_a, u32 *step_b)
1040 unsigned long input_rate;
1043 if (!IS_ERR_OR_NULL(hw->clk))
1044 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1046 input_rate = 38400000;
1048 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
1050 switch (input_rate) {
1066 pr_err("%s: Unexpected reference rate %lu\n",
1067 __func__, input_rate);
1072 static void pllx_check_defaults(struct tegra_clk_pll *pll)
1076 default_val = PLLX_MISC0_DEFAULT_VALUE;
1077 /* ignore lock enable */
1078 _pll_misc_chk_default(clk_base, pll->params, 0, default_val,
1079 PLLX_MISC0_WRITE_MASK & (~PLLX_MISC0_LOCK_ENABLE));
1081 default_val = PLLX_MISC1_DEFAULT_VALUE;
1082 _pll_misc_chk_default(clk_base, pll->params, 1, default_val,
1083 PLLX_MISC1_WRITE_MASK);
1085 /* ignore all but control bit */
1086 default_val = PLLX_MISC2_DEFAULT_VALUE;
1087 _pll_misc_chk_default(clk_base, pll->params, 2,
1088 default_val, PLLX_MISC2_EN_DYNRAMP);
1090 default_val = PLLX_MISC3_DEFAULT_VALUE & (~PLLX_MISC3_IDDQ);
1091 _pll_misc_chk_default(clk_base, pll->params, 3, default_val,
1092 PLLX_MISC3_WRITE_MASK);
1094 default_val = PLLX_MISC4_DEFAULT_VALUE;
1095 _pll_misc_chk_default(clk_base, pll->params, 4, default_val,
1096 PLLX_MISC4_WRITE_MASK);
1098 default_val = PLLX_MISC5_DEFAULT_VALUE;
1099 _pll_misc_chk_default(clk_base, pll->params, 5, default_val,
1100 PLLX_MISC5_WRITE_MASK);
1103 static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
1108 pllx->params->defaults_set = true;
1110 /* Get ready dyn ramp state machine settings */
1111 pllx_get_dyn_steps(&pllx->hw, &step_a, &step_b);
1112 val = PLLX_MISC2_DEFAULT_VALUE & (~PLLX_MISC2_DYNRAMP_STEPA_MASK) &
1113 (~PLLX_MISC2_DYNRAMP_STEPB_MASK);
1114 val |= step_a << PLLX_MISC2_DYNRAMP_STEPA_SHIFT;
1115 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
1117 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
1120 * PLL is ON: check if defaults already set, then set those
1121 * that can be updated in flight.
1123 pllx_check_defaults(pllx);
1125 if (!pllx->params->defaults_set)
1126 pr_warn("PLL_X already enabled. Postponing set full defaults\n");
1127 /* Configure dyn ramp, disable lock override */
1128 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1130 /* Enable lock detect */
1131 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);
1132 val &= ~PLLX_MISC0_LOCK_ENABLE;
1133 val |= PLLX_MISC0_DEFAULT_VALUE & PLLX_MISC0_LOCK_ENABLE;
1134 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]);
1140 /* Enable lock detect and CPU output */
1141 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base +
1142 pllx->params->ext_misc_reg[0]);
1145 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base +
1146 pllx->params->ext_misc_reg[1]);
1148 /* Configure dyn ramp state machine, disable lock override */
1149 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1152 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base +
1153 pllx->params->ext_misc_reg[3]);
1156 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base +
1157 pllx->params->ext_misc_reg[4]);
1158 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base +
1159 pllx->params->ext_misc_reg[5]);
1164 static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
1166 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
1168 pllmb->params->defaults_set = true;
1170 if (val & PLL_ENABLE) {
1173 * PLL is ON: check if defaults already set, then set those
1174 * that can be updated in flight.
1176 val = PLLMB_MISC1_DEFAULT_VALUE & (~PLLMB_MISC1_IDDQ);
1177 mask = PLLMB_MISC1_LOCK_ENABLE | PLLMB_MISC1_LOCK_OVERRIDE;
1178 _pll_misc_chk_default(clk_base, pllmb->params, 0, val,
1179 ~mask & PLLMB_MISC1_WRITE_MASK);
1181 if (!pllmb->params->defaults_set)
1182 pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
1183 /* Enable lock detect */
1184 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
1186 val |= PLLMB_MISC1_DEFAULT_VALUE & mask;
1187 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]);
1193 /* set IDDQ, enable lock detect */
1194 writel_relaxed(PLLMB_MISC1_DEFAULT_VALUE,
1195 clk_base + pllmb->params->ext_misc_reg[0]);
1201 * VCO is exposed to the clock tree directly along with post-divider output.
1202 * Both VCO and post-divider output rates are fixed at 408MHz and 204MHz,
1205 static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled)
1209 /* Ignore lock enable (will be set), make sure not in IDDQ if enabled */
1210 val = PLLP_MISC0_DEFAULT_VALUE & (~PLLP_MISC0_IDDQ);
1211 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
1213 mask |= PLLP_MISC0_IDDQ;
1214 _pll_misc_chk_default(clk_base, pll->params, 0, val,
1215 ~mask & PLLP_MISC0_WRITE_MASK);
1217 /* Ignore branch controls */
1218 val = PLLP_MISC1_DEFAULT_VALUE;
1219 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
1220 _pll_misc_chk_default(clk_base, pll->params, 1, val,
1221 ~mask & PLLP_MISC1_WRITE_MASK);
1224 static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
1227 u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
1229 pllp->params->defaults_set = true;
1231 if (val & PLL_ENABLE) {
1234 * PLL is ON: check if defaults already set, then set those
1235 * that can be updated in flight.
1237 pllp_check_defaults(pllp, true);
1238 if (!pllp->params->defaults_set)
1239 pr_warn("PLL_P already enabled. Postponing set full defaults\n");
1241 /* Enable lock detect */
1242 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
1243 mask = PLLP_MISC0_LOCK_ENABLE | PLLP_MISC0_LOCK_OVERRIDE;
1245 val |= PLLP_MISC0_DEFAULT_VALUE & mask;
1246 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]);
1252 /* set IDDQ, enable lock detect */
1253 writel_relaxed(PLLP_MISC0_DEFAULT_VALUE,
1254 clk_base + pllp->params->ext_misc_reg[0]);
1256 /* Preserve branch control */
1257 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);
1258 mask = PLLP_MISC1_HSIO_EN | PLLP_MISC1_XUSB_EN;
1260 val |= ~mask & PLLP_MISC1_DEFAULT_VALUE;
1261 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]);
1267 * VCO is exposed to the clock tree directly along with post-divider output.
1268 * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz,
1271 static void pllu_check_defaults(struct tegra_clk_pll_params *params,
1276 /* Ignore lock enable (will be set) and IDDQ if under h/w control */
1277 val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ);
1278 mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0);
1279 _pll_misc_chk_default(clk_base, params, 0, val,
1280 ~mask & PLLU_MISC0_WRITE_MASK);
1282 val = PLLU_MISC1_DEFAULT_VALUE;
1283 mask = PLLU_MISC1_LOCK_OVERRIDE;
1284 _pll_misc_chk_default(clk_base, params, 1, val,
1285 ~mask & PLLU_MISC1_WRITE_MASK);
1288 static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu)
1290 u32 val = readl_relaxed(clk_base + pllu->base_reg);
1292 pllu->defaults_set = true;
1294 if (val & PLL_ENABLE) {
1297 * PLL is ON: check if defaults already set, then set those
1298 * that can be updated in flight.
1300 pllu_check_defaults(pllu, false);
1301 if (!pllu->defaults_set)
1302 pr_warn("PLL_U already enabled. Postponing set full defaults\n");
1304 /* Enable lock detect */
1305 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]);
1306 val &= ~PLLU_MISC0_LOCK_ENABLE;
1307 val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE;
1308 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]);
1310 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]);
1311 val &= ~PLLU_MISC1_LOCK_OVERRIDE;
1312 val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE;
1313 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]);
1319 /* set IDDQ, enable lock detect */
1320 writel_relaxed(PLLU_MISC0_DEFAULT_VALUE,
1321 clk_base + pllu->ext_misc_reg[0]);
1322 writel_relaxed(PLLU_MISC1_DEFAULT_VALUE,
1323 clk_base + pllu->ext_misc_reg[1]);
1327 #define mask(w) ((1 << (w)) - 1)
1328 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
1329 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
1330 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
1331 mask(p->params->div_nmp->divp_width))
1333 #define divm_shift(p) ((p)->params->div_nmp->divm_shift)
1334 #define divn_shift(p) ((p)->params->div_nmp->divn_shift)
1335 #define divp_shift(p) ((p)->params->div_nmp->divp_shift)
1337 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
1338 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
1339 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
1341 #define PLL_LOCKDET_DELAY 2 /* Lock detection safety delays */
1342 static int tegra210_wait_for_mask(struct tegra_clk_pll *pll,
1348 for (i = 0; i < pll->params->lock_delay / PLL_LOCKDET_DELAY + 1; i++) {
1349 udelay(PLL_LOCKDET_DELAY);
1350 val = readl_relaxed(clk_base + reg);
1351 if ((val & mask) == mask) {
1352 udelay(PLL_LOCKDET_DELAY);
1359 static int tegra210_pllx_dyn_ramp(struct tegra_clk_pll *pllx,
1360 struct tegra_clk_pll_freq_table *cfg)
1362 u32 val, base, ndiv_new_mask;
1364 ndiv_new_mask = (divn_mask(pllx) >> pllx->params->div_nmp->divn_shift)
1365 << PLLX_MISC2_NDIV_NEW_SHIFT;
1367 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1368 val &= (~ndiv_new_mask);
1369 val |= cfg->n << PLLX_MISC2_NDIV_NEW_SHIFT;
1370 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1373 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1374 val |= PLLX_MISC2_EN_DYNRAMP;
1375 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1378 tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2],
1379 PLLX_MISC2_DYNRAMP_DONE);
1381 base = readl_relaxed(clk_base + pllx->params->base_reg) &
1382 (~divn_mask_shifted(pllx));
1383 base |= cfg->n << pllx->params->div_nmp->divn_shift;
1384 writel_relaxed(base, clk_base + pllx->params->base_reg);
1387 val &= ~PLLX_MISC2_EN_DYNRAMP;
1388 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
1391 pr_debug("%s: dynamic ramp to m = %u n = %u p = %u, Fout = %lu kHz\n",
1392 __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p,
1393 cfg->input_rate / cfg->m * cfg->n /
1394 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000);
1400 * Common configuration for PLLs with fixed input divider policy:
1401 * - always set fixed M-value based on the reference rate
1402 * - always set P-value value 1:1 for output rates above VCO minimum, and
1403 * choose minimum necessary P-value for output rates below VCO maximum
1404 * - calculate N-value based on selected M and P
1405 * - calculate SDM_DIN fractional part
1407 static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,
1408 struct tegra_clk_pll_freq_table *cfg,
1409 unsigned long rate, unsigned long input_rate)
1411 struct tegra_clk_pll *pll = to_clk_pll(hw);
1412 struct tegra_clk_pll_params *params = pll->params;
1414 unsigned long cf, p_rate;
1420 if (!(params->flags & TEGRA_PLL_VCO_OUT)) {
1421 p = DIV_ROUND_UP(params->vco_min, rate);
1422 p = params->round_p_to_pdiv(p, &pdiv);
1424 p = rate >= params->vco_min ? 1 : -EINVAL;
1430 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate);
1433 /* Store P as HW value, as that is what is expected */
1434 cfg->p = tegra_pll_p_div_to_hw(pll, cfg->p);
1437 if (p_rate > params->vco_max)
1438 p_rate = params->vco_max;
1439 cf = input_rate / cfg->m;
1440 cfg->n = p_rate / cf;
1443 cfg->output_rate = input_rate;
1444 if (params->sdm_ctrl_reg) {
1445 unsigned long rem = p_rate - cf * cfg->n;
1446 /* If ssc is enabled SDM enabled as well, even for integer n */
1447 if (rem || params->ssc_ctrl_reg) {
1448 u64 s = rem * PLL_SDM_COEFF;
1451 s -= PLL_SDM_COEFF / 2;
1452 cfg->sdm_data = sdin_din_to_data(s);
1454 cfg->output_rate *= sdin_get_n_eff(cfg);
1455 cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF;
1457 cfg->output_rate *= cfg->n;
1458 cfg->output_rate /= p * cfg->m;
1461 cfg->input_rate = input_rate;
1467 * clk_pll_set_gain - set gain to m, n to calculate correct VCO rate
1469 * @cfg: struct tegra_clk_pll_freq_table * cfg
1472 * Fvco = Fref * NDIV / MDIV
1474 * For fractional mode:
1475 * Fvco = Fref * (NDIV + 0.5 + SDM_DIN / PLL_SDM_COEFF) / MDIV
1477 static void tegra210_clk_pll_set_gain(struct tegra_clk_pll_freq_table *cfg)
1479 cfg->n = sdin_get_n_eff(cfg);
1480 cfg->m *= PLL_SDM_COEFF;
1483 static unsigned long
1484 tegra210_clk_adjust_vco_min(struct tegra_clk_pll_params *params,
1485 unsigned long parent_rate)
1487 unsigned long vco_min = params->vco_min;
1489 params->vco_min += DIV_ROUND_UP(parent_rate, PLL_SDM_COEFF);
1490 vco_min = min(vco_min, params->vco_min);
1495 static struct div_nmp pllx_nmp = {
1504 * PLL post divider maps - two types: quasi-linear and exponential
1507 #define PLL_QLIN_PDIV_MAX 16
1508 static const struct pdiv_map pll_qlin_pdiv_to_hw[] = {
1509 { .pdiv = 1, .hw_val = 0 },
1510 { .pdiv = 2, .hw_val = 1 },
1511 { .pdiv = 3, .hw_val = 2 },
1512 { .pdiv = 4, .hw_val = 3 },
1513 { .pdiv = 5, .hw_val = 4 },
1514 { .pdiv = 6, .hw_val = 5 },
1515 { .pdiv = 8, .hw_val = 6 },
1516 { .pdiv = 9, .hw_val = 7 },
1517 { .pdiv = 10, .hw_val = 8 },
1518 { .pdiv = 12, .hw_val = 9 },
1519 { .pdiv = 15, .hw_val = 10 },
1520 { .pdiv = 16, .hw_val = 11 },
1521 { .pdiv = 18, .hw_val = 12 },
1522 { .pdiv = 20, .hw_val = 13 },
1523 { .pdiv = 24, .hw_val = 14 },
1524 { .pdiv = 30, .hw_val = 15 },
1525 { .pdiv = 32, .hw_val = 16 },
1528 static u32 pll_qlin_p_to_pdiv(u32 p, u32 *pdiv)
1533 for (i = 0; i <= PLL_QLIN_PDIV_MAX; i++) {
1534 if (p <= pll_qlin_pdiv_to_hw[i].pdiv) {
1537 return pll_qlin_pdiv_to_hw[i].pdiv;
1545 #define PLL_EXPO_PDIV_MAX 7
1546 static const struct pdiv_map pll_expo_pdiv_to_hw[] = {
1547 { .pdiv = 1, .hw_val = 0 },
1548 { .pdiv = 2, .hw_val = 1 },
1549 { .pdiv = 4, .hw_val = 2 },
1550 { .pdiv = 8, .hw_val = 3 },
1551 { .pdiv = 16, .hw_val = 4 },
1552 { .pdiv = 32, .hw_val = 5 },
1553 { .pdiv = 64, .hw_val = 6 },
1554 { .pdiv = 128, .hw_val = 7 },
1557 static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
1565 if (i <= PLL_EXPO_PDIV_MAX) {
1574 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
1576 { 12000000, 1000000000, 166, 1, 2, 0 }, /* actual: 996.0 MHz */
1577 { 13000000, 1000000000, 153, 1, 2, 0 }, /* actual: 994.0 MHz */
1578 { 38400000, 1000000000, 156, 3, 2, 0 }, /* actual: 998.4 MHz */
1579 { 0, 0, 0, 0, 0, 0 },
1582 static struct tegra_clk_pll_params pll_x_params = {
1583 .input_min = 12000000,
1584 .input_max = 800000000,
1587 .vco_min = 1350000000,
1588 .vco_max = 3000000000UL,
1589 .base_reg = PLLX_BASE,
1590 .misc_reg = PLLX_MISC0,
1591 .lock_mask = PLL_BASE_LOCK,
1592 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
1594 .ext_misc_reg[0] = PLLX_MISC0,
1595 .ext_misc_reg[1] = PLLX_MISC1,
1596 .ext_misc_reg[2] = PLLX_MISC2,
1597 .ext_misc_reg[3] = PLLX_MISC3,
1598 .ext_misc_reg[4] = PLLX_MISC4,
1599 .ext_misc_reg[5] = PLLX_MISC5,
1600 .iddq_reg = PLLX_MISC3,
1601 .iddq_bit_idx = PLLXP_IDDQ_BIT,
1602 .max_p = PLL_QLIN_PDIV_MAX,
1604 .dyn_ramp_reg = PLLX_MISC2,
1607 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1608 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1609 .div_nmp = &pllx_nmp,
1610 .freq_table = pll_x_freq_table,
1611 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1612 .dyn_ramp = tegra210_pllx_dyn_ramp,
1613 .set_defaults = tegra210_pllx_set_defaults,
1614 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1617 static struct div_nmp pllc_nmp = {
1626 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
1627 { 12000000, 510000000, 85, 1, 2, 0 },
1628 { 13000000, 510000000, 78, 1, 2, 0 }, /* actual: 507.0 MHz */
1629 { 38400000, 510000000, 79, 3, 2, 0 }, /* actual: 505.6 MHz */
1630 { 0, 0, 0, 0, 0, 0 },
1633 static struct tegra_clk_pll_params pll_c_params = {
1634 .input_min = 12000000,
1635 .input_max = 700000000,
1638 .vco_min = 600000000,
1639 .vco_max = 1200000000,
1640 .base_reg = PLLC_BASE,
1641 .misc_reg = PLLC_MISC0,
1642 .lock_mask = PLL_BASE_LOCK,
1644 .iddq_reg = PLLC_MISC1,
1645 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1646 .reset_reg = PLLC_MISC0,
1647 .reset_bit_idx = PLLCX_RESET_BIT,
1648 .max_p = PLL_QLIN_PDIV_MAX,
1649 .ext_misc_reg[0] = PLLC_MISC0,
1650 .ext_misc_reg[1] = PLLC_MISC1,
1651 .ext_misc_reg[2] = PLLC_MISC2,
1652 .ext_misc_reg[3] = PLLC_MISC3,
1653 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1654 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1656 .div_nmp = &pllc_nmp,
1657 .freq_table = pll_cx_freq_table,
1658 .flags = TEGRA_PLL_USE_LOCK,
1659 .set_defaults = _pllc_set_defaults,
1660 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1663 static struct div_nmp pllcx_nmp = {
1672 static struct tegra_clk_pll_params pll_c2_params = {
1673 .input_min = 12000000,
1674 .input_max = 700000000,
1677 .vco_min = 600000000,
1678 .vco_max = 1200000000,
1679 .base_reg = PLLC2_BASE,
1680 .misc_reg = PLLC2_MISC0,
1681 .iddq_reg = PLLC2_MISC1,
1682 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1683 .reset_reg = PLLC2_MISC0,
1684 .reset_bit_idx = PLLCX_RESET_BIT,
1685 .lock_mask = PLLCX_BASE_LOCK,
1687 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1688 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1690 .div_nmp = &pllcx_nmp,
1691 .max_p = PLL_QLIN_PDIV_MAX,
1692 .ext_misc_reg[0] = PLLC2_MISC0,
1693 .ext_misc_reg[1] = PLLC2_MISC1,
1694 .ext_misc_reg[2] = PLLC2_MISC2,
1695 .ext_misc_reg[3] = PLLC2_MISC3,
1696 .freq_table = pll_cx_freq_table,
1697 .flags = TEGRA_PLL_USE_LOCK,
1698 .set_defaults = _pllc2_set_defaults,
1699 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1702 static struct tegra_clk_pll_params pll_c3_params = {
1703 .input_min = 12000000,
1704 .input_max = 700000000,
1707 .vco_min = 600000000,
1708 .vco_max = 1200000000,
1709 .base_reg = PLLC3_BASE,
1710 .misc_reg = PLLC3_MISC0,
1711 .lock_mask = PLLCX_BASE_LOCK,
1713 .iddq_reg = PLLC3_MISC1,
1714 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1715 .reset_reg = PLLC3_MISC0,
1716 .reset_bit_idx = PLLCX_RESET_BIT,
1717 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1718 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1720 .div_nmp = &pllcx_nmp,
1721 .max_p = PLL_QLIN_PDIV_MAX,
1722 .ext_misc_reg[0] = PLLC3_MISC0,
1723 .ext_misc_reg[1] = PLLC3_MISC1,
1724 .ext_misc_reg[2] = PLLC3_MISC2,
1725 .ext_misc_reg[3] = PLLC3_MISC3,
1726 .freq_table = pll_cx_freq_table,
1727 .flags = TEGRA_PLL_USE_LOCK,
1728 .set_defaults = _pllc3_set_defaults,
1729 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1732 static struct div_nmp pllss_nmp = {
1741 static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = {
1742 { 12000000, 600000000, 50, 1, 1, 0 },
1743 { 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */
1744 { 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */
1745 { 0, 0, 0, 0, 0, 0 },
1748 static const struct clk_div_table pll_vco_post_div_table[] = {
1749 { .val = 0, .div = 1 },
1750 { .val = 1, .div = 2 },
1751 { .val = 2, .div = 3 },
1752 { .val = 3, .div = 4 },
1753 { .val = 4, .div = 5 },
1754 { .val = 5, .div = 6 },
1755 { .val = 6, .div = 8 },
1756 { .val = 7, .div = 10 },
1757 { .val = 8, .div = 12 },
1758 { .val = 9, .div = 16 },
1759 { .val = 10, .div = 12 },
1760 { .val = 11, .div = 16 },
1761 { .val = 12, .div = 20 },
1762 { .val = 13, .div = 24 },
1763 { .val = 14, .div = 32 },
1764 { .val = 0, .div = 0 },
1767 static struct tegra_clk_pll_params pll_c4_vco_params = {
1768 .input_min = 9600000,
1769 .input_max = 800000000,
1772 .vco_min = 500000000,
1773 .vco_max = 1080000000,
1774 .base_reg = PLLC4_BASE,
1775 .misc_reg = PLLC4_MISC0,
1776 .lock_mask = PLL_BASE_LOCK,
1778 .max_p = PLL_QLIN_PDIV_MAX,
1779 .ext_misc_reg[0] = PLLC4_MISC0,
1780 .iddq_reg = PLLC4_BASE,
1781 .iddq_bit_idx = PLLSS_IDDQ_BIT,
1782 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1783 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1785 .div_nmp = &pllss_nmp,
1786 .freq_table = pll_c4_vco_freq_table,
1787 .set_defaults = tegra210_pllc4_set_defaults,
1788 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1789 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1792 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
1793 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
1794 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
1795 { 38400000, 297600000, 93, 4, 3, 0 },
1796 { 38400000, 400000000, 125, 4, 3, 0 },
1797 { 38400000, 532800000, 111, 4, 2, 0 },
1798 { 38400000, 665600000, 104, 3, 2, 0 },
1799 { 38400000, 800000000, 125, 3, 2, 0 },
1800 { 38400000, 931200000, 97, 4, 1, 0 },
1801 { 38400000, 1065600000, 111, 4, 1, 0 },
1802 { 38400000, 1200000000, 125, 4, 1, 0 },
1803 { 38400000, 1331200000, 104, 3, 1, 0 },
1804 { 38400000, 1459200000, 76, 2, 1, 0 },
1805 { 38400000, 1600000000, 125, 3, 1, 0 },
1806 { 0, 0, 0, 0, 0, 0 },
1809 static struct div_nmp pllm_nmp = {
1812 .override_divm_shift = 0,
1815 .override_divn_shift = 8,
1818 .override_divp_shift = 27,
1821 static struct tegra_clk_pll_params pll_m_params = {
1822 .input_min = 9600000,
1823 .input_max = 500000000,
1826 .vco_min = 800000000,
1827 .vco_max = 1866000000,
1828 .base_reg = PLLM_BASE,
1829 .misc_reg = PLLM_MISC2,
1830 .lock_mask = PLL_BASE_LOCK,
1831 .lock_enable_bit_idx = PLLM_MISC_LOCK_ENABLE,
1833 .iddq_reg = PLLM_MISC2,
1834 .iddq_bit_idx = PLLM_IDDQ_BIT,
1835 .max_p = PLL_QLIN_PDIV_MAX,
1836 .ext_misc_reg[0] = PLLM_MISC2,
1837 .ext_misc_reg[1] = PLLM_MISC1,
1838 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1839 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1840 .div_nmp = &pllm_nmp,
1841 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
1842 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
1843 .freq_table = pll_m_freq_table,
1844 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
1845 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1848 static struct tegra_clk_pll_params pll_mb_params = {
1849 .input_min = 9600000,
1850 .input_max = 500000000,
1853 .vco_min = 800000000,
1854 .vco_max = 1866000000,
1855 .base_reg = PLLMB_BASE,
1856 .misc_reg = PLLMB_MISC1,
1857 .lock_mask = PLL_BASE_LOCK,
1859 .iddq_reg = PLLMB_MISC1,
1860 .iddq_bit_idx = PLLMB_IDDQ_BIT,
1861 .max_p = PLL_QLIN_PDIV_MAX,
1862 .ext_misc_reg[0] = PLLMB_MISC1,
1863 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1864 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1865 .div_nmp = &pllm_nmp,
1866 .freq_table = pll_m_freq_table,
1867 .flags = TEGRA_PLL_USE_LOCK,
1868 .set_defaults = tegra210_pllmb_set_defaults,
1869 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1873 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
1874 /* PLLE special case: use cpcon field to store cml divider value */
1875 { 672000000, 100000000, 125, 42, 0, 13 },
1876 { 624000000, 100000000, 125, 39, 0, 13 },
1877 { 336000000, 100000000, 125, 21, 0, 13 },
1878 { 312000000, 100000000, 200, 26, 0, 14 },
1879 { 38400000, 100000000, 125, 2, 0, 14 },
1880 { 12000000, 100000000, 200, 1, 0, 14 },
1881 { 0, 0, 0, 0, 0, 0 },
1884 static struct div_nmp plle_nmp = {
1893 static struct tegra_clk_pll_params pll_e_params = {
1894 .input_min = 12000000,
1895 .input_max = 800000000,
1898 .vco_min = 1600000000,
1899 .vco_max = 2500000000U,
1900 .base_reg = PLLE_BASE,
1901 .misc_reg = PLLE_MISC0,
1902 .aux_reg = PLLE_AUX,
1903 .lock_mask = PLLE_MISC_LOCK,
1904 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
1906 .div_nmp = &plle_nmp,
1907 .freq_table = pll_e_freq_table,
1908 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK |
1909 TEGRA_PLL_HAS_LOCK_ENABLE,
1910 .fixed_rate = 100000000,
1911 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1914 static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = {
1915 { 12000000, 672000000, 56, 1, 1, 0 },
1916 { 13000000, 672000000, 51, 1, 1, 0 }, /* actual: 663.0 MHz */
1917 { 38400000, 672000000, 70, 4, 1, 0 },
1918 { 0, 0, 0, 0, 0, 0 },
1921 static struct div_nmp pllre_nmp = {
1930 static struct tegra_clk_pll_params pll_re_vco_params = {
1931 .input_min = 9600000,
1932 .input_max = 800000000,
1935 .vco_min = 350000000,
1936 .vco_max = 700000000,
1937 .base_reg = PLLRE_BASE,
1938 .misc_reg = PLLRE_MISC0,
1939 .lock_mask = PLLRE_MISC_LOCK,
1941 .max_p = PLL_QLIN_PDIV_MAX,
1942 .ext_misc_reg[0] = PLLRE_MISC0,
1943 .iddq_reg = PLLRE_MISC0,
1944 .iddq_bit_idx = PLLRE_IDDQ_BIT,
1945 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1946 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1947 .div_nmp = &pllre_nmp,
1948 .freq_table = pll_re_vco_freq_table,
1949 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_VCO_OUT,
1950 .set_defaults = tegra210_pllre_set_defaults,
1951 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1954 static struct div_nmp pllp_nmp = {
1963 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
1964 { 12000000, 408000000, 34, 1, 1, 0 },
1965 { 38400000, 408000000, 85, 8, 1, 0 }, /* cf = 4.8MHz, allowed exception */
1966 { 0, 0, 0, 0, 0, 0 },
1969 static struct tegra_clk_pll_params pll_p_params = {
1970 .input_min = 9600000,
1971 .input_max = 800000000,
1974 .vco_min = 350000000,
1975 .vco_max = 700000000,
1976 .base_reg = PLLP_BASE,
1977 .misc_reg = PLLP_MISC0,
1978 .lock_mask = PLL_BASE_LOCK,
1980 .iddq_reg = PLLP_MISC0,
1981 .iddq_bit_idx = PLLXP_IDDQ_BIT,
1982 .ext_misc_reg[0] = PLLP_MISC0,
1983 .ext_misc_reg[1] = PLLP_MISC1,
1984 .div_nmp = &pllp_nmp,
1985 .freq_table = pll_p_freq_table,
1986 .fixed_rate = 408000000,
1987 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1988 .set_defaults = tegra210_pllp_set_defaults,
1989 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1992 static struct tegra_clk_pll_params pll_a1_params = {
1993 .input_min = 12000000,
1994 .input_max = 700000000,
1997 .vco_min = 600000000,
1998 .vco_max = 1200000000,
1999 .base_reg = PLLA1_BASE,
2000 .misc_reg = PLLA1_MISC0,
2001 .lock_mask = PLLCX_BASE_LOCK,
2003 .iddq_reg = PLLA1_MISC1,
2004 .iddq_bit_idx = PLLCX_IDDQ_BIT,
2005 .reset_reg = PLLA1_MISC0,
2006 .reset_bit_idx = PLLCX_RESET_BIT,
2007 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2008 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2009 .div_nmp = &pllc_nmp,
2010 .ext_misc_reg[0] = PLLA1_MISC0,
2011 .ext_misc_reg[1] = PLLA1_MISC1,
2012 .ext_misc_reg[2] = PLLA1_MISC2,
2013 .ext_misc_reg[3] = PLLA1_MISC3,
2014 .freq_table = pll_cx_freq_table,
2015 .flags = TEGRA_PLL_USE_LOCK,
2016 .set_defaults = _plla1_set_defaults,
2017 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2020 static struct div_nmp plla_nmp = {
2029 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
2030 { 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */
2031 { 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */
2032 { 12000000, 240000000, 60, 1, 3, 1, 0 },
2033 { 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */
2034 { 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */
2035 { 13000000, 240000000, 55, 1, 3, 1, 0 }, /* actual: 238.3 MHz */
2036 { 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */
2037 { 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */
2038 { 38400000, 240000000, 75, 3, 3, 1, 0 },
2039 { 0, 0, 0, 0, 0, 0, 0 },
2042 static struct tegra_clk_pll_params pll_a_params = {
2043 .input_min = 12000000,
2044 .input_max = 800000000,
2047 .vco_min = 500000000,
2048 .vco_max = 1000000000,
2049 .base_reg = PLLA_BASE,
2050 .misc_reg = PLLA_MISC0,
2051 .lock_mask = PLL_BASE_LOCK,
2053 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2054 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2055 .iddq_reg = PLLA_BASE,
2056 .iddq_bit_idx = PLLA_IDDQ_BIT,
2057 .div_nmp = &plla_nmp,
2058 .sdm_din_reg = PLLA_MISC1,
2059 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2060 .sdm_ctrl_reg = PLLA_MISC2,
2061 .sdm_ctrl_en_mask = PLLA_SDM_EN_MASK,
2062 .ext_misc_reg[0] = PLLA_MISC0,
2063 .ext_misc_reg[1] = PLLA_MISC1,
2064 .ext_misc_reg[2] = PLLA_MISC2,
2065 .freq_table = pll_a_freq_table,
2066 .flags = TEGRA_PLL_USE_LOCK | TEGRA_MDIV_NEW,
2067 .set_defaults = tegra210_plla_set_defaults,
2068 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2069 .set_gain = tegra210_clk_pll_set_gain,
2070 .adjust_vco = tegra210_clk_adjust_vco_min,
2073 static struct div_nmp plld_nmp = {
2082 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
2083 { 12000000, 594000000, 99, 1, 2, 0, 0 },
2084 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
2085 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
2086 { 0, 0, 0, 0, 0, 0, 0 },
2089 static struct tegra_clk_pll_params pll_d_params = {
2090 .input_min = 12000000,
2091 .input_max = 800000000,
2094 .vco_min = 750000000,
2095 .vco_max = 1500000000,
2096 .base_reg = PLLD_BASE,
2097 .misc_reg = PLLD_MISC0,
2098 .lock_mask = PLL_BASE_LOCK,
2100 .iddq_reg = PLLD_MISC0,
2101 .iddq_bit_idx = PLLD_IDDQ_BIT,
2102 .round_p_to_pdiv = pll_expo_p_to_pdiv,
2103 .pdiv_tohw = pll_expo_pdiv_to_hw,
2104 .div_nmp = &plld_nmp,
2105 .sdm_din_reg = PLLD_MISC0,
2106 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2107 .sdm_ctrl_reg = PLLD_MISC0,
2108 .sdm_ctrl_en_mask = PLLD_SDM_EN_MASK,
2109 .ext_misc_reg[0] = PLLD_MISC0,
2110 .ext_misc_reg[1] = PLLD_MISC1,
2111 .freq_table = pll_d_freq_table,
2112 .flags = TEGRA_PLL_USE_LOCK,
2114 .set_defaults = tegra210_plld_set_defaults,
2115 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2116 .set_gain = tegra210_clk_pll_set_gain,
2117 .adjust_vco = tegra210_clk_adjust_vco_min,
2120 static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = {
2121 { 12000000, 594000000, 99, 1, 2, 0, 0xf000 },
2122 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
2123 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
2124 { 0, 0, 0, 0, 0, 0, 0 },
2127 /* s/w policy, always tegra_pll_ref */
2128 static struct tegra_clk_pll_params pll_d2_params = {
2129 .input_min = 12000000,
2130 .input_max = 800000000,
2133 .vco_min = 750000000,
2134 .vco_max = 1500000000,
2135 .base_reg = PLLD2_BASE,
2136 .misc_reg = PLLD2_MISC0,
2137 .lock_mask = PLL_BASE_LOCK,
2139 .iddq_reg = PLLD2_BASE,
2140 .iddq_bit_idx = PLLSS_IDDQ_BIT,
2141 .sdm_din_reg = PLLD2_MISC3,
2142 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2143 .sdm_ctrl_reg = PLLD2_MISC1,
2144 .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK,
2145 /* disable spread-spectrum for pll_d2 */
2147 .ssc_ctrl_en_mask = 0,
2148 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2149 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2150 .div_nmp = &pllss_nmp,
2151 .ext_misc_reg[0] = PLLD2_MISC0,
2152 .ext_misc_reg[1] = PLLD2_MISC1,
2153 .ext_misc_reg[2] = PLLD2_MISC2,
2154 .ext_misc_reg[3] = PLLD2_MISC3,
2155 .max_p = PLL_QLIN_PDIV_MAX,
2157 .freq_table = tegra210_pll_d2_freq_table,
2158 .set_defaults = tegra210_plld2_set_defaults,
2159 .flags = TEGRA_PLL_USE_LOCK,
2160 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2161 .set_gain = tegra210_clk_pll_set_gain,
2162 .adjust_vco = tegra210_clk_adjust_vco_min,
2165 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
2166 { 12000000, 270000000, 90, 1, 4, 0, 0xf000 },
2167 { 13000000, 270000000, 83, 1, 4, 0, 0xf000 }, /* actual: 269.8 MHz */
2168 { 38400000, 270000000, 28, 1, 4, 0, 0xf400 },
2169 { 0, 0, 0, 0, 0, 0, 0 },
2172 static struct tegra_clk_pll_params pll_dp_params = {
2173 .input_min = 12000000,
2174 .input_max = 800000000,
2177 .vco_min = 750000000,
2178 .vco_max = 1500000000,
2179 .base_reg = PLLDP_BASE,
2180 .misc_reg = PLLDP_MISC,
2181 .lock_mask = PLL_BASE_LOCK,
2183 .iddq_reg = PLLDP_BASE,
2184 .iddq_bit_idx = PLLSS_IDDQ_BIT,
2185 .sdm_din_reg = PLLDP_SS_CTRL2,
2186 .sdm_din_mask = PLLA_SDM_DIN_MASK,
2187 .sdm_ctrl_reg = PLLDP_SS_CFG,
2188 .sdm_ctrl_en_mask = PLLDP_SDM_EN_MASK,
2189 .ssc_ctrl_reg = PLLDP_SS_CFG,
2190 .ssc_ctrl_en_mask = PLLDP_SSC_EN_MASK,
2191 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2192 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2193 .div_nmp = &pllss_nmp,
2194 .ext_misc_reg[0] = PLLDP_MISC,
2195 .ext_misc_reg[1] = PLLDP_SS_CFG,
2196 .ext_misc_reg[2] = PLLDP_SS_CTRL1,
2197 .ext_misc_reg[3] = PLLDP_SS_CTRL2,
2198 .max_p = PLL_QLIN_PDIV_MAX,
2200 .freq_table = pll_dp_freq_table,
2201 .set_defaults = tegra210_plldp_set_defaults,
2202 .flags = TEGRA_PLL_USE_LOCK,
2203 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
2204 .set_gain = tegra210_clk_pll_set_gain,
2205 .adjust_vco = tegra210_clk_adjust_vco_min,
2208 static struct div_nmp pllu_nmp = {
2217 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
2218 { 12000000, 480000000, 40, 1, 0, 0 },
2219 { 13000000, 480000000, 36, 1, 0, 0 }, /* actual: 468.0 MHz */
2220 { 38400000, 480000000, 25, 2, 0, 0 },
2221 { 0, 0, 0, 0, 0, 0 },
2224 static struct tegra_clk_pll_params pll_u_vco_params = {
2225 .input_min = 9600000,
2226 .input_max = 800000000,
2229 .vco_min = 350000000,
2230 .vco_max = 700000000,
2231 .base_reg = PLLU_BASE,
2232 .misc_reg = PLLU_MISC0,
2233 .lock_mask = PLL_BASE_LOCK,
2235 .iddq_reg = PLLU_MISC0,
2236 .iddq_bit_idx = PLLU_IDDQ_BIT,
2237 .ext_misc_reg[0] = PLLU_MISC0,
2238 .ext_misc_reg[1] = PLLU_MISC1,
2239 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
2240 .pdiv_tohw = pll_qlin_pdiv_to_hw,
2241 .div_nmp = &pllu_nmp,
2242 .freq_table = pll_u_freq_table,
2243 .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
2246 struct utmi_clk_param {
2247 /* Oscillator Frequency in KHz */
2249 /* UTMIP PLL Enable Delay Count */
2250 u8 enable_delay_count;
2251 /* UTMIP PLL Stable count */
2253 /* UTMIP PLL Active delay count */
2254 u8 active_delay_count;
2255 /* UTMIP PLL Xtal frequency count */
2256 u16 xtal_freq_count;
2259 static const struct utmi_clk_param utmi_parameters[] = {
2261 .osc_frequency = 38400000, .enable_delay_count = 0x0,
2262 .stable_count = 0x0, .active_delay_count = 0x6,
2263 .xtal_freq_count = 0x80
2265 .osc_frequency = 13000000, .enable_delay_count = 0x02,
2266 .stable_count = 0x33, .active_delay_count = 0x05,
2267 .xtal_freq_count = 0x7f
2269 .osc_frequency = 19200000, .enable_delay_count = 0x03,
2270 .stable_count = 0x4b, .active_delay_count = 0x06,
2271 .xtal_freq_count = 0xbb
2273 .osc_frequency = 12000000, .enable_delay_count = 0x02,
2274 .stable_count = 0x2f, .active_delay_count = 0x08,
2275 .xtal_freq_count = 0x76
2277 .osc_frequency = 26000000, .enable_delay_count = 0x04,
2278 .stable_count = 0x66, .active_delay_count = 0x09,
2279 .xtal_freq_count = 0xfe
2281 .osc_frequency = 16800000, .enable_delay_count = 0x03,
2282 .stable_count = 0x41, .active_delay_count = 0x0a,
2283 .xtal_freq_count = 0xa4
2287 static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
2288 [tegra_clk_ispb] = { .dt_id = TEGRA210_CLK_ISPB, .present = true },
2289 [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true },
2290 [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true },
2291 [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true },
2292 [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true },
2293 [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true },
2294 [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true },
2295 [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true },
2296 [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true },
2297 [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true },
2298 [tegra_clk_isp_9] = { .dt_id = TEGRA210_CLK_ISP, .present = true },
2299 [tegra_clk_disp2_8] = { .dt_id = TEGRA210_CLK_DISP2, .present = true },
2300 [tegra_clk_disp1_8] = { .dt_id = TEGRA210_CLK_DISP1, .present = true },
2301 [tegra_clk_host1x_9] = { .dt_id = TEGRA210_CLK_HOST1X, .present = true },
2302 [tegra_clk_i2s0] = { .dt_id = TEGRA210_CLK_I2S0, .present = true },
2303 [tegra_clk_apbdma] = { .dt_id = TEGRA210_CLK_APBDMA, .present = true },
2304 [tegra_clk_kfuse] = { .dt_id = TEGRA210_CLK_KFUSE, .present = true },
2305 [tegra_clk_sbc1_9] = { .dt_id = TEGRA210_CLK_SBC1, .present = true },
2306 [tegra_clk_sbc2_9] = { .dt_id = TEGRA210_CLK_SBC2, .present = true },
2307 [tegra_clk_sbc3_9] = { .dt_id = TEGRA210_CLK_SBC3, .present = true },
2308 [tegra_clk_i2c5] = { .dt_id = TEGRA210_CLK_I2C5, .present = true },
2309 [tegra_clk_csi] = { .dt_id = TEGRA210_CLK_CSI, .present = true },
2310 [tegra_clk_i2c2] = { .dt_id = TEGRA210_CLK_I2C2, .present = true },
2311 [tegra_clk_uartc_8] = { .dt_id = TEGRA210_CLK_UARTC, .present = true },
2312 [tegra_clk_mipi_cal] = { .dt_id = TEGRA210_CLK_MIPI_CAL, .present = true },
2313 [tegra_clk_emc] = { .dt_id = TEGRA210_CLK_EMC, .present = true },
2314 [tegra_clk_usb2] = { .dt_id = TEGRA210_CLK_USB2, .present = true },
2315 [tegra_clk_bsev] = { .dt_id = TEGRA210_CLK_BSEV, .present = true },
2316 [tegra_clk_uartd_8] = { .dt_id = TEGRA210_CLK_UARTD, .present = true },
2317 [tegra_clk_i2c3] = { .dt_id = TEGRA210_CLK_I2C3, .present = true },
2318 [tegra_clk_sbc4_9] = { .dt_id = TEGRA210_CLK_SBC4, .present = true },
2319 [tegra_clk_sdmmc3_9] = { .dt_id = TEGRA210_CLK_SDMMC3, .present = true },
2320 [tegra_clk_pcie] = { .dt_id = TEGRA210_CLK_PCIE, .present = true },
2321 [tegra_clk_owr_8] = { .dt_id = TEGRA210_CLK_OWR, .present = true },
2322 [tegra_clk_afi] = { .dt_id = TEGRA210_CLK_AFI, .present = true },
2323 [tegra_clk_csite_8] = { .dt_id = TEGRA210_CLK_CSITE, .present = true },
2324 [tegra_clk_soc_therm_8] = { .dt_id = TEGRA210_CLK_SOC_THERM, .present = true },
2325 [tegra_clk_dtv] = { .dt_id = TEGRA210_CLK_DTV, .present = true },
2326 [tegra_clk_i2cslow] = { .dt_id = TEGRA210_CLK_I2CSLOW, .present = true },
2327 [tegra_clk_tsec_8] = { .dt_id = TEGRA210_CLK_TSEC, .present = true },
2328 [tegra_clk_xusb_host] = { .dt_id = TEGRA210_CLK_XUSB_HOST, .present = true },
2329 [tegra_clk_csus] = { .dt_id = TEGRA210_CLK_CSUS, .present = true },
2330 [tegra_clk_mselect] = { .dt_id = TEGRA210_CLK_MSELECT, .present = true },
2331 [tegra_clk_tsensor] = { .dt_id = TEGRA210_CLK_TSENSOR, .present = true },
2332 [tegra_clk_i2s3] = { .dt_id = TEGRA210_CLK_I2S3, .present = true },
2333 [tegra_clk_i2s4] = { .dt_id = TEGRA210_CLK_I2S4, .present = true },
2334 [tegra_clk_i2c4] = { .dt_id = TEGRA210_CLK_I2C4, .present = true },
2335 [tegra_clk_d_audio] = { .dt_id = TEGRA210_CLK_D_AUDIO, .present = true },
2336 [tegra_clk_hda2codec_2x_8] = { .dt_id = TEGRA210_CLK_HDA2CODEC_2X, .present = true },
2337 [tegra_clk_spdif_2x] = { .dt_id = TEGRA210_CLK_SPDIF_2X, .present = true },
2338 [tegra_clk_actmon] = { .dt_id = TEGRA210_CLK_ACTMON, .present = true },
2339 [tegra_clk_extern1] = { .dt_id = TEGRA210_CLK_EXTERN1, .present = true },
2340 [tegra_clk_extern2] = { .dt_id = TEGRA210_CLK_EXTERN2, .present = true },
2341 [tegra_clk_extern3] = { .dt_id = TEGRA210_CLK_EXTERN3, .present = true },
2342 [tegra_clk_sata_oob_8] = { .dt_id = TEGRA210_CLK_SATA_OOB, .present = true },
2343 [tegra_clk_sata_8] = { .dt_id = TEGRA210_CLK_SATA, .present = true },
2344 [tegra_clk_hda_8] = { .dt_id = TEGRA210_CLK_HDA, .present = true },
2345 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA210_CLK_HDA2HDMI, .present = true },
2346 [tegra_clk_cilab] = { .dt_id = TEGRA210_CLK_CILAB, .present = true },
2347 [tegra_clk_cilcd] = { .dt_id = TEGRA210_CLK_CILCD, .present = true },
2348 [tegra_clk_cile] = { .dt_id = TEGRA210_CLK_CILE, .present = true },
2349 [tegra_clk_dsialp] = { .dt_id = TEGRA210_CLK_DSIALP, .present = true },
2350 [tegra_clk_dsiblp] = { .dt_id = TEGRA210_CLK_DSIBLP, .present = true },
2351 [tegra_clk_entropy_8] = { .dt_id = TEGRA210_CLK_ENTROPY, .present = true },
2352 [tegra_clk_xusb_ss] = { .dt_id = TEGRA210_CLK_XUSB_SS, .present = true },
2353 [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true },
2354 [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true },
2355 [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true },
2356 [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true },
2357 [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },
2358 [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },
2359 [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
2360 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true },
2361 [tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },
2362 [tegra_clk_sor1_src] = { .dt_id = TEGRA210_CLK_SOR1_SRC, .present = true },
2363 [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
2364 [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },
2365 [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },
2366 [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true },
2367 [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true },
2368 [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true },
2369 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true },
2370 [tegra_clk_fuse] = { .dt_id = TEGRA210_CLK_FUSE, .present = true },
2371 [tegra_clk_fuse_burn] = { .dt_id = TEGRA210_CLK_FUSE_BURN, .present = true },
2372 [tegra_clk_clk_32k] = { .dt_id = TEGRA210_CLK_CLK_32K, .present = true },
2373 [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true },
2374 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true },
2375 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true },
2376 [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true },
2377 [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true },
2378 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true },
2379 [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true },
2380 [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true },
2381 [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true },
2382 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },
2383 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true },
2384 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true },
2385 [tegra_clk_pll_p_out4_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT4, .present = true },
2386 [tegra_clk_pll_p_out_hsio] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_HSIO, .present = true },
2387 [tegra_clk_pll_p_out_xusb] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_XUSB, .present = true },
2388 [tegra_clk_pll_p_out_cpu] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_CPU, .present = true },
2389 [tegra_clk_pll_p_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_P_OUT_ADSP, .present = true },
2390 [tegra_clk_pll_a] = { .dt_id = TEGRA210_CLK_PLL_A, .present = true },
2391 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true },
2392 [tegra_clk_pll_d] = { .dt_id = TEGRA210_CLK_PLL_D, .present = true },
2393 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA210_CLK_PLL_D_OUT0, .present = true },
2394 [tegra_clk_pll_d2] = { .dt_id = TEGRA210_CLK_PLL_D2, .present = true },
2395 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA210_CLK_PLL_D2_OUT0, .present = true },
2396 [tegra_clk_pll_u] = { .dt_id = TEGRA210_CLK_PLL_U, .present = true },
2397 [tegra_clk_pll_u_out] = { .dt_id = TEGRA210_CLK_PLL_U_OUT, .present = true },
2398 [tegra_clk_pll_u_out1] = { .dt_id = TEGRA210_CLK_PLL_U_OUT1, .present = true },
2399 [tegra_clk_pll_u_out2] = { .dt_id = TEGRA210_CLK_PLL_U_OUT2, .present = true },
2400 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA210_CLK_PLL_U_480M, .present = true },
2401 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA210_CLK_PLL_U_60M, .present = true },
2402 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA210_CLK_PLL_U_48M, .present = true },
2403 [tegra_clk_pll_x] = { .dt_id = TEGRA210_CLK_PLL_X, .present = true },
2404 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA210_CLK_PLL_X_OUT0, .present = true },
2405 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA210_CLK_PLL_RE_VCO, .present = true },
2406 [tegra_clk_pll_re_out] = { .dt_id = TEGRA210_CLK_PLL_RE_OUT, .present = true },
2407 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC, .present = true },
2408 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA210_CLK_I2S0_SYNC, .present = true },
2409 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA210_CLK_I2S1_SYNC, .present = true },
2410 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA210_CLK_I2S2_SYNC, .present = true },
2411 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA210_CLK_I2S3_SYNC, .present = true },
2412 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA210_CLK_I2S4_SYNC, .present = true },
2413 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA210_CLK_VIMCLK_SYNC, .present = true },
2414 [tegra_clk_audio0] = { .dt_id = TEGRA210_CLK_AUDIO0, .present = true },
2415 [tegra_clk_audio1] = { .dt_id = TEGRA210_CLK_AUDIO1, .present = true },
2416 [tegra_clk_audio2] = { .dt_id = TEGRA210_CLK_AUDIO2, .present = true },
2417 [tegra_clk_audio3] = { .dt_id = TEGRA210_CLK_AUDIO3, .present = true },
2418 [tegra_clk_audio4] = { .dt_id = TEGRA210_CLK_AUDIO4, .present = true },
2419 [tegra_clk_spdif] = { .dt_id = TEGRA210_CLK_SPDIF, .present = true },
2420 [tegra_clk_clk_out_1] = { .dt_id = TEGRA210_CLK_CLK_OUT_1, .present = true },
2421 [tegra_clk_clk_out_2] = { .dt_id = TEGRA210_CLK_CLK_OUT_2, .present = true },
2422 [tegra_clk_clk_out_3] = { .dt_id = TEGRA210_CLK_CLK_OUT_3, .present = true },
2423 [tegra_clk_blink] = { .dt_id = TEGRA210_CLK_BLINK, .present = true },
2424 [tegra_clk_xusb_gate] = { .dt_id = TEGRA210_CLK_XUSB_GATE, .present = true },
2425 [tegra_clk_xusb_host_src_8] = { .dt_id = TEGRA210_CLK_XUSB_HOST_SRC, .present = true },
2426 [tegra_clk_xusb_falcon_src_8] = { .dt_id = TEGRA210_CLK_XUSB_FALCON_SRC, .present = true },
2427 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA210_CLK_XUSB_FS_SRC, .present = true },
2428 [tegra_clk_xusb_ss_src_8] = { .dt_id = TEGRA210_CLK_XUSB_SS_SRC, .present = true },
2429 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA210_CLK_XUSB_SS_DIV2, .present = true },
2430 [tegra_clk_xusb_dev_src_8] = { .dt_id = TEGRA210_CLK_XUSB_DEV_SRC, .present = true },
2431 [tegra_clk_xusb_dev] = { .dt_id = TEGRA210_CLK_XUSB_DEV, .present = true },
2432 [tegra_clk_xusb_hs_src_4] = { .dt_id = TEGRA210_CLK_XUSB_HS_SRC, .present = true },
2433 [tegra_clk_xusb_ssp_src] = { .dt_id = TEGRA210_CLK_XUSB_SSP_SRC, .present = true },
2434 [tegra_clk_usb2_hsic_trk] = { .dt_id = TEGRA210_CLK_USB2_HSIC_TRK, .present = true },
2435 [tegra_clk_hsic_trk] = { .dt_id = TEGRA210_CLK_HSIC_TRK, .present = true },
2436 [tegra_clk_usb2_trk] = { .dt_id = TEGRA210_CLK_USB2_TRK, .present = true },
2437 [tegra_clk_sclk] = { .dt_id = TEGRA210_CLK_SCLK, .present = true },
2438 [tegra_clk_sclk_mux] = { .dt_id = TEGRA210_CLK_SCLK_MUX, .present = true },
2439 [tegra_clk_hclk] = { .dt_id = TEGRA210_CLK_HCLK, .present = true },
2440 [tegra_clk_pclk] = { .dt_id = TEGRA210_CLK_PCLK, .present = true },
2441 [tegra_clk_cclk_g] = { .dt_id = TEGRA210_CLK_CCLK_G, .present = true },
2442 [tegra_clk_cclk_lp] = { .dt_id = TEGRA210_CLK_CCLK_LP, .present = true },
2443 [tegra_clk_dfll_ref] = { .dt_id = TEGRA210_CLK_DFLL_REF, .present = true },
2444 [tegra_clk_dfll_soc] = { .dt_id = TEGRA210_CLK_DFLL_SOC, .present = true },
2445 [tegra_clk_vi_sensor2_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR2, .present = true },
2446 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA210_CLK_PLL_P_OUT5, .present = true },
2447 [tegra_clk_pll_c4] = { .dt_id = TEGRA210_CLK_PLL_C4, .present = true },
2448 [tegra_clk_pll_dp] = { .dt_id = TEGRA210_CLK_PLL_DP, .present = true },
2449 [tegra_clk_audio0_mux] = { .dt_id = TEGRA210_CLK_AUDIO0_MUX, .present = true },
2450 [tegra_clk_audio1_mux] = { .dt_id = TEGRA210_CLK_AUDIO1_MUX, .present = true },
2451 [tegra_clk_audio2_mux] = { .dt_id = TEGRA210_CLK_AUDIO2_MUX, .present = true },
2452 [tegra_clk_audio3_mux] = { .dt_id = TEGRA210_CLK_AUDIO3_MUX, .present = true },
2453 [tegra_clk_audio4_mux] = { .dt_id = TEGRA210_CLK_AUDIO4_MUX, .present = true },
2454 [tegra_clk_spdif_mux] = { .dt_id = TEGRA210_CLK_SPDIF_MUX, .present = true },
2455 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_1_MUX, .present = true },
2456 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_2_MUX, .present = true },
2457 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA210_CLK_CLK_OUT_3_MUX, .present = true },
2458 [tegra_clk_maud] = { .dt_id = TEGRA210_CLK_MAUD, .present = true },
2459 [tegra_clk_mipibif] = { .dt_id = TEGRA210_CLK_MIPIBIF, .present = true },
2460 [tegra_clk_qspi] = { .dt_id = TEGRA210_CLK_QSPI, .present = true },
2461 [tegra_clk_sdmmc_legacy] = { .dt_id = TEGRA210_CLK_SDMMC_LEGACY, .present = true },
2462 [tegra_clk_tsecb] = { .dt_id = TEGRA210_CLK_TSECB, .present = true },
2463 [tegra_clk_uartape] = { .dt_id = TEGRA210_CLK_UARTAPE, .present = true },
2464 [tegra_clk_vi_i2c] = { .dt_id = TEGRA210_CLK_VI_I2C, .present = true },
2465 [tegra_clk_ape] = { .dt_id = TEGRA210_CLK_APE, .present = true },
2466 [tegra_clk_dbgapb] = { .dt_id = TEGRA210_CLK_DBGAPB, .present = true },
2467 [tegra_clk_nvdec] = { .dt_id = TEGRA210_CLK_NVDEC, .present = true },
2468 [tegra_clk_nvenc] = { .dt_id = TEGRA210_CLK_NVENC, .present = true },
2469 [tegra_clk_nvjpg] = { .dt_id = TEGRA210_CLK_NVJPG, .present = true },
2470 [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true },
2471 [tegra_clk_pll_c4_out1] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT1, .present = true },
2472 [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
2473 [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
2474 [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
2475 [tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
2476 [tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true },
2477 [tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true },
2478 [tegra_clk_dmic1] = { .dt_id = TEGRA210_CLK_DMIC1, .present = true },
2479 [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true },
2480 [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true },
2481 [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true },
2482 [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true },
2483 [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true },
2484 [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true },
2485 [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true },
2486 [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true },
2487 [tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true },
2488 [tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true },
2489 [tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true },
2490 [tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true },
2491 [tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true },
2492 [tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true },
2493 [tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true },
2496 static struct tegra_devclk devclks[] __initdata = {
2497 { .con_id = "clk_m", .dt_id = TEGRA210_CLK_CLK_M },
2498 { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
2499 { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K },
2500 { .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 },
2501 { .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 },
2502 { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C },
2503 { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 },
2504 { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 },
2505 { .con_id = "pll_c3", .dt_id = TEGRA210_CLK_PLL_C3 },
2506 { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P },
2507 { .con_id = "pll_p_out1", .dt_id = TEGRA210_CLK_PLL_P_OUT1 },
2508 { .con_id = "pll_p_out2", .dt_id = TEGRA210_CLK_PLL_P_OUT2 },
2509 { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 },
2510 { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 },
2511 { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M },
2512 { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X },
2513 { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 },
2514 { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U },
2515 { .con_id = "pll_u_out", .dt_id = TEGRA210_CLK_PLL_U_OUT },
2516 { .con_id = "pll_u_out1", .dt_id = TEGRA210_CLK_PLL_U_OUT1 },
2517 { .con_id = "pll_u_out2", .dt_id = TEGRA210_CLK_PLL_U_OUT2 },
2518 { .con_id = "pll_u_480M", .dt_id = TEGRA210_CLK_PLL_U_480M },
2519 { .con_id = "pll_u_60M", .dt_id = TEGRA210_CLK_PLL_U_60M },
2520 { .con_id = "pll_u_48M", .dt_id = TEGRA210_CLK_PLL_U_48M },
2521 { .con_id = "pll_d", .dt_id = TEGRA210_CLK_PLL_D },
2522 { .con_id = "pll_d_out0", .dt_id = TEGRA210_CLK_PLL_D_OUT0 },
2523 { .con_id = "pll_d2", .dt_id = TEGRA210_CLK_PLL_D2 },
2524 { .con_id = "pll_d2_out0", .dt_id = TEGRA210_CLK_PLL_D2_OUT0 },
2525 { .con_id = "pll_a", .dt_id = TEGRA210_CLK_PLL_A },
2526 { .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 },
2527 { .con_id = "pll_re_vco", .dt_id = TEGRA210_CLK_PLL_RE_VCO },
2528 { .con_id = "pll_re_out", .dt_id = TEGRA210_CLK_PLL_RE_OUT },
2529 { .con_id = "spdif_in_sync", .dt_id = TEGRA210_CLK_SPDIF_IN_SYNC },
2530 { .con_id = "i2s0_sync", .dt_id = TEGRA210_CLK_I2S0_SYNC },
2531 { .con_id = "i2s1_sync", .dt_id = TEGRA210_CLK_I2S1_SYNC },
2532 { .con_id = "i2s2_sync", .dt_id = TEGRA210_CLK_I2S2_SYNC },
2533 { .con_id = "i2s3_sync", .dt_id = TEGRA210_CLK_I2S3_SYNC },
2534 { .con_id = "i2s4_sync", .dt_id = TEGRA210_CLK_I2S4_SYNC },
2535 { .con_id = "vimclk_sync", .dt_id = TEGRA210_CLK_VIMCLK_SYNC },
2536 { .con_id = "audio0", .dt_id = TEGRA210_CLK_AUDIO0 },
2537 { .con_id = "audio1", .dt_id = TEGRA210_CLK_AUDIO1 },
2538 { .con_id = "audio2", .dt_id = TEGRA210_CLK_AUDIO2 },
2539 { .con_id = "audio3", .dt_id = TEGRA210_CLK_AUDIO3 },
2540 { .con_id = "audio4", .dt_id = TEGRA210_CLK_AUDIO4 },
2541 { .con_id = "spdif", .dt_id = TEGRA210_CLK_SPDIF },
2542 { .con_id = "spdif_2x", .dt_id = TEGRA210_CLK_SPDIF_2X },
2543 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA210_CLK_EXTERN1 },
2544 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA210_CLK_EXTERN2 },
2545 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA210_CLK_EXTERN3 },
2546 { .con_id = "blink", .dt_id = TEGRA210_CLK_BLINK },
2547 { .con_id = "cclk_g", .dt_id = TEGRA210_CLK_CCLK_G },
2548 { .con_id = "cclk_lp", .dt_id = TEGRA210_CLK_CCLK_LP },
2549 { .con_id = "sclk", .dt_id = TEGRA210_CLK_SCLK },
2550 { .con_id = "hclk", .dt_id = TEGRA210_CLK_HCLK },
2551 { .con_id = "pclk", .dt_id = TEGRA210_CLK_PCLK },
2552 { .con_id = "fuse", .dt_id = TEGRA210_CLK_FUSE },
2553 { .dev_id = "rtc-tegra", .dt_id = TEGRA210_CLK_RTC },
2554 { .dev_id = "timer", .dt_id = TEGRA210_CLK_TIMER },
2555 { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 },
2556 { .con_id = "pll_c4_out1", .dt_id = TEGRA210_CLK_PLL_C4_OUT1 },
2557 { .con_id = "pll_c4_out2", .dt_id = TEGRA210_CLK_PLL_C4_OUT2 },
2558 { .con_id = "pll_c4_out3", .dt_id = TEGRA210_CLK_PLL_C4_OUT3 },
2559 { .con_id = "dpaux", .dt_id = TEGRA210_CLK_DPAUX },
2560 { .con_id = "sor0", .dt_id = TEGRA210_CLK_SOR0 },
2563 static struct tegra_audio_clk_info tegra210_audio_plls[] = {
2564 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" },
2565 { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" },
2568 static const char * const aclk_parents[] = {
2569 "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3",
2573 static const unsigned int nvjpg_slcg_clkids[] = { TEGRA210_CLK_NVDEC };
2574 static const unsigned int nvdec_slcg_clkids[] = { TEGRA210_CLK_NVJPG };
2575 static const unsigned int sor_slcg_clkids[] = { TEGRA210_CLK_HDA2CODEC_2X,
2576 TEGRA210_CLK_HDA2HDMI, TEGRA210_CLK_DISP1, TEGRA210_CLK_DISP2 };
2577 static const unsigned int disp_slcg_clkids[] = { TEGRA210_CLK_LA,
2578 TEGRA210_CLK_HOST1X};
2579 static const unsigned int xusba_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,
2580 TEGRA210_CLK_XUSB_DEV };
2581 static const unsigned int xusbb_slcg_clkids[] = { TEGRA210_CLK_XUSB_HOST,
2582 TEGRA210_CLK_XUSB_SS };
2583 static const unsigned int xusbc_slcg_clkids[] = { TEGRA210_CLK_XUSB_DEV,
2584 TEGRA210_CLK_XUSB_SS };
2585 static const unsigned int venc_slcg_clkids[] = { TEGRA210_CLK_HOST1X,
2586 TEGRA210_CLK_PLL_D };
2587 static const unsigned int ape_slcg_clkids[] = { TEGRA210_CLK_ACLK,
2588 TEGRA210_CLK_I2S0, TEGRA210_CLK_I2S1, TEGRA210_CLK_I2S2,
2589 TEGRA210_CLK_I2S3, TEGRA210_CLK_I2S4, TEGRA210_CLK_SPDIF_OUT,
2590 TEGRA210_CLK_D_AUDIO };
2591 static const unsigned int vic_slcg_clkids[] = { TEGRA210_CLK_HOST1X };
2593 static struct tegra210_domain_mbist_war tegra210_pg_mbist_war[] = {
2594 [TEGRA_POWERGATE_VENC] = {
2595 .handle_lvl2_ovr = tegra210_venc_mbist_war,
2596 .num_clks = ARRAY_SIZE(venc_slcg_clkids),
2597 .clk_init_data = venc_slcg_clkids,
2599 [TEGRA_POWERGATE_SATA] = {
2600 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2601 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2602 .lvl2_mask = BIT(0) | BIT(17) | BIT(19),
2604 [TEGRA_POWERGATE_MPE] = {
2605 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2606 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2607 .lvl2_mask = BIT(29),
2609 [TEGRA_POWERGATE_SOR] = {
2610 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2611 .num_clks = ARRAY_SIZE(sor_slcg_clkids),
2612 .clk_init_data = sor_slcg_clkids,
2613 .lvl2_offset = LVL2_CLK_GATE_OVRA,
2614 .lvl2_mask = BIT(1) | BIT(2),
2616 [TEGRA_POWERGATE_DIS] = {
2617 .handle_lvl2_ovr = tegra210_disp_mbist_war,
2618 .num_clks = ARRAY_SIZE(disp_slcg_clkids),
2619 .clk_init_data = disp_slcg_clkids,
2621 [TEGRA_POWERGATE_DISB] = {
2622 .num_clks = ARRAY_SIZE(disp_slcg_clkids),
2623 .clk_init_data = disp_slcg_clkids,
2624 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2625 .lvl2_offset = LVL2_CLK_GATE_OVRA,
2626 .lvl2_mask = BIT(2),
2628 [TEGRA_POWERGATE_XUSBA] = {
2629 .num_clks = ARRAY_SIZE(xusba_slcg_clkids),
2630 .clk_init_data = xusba_slcg_clkids,
2631 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2632 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2633 .lvl2_mask = BIT(30) | BIT(31),
2635 [TEGRA_POWERGATE_XUSBB] = {
2636 .num_clks = ARRAY_SIZE(xusbb_slcg_clkids),
2637 .clk_init_data = xusbb_slcg_clkids,
2638 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2639 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2640 .lvl2_mask = BIT(30) | BIT(31),
2642 [TEGRA_POWERGATE_XUSBC] = {
2643 .num_clks = ARRAY_SIZE(xusbc_slcg_clkids),
2644 .clk_init_data = xusbc_slcg_clkids,
2645 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2646 .lvl2_offset = LVL2_CLK_GATE_OVRC,
2647 .lvl2_mask = BIT(30) | BIT(31),
2649 [TEGRA_POWERGATE_VIC] = {
2650 .num_clks = ARRAY_SIZE(vic_slcg_clkids),
2651 .clk_init_data = vic_slcg_clkids,
2652 .handle_lvl2_ovr = tegra210_vic_mbist_war,
2654 [TEGRA_POWERGATE_NVDEC] = {
2655 .num_clks = ARRAY_SIZE(nvdec_slcg_clkids),
2656 .clk_init_data = nvdec_slcg_clkids,
2657 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2658 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2659 .lvl2_mask = BIT(9) | BIT(31),
2661 [TEGRA_POWERGATE_NVJPG] = {
2662 .num_clks = ARRAY_SIZE(nvjpg_slcg_clkids),
2663 .clk_init_data = nvjpg_slcg_clkids,
2664 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2665 .lvl2_offset = LVL2_CLK_GATE_OVRE,
2666 .lvl2_mask = BIT(9) | BIT(31),
2668 [TEGRA_POWERGATE_AUD] = {
2669 .num_clks = ARRAY_SIZE(ape_slcg_clkids),
2670 .clk_init_data = ape_slcg_clkids,
2671 .handle_lvl2_ovr = tegra210_ape_mbist_war,
2673 [TEGRA_POWERGATE_VE2] = {
2674 .handle_lvl2_ovr = tegra210_generic_mbist_war,
2675 .lvl2_offset = LVL2_CLK_GATE_OVRD,
2676 .lvl2_mask = BIT(22),
2680 int tegra210_clk_handle_mbist_war(unsigned int id)
2683 struct tegra210_domain_mbist_war *mbist_war;
2685 if (id >= ARRAY_SIZE(tegra210_pg_mbist_war)) {
2686 WARN(1, "unknown domain id in MBIST WAR handler\n");
2690 mbist_war = &tegra210_pg_mbist_war[id];
2691 if (!mbist_war->handle_lvl2_ovr)
2694 if (mbist_war->num_clks && !mbist_war->clks)
2697 err = clk_bulk_prepare_enable(mbist_war->num_clks, mbist_war->clks);
2701 mutex_lock(&lvl2_ovr_lock);
2703 mbist_war->handle_lvl2_ovr(mbist_war);
2705 mutex_unlock(&lvl2_ovr_lock);
2707 clk_bulk_disable_unprepare(mbist_war->num_clks, mbist_war->clks);
2712 void tegra210_put_utmipll_in_iddq(void)
2716 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2718 if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) {
2719 pr_err("trying to assert IDDQ while UTMIPLL is locked\n");
2723 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2724 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2726 EXPORT_SYMBOL_GPL(tegra210_put_utmipll_in_iddq);
2728 void tegra210_put_utmipll_out_iddq(void)
2732 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2733 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2734 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2736 EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq);
2738 static void tegra210_utmi_param_configure(void)
2743 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2744 if (osc_freq == utmi_parameters[i].osc_frequency)
2748 if (i >= ARRAY_SIZE(utmi_parameters)) {
2749 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
2754 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2755 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2756 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2760 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2762 /* Program UTMIP PLL stable and active counts */
2763 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
2764 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2765 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
2767 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2769 UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count);
2770 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2772 /* Program UTMIP PLL delay and oscillator frequency counts */
2773 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2775 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2777 UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count);
2779 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2781 UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].xtal_freq_count);
2783 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
2784 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2786 /* Remove power downs from UTMIP PLL control bits */
2787 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2788 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2789 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2790 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2794 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
2795 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2796 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2797 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2798 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2799 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2800 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2801 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2802 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2804 /* Setup HW control of UTMIPLL */
2805 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2806 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2807 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2808 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2810 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2811 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2812 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2813 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2817 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2818 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
2819 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2823 /* Enable HW control UTMIPLL */
2824 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2825 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2826 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2829 static int tegra210_enable_pllu(void)
2831 struct tegra_clk_pll_freq_table *fentry;
2832 struct tegra_clk_pll pllu;
2835 for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
2836 if (fentry->input_rate == pll_ref_freq)
2840 if (!fentry->input_rate) {
2841 pr_err("Unknown PLL_U reference frequency %lu\n", pll_ref_freq);
2845 /* clear IDDQ bit */
2846 pllu.params = &pll_u_vco_params;
2847 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
2848 reg &= ~BIT(pllu.params->iddq_bit_idx);
2849 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
2852 reg = readl_relaxed(clk_base + PLLU_BASE);
2853 reg &= ~GENMASK(20, 0);
2855 reg |= fentry->n << 8;
2856 reg |= fentry->p << 16;
2857 writel(reg, clk_base + PLLU_BASE);
2860 writel(reg, clk_base + PLLU_BASE);
2862 readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg,
2863 reg & PLL_BASE_LOCK, 2, 1000);
2864 if (!(reg & PLL_BASE_LOCK)) {
2865 pr_err("Timed out waiting for PLL_U to lock\n");
2872 static int tegra210_init_pllu(void)
2877 tegra210_pllu_set_defaults(&pll_u_vco_params);
2878 /* skip initialization when pllu is in hw controlled mode */
2879 reg = readl_relaxed(clk_base + PLLU_BASE);
2880 if (reg & PLLU_BASE_OVERRIDE) {
2881 if (!(reg & PLL_ENABLE)) {
2882 err = tegra210_enable_pllu();
2888 /* enable hw controlled mode */
2889 reg = readl_relaxed(clk_base + PLLU_BASE);
2890 reg &= ~PLLU_BASE_OVERRIDE;
2891 writel(reg, clk_base + PLLU_BASE);
2893 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2894 reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
2895 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
2896 PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
2897 reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
2898 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
2899 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2901 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2902 reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK;
2903 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2906 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2907 reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
2908 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2911 reg = readl_relaxed(clk_base + PLLU_BASE);
2912 reg &= ~PLLU_BASE_CLKENABLE_USB;
2913 writel_relaxed(reg, clk_base + PLLU_BASE);
2916 /* enable UTMIPLL hw control if not yet done by the bootloader */
2917 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2918 if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE))
2919 tegra210_utmi_param_configure();
2924 static const char * const sor1_out_parents[] = {
2926 * Bit 0 of the mux selects sor1_pad_clkout, irrespective of bit 1, so
2927 * the sor1_pad_clkout parent appears twice in the list below. This is
2928 * merely to support clk_get_parent() if firmware happened to set
2929 * these bits to 0b11. While not an invalid setting, code should
2930 * always set the bits to 0b01 to select sor1_pad_clkout.
2932 "sor_safe", "sor1_pad_clkout", "sor1", "sor1_pad_clkout",
2935 static const char * const sor1_parents[] = {
2936 "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m",
2939 static u32 sor1_parents_idx[] = { 0, 2, 5, 6 };
2941 static struct tegra_periph_init_data tegra210_periph[] = {
2942 TEGRA_INIT_DATA_TABLE("sor1", NULL, NULL, sor1_parents,
2943 CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1,
2944 TEGRA_DIVIDER_ROUND_UP, 183, 0, tegra_clk_sor1,
2945 sor1_parents_idx, 0, &sor1_lock),
2948 static const char * const la_parents[] = {
2949 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_re_out1", "pll_a1", "clk_m", "pll_c4_out0"
2952 static struct tegra_clk_periph tegra210_la =
2953 TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, 0);
2955 static __init void tegra210_periph_clk_init(void __iomem *clk_base,
2956 void __iomem *pmc_base)
2962 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
2964 clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
2966 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
2968 clks[TEGRA210_CLK_SOR_SAFE] = clk;
2970 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
2972 clks[TEGRA210_CLK_DPAUX] = clk;
2974 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
2976 clks[TEGRA210_CLK_DPAUX1] = clk;
2978 clk = clk_register_mux_table(NULL, "sor1_out", sor1_out_parents,
2979 ARRAY_SIZE(sor1_out_parents), 0,
2980 clk_base + CLK_SOURCE_SOR1, 14, 0x3,
2981 0, NULL, &sor1_lock);
2982 clks[TEGRA210_CLK_SOR1_OUT] = clk;
2985 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
2986 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
2987 clks[TEGRA210_CLK_PLL_D_DSI_OUT] = clk;
2990 clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
2992 periph_clk_enb_refcnt);
2993 clks[TEGRA210_CLK_DSIA] = clk;
2996 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
2998 periph_clk_enb_refcnt);
2999 clks[TEGRA210_CLK_DSIB] = clk;
3002 clk = tegra_clk_register_periph("la", la_parents,
3003 ARRAY_SIZE(la_parents), &tegra210_la, clk_base,
3005 clks[TEGRA210_CLK_LA] = clk;
3008 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
3009 ARRAY_SIZE(mux_pllmcp_clkm), 0,
3010 clk_base + CLK_SOURCE_EMC,
3011 29, 3, 0, &emc_lock);
3013 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
3015 clks[TEGRA210_CLK_MC] = clk;
3018 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
3020 clk_register_clkdev(clk, "cml0", NULL);
3021 clks[TEGRA210_CLK_CML0] = clk;
3024 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
3026 clk_register_clkdev(clk, "cml1", NULL);
3027 clks[TEGRA210_CLK_CML1] = clk;
3029 clk = tegra_clk_register_super_clk("aclk", aclk_parents,
3030 ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,
3032 clks[TEGRA210_CLK_ACLK] = clk;
3034 clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base,
3035 CLK_SOURCE_SDMMC2, 9,
3036 TEGRA_DIVIDER_ROUND_UP, 0, NULL);
3037 clks[TEGRA210_CLK_SDMMC2] = clk;
3039 clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base,
3040 CLK_SOURCE_SDMMC4, 15,
3041 TEGRA_DIVIDER_ROUND_UP, 0, NULL);
3042 clks[TEGRA210_CLK_SDMMC4] = clk;
3044 for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) {
3045 struct tegra_periph_init_data *init = &tegra210_periph[i];
3048 clkp = tegra_lookup_dt_id(init->clk_id, tegra210_clks);
3050 pr_warn("clock %u not found\n", init->clk_id);
3054 clk = tegra_clk_register_periph_data(clk_base, init);
3058 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
3061 static void __init tegra210_pll_init(void __iomem *clk_base,
3067 clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base,
3068 pmc, 0, &pll_c_params, NULL);
3069 if (!WARN_ON(IS_ERR(clk)))
3070 clk_register_clkdev(clk, "pll_c", NULL);
3071 clks[TEGRA210_CLK_PLL_C] = clk;
3074 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
3075 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3077 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
3078 clk_base + PLLC_OUT, 1, 0,
3079 CLK_SET_RATE_PARENT, 0, NULL);
3080 clk_register_clkdev(clk, "pll_c_out1", NULL);
3081 clks[TEGRA210_CLK_PLL_C_OUT1] = clk;
3084 clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
3085 CLK_SET_RATE_PARENT, 1, 1);
3086 clk_register_clkdev(clk, "pll_c_ud", NULL);
3087 clks[TEGRA210_CLK_PLL_C_UD] = clk;
3090 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base,
3091 pmc, 0, &pll_c2_params, NULL);
3092 clk_register_clkdev(clk, "pll_c2", NULL);
3093 clks[TEGRA210_CLK_PLL_C2] = clk;
3096 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base,
3097 pmc, 0, &pll_c3_params, NULL);
3098 clk_register_clkdev(clk, "pll_c3", NULL);
3099 clks[TEGRA210_CLK_PLL_C3] = clk;
3102 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc,
3103 CLK_SET_RATE_GATE, &pll_m_params, NULL);
3104 clk_register_clkdev(clk, "pll_m", NULL);
3105 clks[TEGRA210_CLK_PLL_M] = clk;
3108 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc,
3109 CLK_SET_RATE_GATE, &pll_mb_params, NULL);
3110 clk_register_clkdev(clk, "pll_mb", NULL);
3111 clks[TEGRA210_CLK_PLL_MB] = clk;
3114 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
3115 CLK_SET_RATE_PARENT, 1, 1);
3116 clk_register_clkdev(clk, "pll_m_ud", NULL);
3117 clks[TEGRA210_CLK_PLL_M_UD] = clk;
3120 if (!tegra210_init_pllu()) {
3121 clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0,
3123 clk_register_clkdev(clk, "pll_u_vco", NULL);
3124 clks[TEGRA210_CLK_PLL_U] = clk;
3128 clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0,
3129 clk_base + PLLU_BASE, 16, 4, 0,
3130 pll_vco_post_div_table, NULL);
3131 clk_register_clkdev(clk, "pll_u_out", NULL);
3132 clks[TEGRA210_CLK_PLL_U_OUT] = clk;
3135 clk = tegra_clk_register_divider("pll_u_out1_div", "pll_u_out",
3136 clk_base + PLLU_OUTA, 0,
3137 TEGRA_DIVIDER_ROUND_UP,
3138 8, 8, 1, &pll_u_lock);
3139 clk = tegra_clk_register_pll_out("pll_u_out1", "pll_u_out1_div",
3140 clk_base + PLLU_OUTA, 1, 0,
3141 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
3142 clk_register_clkdev(clk, "pll_u_out1", NULL);
3143 clks[TEGRA210_CLK_PLL_U_OUT1] = clk;
3146 clk = tegra_clk_register_divider("pll_u_out2_div", "pll_u_out",
3147 clk_base + PLLU_OUTA, 0,
3148 TEGRA_DIVIDER_ROUND_UP,
3149 24, 8, 1, &pll_u_lock);
3150 clk = tegra_clk_register_pll_out("pll_u_out2", "pll_u_out2_div",
3151 clk_base + PLLU_OUTA, 17, 16,
3152 CLK_SET_RATE_PARENT, 0, &pll_u_lock);
3153 clk_register_clkdev(clk, "pll_u_out2", NULL);
3154 clks[TEGRA210_CLK_PLL_U_OUT2] = clk;
3157 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u_vco",
3158 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3159 22, 0, &pll_u_lock);
3160 clk_register_clkdev(clk, "pll_u_480M", NULL);
3161 clks[TEGRA210_CLK_PLL_U_480M] = clk;
3164 clk = clk_register_gate(NULL, "pll_u_60M", "pll_u_out2",
3165 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3166 23, 0, &pll_u_lock);
3167 clk_register_clkdev(clk, "pll_u_60M", NULL);
3168 clks[TEGRA210_CLK_PLL_U_60M] = clk;
3171 clk = clk_register_gate(NULL, "pll_u_48M", "pll_u_out1",
3172 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
3173 25, 0, &pll_u_lock);
3174 clk_register_clkdev(clk, "pll_u_48M", NULL);
3175 clks[TEGRA210_CLK_PLL_U_48M] = clk;
3178 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
3179 &pll_d_params, &pll_d_lock);
3180 clk_register_clkdev(clk, "pll_d", NULL);
3181 clks[TEGRA210_CLK_PLL_D] = clk;
3184 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
3185 CLK_SET_RATE_PARENT, 1, 2);
3186 clk_register_clkdev(clk, "pll_d_out0", NULL);
3187 clks[TEGRA210_CLK_PLL_D_OUT0] = clk;
3190 clk = tegra_clk_register_pllre_tegra210("pll_re_vco", "pll_ref",
3193 &pll_re_lock, pll_ref_freq);
3194 clk_register_clkdev(clk, "pll_re_vco", NULL);
3195 clks[TEGRA210_CLK_PLL_RE_VCO] = clk;
3197 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
3198 clk_base + PLLRE_BASE, 16, 5, 0,
3199 pll_vco_post_div_table, &pll_re_lock);
3200 clk_register_clkdev(clk, "pll_re_out", NULL);
3201 clks[TEGRA210_CLK_PLL_RE_OUT] = clk;
3203 clk = tegra_clk_register_divider("pll_re_out1_div", "pll_re_vco",
3204 clk_base + PLLRE_OUT1, 0,
3205 TEGRA_DIVIDER_ROUND_UP,
3207 clk = tegra_clk_register_pll_out("pll_re_out1", "pll_re_out1_div",
3208 clk_base + PLLRE_OUT1, 1, 0,
3209 CLK_SET_RATE_PARENT, 0, NULL);
3210 clks[TEGRA210_CLK_PLL_RE_OUT1] = clk;
3213 clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref",
3214 clk_base, 0, &pll_e_params, NULL);
3215 clk_register_clkdev(clk, "pll_e", NULL);
3216 clks[TEGRA210_CLK_PLL_E] = clk;
3219 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc,
3220 0, &pll_c4_vco_params, NULL, pll_ref_freq);
3221 clk_register_clkdev(clk, "pll_c4_vco", NULL);
3222 clks[TEGRA210_CLK_PLL_C4] = clk;
3225 clk = clk_register_divider_table(NULL, "pll_c4_out0", "pll_c4_vco", 0,
3226 clk_base + PLLC4_BASE, 19, 4, 0,
3227 pll_vco_post_div_table, NULL);
3228 clk_register_clkdev(clk, "pll_c4_out0", NULL);
3229 clks[TEGRA210_CLK_PLL_C4_OUT0] = clk;
3232 clk = clk_register_fixed_factor(NULL, "pll_c4_out1", "pll_c4_vco",
3233 CLK_SET_RATE_PARENT, 1, 3);
3234 clk_register_clkdev(clk, "pll_c4_out1", NULL);
3235 clks[TEGRA210_CLK_PLL_C4_OUT1] = clk;
3238 clk = clk_register_fixed_factor(NULL, "pll_c4_out2", "pll_c4_vco",
3239 CLK_SET_RATE_PARENT, 1, 5);
3240 clk_register_clkdev(clk, "pll_c4_out2", NULL);
3241 clks[TEGRA210_CLK_PLL_C4_OUT2] = clk;
3244 clk = tegra_clk_register_divider("pll_c4_out3_div", "pll_c4_out0",
3245 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
3247 clk = tegra_clk_register_pll_out("pll_c4_out3", "pll_c4_out3_div",
3248 clk_base + PLLC4_OUT, 1, 0,
3249 CLK_SET_RATE_PARENT, 0, NULL);
3250 clk_register_clkdev(clk, "pll_c4_out3", NULL);
3251 clks[TEGRA210_CLK_PLL_C4_OUT3] = clk;
3254 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base,
3255 0, &pll_dp_params, NULL);
3256 clk_register_clkdev(clk, "pll_dp", NULL);
3257 clks[TEGRA210_CLK_PLL_DP] = clk;
3260 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base,
3261 0, &pll_d2_params, NULL);
3262 clk_register_clkdev(clk, "pll_d2", NULL);
3263 clks[TEGRA210_CLK_PLL_D2] = clk;
3266 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
3267 CLK_SET_RATE_PARENT, 1, 1);
3268 clk_register_clkdev(clk, "pll_d2_out0", NULL);
3269 clks[TEGRA210_CLK_PLL_D2_OUT0] = clk;
3272 clk = clk_register_fixed_factor(NULL, "pll_p_out2", "pll_p",
3273 CLK_SET_RATE_PARENT, 1, 2);
3274 clk_register_clkdev(clk, "pll_p_out2", NULL);
3275 clks[TEGRA210_CLK_PLL_P_OUT2] = clk;
3279 /* Tegra210 CPU clock and reset control functions */
3280 static void tegra210_wait_cpu_in_reset(u32 cpu)
3285 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
3287 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
3290 static void tegra210_disable_cpu_clock(u32 cpu)
3292 /* flow controller would take care in the power sequence. */
3295 #ifdef CONFIG_PM_SLEEP
3296 static void tegra210_cpu_clock_suspend(void)
3298 /* switch coresite to clk_m, save off original source */
3299 tegra210_cpu_clk_sctx.clk_csite_src =
3300 readl(clk_base + CLK_SOURCE_CSITE);
3301 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
3304 static void tegra210_cpu_clock_resume(void)
3306 writel(tegra210_cpu_clk_sctx.clk_csite_src,
3307 clk_base + CLK_SOURCE_CSITE);
3311 static struct tegra_cpu_car_ops tegra210_cpu_car_ops = {
3312 .wait_for_reset = tegra210_wait_cpu_in_reset,
3313 .disable_clock = tegra210_disable_cpu_clock,
3314 #ifdef CONFIG_PM_SLEEP
3315 .suspend = tegra210_cpu_clock_suspend,
3316 .resume = tegra210_cpu_clock_resume,
3320 static const struct of_device_id pmc_match[] __initconst = {
3321 { .compatible = "nvidia,tegra210-pmc" },
3325 static struct tegra_clk_init_table init_table[] __initdata = {
3326 { TEGRA210_CLK_UARTA, TEGRA210_CLK_PLL_P, 408000000, 0 },
3327 { TEGRA210_CLK_UARTB, TEGRA210_CLK_PLL_P, 408000000, 0 },
3328 { TEGRA210_CLK_UARTC, TEGRA210_CLK_PLL_P, 408000000, 0 },
3329 { TEGRA210_CLK_UARTD, TEGRA210_CLK_PLL_P, 408000000, 0 },
3330 { TEGRA210_CLK_PLL_A, TEGRA210_CLK_CLK_MAX, 564480000, 1 },
3331 { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 1 },
3332 { TEGRA210_CLK_EXTERN1, TEGRA210_CLK_PLL_A_OUT0, 0, 1 },
3333 { TEGRA210_CLK_CLK_OUT_1_MUX, TEGRA210_CLK_EXTERN1, 0, 1 },
3334 { TEGRA210_CLK_CLK_OUT_1, TEGRA210_CLK_CLK_MAX, 0, 1 },
3335 { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3336 { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3337 { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3338 { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3339 { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3340 { TEGRA210_CLK_HOST1X, TEGRA210_CLK_PLL_P, 136000000, 1 },
3341 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
3342 { TEGRA210_CLK_SCLK, TEGRA210_CLK_CLK_MAX, 102000000, 0 },
3343 { TEGRA210_CLK_DFLL_SOC, TEGRA210_CLK_PLL_P, 51000000, 1 },
3344 { TEGRA210_CLK_DFLL_REF, TEGRA210_CLK_PLL_P, 51000000, 1 },
3345 { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
3346 { TEGRA210_CLK_PLL_RE_VCO, TEGRA210_CLK_CLK_MAX, 672000000, 1 },
3347 { TEGRA210_CLK_XUSB_GATE, TEGRA210_CLK_CLK_MAX, 0, 1 },
3348 { TEGRA210_CLK_XUSB_SS_SRC, TEGRA210_CLK_PLL_U_480M, 120000000, 0 },
3349 { TEGRA210_CLK_XUSB_FS_SRC, TEGRA210_CLK_PLL_U_48M, 48000000, 0 },
3350 { TEGRA210_CLK_XUSB_HS_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
3351 { TEGRA210_CLK_XUSB_SSP_SRC, TEGRA210_CLK_XUSB_SS_SRC, 120000000, 0 },
3352 { TEGRA210_CLK_XUSB_FALCON_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 204000000, 0 },
3353 { TEGRA210_CLK_XUSB_HOST_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
3354 { TEGRA210_CLK_XUSB_DEV_SRC, TEGRA210_CLK_PLL_P_OUT_XUSB, 102000000, 0 },
3355 { TEGRA210_CLK_SATA, TEGRA210_CLK_PLL_P, 104000000, 0 },
3356 { TEGRA210_CLK_SATA_OOB, TEGRA210_CLK_PLL_P, 204000000, 0 },
3357 { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
3358 { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
3359 /* TODO find a way to enable this on-demand */
3360 { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
3361 { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
3362 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
3363 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
3364 { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 },
3365 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },
3366 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },
3367 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },
3368 { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 },
3369 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
3370 { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
3371 { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
3372 { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
3373 /* This MUST be the last entry. */
3374 { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
3378 * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs
3380 * Program an initial clock rate and enable or disable clocks needed
3381 * by the rest of the kernel, for Tegra210 SoCs. It is intended to be
3382 * called by assigning a pointer to it to tegra_clk_apply_init_table -
3383 * this will be called as an arch_initcall. No return value.
3385 static void __init tegra210_clock_apply_init_table(void)
3387 tegra_init_from_table(init_table, clks, TEGRA210_CLK_CLK_MAX);
3391 * tegra210_car_barrier - wait for pending writes to the CAR to complete
3393 * Wait for any outstanding writes to the CAR MMIO space from this CPU
3394 * to complete before continuing execution. No return value.
3396 static void tegra210_car_barrier(void)
3398 readl_relaxed(clk_base + RST_DFLL_DVCO);
3402 * tegra210_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
3404 * Assert the reset line of the DFLL's DVCO. No return value.
3406 static void tegra210_clock_assert_dfll_dvco_reset(void)
3410 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3411 v |= (1 << DVFS_DFLL_RESET_SHIFT);
3412 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3413 tegra210_car_barrier();
3417 * tegra210_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
3419 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
3420 * operate. No return value.
3422 static void tegra210_clock_deassert_dfll_dvco_reset(void)
3426 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3427 v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
3428 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3429 tegra210_car_barrier();
3432 static int tegra210_reset_assert(unsigned long id)
3434 if (id == TEGRA210_RST_DFLL_DVCO)
3435 tegra210_clock_assert_dfll_dvco_reset();
3436 else if (id == TEGRA210_RST_ADSP)
3437 writel(GENMASK(26, 21) | BIT(7),
3438 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET);
3445 static int tegra210_reset_deassert(unsigned long id)
3447 if (id == TEGRA210_RST_DFLL_DVCO)
3448 tegra210_clock_deassert_dfll_dvco_reset();
3449 else if (id == TEGRA210_RST_ADSP) {
3450 writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3452 * Considering adsp cpu clock (min: 12.5MHZ, max: 1GHz)
3453 * a delay of 5us ensures that it's at least
3454 * 6 * adsp_cpu_cycle_period long.
3457 writel(GENMASK(26, 22) | BIT(7),
3458 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3465 static void tegra210_mbist_clk_init(void)
3469 for (i = 0; i < ARRAY_SIZE(tegra210_pg_mbist_war); i++) {
3470 unsigned int num_clks = tegra210_pg_mbist_war[i].num_clks;
3471 struct clk_bulk_data *clk_data;
3476 clk_data = kmalloc_array(num_clks, sizeof(*clk_data),
3478 if (WARN_ON(!clk_data))
3481 tegra210_pg_mbist_war[i].clks = clk_data;
3482 for (j = 0; j < num_clks; j++) {
3483 int clk_id = tegra210_pg_mbist_war[i].clk_init_data[j];
3484 struct clk *clk = clks[clk_id];
3486 if (WARN(IS_ERR(clk), "clk_id: %d\n", clk_id)) {
3488 tegra210_pg_mbist_war[i].clks = NULL;
3491 clk_data[j].clk = clk;
3497 * tegra210_clock_init - Tegra210-specific clock initialization
3498 * @np: struct device_node * of the DT node for the SoC CAR IP block
3500 * Register most SoC clocks for the Tegra210 system-on-chip. Intended
3501 * to be called by the OF init code when a DT node with the
3502 * "nvidia,tegra210-car" string is encountered, and declared with
3503 * CLK_OF_DECLARE. No return value.
3505 static void __init tegra210_clock_init(struct device_node *np)
3507 struct device_node *node;
3508 u32 value, clk_m_div;
3510 clk_base = of_iomap(np, 0);
3512 pr_err("ioremap tegra210 CAR failed\n");
3516 node = of_find_matching_node(NULL, pmc_match);
3518 pr_err("Failed to find pmc node\n");
3523 pmc_base = of_iomap(node, 0);
3525 pr_err("Can't map pmc registers\n");
3530 ahub_base = ioremap(TEGRA210_AHUB_BASE, SZ_64K);
3532 pr_err("ioremap tegra210 APE failed\n");
3536 dispa_base = ioremap(TEGRA210_DISPA_BASE, SZ_256K);
3538 pr_err("ioremap tegra210 DISPA failed\n");
3542 vic_base = ioremap(TEGRA210_VIC_BASE, SZ_256K);
3544 pr_err("ioremap tegra210 VIC failed\n");
3548 clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX,
3549 TEGRA210_CAR_BANK_COUNT);
3553 value = clk_readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
3554 clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1;
3556 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,
3557 ARRAY_SIZE(tegra210_input_freq), clk_m_div,
3558 &osc_freq, &pll_ref_freq) < 0)
3561 tegra_fixed_clk_init(tegra210_clks);
3562 tegra210_pll_init(clk_base, pmc_base);
3563 tegra210_periph_clk_init(clk_base, pmc_base);
3564 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
3565 tegra210_audio_plls,
3566 ARRAY_SIZE(tegra210_audio_plls));
3567 tegra_pmc_clk_init(pmc_base, tegra210_clks);
3569 /* For Tegra210, PLLD is the only source for DSIA & DSIB */
3570 value = clk_readl(clk_base + PLLD_BASE);
3572 clk_writel(value, clk_base + PLLD_BASE);
3574 tegra_clk_apply_init_table = tegra210_clock_apply_init_table;
3576 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks,
3578 tegra_init_special_resets(2, tegra210_reset_assert,
3579 tegra210_reset_deassert);
3581 tegra_add_of_provider(np, of_clk_src_onecell_get);
3582 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
3584 tegra210_mbist_clk_init();
3586 tegra_cpu_car_ops = &tegra210_cpu_car_ops;
3588 CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init);