drivers/clk/tegra/clk-pll.c

   1 /*
   2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/slab.h>
  18 #include <linux/io.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/clk-provider.h>
  23
  24 #include "clk.h"
  25
  26 #define PLL_BASE_BYPASS BIT(31)
  27 #define PLL_BASE_ENABLE BIT(30)
  28 #define PLL_BASE_REF_ENABLE BIT(29)
  29 #define PLL_BASE_OVERRIDE BIT(28)
  30
  31 #define PLL_BASE_DIVP_SHIFT 20
  32 #define PLL_BASE_DIVP_WIDTH 3
  33 #define PLL_BASE_DIVN_SHIFT 8
  34 #define PLL_BASE_DIVN_WIDTH 10
  35 #define PLL_BASE_DIVM_SHIFT 0
  36 #define PLL_BASE_DIVM_WIDTH 5
  37 #define PLLU_POST_DIVP_MASK 0x1
  38
  39 #define PLL_MISC_DCCON_SHIFT 20
  40 #define PLL_MISC_CPCON_SHIFT 8
  41 #define PLL_MISC_CPCON_WIDTH 4
  42 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
  43 #define PLL_MISC_LFCON_SHIFT 4
  44 #define PLL_MISC_LFCON_WIDTH 4
  45 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
  46 #define PLL_MISC_VCOCON_SHIFT 0
  47 #define PLL_MISC_VCOCON_WIDTH 4
  48 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
  49
  50 #define OUT_OF_TABLE_CPCON 8
  51
  52 #define PMC_PLLP_WB0_OVERRIDE 0xf8
  53 #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12)
  54 #define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11)
  55
  56 #define PLL_POST_LOCK_DELAY 50
  57
  58 #define PLLDU_LFCON_SET_DIVN 600
  59
  60 #define PLLE_BASE_DIVCML_SHIFT 24
  61 #define PLLE_BASE_DIVCML_MASK 0xf
  62 #define PLLE_BASE_DIVP_SHIFT 16
  63 #define PLLE_BASE_DIVP_WIDTH 6
  64 #define PLLE_BASE_DIVN_SHIFT 8
  65 #define PLLE_BASE_DIVN_WIDTH 8
  66 #define PLLE_BASE_DIVM_SHIFT 0
  67 #define PLLE_BASE_DIVM_WIDTH 8
  68 #define PLLE_BASE_ENABLE BIT(31)
  69
  70 #define PLLE_MISC_SETUP_BASE_SHIFT 16
  71 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
  72 #define PLLE_MISC_LOCK_ENABLE BIT(9)
  73 #define PLLE_MISC_READY BIT(15)
  74 #define PLLE_MISC_SETUP_EX_SHIFT 2
  75 #define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT)
  76 #define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK |       \
  77                               PLLE_MISC_SETUP_EX_MASK)
  78 #define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT)
  79
  80 #define PLLE_SS_CTRL 0x68
  81 #define PLLE_SS_CNTL_BYPASS_SS BIT(10)
  82 #define PLLE_SS_CNTL_INTERP_RESET BIT(11)
  83 #define PLLE_SS_CNTL_SSC_BYP BIT(12)
  84 #define PLLE_SS_CNTL_CENTER BIT(14)
  85 #define PLLE_SS_CNTL_INVERT BIT(15)
  86 #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\
  87                                 PLLE_SS_CNTL_SSC_BYP)
  88 #define PLLE_SS_MAX_MASK 0x1ff
  89 #define PLLE_SS_MAX_VAL_TEGRA114 0x25
  90 #define PLLE_SS_MAX_VAL_TEGRA210 0x21
  91 #define PLLE_SS_INC_MASK (0xff << 16)
  92 #define PLLE_SS_INC_VAL (0x1 << 16)
  93 #define PLLE_SS_INCINTRV_MASK (0x3f << 24)
  94 #define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24)
  95 #define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24)
  96 #define PLLE_SS_COEFFICIENTS_MASK \
  97         (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK)
  98 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \
  99         (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\
 100          PLLE_SS_INCINTRV_VAL_TEGRA114)
 101 #define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \
 102         (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\
 103          PLLE_SS_INCINTRV_VAL_TEGRA210)
 104
 105 #define PLLE_AUX_PLLP_SEL       BIT(2)
 106 #define PLLE_AUX_USE_LOCKDET    BIT(3)
 107 #define PLLE_AUX_ENABLE_SWCTL   BIT(4)
 108 #define PLLE_AUX_SS_SWCTL       BIT(6)
 109 #define PLLE_AUX_SEQ_ENABLE     BIT(24)
 110 #define PLLE_AUX_SEQ_START_STATE BIT(25)
 111 #define PLLE_AUX_PLLRE_SEL      BIT(28)
 112 #define PLLE_AUX_SS_SEQ_INCLUDE BIT(31)
 113
 114 #define XUSBIO_PLL_CFG0         0x51c
 115 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL      BIT(0)
 116 #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL        BIT(2)
 117 #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET      BIT(6)
 118 #define XUSBIO_PLL_CFG0_SEQ_ENABLE              BIT(24)
 119 #define XUSBIO_PLL_CFG0_SEQ_START_STATE         BIT(25)
 120
 121 #define SATA_PLL_CFG0           0x490
 122 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL        BIT(0)
 123 #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET        BIT(2)
 124 #define SATA_PLL_CFG0_SEQ_ENABLE                BIT(24)
 125 #define SATA_PLL_CFG0_SEQ_START_STATE           BIT(25)
 126
 127 #define PLLE_MISC_PLLE_PTS      BIT(8)
 128 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
 129 #define PLLE_MISC_IDDQ_SW_CTRL  BIT(14)
 130 #define PLLE_MISC_VREG_BG_CTRL_SHIFT    4
 131 #define PLLE_MISC_VREG_BG_CTRL_MASK     (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT)
 132 #define PLLE_MISC_VREG_CTRL_SHIFT       2
 133 #define PLLE_MISC_VREG_CTRL_MASK        (2 << PLLE_MISC_VREG_CTRL_SHIFT)
 134
 135 #define PLLCX_MISC_STROBE       BIT(31)
 136 #define PLLCX_MISC_RESET        BIT(30)
 137 #define PLLCX_MISC_SDM_DIV_SHIFT 28
 138 #define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT)
 139 #define PLLCX_MISC_FILT_DIV_SHIFT 26
 140 #define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT)
 141 #define PLLCX_MISC_ALPHA_SHIFT 18
 142 #define PLLCX_MISC_DIV_LOW_RANGE \
 143                 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 144                 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT))
 145 #define PLLCX_MISC_DIV_HIGH_RANGE \
 146                 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \
 147                 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT))
 148 #define PLLCX_MISC_COEF_LOW_RANGE \
 149                 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT))
 150 #define PLLCX_MISC_KA_SHIFT 2
 151 #define PLLCX_MISC_KB_SHIFT 9
 152 #define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \
 153                             (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \
 154                             PLLCX_MISC_DIV_LOW_RANGE | \
 155                             PLLCX_MISC_RESET)
 156 #define PLLCX_MISC1_DEFAULT 0x000d2308
 157 #define PLLCX_MISC2_DEFAULT 0x30211200
 158 #define PLLCX_MISC3_DEFAULT 0x200
 159
 160 #define PMC_SATA_PWRGT 0x1ac
 161 #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5)
 162 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4)
 163
 164 #define PLLSS_MISC_KCP          0
 165 #define PLLSS_MISC_KVCO         0
 166 #define PLLSS_MISC_SETUP        0
 167 #define PLLSS_EN_SDM            0
 168 #define PLLSS_EN_SSC            0
 169 #define PLLSS_EN_DITHER2        0
 170 #define PLLSS_EN_DITHER         1
 171 #define PLLSS_SDM_RESET         0
 172 #define PLLSS_CLAMP             0
 173 #define PLLSS_SDM_SSC_MAX       0
 174 #define PLLSS_SDM_SSC_MIN       0
 175 #define PLLSS_SDM_SSC_STEP      0
 176 #define PLLSS_SDM_DIN           0
 177 #define PLLSS_MISC_DEFAULT ((PLLSS_MISC_KCP << 25) | \
 178                             (PLLSS_MISC_KVCO << 24) | \
 179                             PLLSS_MISC_SETUP)
 180 #define PLLSS_CFG_DEFAULT ((PLLSS_EN_SDM << 31) | \
 181                            (PLLSS_EN_SSC << 30) | \
 182                            (PLLSS_EN_DITHER2 << 29) | \
 183                            (PLLSS_EN_DITHER << 28) | \
 184                            (PLLSS_SDM_RESET) << 27 | \
 185                            (PLLSS_CLAMP << 22))
 186 #define PLLSS_CTRL1_DEFAULT \
 187                         ((PLLSS_SDM_SSC_MAX << 16) | PLLSS_SDM_SSC_MIN)
 188 #define PLLSS_CTRL2_DEFAULT \
 189                         ((PLLSS_SDM_SSC_STEP << 16) | PLLSS_SDM_DIN)
 190 #define PLLSS_LOCK_OVERRIDE     BIT(24)
 191 #define PLLSS_REF_SRC_SEL_SHIFT 25
 192 #define PLLSS_REF_SRC_SEL_MASK  (3 << PLLSS_REF_SRC_SEL_SHIFT)
 193
 194 #define UTMIP_PLL_CFG1 0x484
 195 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
 196 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
 197 #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
 198 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
 199 #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
 200 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
 201 #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
 202
 203 #define UTMIP_PLL_CFG2 0x488
 204 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
 205 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
 206 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
 207 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
 208 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
 209 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
 210 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
 211 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
 212 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
 213 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
 214 #define UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN BIT(30)
 215
 216 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
 217 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
 218 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
 219 #define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
 220 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4)
 221 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5)
 222 #define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
 223 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
 224 #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25)
 225
 226 #define PLLU_HW_PWRDN_CFG0 0x530
 227 #define PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL BIT(0)
 228 #define PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2)
 229 #define PLLU_HW_PWRDN_CFG0_USE_LOCKDET BIT(6)
 230 #define PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT BIT(7)
 231 #define PLLU_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24)
 232 #define PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE BIT(28)
 233
 234 #define XUSB_PLL_CFG0 0x534
 235 #define XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY 0x3ff
 236 #define XUSB_PLL_CFG0_PLLU_LOCK_DLY (0x3ff << 14)
 237
 238 #define PLLU_BASE_CLKENABLE_USB BIT(21)
 239 #define PLLU_BASE_OVERRIDE BIT(24)
 240
 241 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
 242 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
 243 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
 244 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
 245 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
 246 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
 247
 248 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
 249 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
 250 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
 251 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
 252 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
 253 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
 254
 255 #define mask(w) ((1 << (w)) - 1)
 256 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
 257 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
 258 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
 259                       mask(p->params->div_nmp->divp_width))
 260 #define sdm_din_mask(p) p->params->sdm_din_mask
 261 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
 262
 263 #define divm_shift(p) (p)->params->div_nmp->divm_shift
 264 #define divn_shift(p) (p)->params->div_nmp->divn_shift
 265 #define divp_shift(p) (p)->params->div_nmp->divp_shift
 266
 267 #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p))
 268 #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p))
 269 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
 270
 271 #define divm_max(p) (divm_mask(p))
 272 #define divn_max(p) (divn_mask(p))
 273 #define divp_max(p) (1 << (divp_mask(p)))
 274
 275 #define sdin_din_to_data(din)   ((u16)((din) ? : 0xFFFFU))
 276 #define sdin_data_to_din(dat)   (((dat) == 0xFFFFU) ? 0 : (s16)dat)
 277
 278 static struct div_nmp default_nmp = {
 279         .divn_shift = PLL_BASE_DIVN_SHIFT,
 280         .divn_width = PLL_BASE_DIVN_WIDTH,
 281         .divm_shift = PLL_BASE_DIVM_SHIFT,
 282         .divm_width = PLL_BASE_DIVM_WIDTH,
 283         .divp_shift = PLL_BASE_DIVP_SHIFT,
 284         .divp_width = PLL_BASE_DIVP_WIDTH,
 285 };
 286
 287 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)
 288 {
 289         u32 val;
 290
 291         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))
 292                 return;
 293
 294         if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))
 295                 return;
 296
 297         val = pll_readl_misc(pll);
 298         val |= BIT(pll->params->lock_enable_bit_idx);
 299         pll_writel_misc(val, pll);
 300 }
 301
 302 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)
 303 {
 304         int i;
 305         u32 val, lock_mask;
 306         void __iomem *lock_addr;
 307
 308         if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {
 309                 udelay(pll->params->lock_delay);
 310                 return 0;
 311         }
 312
 313         lock_addr = pll->clk_base;
 314         if (pll->params->flags & TEGRA_PLL_LOCK_MISC)
 315                 lock_addr += pll->params->misc_reg;
 316         else
 317                 lock_addr += pll->params->base_reg;
 318
 319         lock_mask = pll->params->lock_mask;
 320
 321         for (i = 0; i < pll->params->lock_delay; i++) {
 322                 val = readl_relaxed(lock_addr);
 323                 if ((val & lock_mask) == lock_mask) {
 324                         udelay(PLL_POST_LOCK_DELAY);
 325                         return 0;
 326                 }
 327                 udelay(2); /* timeout = 2 * lock time */
 328         }
 329
 330         pr_err("%s: Timed out waiting for pll %s lock\n", __func__,
 331                clk_hw_get_name(&pll->hw));
 332
 333         return -1;
 334 }
 335
 336 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll)
 337 {
 338         return clk_pll_wait_for_lock(pll);
 339 }
 340
 341 static int clk_pll_is_enabled(struct clk_hw *hw)
 342 {
 343         struct tegra_clk_pll *pll = to_clk_pll(hw);
 344         u32 val;
 345
 346         if (pll->params->flags & TEGRA_PLLM) {
 347                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 348                 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)
 349                         return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;
 350         }
 351
 352         val = pll_readl_base(pll);
 353
 354         return val & PLL_BASE_ENABLE ? 1 : 0;
 355 }
 356
 357 static void _clk_pll_enable(struct clk_hw *hw)
 358 {
 359         struct tegra_clk_pll *pll = to_clk_pll(hw);
 360         u32 val;
 361
 362         if (pll->params->iddq_reg) {
 363                 val = pll_readl(pll->params->iddq_reg, pll);
 364                 val &= ~BIT(pll->params->iddq_bit_idx);
 365                 pll_writel(val, pll->params->iddq_reg, pll);
 366                 udelay(5);
 367         }
 368
 369         if (pll->params->reset_reg) {
 370                 val = pll_readl(pll->params->reset_reg, pll);
 371                 val &= ~BIT(pll->params->reset_bit_idx);
 372                 pll_writel(val, pll->params->reset_reg, pll);
 373         }
 374
 375         clk_pll_enable_lock(pll);
 376
 377         val = pll_readl_base(pll);
 378         if (pll->params->flags & TEGRA_PLL_BYPASS)
 379                 val &= ~PLL_BASE_BYPASS;
 380         val |= PLL_BASE_ENABLE;
 381         pll_writel_base(val, pll);
 382
 383         if (pll->params->flags & TEGRA_PLLM) {
 384                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 385                 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 386                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 387         }
 388 }
 389
 390 static void _clk_pll_disable(struct clk_hw *hw)
 391 {
 392         struct tegra_clk_pll *pll = to_clk_pll(hw);
 393         u32 val;
 394
 395         val = pll_readl_base(pll);
 396         if (pll->params->flags & TEGRA_PLL_BYPASS)
 397                 val &= ~PLL_BASE_BYPASS;
 398         val &= ~PLL_BASE_ENABLE;
 399         pll_writel_base(val, pll);
 400
 401         if (pll->params->flags & TEGRA_PLLM) {
 402                 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 403                 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
 404                 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
 405         }
 406
 407         if (pll->params->reset_reg) {
 408                 val = pll_readl(pll->params->reset_reg, pll);
 409                 val |= BIT(pll->params->reset_bit_idx);
 410                 pll_writel(val, pll->params->reset_reg, pll);
 411         }
 412
 413         if (pll->params->iddq_reg) {
 414                 val = pll_readl(pll->params->iddq_reg, pll);
 415                 val |= BIT(pll->params->iddq_bit_idx);
 416                 pll_writel(val, pll->params->iddq_reg, pll);
 417                 udelay(2);
 418         }
 419 }
 420
 421 static void pll_clk_start_ss(struct tegra_clk_pll *pll)
 422 {
 423         if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 424                 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 425
 426                 val |= pll->params->ssc_ctrl_en_mask;
 427                 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 428         }
 429 }
 430
 431 static void pll_clk_stop_ss(struct tegra_clk_pll *pll)
 432 {
 433         if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) {
 434                 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
 435
 436                 val &= ~pll->params->ssc_ctrl_en_mask;
 437                 pll_writel(val, pll->params->ssc_ctrl_reg, pll);
 438         }
 439 }
 440
 441 static int clk_pll_enable(struct clk_hw *hw)
 442 {
 443         struct tegra_clk_pll *pll = to_clk_pll(hw);
 444         unsigned long flags = 0;
 445         int ret;
 446
 447         if (pll->lock)
 448                 spin_lock_irqsave(pll->lock, flags);
 449
 450         _clk_pll_enable(hw);
 451
 452         ret = clk_pll_wait_for_lock(pll);
 453
 454         pll_clk_start_ss(pll);
 455
 456         if (pll->lock)
 457                 spin_unlock_irqrestore(pll->lock, flags);
 458
 459         return ret;
 460 }
 461
 462 static void clk_pll_disable(struct clk_hw *hw)
 463 {
 464         struct tegra_clk_pll *pll = to_clk_pll(hw);
 465         unsigned long flags = 0;
 466
 467         if (pll->lock)
 468                 spin_lock_irqsave(pll->lock, flags);
 469
 470         pll_clk_stop_ss(pll);
 471
 472         _clk_pll_disable(hw);
 473
 474         if (pll->lock)
 475                 spin_unlock_irqrestore(pll->lock, flags);
 476 }
 477
 478 static int _p_div_to_hw(struct clk_hw *hw, u8 p_div)
 479 {
 480         struct tegra_clk_pll *pll = to_clk_pll(hw);
 481         const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 482
 483         if (p_tohw) {
 484                 while (p_tohw->pdiv) {
 485                         if (p_div <= p_tohw->pdiv)
 486                                 return p_tohw->hw_val;
 487                         p_tohw++;
 488                 }
 489                 return -EINVAL;
 490         }
 491         return -EINVAL;
 492 }
 493
 494 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div)
 495 {
 496         return _p_div_to_hw(&pll->hw, p_div);
 497 }
 498
 499 static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw)
 500 {
 501         struct tegra_clk_pll *pll = to_clk_pll(hw);
 502         const struct pdiv_map *p_tohw = pll->params->pdiv_tohw;
 503
 504         if (p_tohw) {
 505                 while (p_tohw->pdiv) {
 506                         if (p_div_hw == p_tohw->hw_val)
 507                                 return p_tohw->pdiv;
 508                         p_tohw++;
 509                 }
 510                 return -EINVAL;
 511         }
 512
 513         return 1 << p_div_hw;
 514 }
 515
 516 static int _get_table_rate(struct clk_hw *hw,
 517                            struct tegra_clk_pll_freq_table *cfg,
 518                            unsigned long rate, unsigned long parent_rate)
 519 {
 520         struct tegra_clk_pll *pll = to_clk_pll(hw);
 521         struct tegra_clk_pll_freq_table *sel;
 522         int p;
 523
 524         for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
 525                 if (sel->input_rate == parent_rate &&
 526                     sel->output_rate == rate)
 527                         break;
 528
 529         if (sel->input_rate == 0)
 530                 return -EINVAL;
 531
 532         if (pll->params->pdiv_tohw) {
 533                 p = _p_div_to_hw(hw, sel->p);
 534                 if (p < 0)
 535                         return p;
 536         } else {
 537                 p = ilog2(sel->p);
 538         }
 539
 540         cfg->input_rate = sel->input_rate;
 541         cfg->output_rate = sel->output_rate;
 542         cfg->m = sel->m;
 543         cfg->n = sel->n;
 544         cfg->p = p;
 545         cfg->cpcon = sel->cpcon;
 546         cfg->sdm_data = sel->sdm_data;
 547
 548         return 0;
 549 }
 550
 551 static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 552                       unsigned long rate, unsigned long parent_rate)
 553 {
 554         struct tegra_clk_pll *pll = to_clk_pll(hw);
 555         unsigned long cfreq;
 556         u32 p_div = 0;
 557         int ret;
 558
 559         switch (parent_rate) {
 560         case 12000000:
 561         case 26000000:
 562                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
 563                 break;
 564         case 13000000:
 565                 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
 566                 break;
 567         case 16800000:
 568         case 19200000:
 569                 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
 570                 break;
 571         case 9600000:
 572         case 28800000:
 573                 /*
 574                  * PLL_P_OUT1 rate is not listed in PLLA table
 575                  */
 576                 cfreq = parent_rate / (parent_rate / 1000000);
 577                 break;
 578         default:
 579                 pr_err("%s Unexpected reference rate %lu\n",
 580                        __func__, parent_rate);
 581                 BUG();
 582         }
 583
 584         /* Raise VCO to guarantee 0.5% accuracy */
 585         for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
 586              cfg->output_rate <<= 1)
 587                 p_div++;
 588
 589         cfg->m = parent_rate / cfreq;
 590         cfg->n = cfg->output_rate / cfreq;
 591         cfg->cpcon = OUT_OF_TABLE_CPCON;
 592
 593         if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
 594             (1 << p_div) > divp_max(pll)
 595             || cfg->output_rate > pll->params->vco_max) {
 596                 return -EINVAL;
 597         }
 598
 599         cfg->output_rate >>= p_div;
 600
 601         if (pll->params->pdiv_tohw) {
 602                 ret = _p_div_to_hw(hw, 1 << p_div);
 603                 if (ret < 0)
 604                         return ret;
 605                 else
 606                         cfg->p = ret;
 607         } else
 608                 cfg->p = p_div;
 609
 610         return 0;
 611 }
 612
 613 /*
 614  * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
 615  * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
 616  * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
 617  * to indicate that SDM is disabled.
 618  *
 619  * Effective ndiv value when SDM is enabled: ndiv + 1/2 + sdm_din/2^13
 620  */
 621 static void clk_pll_set_sdm_data(struct clk_hw *hw,
 622                                  struct tegra_clk_pll_freq_table *cfg)
 623 {
 624         struct tegra_clk_pll *pll = to_clk_pll(hw);
 625         u32 val;
 626         bool enabled;
 627
 628         if (!pll->params->sdm_din_reg)
 629                 return;
 630
 631         if (cfg->sdm_data) {
 632                 val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
 633                 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
 634                 pll_writel_sdm_din(val, pll);
 635         }
 636
 637         val = pll_readl_sdm_ctrl(pll);
 638         enabled = (val & sdm_en_mask(pll));
 639
 640         if (cfg->sdm_data == 0 && enabled)
 641                 val &= ~pll->params->sdm_ctrl_en_mask;
 642
 643         if (cfg->sdm_data != 0 && !enabled)
 644                 val |= pll->params->sdm_ctrl_en_mask;
 645
 646         pll_writel_sdm_ctrl(val, pll);
 647 }
 648
 649 static void _update_pll_mnp(struct tegra_clk_pll *pll,
 650                             struct tegra_clk_pll_freq_table *cfg)
 651 {
 652         u32 val;
 653         struct tegra_clk_pll_params *params = pll->params;
 654         struct div_nmp *div_nmp = params->div_nmp;
 655
 656         if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 657                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 658                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 659                 val = pll_override_readl(params->pmc_divp_reg, pll);
 660                 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
 661                 val |= cfg->p << div_nmp->override_divp_shift;
 662                 pll_override_writel(val, params->pmc_divp_reg, pll);
 663
 664                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 665                 val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |
 666                         ~(divn_mask(pll) << div_nmp->override_divn_shift);
 667                 val |= (cfg->m << div_nmp->override_divm_shift) |
 668                         (cfg->n << div_nmp->override_divn_shift);
 669                 pll_override_writel(val, params->pmc_divnm_reg, pll);
 670         } else {
 671                 val = pll_readl_base(pll);
 672
 673                 val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
 674                          divp_mask_shifted(pll));
 675
 676                 val |= (cfg->m << divm_shift(pll)) |
 677                        (cfg->n << divn_shift(pll)) |
 678                        (cfg->p << divp_shift(pll));
 679
 680                 pll_writel_base(val, pll);
 681
 682                 clk_pll_set_sdm_data(&pll->hw, cfg);
 683         }
 684 }
 685
 686 static void _get_pll_mnp(struct tegra_clk_pll *pll,
 687                          struct tegra_clk_pll_freq_table *cfg)
 688 {
 689         u32 val;
 690         struct tegra_clk_pll_params *params = pll->params;
 691         struct div_nmp *div_nmp = params->div_nmp;
 692
 693         *cfg = (struct tegra_clk_pll_freq_table) { };
 694
 695         if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 696                 (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 697                         PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
 698                 val = pll_override_readl(params->pmc_divp_reg, pll);
 699                 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
 700
 701                 val = pll_override_readl(params->pmc_divnm_reg, pll);
 702                 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
 703                 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
 704         }  else {
 705                 val = pll_readl_base(pll);
 706
 707                 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
 708                 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
 709                 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
 710
 711                 if (pll->params->sdm_din_reg) {
 712                         if (sdm_en_mask(pll) & pll_readl_sdm_ctrl(pll)) {
 713                                 val = pll_readl_sdm_din(pll);
 714                                 val &= sdm_din_mask(pll);
 715                                 cfg->sdm_data = sdin_din_to_data(val);
 716                         }
 717                 }
 718         }
 719 }
 720
 721 static void _update_pll_cpcon(struct tegra_clk_pll *pll,
 722                               struct tegra_clk_pll_freq_table *cfg,
 723                               unsigned long rate)
 724 {
 725         u32 val;
 726
 727         val = pll_readl_misc(pll);
 728
 729         val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
 730         val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
 731
 732         if (pll->params->flags & TEGRA_PLL_SET_LFCON) {
 733                 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
 734                 if (cfg->n >= PLLDU_LFCON_SET_DIVN)
 735                         val |= 1 << PLL_MISC_LFCON_SHIFT;
 736         } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {
 737                 val &= ~(1 << PLL_MISC_DCCON_SHIFT);
 738                 if (rate >= (pll->params->vco_max >> 1))
 739                         val |= 1 << PLL_MISC_DCCON_SHIFT;
 740         }
 741
 742         pll_writel_misc(val, pll);
 743 }
 744
 745 static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 746                         unsigned long rate)
 747 {
 748         struct tegra_clk_pll *pll = to_clk_pll(hw);
 749         struct tegra_clk_pll_freq_table old_cfg;
 750         int state, ret = 0;
 751
 752         state = clk_pll_is_enabled(hw);
 753
 754         _get_pll_mnp(pll, &old_cfg);
 755
 756         if (state && pll->params->defaults_set && pll->params->dyn_ramp &&
 757                         (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) {
 758                 ret = pll->params->dyn_ramp(pll, cfg);
 759                 if (!ret)
 760                         return 0;
 761         }
 762
 763         if (state) {
 764                 pll_clk_stop_ss(pll);
 765                 _clk_pll_disable(hw);
 766         }
 767
 768         if (!pll->params->defaults_set && pll->params->set_defaults)
 769                 pll->params->set_defaults(pll);
 770
 771         _update_pll_mnp(pll, cfg);
 772
 773         if (pll->params->flags & TEGRA_PLL_HAS_CPCON)
 774                 _update_pll_cpcon(pll, cfg, rate);
 775
 776         if (state) {
 777                 _clk_pll_enable(hw);
 778                 ret = clk_pll_wait_for_lock(pll);
 779                 pll_clk_start_ss(pll);
 780         }
 781
 782         return ret;
 783 }
 784
 785 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 786                         unsigned long parent_rate)
 787 {
 788         struct tegra_clk_pll *pll = to_clk_pll(hw);
 789         struct tegra_clk_pll_freq_table cfg, old_cfg;
 790         unsigned long flags = 0;
 791         int ret = 0;
 792
 793         if (pll->params->flags & TEGRA_PLL_FIXED) {
 794                 if (rate != pll->params->fixed_rate) {
 795                         pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
 796                                 __func__, clk_hw_get_name(hw),
 797                                 pll->params->fixed_rate, rate);
 798                         return -EINVAL;
 799                 }
 800                 return 0;
 801         }
 802
 803         if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
 804             pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
 805                 pr_err("%s: Failed to set %s rate %lu\n", __func__,
 806                        clk_hw_get_name(hw), rate);
 807                 WARN_ON(1);
 808                 return -EINVAL;
 809         }
 810         if (pll->lock)
 811                 spin_lock_irqsave(pll->lock, flags);
 812
 813         _get_pll_mnp(pll, &old_cfg);
 814         if (pll->params->flags & TEGRA_PLL_VCO_OUT)
 815                 cfg.p = old_cfg.p;
 816
 817         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p ||
 818                 old_cfg.sdm_data != cfg.sdm_data)
 819                 ret = _program_pll(hw, &cfg, rate);
 820
 821         if (pll->lock)
 822                 spin_unlock_irqrestore(pll->lock, flags);
 823
 824         return ret;
 825 }
 826
 827 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 828                         unsigned long *prate)
 829 {
 830         struct tegra_clk_pll *pll = to_clk_pll(hw);
 831         struct tegra_clk_pll_freq_table cfg;
 832
 833         if (pll->params->flags & TEGRA_PLL_FIXED) {
 834                 /* PLLM/MB are used for memory; we do not change rate */
 835                 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB))
 836                         return clk_hw_get_rate(hw);
 837                 return pll->params->fixed_rate;
 838         }
 839
 840         if (_get_table_rate(hw, &cfg, rate, *prate) &&
 841             pll->params->calc_rate(hw, &cfg, rate, *prate))
 842                 return -EINVAL;
 843
 844         return cfg.output_rate;
 845 }
 846
 847 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 848                                          unsigned long parent_rate)
 849 {
 850         struct tegra_clk_pll *pll = to_clk_pll(hw);
 851         struct tegra_clk_pll_freq_table cfg;
 852         u32 val;
 853         u64 rate = parent_rate;
 854         int pdiv;
 855
 856         val = pll_readl_base(pll);
 857
 858         if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
 859                 return parent_rate;
 860
 861         if ((pll->params->flags & TEGRA_PLL_FIXED) &&
 862             !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 863                         !(val & PLL_BASE_OVERRIDE)) {
 864                 struct tegra_clk_pll_freq_table sel;
 865                 if (_get_table_rate(hw, &sel, pll->params->fixed_rate,
 866                                         parent_rate)) {
 867                         pr_err("Clock %s has unknown fixed frequency\n",
 868                                clk_hw_get_name(hw));
 869                         BUG();
 870                 }
 871                 return pll->params->fixed_rate;
 872         }
 873
 874         _get_pll_mnp(pll, &cfg);
 875
 876         if (pll->params->flags & TEGRA_PLL_VCO_OUT) {
 877                 pdiv = 1;
 878         } else {
 879                 pdiv = _hw_to_p_div(hw, cfg.p);
 880                 if (pdiv < 0) {
 881                         WARN(1, "Clock %s has invalid pdiv value : 0x%x\n",
 882                              clk_hw_get_name(hw), cfg.p);
 883                         pdiv = 1;
 884                 }
 885         }
 886
 887         if (pll->params->set_gain)
 888                 pll->params->set_gain(&cfg);
 889
 890         cfg.m *= pdiv;
 891
 892         rate *= cfg.n;
 893         do_div(rate, cfg.m);
 894
 895         return rate;
 896 }
 897
 898 static int clk_plle_training(struct tegra_clk_pll *pll)
 899 {
 900         u32 val;
 901         unsigned long timeout;
 902
 903         if (!pll->pmc)
 904                 return -ENOSYS;
 905
 906         /*
 907          * PLLE is already disabled, and setup cleared;
 908          * create falling edge on PLLE IDDQ input.
 909          */
 910         val = readl(pll->pmc + PMC_SATA_PWRGT);
 911         val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 912         writel(val, pll->pmc + PMC_SATA_PWRGT);
 913
 914         val = readl(pll->pmc + PMC_SATA_PWRGT);
 915         val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
 916         writel(val, pll->pmc + PMC_SATA_PWRGT);
 917
 918         val = readl(pll->pmc + PMC_SATA_PWRGT);
 919         val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
 920         writel(val, pll->pmc + PMC_SATA_PWRGT);
 921
 922         val = pll_readl_misc(pll);
 923
 924         timeout = jiffies + msecs_to_jiffies(100);
 925         while (1) {
 926                 val = pll_readl_misc(pll);
 927                 if (val & PLLE_MISC_READY)
 928                         break;
 929                 if (time_after(jiffies, timeout)) {
 930                         pr_err("%s: timeout waiting for PLLE\n", __func__);
 931                         return -EBUSY;
 932                 }
 933                 udelay(300);
 934         }
 935
 936         return 0;
 937 }
 938
 939 static int clk_plle_enable(struct clk_hw *hw)
 940 {
 941         struct tegra_clk_pll *pll = to_clk_pll(hw);
 942         unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
 943         struct tegra_clk_pll_freq_table sel;
 944         u32 val;
 945         int err;
 946
 947         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
 948                 return -EINVAL;
 949
 950         clk_pll_disable(hw);
 951
 952         val = pll_readl_misc(pll);
 953         val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
 954         pll_writel_misc(val, pll);
 955
 956         val = pll_readl_misc(pll);
 957         if (!(val & PLLE_MISC_READY)) {
 958                 err = clk_plle_training(pll);
 959                 if (err)
 960                         return err;
 961         }
 962
 963         if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {
 964                 /* configure dividers */
 965                 val = pll_readl_base(pll);
 966                 val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
 967                          divm_mask_shifted(pll));
 968                 val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
 969                 val |= sel.m << divm_shift(pll);
 970                 val |= sel.n << divn_shift(pll);
 971                 val |= sel.p << divp_shift(pll);
 972                 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
 973                 pll_writel_base(val, pll);
 974         }
 975
 976         val = pll_readl_misc(pll);
 977         val |= PLLE_MISC_SETUP_VALUE;
 978         val |= PLLE_MISC_LOCK_ENABLE;
 979         pll_writel_misc(val, pll);
 980
 981         val = readl(pll->clk_base + PLLE_SS_CTRL);
 982         val &= ~PLLE_SS_COEFFICIENTS_MASK;
 983         val |= PLLE_SS_DISABLE;
 984         writel(val, pll->clk_base + PLLE_SS_CTRL);
 985
 986         val = pll_readl_base(pll);
 987         val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 988         pll_writel_base(val, pll);
 989
 990         clk_pll_wait_for_lock(pll);
 991
 992         return 0;
 993 }
 994
 995 static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
 996                                          unsigned long parent_rate)
 997 {
 998         struct tegra_clk_pll *pll = to_clk_pll(hw);
 999         u32 val = pll_readl_base(pll);
1000         u32 divn = 0, divm = 0, divp = 0;
1001         u64 rate = parent_rate;
1002
1003         divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
1004         divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
1005         divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1006         divm *= divp;
1007
1008         rate *= divn;
1009         do_div(rate, divm);
1010         return rate;
1011 }
1012
1013 const struct clk_ops tegra_clk_pll_ops = {
1014         .is_enabled = clk_pll_is_enabled,
1015         .enable = clk_pll_enable,
1016         .disable = clk_pll_disable,
1017         .recalc_rate = clk_pll_recalc_rate,
1018         .round_rate = clk_pll_round_rate,
1019         .set_rate = clk_pll_set_rate,
1020 };
1021
1022 const struct clk_ops tegra_clk_plle_ops = {
1023         .recalc_rate = clk_plle_recalc_rate,
1024         .is_enabled = clk_pll_is_enabled,
1025         .disable = clk_pll_disable,
1026         .enable = clk_plle_enable,
1027 };
1028
1029 /*
1030  * Structure defining the fields for USB UTMI clocks Parameters.
1031  */
1032 struct utmi_clk_param {
1033         /* Oscillator Frequency in Hz */
1034         u32 osc_frequency;
1035         /* UTMIP PLL Enable Delay Count  */
1036         u8 enable_delay_count;
1037         /* UTMIP PLL Stable count */
1038         u8 stable_count;
1039         /*  UTMIP PLL Active delay count */
1040         u8 active_delay_count;
1041         /* UTMIP PLL Xtal frequency count */
1042         u8 xtal_freq_count;
1043 };
1044
1045 static const struct utmi_clk_param utmi_parameters[] = {
1046         {
1047                 .osc_frequency = 13000000, .enable_delay_count = 0x02,
1048                 .stable_count = 0x33, .active_delay_count = 0x05,
1049                 .xtal_freq_count = 0x7f
1050         }, {
1051                 .osc_frequency = 19200000, .enable_delay_count = 0x03,
1052                 .stable_count = 0x4b, .active_delay_count = 0x06,
1053                 .xtal_freq_count = 0xbb
1054         }, {
1055                 .osc_frequency = 12000000, .enable_delay_count = 0x02,
1056                 .stable_count = 0x2f, .active_delay_count = 0x04,
1057                 .xtal_freq_count = 0x76
1058         }, {
1059                 .osc_frequency = 26000000, .enable_delay_count = 0x04,
1060                 .stable_count = 0x66, .active_delay_count = 0x09,
1061                 .xtal_freq_count = 0xfe
1062         }, {
1063                 .osc_frequency = 16800000, .enable_delay_count = 0x03,
1064                 .stable_count = 0x41, .active_delay_count = 0x0a,
1065                 .xtal_freq_count = 0xa4
1066         }, {
1067                 .osc_frequency = 38400000, .enable_delay_count = 0x0,
1068                 .stable_count = 0x0, .active_delay_count = 0x6,
1069                 .xtal_freq_count = 0x80
1070         },
1071 };
1072
1073 static int clk_pllu_enable(struct clk_hw *hw)
1074 {
1075         struct tegra_clk_pll *pll = to_clk_pll(hw);
1076         struct clk_hw *pll_ref = clk_hw_get_parent(hw);
1077         struct clk_hw *osc = clk_hw_get_parent(pll_ref);
1078         const struct utmi_clk_param *params = NULL;
1079         unsigned long flags = 0, input_rate;
1080         unsigned int i;
1081         int ret = 0;
1082         u32 value;
1083
1084         if (!osc) {
1085                 pr_err("%s: failed to get OSC clock\n", __func__);
1086                 return -EINVAL;
1087         }
1088
1089         input_rate = clk_hw_get_rate(osc);
1090
1091         if (pll->lock)
1092                 spin_lock_irqsave(pll->lock, flags);
1093
1094         _clk_pll_enable(hw);
1095
1096         ret = clk_pll_wait_for_lock(pll);
1097         if (ret < 0)
1098                 goto out;
1099
1100         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1101                 if (input_rate == utmi_parameters[i].osc_frequency) {
1102                         params = &utmi_parameters[i];
1103                         break;
1104                 }
1105         }
1106
1107         if (!params) {
1108                 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1109                        input_rate);
1110                 ret = -EINVAL;
1111                 goto out;
1112         }
1113
1114         value = pll_readl_base(pll);
1115         value &= ~PLLU_BASE_OVERRIDE;
1116         pll_writel_base(value, pll);
1117
1118         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1119         /* Program UTMIP PLL stable and active counts */
1120         value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1121         value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1122         value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1123         value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1124         /* Remove power downs from UTMIP PLL control bits */
1125         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1126         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1127         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1128         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1129
1130         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1131         /* Program UTMIP PLL delay and oscillator frequency counts */
1132         value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1133         value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1134         value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1135         value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1136         /* Remove power downs from UTMIP PLL control bits */
1137         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1138         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1139         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1140         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1141
1142 out:
1143         if (pll->lock)
1144                 spin_unlock_irqrestore(pll->lock, flags);
1145
1146         return ret;
1147 }
1148
1149 static const struct clk_ops tegra_clk_pllu_ops = {
1150         .is_enabled = clk_pll_is_enabled,
1151         .enable = clk_pllu_enable,
1152         .disable = clk_pll_disable,
1153         .recalc_rate = clk_pll_recalc_rate,
1154         .round_rate = clk_pll_round_rate,
1155         .set_rate = clk_pll_set_rate,
1156 };
1157
1158 static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params,
1159                            unsigned long parent_rate)
1160 {
1161         u16 mdiv = parent_rate / pll_params->cf_min;
1162
1163         if (pll_params->flags & TEGRA_MDIV_NEW)
1164                 return (!pll_params->mdiv_default ? mdiv :
1165                         min(mdiv, pll_params->mdiv_default));
1166
1167         if (pll_params->mdiv_default)
1168                 return pll_params->mdiv_default;
1169
1170         if (parent_rate > pll_params->cf_max)
1171                 return 2;
1172         else
1173                 return 1;
1174 }
1175
1176 static int _calc_dynamic_ramp_rate(struct clk_hw *hw,
1177                                 struct tegra_clk_pll_freq_table *cfg,
1178                                 unsigned long rate, unsigned long parent_rate)
1179 {
1180         struct tegra_clk_pll *pll = to_clk_pll(hw);
1181         unsigned int p;
1182         int p_div;
1183
1184         if (!rate)
1185                 return -EINVAL;
1186
1187         p = DIV_ROUND_UP(pll->params->vco_min, rate);
1188         cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);
1189         cfg->output_rate = rate * p;
1190         cfg->n = cfg->output_rate * cfg->m / parent_rate;
1191         cfg->input_rate = parent_rate;
1192
1193         p_div = _p_div_to_hw(hw, p);
1194         if (p_div < 0)
1195                 return p_div;
1196
1197         cfg->p = p_div;
1198
1199         if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)
1200                 return -EINVAL;
1201
1202         return 0;
1203 }
1204
1205 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1206         defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1207         defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1208         defined(CONFIG_ARCH_TEGRA_210_SOC)
1209
1210 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1211 {
1212         struct tegra_clk_pll *pll = to_clk_pll(hw);
1213
1214         return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1215 }
1216
1217 static unsigned long _clip_vco_min(unsigned long vco_min,
1218                                    unsigned long parent_rate)
1219 {
1220         return DIV_ROUND_UP(vco_min, parent_rate) * parent_rate;
1221 }
1222
1223 static int _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params,
1224                                void __iomem *clk_base,
1225                                unsigned long parent_rate)
1226 {
1227         u32 val;
1228         u32 step_a, step_b;
1229
1230         switch (parent_rate) {
1231         case 12000000:
1232         case 13000000:
1233         case 26000000:
1234                 step_a = 0x2B;
1235                 step_b = 0x0B;
1236                 break;
1237         case 16800000:
1238                 step_a = 0x1A;
1239                 step_b = 0x09;
1240                 break;
1241         case 19200000:
1242                 step_a = 0x12;
1243                 step_b = 0x08;
1244                 break;
1245         default:
1246                 pr_err("%s: Unexpected reference rate %lu\n",
1247                         __func__, parent_rate);
1248                 WARN_ON(1);
1249                 return -EINVAL;
1250         }
1251
1252         val = step_a << pll_params->stepa_shift;
1253         val |= step_b << pll_params->stepb_shift;
1254         writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1255
1256         return 0;
1257 }
1258
1259 static int _pll_ramp_calc_pll(struct clk_hw *hw,
1260                               struct tegra_clk_pll_freq_table *cfg,
1261                               unsigned long rate, unsigned long parent_rate)
1262 {
1263         struct tegra_clk_pll *pll = to_clk_pll(hw);
1264         int err = 0;
1265
1266         err = _get_table_rate(hw, cfg, rate, parent_rate);
1267         if (err < 0)
1268                 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1269         else {
1270                 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {
1271                         WARN_ON(1);
1272                         err = -EINVAL;
1273                         goto out;
1274                 }
1275         }
1276
1277         if (cfg->p >  pll->params->max_p)
1278                 err = -EINVAL;
1279
1280 out:
1281         return err;
1282 }
1283
1284 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1285                                 unsigned long parent_rate)
1286 {
1287         struct tegra_clk_pll *pll = to_clk_pll(hw);
1288         struct tegra_clk_pll_freq_table cfg, old_cfg;
1289         unsigned long flags = 0;
1290         int ret;
1291
1292         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1293         if (ret < 0)
1294                 return ret;
1295
1296         if (pll->lock)
1297                 spin_lock_irqsave(pll->lock, flags);
1298
1299         _get_pll_mnp(pll, &old_cfg);
1300         if (pll->params->flags & TEGRA_PLL_VCO_OUT)
1301                 cfg.p = old_cfg.p;
1302
1303         if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p)
1304                 ret = _program_pll(hw, &cfg, rate);
1305
1306         if (pll->lock)
1307                 spin_unlock_irqrestore(pll->lock, flags);
1308
1309         return ret;
1310 }
1311
1312 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1313                                 unsigned long *prate)
1314 {
1315         struct tegra_clk_pll *pll = to_clk_pll(hw);
1316         struct tegra_clk_pll_freq_table cfg;
1317         int ret, p_div;
1318         u64 output_rate = *prate;
1319
1320         ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1321         if (ret < 0)
1322                 return ret;
1323
1324         p_div = _hw_to_p_div(hw, cfg.p);
1325         if (p_div < 0)
1326                 return p_div;
1327
1328         if (pll->params->set_gain)
1329                 pll->params->set_gain(&cfg);
1330
1331         output_rate *= cfg.n;
1332         do_div(output_rate, cfg.m * p_div);
1333
1334         return output_rate;
1335 }
1336
1337 static void _pllcx_strobe(struct tegra_clk_pll *pll)
1338 {
1339         u32 val;
1340
1341         val = pll_readl_misc(pll);
1342         val |= PLLCX_MISC_STROBE;
1343         pll_writel_misc(val, pll);
1344         udelay(2);
1345
1346         val &= ~PLLCX_MISC_STROBE;
1347         pll_writel_misc(val, pll);
1348 }
1349
1350 static int clk_pllc_enable(struct clk_hw *hw)
1351 {
1352         struct tegra_clk_pll *pll = to_clk_pll(hw);
1353         u32 val;
1354         int ret;
1355         unsigned long flags = 0;
1356
1357         if (pll->lock)
1358                 spin_lock_irqsave(pll->lock, flags);
1359
1360         _clk_pll_enable(hw);
1361         udelay(2);
1362
1363         val = pll_readl_misc(pll);
1364         val &= ~PLLCX_MISC_RESET;
1365         pll_writel_misc(val, pll);
1366         udelay(2);
1367
1368         _pllcx_strobe(pll);
1369
1370         ret = clk_pll_wait_for_lock(pll);
1371
1372         if (pll->lock)
1373                 spin_unlock_irqrestore(pll->lock, flags);
1374
1375         return ret;
1376 }
1377
1378 static void _clk_pllc_disable(struct clk_hw *hw)
1379 {
1380         struct tegra_clk_pll *pll = to_clk_pll(hw);
1381         u32 val;
1382
1383         _clk_pll_disable(hw);
1384
1385         val = pll_readl_misc(pll);
1386         val |= PLLCX_MISC_RESET;
1387         pll_writel_misc(val, pll);
1388         udelay(2);
1389 }
1390
1391 static void clk_pllc_disable(struct clk_hw *hw)
1392 {
1393         struct tegra_clk_pll *pll = to_clk_pll(hw);
1394         unsigned long flags = 0;
1395
1396         if (pll->lock)
1397                 spin_lock_irqsave(pll->lock, flags);
1398
1399         _clk_pllc_disable(hw);
1400
1401         if (pll->lock)
1402                 spin_unlock_irqrestore(pll->lock, flags);
1403 }
1404
1405 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,
1406                                         unsigned long input_rate, u32 n)
1407 {
1408         u32 val, n_threshold;
1409
1410         switch (input_rate) {
1411         case 12000000:
1412                 n_threshold = 70;
1413                 break;
1414         case 13000000:
1415         case 26000000:
1416                 n_threshold = 71;
1417                 break;
1418         case 16800000:
1419                 n_threshold = 55;
1420                 break;
1421         case 19200000:
1422                 n_threshold = 48;
1423                 break;
1424         default:
1425                 pr_err("%s: Unexpected reference rate %lu\n",
1426                         __func__, input_rate);
1427                 return -EINVAL;
1428         }
1429
1430         val = pll_readl_misc(pll);
1431         val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1432         val |= n <= n_threshold ?
1433                 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE;
1434         pll_writel_misc(val, pll);
1435
1436         return 0;
1437 }
1438
1439 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1440                                 unsigned long parent_rate)
1441 {
1442         struct tegra_clk_pll_freq_table cfg, old_cfg;
1443         struct tegra_clk_pll *pll = to_clk_pll(hw);
1444         unsigned long flags = 0;
1445         int state, ret = 0;
1446
1447         if (pll->lock)
1448                 spin_lock_irqsave(pll->lock, flags);
1449
1450         ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1451         if (ret < 0)
1452                 goto out;
1453
1454         _get_pll_mnp(pll, &old_cfg);
1455
1456         if (cfg.m != old_cfg.m) {
1457                 WARN_ON(1);
1458                 goto out;
1459         }
1460
1461         if (old_cfg.n == cfg.n && old_cfg.p == cfg.p)
1462                 goto out;
1463
1464         state = clk_pll_is_enabled(hw);
1465         if (state)
1466                 _clk_pllc_disable(hw);
1467
1468         ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
1469         if (ret < 0)
1470                 goto out;
1471
1472         _update_pll_mnp(pll, &cfg);
1473
1474         if (state)
1475                 ret = clk_pllc_enable(hw);
1476
1477 out:
1478         if (pll->lock)
1479                 spin_unlock_irqrestore(pll->lock, flags);
1480
1481         return ret;
1482 }
1483
1484 static long _pllre_calc_rate(struct tegra_clk_pll *pll,
1485                              struct tegra_clk_pll_freq_table *cfg,
1486                              unsigned long rate, unsigned long parent_rate)
1487 {
1488         u16 m, n;
1489         u64 output_rate = parent_rate;
1490
1491         m = _pll_fixed_mdiv(pll->params, parent_rate);
1492         n = rate * m / parent_rate;
1493
1494         output_rate *= n;
1495         do_div(output_rate, m);
1496
1497         if (cfg) {
1498                 cfg->m = m;
1499                 cfg->n = n;
1500         }
1501
1502         return output_rate;
1503 }
1504
1505 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1506                                 unsigned long parent_rate)
1507 {
1508         struct tegra_clk_pll_freq_table cfg, old_cfg;
1509         struct tegra_clk_pll *pll = to_clk_pll(hw);
1510         unsigned long flags = 0;
1511         int state, ret = 0;
1512
1513         if (pll->lock)
1514                 spin_lock_irqsave(pll->lock, flags);
1515
1516         _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1517         _get_pll_mnp(pll, &old_cfg);
1518         cfg.p = old_cfg.p;
1519
1520         if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) {
1521                 state = clk_pll_is_enabled(hw);
1522                 if (state)
1523                         _clk_pll_disable(hw);
1524
1525                 _update_pll_mnp(pll, &cfg);
1526
1527                 if (state) {
1528                         _clk_pll_enable(hw);
1529                         ret = clk_pll_wait_for_lock(pll);
1530                 }
1531         }
1532
1533         if (pll->lock)
1534                 spin_unlock_irqrestore(pll->lock, flags);
1535
1536         return ret;
1537 }
1538
1539 static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
1540                                          unsigned long parent_rate)
1541 {
1542         struct tegra_clk_pll_freq_table cfg;
1543         struct tegra_clk_pll *pll = to_clk_pll(hw);
1544         u64 rate = parent_rate;
1545
1546         _get_pll_mnp(pll, &cfg);
1547
1548         rate *= cfg.n;
1549         do_div(rate, cfg.m);
1550
1551         return rate;
1552 }
1553
1554 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1555                                  unsigned long *prate)
1556 {
1557         struct tegra_clk_pll *pll = to_clk_pll(hw);
1558
1559         return _pllre_calc_rate(pll, NULL, rate, *prate);
1560 }
1561
1562 static int clk_plle_tegra114_enable(struct clk_hw *hw)
1563 {
1564         struct tegra_clk_pll *pll = to_clk_pll(hw);
1565         struct tegra_clk_pll_freq_table sel;
1566         u32 val;
1567         int ret;
1568         unsigned long flags = 0;
1569         unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1570
1571         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1572                 return -EINVAL;
1573
1574         if (pll->lock)
1575                 spin_lock_irqsave(pll->lock, flags);
1576
1577         val = pll_readl_base(pll);
1578         val &= ~BIT(29); /* Disable lock override */
1579         pll_writel_base(val, pll);
1580
1581         val = pll_readl(pll->params->aux_reg, pll);
1582         val |= PLLE_AUX_ENABLE_SWCTL;
1583         val &= ~PLLE_AUX_SEQ_ENABLE;
1584         pll_writel(val, pll->params->aux_reg, pll);
1585         udelay(1);
1586
1587         val = pll_readl_misc(pll);
1588         val |= PLLE_MISC_LOCK_ENABLE;
1589         val |= PLLE_MISC_IDDQ_SW_CTRL;
1590         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1591         val |= PLLE_MISC_PLLE_PTS;
1592         val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
1593         pll_writel_misc(val, pll);
1594         udelay(5);
1595
1596         val = pll_readl(PLLE_SS_CTRL, pll);
1597         val |= PLLE_SS_DISABLE;
1598         pll_writel(val, PLLE_SS_CTRL, pll);
1599
1600         val = pll_readl_base(pll);
1601         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1602                  divm_mask_shifted(pll));
1603         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1604         val |= sel.m << divm_shift(pll);
1605         val |= sel.n << divn_shift(pll);
1606         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1607         pll_writel_base(val, pll);
1608         udelay(1);
1609
1610         _clk_pll_enable(hw);
1611         ret = clk_pll_wait_for_lock(pll);
1612
1613         if (ret < 0)
1614                 goto out;
1615
1616         val = pll_readl(PLLE_SS_CTRL, pll);
1617         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1618         val &= ~PLLE_SS_COEFFICIENTS_MASK;
1619         val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
1620         pll_writel(val, PLLE_SS_CTRL, pll);
1621         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1622         pll_writel(val, PLLE_SS_CTRL, pll);
1623         udelay(1);
1624         val &= ~PLLE_SS_CNTL_INTERP_RESET;
1625         pll_writel(val, PLLE_SS_CTRL, pll);
1626         udelay(1);
1627
1628         /* Enable hw control of xusb brick pll */
1629         val = pll_readl_misc(pll);
1630         val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1631         pll_writel_misc(val, pll);
1632
1633         val = pll_readl(pll->params->aux_reg, pll);
1634         val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1635         val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1636         pll_writel(val, pll->params->aux_reg, pll);
1637         udelay(1);
1638         val |= PLLE_AUX_SEQ_ENABLE;
1639         pll_writel(val, pll->params->aux_reg, pll);
1640
1641         val = pll_readl(XUSBIO_PLL_CFG0, pll);
1642         val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1643                 XUSBIO_PLL_CFG0_SEQ_START_STATE);
1644         val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1645                  XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
1646         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1647         udelay(1);
1648         val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1649         pll_writel(val, XUSBIO_PLL_CFG0, pll);
1650
1651         /* Enable hw control of SATA pll */
1652         val = pll_readl(SATA_PLL_CFG0, pll);
1653         val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1654         val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1655         val |= SATA_PLL_CFG0_SEQ_START_STATE;
1656         pll_writel(val, SATA_PLL_CFG0, pll);
1657
1658         udelay(1);
1659
1660         val = pll_readl(SATA_PLL_CFG0, pll);
1661         val |= SATA_PLL_CFG0_SEQ_ENABLE;
1662         pll_writel(val, SATA_PLL_CFG0, pll);
1663
1664 out:
1665         if (pll->lock)
1666                 spin_unlock_irqrestore(pll->lock, flags);
1667
1668         return ret;
1669 }
1670
1671 static void clk_plle_tegra114_disable(struct clk_hw *hw)
1672 {
1673         struct tegra_clk_pll *pll = to_clk_pll(hw);
1674         unsigned long flags = 0;
1675         u32 val;
1676
1677         if (pll->lock)
1678                 spin_lock_irqsave(pll->lock, flags);
1679
1680         _clk_pll_disable(hw);
1681
1682         val = pll_readl_misc(pll);
1683         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1684         pll_writel_misc(val, pll);
1685         udelay(1);
1686
1687         if (pll->lock)
1688                 spin_unlock_irqrestore(pll->lock, flags);
1689 }
1690
1691 static int clk_pllu_tegra114_enable(struct clk_hw *hw)
1692 {
1693         struct tegra_clk_pll *pll = to_clk_pll(hw);
1694         const struct utmi_clk_param *params = NULL;
1695         struct clk *osc = __clk_lookup("osc");
1696         unsigned long flags = 0, input_rate;
1697         unsigned int i;
1698         int ret = 0;
1699         u32 value;
1700
1701         if (!osc) {
1702                 pr_err("%s: failed to get OSC clock\n", __func__);
1703                 return -EINVAL;
1704         }
1705
1706         input_rate = clk_hw_get_rate(__clk_get_hw(osc));
1707
1708         if (pll->lock)
1709                 spin_lock_irqsave(pll->lock, flags);
1710
1711         _clk_pll_enable(hw);
1712
1713         ret = clk_pll_wait_for_lock(pll);
1714         if (ret < 0)
1715                 goto out;
1716
1717         for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1718                 if (input_rate == utmi_parameters[i].osc_frequency) {
1719                         params = &utmi_parameters[i];
1720                         break;
1721                 }
1722         }
1723
1724         if (!params) {
1725                 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1726                        input_rate);
1727                 ret = -EINVAL;
1728                 goto out;
1729         }
1730
1731         value = pll_readl_base(pll);
1732         value &= ~PLLU_BASE_OVERRIDE;
1733         pll_writel_base(value, pll);
1734
1735         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
1736         /* Program UTMIP PLL stable and active counts */
1737         value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1738         value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
1739         value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1740         value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
1741         /* Remove power downs from UTMIP PLL control bits */
1742         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1743         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1744         value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1745         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
1746
1747         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1748         /* Program UTMIP PLL delay and oscillator frequency counts */
1749         value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1750         value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
1751         value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1752         value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
1753         /* Remove power downs from UTMIP PLL control bits */
1754         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1755         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1756         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;
1757         value &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1758         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1759
1760         /* Setup HW control of UTMIPLL */
1761         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1762         value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
1763         value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
1764         value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;
1765         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1766
1767         value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
1768         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
1769         value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1770         writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
1771
1772         udelay(1);
1773
1774         /*
1775          * Setup SW override of UTMIPLL assuming USB2.0 ports are assigned
1776          * to USB2
1777          */
1778         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1779         value |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;
1780         value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
1781         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1782
1783         udelay(1);
1784
1785         /* Enable HW control of UTMIPLL */
1786         value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1787         value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
1788         writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
1789
1790 out:
1791         if (pll->lock)
1792                 spin_unlock_irqrestore(pll->lock, flags);
1793
1794         return ret;
1795 }
1796 #endif
1797
1798 static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,
1799                 void __iomem *pmc, struct tegra_clk_pll_params *pll_params,
1800                 spinlock_t *lock)
1801 {
1802         struct tegra_clk_pll *pll;
1803
1804         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1805         if (!pll)
1806                 return ERR_PTR(-ENOMEM);
1807
1808         pll->clk_base = clk_base;
1809         pll->pmc = pmc;
1810
1811         pll->params = pll_params;
1812         pll->lock = lock;
1813
1814         if (!pll_params->div_nmp)
1815                 pll_params->div_nmp = &default_nmp;
1816
1817         return pll;
1818 }
1819
1820 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,
1821                 const char *name, const char *parent_name, unsigned long flags,
1822                 const struct clk_ops *ops)
1823 {
1824         struct clk_init_data init;
1825
1826         init.name = name;
1827         init.ops = ops;
1828         init.flags = flags;
1829         init.parent_names = (parent_name ? &parent_name : NULL);
1830         init.num_parents = (parent_name ? 1 : 0);
1831
1832         /* Default to _calc_rate if unspecified */
1833         if (!pll->params->calc_rate) {
1834                 if (pll->params->flags & TEGRA_PLLM)
1835                         pll->params->calc_rate = _calc_dynamic_ramp_rate;
1836                 else
1837                         pll->params->calc_rate = _calc_rate;
1838         }
1839
1840         if (pll->params->set_defaults)
1841                 pll->params->set_defaults(pll);
1842
1843         /* Data in .init is copied by clk_register(), so stack variable OK */
1844         pll->hw.init = &init;
1845
1846         return clk_register(NULL, &pll->hw);
1847 }
1848
1849 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
1850                 void __iomem *clk_base, void __iomem *pmc,
1851                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1852                 spinlock_t *lock)
1853 {
1854         struct tegra_clk_pll *pll;
1855         struct clk *clk;
1856
1857         pll_params->flags |= TEGRA_PLL_BYPASS;
1858
1859         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1860         if (IS_ERR(pll))
1861                 return ERR_CAST(pll);
1862
1863         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1864                                       &tegra_clk_pll_ops);
1865         if (IS_ERR(clk))
1866                 kfree(pll);
1867
1868         return clk;
1869 }
1870
1871 static struct div_nmp pll_e_nmp = {
1872         .divn_shift = PLLE_BASE_DIVN_SHIFT,
1873         .divn_width = PLLE_BASE_DIVN_WIDTH,
1874         .divm_shift = PLLE_BASE_DIVM_SHIFT,
1875         .divm_width = PLLE_BASE_DIVM_WIDTH,
1876         .divp_shift = PLLE_BASE_DIVP_SHIFT,
1877         .divp_width = PLLE_BASE_DIVP_WIDTH,
1878 };
1879
1880 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
1881                 void __iomem *clk_base, void __iomem *pmc,
1882                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
1883                 spinlock_t *lock)
1884 {
1885         struct tegra_clk_pll *pll;
1886         struct clk *clk;
1887
1888         pll_params->flags |= TEGRA_PLL_BYPASS;
1889
1890         if (!pll_params->div_nmp)
1891                 pll_params->div_nmp = &pll_e_nmp;
1892
1893         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
1894         if (IS_ERR(pll))
1895                 return ERR_CAST(pll);
1896
1897         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1898                                       &tegra_clk_plle_ops);
1899         if (IS_ERR(clk))
1900                 kfree(pll);
1901
1902         return clk;
1903 }
1904
1905 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
1906                 void __iomem *clk_base, unsigned long flags,
1907                 struct tegra_clk_pll_params *pll_params, spinlock_t *lock)
1908 {
1909         struct tegra_clk_pll *pll;
1910         struct clk *clk;
1911
1912         pll_params->flags |= TEGRA_PLLU;
1913
1914         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
1915         if (IS_ERR(pll))
1916                 return ERR_CAST(pll);
1917
1918         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
1919                                       &tegra_clk_pllu_ops);
1920         if (IS_ERR(clk))
1921                 kfree(pll);
1922
1923         return clk;
1924 }
1925
1926 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
1927         defined(CONFIG_ARCH_TEGRA_124_SOC) || \
1928         defined(CONFIG_ARCH_TEGRA_132_SOC) || \
1929         defined(CONFIG_ARCH_TEGRA_210_SOC)
1930 static const struct clk_ops tegra_clk_pllxc_ops = {
1931         .is_enabled = clk_pll_is_enabled,
1932         .enable = clk_pll_enable,
1933         .disable = clk_pll_disable,
1934         .recalc_rate = clk_pll_recalc_rate,
1935         .round_rate = clk_pll_ramp_round_rate,
1936         .set_rate = clk_pllxc_set_rate,
1937 };
1938
1939 static const struct clk_ops tegra_clk_pllc_ops = {
1940         .is_enabled = clk_pll_is_enabled,
1941         .enable = clk_pllc_enable,
1942         .disable = clk_pllc_disable,
1943         .recalc_rate = clk_pll_recalc_rate,
1944         .round_rate = clk_pll_ramp_round_rate,
1945         .set_rate = clk_pllc_set_rate,
1946 };
1947
1948 static const struct clk_ops tegra_clk_pllre_ops = {
1949         .is_enabled = clk_pll_is_enabled,
1950         .enable = clk_pll_enable,
1951         .disable = clk_pll_disable,
1952         .recalc_rate = clk_pllre_recalc_rate,
1953         .round_rate = clk_pllre_round_rate,
1954         .set_rate = clk_pllre_set_rate,
1955 };
1956
1957 static const struct clk_ops tegra_clk_plle_tegra114_ops = {
1958         .is_enabled =  clk_pll_is_enabled,
1959         .enable = clk_plle_tegra114_enable,
1960         .disable = clk_plle_tegra114_disable,
1961         .recalc_rate = clk_pll_recalc_rate,
1962 };
1963
1964 static const struct clk_ops tegra_clk_pllu_tegra114_ops = {
1965         .is_enabled =  clk_pll_is_enabled,
1966         .enable = clk_pllu_tegra114_enable,
1967         .disable = clk_pll_disable,
1968         .recalc_rate = clk_pll_recalc_rate,
1969 };
1970
1971 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
1972                           void __iomem *clk_base, void __iomem *pmc,
1973                           unsigned long flags,
1974                           struct tegra_clk_pll_params *pll_params,
1975                           spinlock_t *lock)
1976 {
1977         struct tegra_clk_pll *pll;
1978         struct clk *clk, *parent;
1979         unsigned long parent_rate;
1980         u32 val, val_iddq;
1981
1982         parent = __clk_lookup(parent_name);
1983         if (!parent) {
1984                 WARN(1, "parent clk %s of %s must be registered first\n",
1985                         parent_name, name);
1986                 return ERR_PTR(-EINVAL);
1987         }
1988
1989         if (!pll_params->pdiv_tohw)
1990                 return ERR_PTR(-EINVAL);
1991
1992         parent_rate = clk_get_rate(parent);
1993
1994         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
1995
1996         if (pll_params->adjust_vco)
1997                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
1998                                                              parent_rate);
1999
2000         /*
2001          * If the pll has a set_defaults callback, it will take care of
2002          * configuring dynamic ramping and setting IDDQ in that path.
2003          */
2004         if (!pll_params->set_defaults) {
2005                 int err;
2006
2007                 err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
2008                 if (err)
2009                         return ERR_PTR(err);
2010
2011                 val = readl_relaxed(clk_base + pll_params->base_reg);
2012                 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2013
2014                 if (val & PLL_BASE_ENABLE)
2015                         WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx));
2016                 else {
2017                         val_iddq |= BIT(pll_params->iddq_bit_idx);
2018                         writel_relaxed(val_iddq,
2019                                        clk_base + pll_params->iddq_reg);
2020                 }
2021         }
2022
2023         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2024         if (IS_ERR(pll))
2025                 return ERR_CAST(pll);
2026
2027         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2028                                       &tegra_clk_pllxc_ops);
2029         if (IS_ERR(clk))
2030                 kfree(pll);
2031
2032         return clk;
2033 }
2034
2035 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
2036                           void __iomem *clk_base, void __iomem *pmc,
2037                           unsigned long flags,
2038                           struct tegra_clk_pll_params *pll_params,
2039                           spinlock_t *lock, unsigned long parent_rate)
2040 {
2041         u32 val;
2042         struct tegra_clk_pll *pll;
2043         struct clk *clk;
2044
2045         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2046
2047         if (pll_params->adjust_vco)
2048                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2049                                                              parent_rate);
2050
2051         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2052         if (IS_ERR(pll))
2053                 return ERR_CAST(pll);
2054
2055         /* program minimum rate by default */
2056
2057         val = pll_readl_base(pll);
2058         if (val & PLL_BASE_ENABLE)
2059                 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) &
2060                                 BIT(pll_params->iddq_bit_idx));
2061         else {
2062                 int m;
2063
2064                 m = _pll_fixed_mdiv(pll_params, parent_rate);
2065                 val = m << divm_shift(pll);
2066                 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2067                 pll_writel_base(val, pll);
2068         }
2069
2070         /* disable lock override */
2071
2072         val = pll_readl_misc(pll);
2073         val &= ~BIT(29);
2074         pll_writel_misc(val, pll);
2075
2076         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2077                                       &tegra_clk_pllre_ops);
2078         if (IS_ERR(clk))
2079                 kfree(pll);
2080
2081         return clk;
2082 }
2083
2084 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
2085                           void __iomem *clk_base, void __iomem *pmc,
2086                           unsigned long flags,
2087                           struct tegra_clk_pll_params *pll_params,
2088                           spinlock_t *lock)
2089 {
2090         struct tegra_clk_pll *pll;
2091         struct clk *clk, *parent;
2092         unsigned long parent_rate;
2093
2094         if (!pll_params->pdiv_tohw)
2095                 return ERR_PTR(-EINVAL);
2096
2097         parent = __clk_lookup(parent_name);
2098         if (!parent) {
2099                 WARN(1, "parent clk %s of %s must be registered first\n",
2100                         parent_name, name);
2101                 return ERR_PTR(-EINVAL);
2102         }
2103
2104         parent_rate = clk_get_rate(parent);
2105
2106         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2107
2108         if (pll_params->adjust_vco)
2109                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2110                                                              parent_rate);
2111
2112         pll_params->flags |= TEGRA_PLL_BYPASS;
2113         pll_params->flags |= TEGRA_PLLM;
2114         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2115         if (IS_ERR(pll))
2116                 return ERR_CAST(pll);
2117
2118         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2119                                       &tegra_clk_pll_ops);
2120         if (IS_ERR(clk))
2121                 kfree(pll);
2122
2123         return clk;
2124 }
2125
2126 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
2127                           void __iomem *clk_base, void __iomem *pmc,
2128                           unsigned long flags,
2129                           struct tegra_clk_pll_params *pll_params,
2130                           spinlock_t *lock)
2131 {
2132         struct clk *parent, *clk;
2133         const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2134         struct tegra_clk_pll *pll;
2135         struct tegra_clk_pll_freq_table cfg;
2136         unsigned long parent_rate;
2137
2138         if (!p_tohw)
2139                 return ERR_PTR(-EINVAL);
2140
2141         parent = __clk_lookup(parent_name);
2142         if (!parent) {
2143                 WARN(1, "parent clk %s of %s must be registered first\n",
2144                         parent_name, name);
2145                 return ERR_PTR(-EINVAL);
2146         }
2147
2148         parent_rate = clk_get_rate(parent);
2149
2150         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2151
2152         pll_params->flags |= TEGRA_PLL_BYPASS;
2153         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2154         if (IS_ERR(pll))
2155                 return ERR_CAST(pll);
2156
2157         /*
2158          * Most of PLLC register fields are shadowed, and can not be read
2159          * directly from PLL h/w. Hence, actual PLLC boot state is unknown.
2160          * Initialize PLL to default state: disabled, reset; shadow registers
2161          * loaded with default parameters; dividers are preset for half of
2162          * minimum VCO rate (the latter assured that shadowed divider settings
2163          * are within supported range).
2164          */
2165
2166         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2167         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2168
2169         while (p_tohw->pdiv) {
2170                 if (p_tohw->pdiv == 2) {
2171                         cfg.p = p_tohw->hw_val;
2172                         break;
2173                 }
2174                 p_tohw++;
2175         }
2176
2177         if (!p_tohw->pdiv) {
2178                 WARN_ON(1);
2179                 return ERR_PTR(-EINVAL);
2180         }
2181
2182         pll_writel_base(0, pll);
2183         _update_pll_mnp(pll, &cfg);
2184
2185         pll_writel_misc(PLLCX_MISC_DEFAULT, pll);
2186         pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);
2187         pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);
2188         pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);
2189
2190         _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);
2191
2192         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2193                                       &tegra_clk_pllc_ops);
2194         if (IS_ERR(clk))
2195                 kfree(pll);
2196
2197         return clk;
2198 }
2199
2200 struct clk *tegra_clk_register_plle_tegra114(const char *name,
2201                                 const char *parent_name,
2202                                 void __iomem *clk_base, unsigned long flags,
2203                                 struct tegra_clk_pll_params *pll_params,
2204                                 spinlock_t *lock)
2205 {
2206         struct tegra_clk_pll *pll;
2207         struct clk *clk;
2208         u32 val, val_aux;
2209
2210         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2211         if (IS_ERR(pll))
2212                 return ERR_CAST(pll);
2213
2214         /* ensure parent is set to pll_re_vco */
2215
2216         val = pll_readl_base(pll);
2217         val_aux = pll_readl(pll_params->aux_reg, pll);
2218
2219         if (val & PLL_BASE_ENABLE) {
2220                 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2221                         (val_aux & PLLE_AUX_PLLP_SEL))
2222                         WARN(1, "pll_e enabled with unsupported parent %s\n",
2223                           (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2224                                         "pll_re_vco");
2225         } else {
2226                 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2227                 pll_writel(val_aux, pll_params->aux_reg, pll);
2228         }
2229
2230         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2231                                       &tegra_clk_plle_tegra114_ops);
2232         if (IS_ERR(clk))
2233                 kfree(pll);
2234
2235         return clk;
2236 }
2237
2238 struct clk *
2239 tegra_clk_register_pllu_tegra114(const char *name, const char *parent_name,
2240                                  void __iomem *clk_base, unsigned long flags,
2241                                  struct tegra_clk_pll_params *pll_params,
2242                                  spinlock_t *lock)
2243 {
2244         struct tegra_clk_pll *pll;
2245         struct clk *clk;
2246
2247         pll_params->flags |= TEGRA_PLLU;
2248
2249         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2250         if (IS_ERR(pll))
2251                 return ERR_CAST(pll);
2252
2253         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2254                                       &tegra_clk_pllu_tegra114_ops);
2255         if (IS_ERR(clk))
2256                 kfree(pll);
2257
2258         return clk;
2259 }
2260 #endif
2261
2262 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC) || defined(CONFIG_ARCH_TEGRA_210_SOC)
2263 static const struct clk_ops tegra_clk_pllss_ops = {
2264         .is_enabled = clk_pll_is_enabled,
2265         .enable = clk_pll_enable,
2266         .disable = clk_pll_disable,
2267         .recalc_rate = clk_pll_recalc_rate,
2268         .round_rate = clk_pll_ramp_round_rate,
2269         .set_rate = clk_pllxc_set_rate,
2270 };
2271
2272 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
2273                                 void __iomem *clk_base, unsigned long flags,
2274                                 struct tegra_clk_pll_params *pll_params,
2275                                 spinlock_t *lock)
2276 {
2277         struct tegra_clk_pll *pll;
2278         struct clk *clk, *parent;
2279         struct tegra_clk_pll_freq_table cfg;
2280         unsigned long parent_rate;
2281         u32 val, val_iddq;
2282         int i;
2283
2284         if (!pll_params->div_nmp)
2285                 return ERR_PTR(-EINVAL);
2286
2287         parent = __clk_lookup(parent_name);
2288         if (!parent) {
2289                 WARN(1, "parent clk %s of %s must be registered first\n",
2290                         parent_name, name);
2291                 return ERR_PTR(-EINVAL);
2292         }
2293
2294         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2295         if (IS_ERR(pll))
2296                 return ERR_CAST(pll);
2297
2298         val = pll_readl_base(pll);
2299         val &= ~PLLSS_REF_SRC_SEL_MASK;
2300         pll_writel_base(val, pll);
2301
2302         parent_rate = clk_get_rate(parent);
2303
2304         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2305
2306         /* initialize PLL to minimum rate */
2307
2308         cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
2309         cfg.n = cfg.m * pll_params->vco_min / parent_rate;
2310
2311         for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++)
2312                 ;
2313         if (!i) {
2314                 kfree(pll);
2315                 return ERR_PTR(-EINVAL);
2316         }
2317
2318         cfg.p = pll_params->pdiv_tohw[i-1].hw_val;
2319
2320         _update_pll_mnp(pll, &cfg);
2321
2322         pll_writel_misc(PLLSS_MISC_DEFAULT, pll);
2323         pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);
2324         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);
2325         pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
2326
2327         val = pll_readl_base(pll);
2328         val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
2329         if (val & PLL_BASE_ENABLE) {
2330                 if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
2331                         WARN(1, "%s is on but IDDQ set\n", name);
2332                         kfree(pll);
2333                         return ERR_PTR(-EINVAL);
2334                 }
2335         } else {
2336                 val_iddq |= BIT(pll_params->iddq_bit_idx);
2337                 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
2338         }
2339
2340         val &= ~PLLSS_LOCK_OVERRIDE;
2341         pll_writel_base(val, pll);
2342
2343         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2344                                         &tegra_clk_pllss_ops);
2345
2346         if (IS_ERR(clk))
2347                 kfree(pll);
2348
2349         return clk;
2350 }
2351 #endif
2352
2353 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
2354 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
2355                           const char *parent_name, void __iomem *clk_base,
2356                           void __iomem *pmc, unsigned long flags,
2357                           struct tegra_clk_pll_params *pll_params,
2358                           spinlock_t *lock, unsigned long parent_rate)
2359 {
2360         struct tegra_clk_pll *pll;
2361         struct clk *clk;
2362
2363         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2364
2365         if (pll_params->adjust_vco)
2366                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2367                                                              parent_rate);
2368
2369         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2370         if (IS_ERR(pll))
2371                 return ERR_CAST(pll);
2372
2373         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2374                                       &tegra_clk_pll_ops);
2375         if (IS_ERR(clk))
2376                 kfree(pll);
2377
2378         return clk;
2379 }
2380
2381 static int clk_plle_tegra210_enable(struct clk_hw *hw)
2382 {
2383         struct tegra_clk_pll *pll = to_clk_pll(hw);
2384         struct tegra_clk_pll_freq_table sel;
2385         u32 val;
2386         int ret = 0;
2387         unsigned long flags = 0;
2388         unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2389
2390         if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
2391                 return -EINVAL;
2392
2393         if (pll->lock)
2394                 spin_lock_irqsave(pll->lock, flags);
2395
2396         val = pll_readl(pll->params->aux_reg, pll);
2397         if (val & PLLE_AUX_SEQ_ENABLE)
2398                 goto out;
2399
2400         val = pll_readl_base(pll);
2401         val &= ~BIT(30); /* Disable lock override */
2402         pll_writel_base(val, pll);
2403
2404         val = pll_readl_misc(pll);
2405         val |= PLLE_MISC_LOCK_ENABLE;
2406         val |= PLLE_MISC_IDDQ_SW_CTRL;
2407         val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2408         val |= PLLE_MISC_PLLE_PTS;
2409         val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
2410         pll_writel_misc(val, pll);
2411         udelay(5);
2412
2413         val = pll_readl(PLLE_SS_CTRL, pll);
2414         val |= PLLE_SS_DISABLE;
2415         pll_writel(val, PLLE_SS_CTRL, pll);
2416
2417         val = pll_readl_base(pll);
2418         val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2419                  divm_mask_shifted(pll));
2420         val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2421         val |= sel.m << divm_shift(pll);
2422         val |= sel.n << divn_shift(pll);
2423         val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2424         pll_writel_base(val, pll);
2425         udelay(1);
2426
2427         val = pll_readl_base(pll);
2428         val |= PLLE_BASE_ENABLE;
2429         pll_writel_base(val, pll);
2430
2431         ret = clk_pll_wait_for_lock(pll);
2432
2433         if (ret < 0)
2434                 goto out;
2435
2436         val = pll_readl(PLLE_SS_CTRL, pll);
2437         val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2438         val &= ~PLLE_SS_COEFFICIENTS_MASK;
2439         val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
2440         pll_writel(val, PLLE_SS_CTRL, pll);
2441         val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2442         pll_writel(val, PLLE_SS_CTRL, pll);
2443         udelay(1);
2444         val &= ~PLLE_SS_CNTL_INTERP_RESET;
2445         pll_writel(val, PLLE_SS_CTRL, pll);
2446         udelay(1);
2447
2448         val = pll_readl_misc(pll);
2449         val &= ~PLLE_MISC_IDDQ_SW_CTRL;
2450         pll_writel_misc(val, pll);
2451
2452         val = pll_readl(pll->params->aux_reg, pll);
2453         val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
2454         val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
2455         pll_writel(val, pll->params->aux_reg, pll);
2456         udelay(1);
2457         val |= PLLE_AUX_SEQ_ENABLE;
2458         pll_writel(val, pll->params->aux_reg, pll);
2459
2460 out:
2461         if (pll->lock)
2462                 spin_unlock_irqrestore(pll->lock, flags);
2463
2464         return ret;
2465 }
2466
2467 static void clk_plle_tegra210_disable(struct clk_hw *hw)
2468 {
2469         struct tegra_clk_pll *pll = to_clk_pll(hw);
2470         unsigned long flags = 0;
2471         u32 val;
2472
2473         if (pll->lock)
2474                 spin_lock_irqsave(pll->lock, flags);
2475
2476         /* If PLLE HW sequencer is enabled, SW should not disable PLLE */
2477         val = pll_readl(pll->params->aux_reg, pll);
2478         if (val & PLLE_AUX_SEQ_ENABLE)
2479                 goto out;
2480
2481         val = pll_readl_base(pll);
2482         val &= ~PLLE_BASE_ENABLE;
2483         pll_writel_base(val, pll);
2484
2485         val = pll_readl(pll->params->aux_reg, pll);
2486         val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
2487         pll_writel(val, pll->params->aux_reg, pll);
2488
2489         val = pll_readl_misc(pll);
2490         val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2491         pll_writel_misc(val, pll);
2492         udelay(1);
2493
2494 out:
2495         if (pll->lock)
2496                 spin_unlock_irqrestore(pll->lock, flags);
2497 }
2498
2499 static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2500 {
2501         struct tegra_clk_pll *pll = to_clk_pll(hw);
2502         u32 val;
2503
2504         val = pll_readl_base(pll);
2505
2506         return val & PLLE_BASE_ENABLE ? 1 : 0;
2507 }
2508
2509 static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2510         .is_enabled =  clk_plle_tegra210_is_enabled,
2511         .enable = clk_plle_tegra210_enable,
2512         .disable = clk_plle_tegra210_disable,
2513         .recalc_rate = clk_pll_recalc_rate,
2514 };
2515
2516 struct clk *tegra_clk_register_plle_tegra210(const char *name,
2517                                 const char *parent_name,
2518                                 void __iomem *clk_base, unsigned long flags,
2519                                 struct tegra_clk_pll_params *pll_params,
2520                                 spinlock_t *lock)
2521 {
2522         struct tegra_clk_pll *pll;
2523         struct clk *clk;
2524         u32 val, val_aux;
2525
2526         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2527         if (IS_ERR(pll))
2528                 return ERR_CAST(pll);
2529
2530         /* ensure parent is set to pll_re_vco */
2531
2532         val = pll_readl_base(pll);
2533         val_aux = pll_readl(pll_params->aux_reg, pll);
2534
2535         if (val & PLLE_BASE_ENABLE) {
2536                 if ((val_aux & PLLE_AUX_PLLRE_SEL) ||
2537                         (val_aux & PLLE_AUX_PLLP_SEL))
2538                         WARN(1, "pll_e enabled with unsupported parent %s\n",
2539                           (val_aux & PLLE_AUX_PLLP_SEL) ? "pllp_out0" :
2540                                         "pll_re_vco");
2541         } else {
2542                 val_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);
2543                 pll_writel(val_aux, pll_params->aux_reg, pll);
2544         }
2545
2546         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2547                                       &tegra_clk_plle_tegra210_ops);
2548         if (IS_ERR(clk))
2549                 kfree(pll);
2550
2551         return clk;
2552 }
2553
2554 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
2555                         const char *parent_name, void __iomem *clk_base,
2556                         void __iomem *pmc, unsigned long flags,
2557                         struct tegra_clk_pll_params *pll_params,
2558                         spinlock_t *lock)
2559 {
2560         struct clk *parent, *clk;
2561         const struct pdiv_map *p_tohw = pll_params->pdiv_tohw;
2562         struct tegra_clk_pll *pll;
2563         unsigned long parent_rate;
2564
2565         if (!p_tohw)
2566                 return ERR_PTR(-EINVAL);
2567
2568         parent = __clk_lookup(parent_name);
2569         if (!parent) {
2570                 WARN(1, "parent clk %s of %s must be registered first\n",
2571                         name, parent_name);
2572                 return ERR_PTR(-EINVAL);
2573         }
2574
2575         parent_rate = clk_get_rate(parent);
2576
2577         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2578
2579         if (pll_params->adjust_vco)
2580                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2581                                                              parent_rate);
2582
2583         pll_params->flags |= TEGRA_PLL_BYPASS;
2584         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2585         if (IS_ERR(pll))
2586                 return ERR_CAST(pll);
2587
2588         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2589                                       &tegra_clk_pll_ops);
2590         if (IS_ERR(clk))
2591                 kfree(pll);
2592
2593         return clk;
2594 }
2595
2596 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
2597                                 const char *parent_name, void __iomem *clk_base,
2598                                 unsigned long flags,
2599                                 struct tegra_clk_pll_params *pll_params,
2600                                 spinlock_t *lock)
2601 {
2602         struct tegra_clk_pll *pll;
2603         struct clk *clk, *parent;
2604         unsigned long parent_rate;
2605         u32 val;
2606
2607         if (!pll_params->div_nmp)
2608                 return ERR_PTR(-EINVAL);
2609
2610         parent = __clk_lookup(parent_name);
2611         if (!parent) {
2612                 WARN(1, "parent clk %s of %s must be registered first\n",
2613                         name, parent_name);
2614                 return ERR_PTR(-EINVAL);
2615         }
2616
2617         val = readl_relaxed(clk_base + pll_params->base_reg);
2618         if (val & PLLSS_REF_SRC_SEL_MASK) {
2619                 WARN(1, "not supported reference clock for %s\n", name);
2620                 return ERR_PTR(-EINVAL);
2621         }
2622
2623         parent_rate = clk_get_rate(parent);
2624
2625         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2626
2627         if (pll_params->adjust_vco)
2628                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2629                                                              parent_rate);
2630
2631         pll_params->flags |= TEGRA_PLL_BYPASS;
2632         pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2633         if (IS_ERR(pll))
2634                 return ERR_CAST(pll);
2635
2636         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2637                                         &tegra_clk_pll_ops);
2638
2639         if (IS_ERR(clk))
2640                 kfree(pll);
2641
2642         return clk;
2643 }
2644
2645 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2646                           void __iomem *clk_base, void __iomem *pmc,
2647                           unsigned long flags,
2648                           struct tegra_clk_pll_params *pll_params,
2649                           spinlock_t *lock)
2650 {
2651         struct tegra_clk_pll *pll;
2652         struct clk *clk, *parent;
2653         unsigned long parent_rate;
2654
2655         if (!pll_params->pdiv_tohw)
2656                 return ERR_PTR(-EINVAL);
2657
2658         parent = __clk_lookup(parent_name);
2659         if (!parent) {
2660                 WARN(1, "parent clk %s of %s must be registered first\n",
2661                         parent_name, name);
2662                 return ERR_PTR(-EINVAL);
2663         }
2664
2665         parent_rate = clk_get_rate(parent);
2666
2667         pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
2668
2669         if (pll_params->adjust_vco)
2670                 pll_params->vco_min = pll_params->adjust_vco(pll_params,
2671                                                              parent_rate);
2672
2673         pll_params->flags |= TEGRA_PLL_BYPASS;
2674         pll_params->flags |= TEGRA_PLLMB;
2675         pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
2676         if (IS_ERR(pll))
2677                 return ERR_CAST(pll);
2678
2679         clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2680                                       &tegra_clk_pll_ops);
2681         if (IS_ERR(clk))
2682                 kfree(pll);
2683
2684         return clk;
2685 }
2686
2687 #endif